From 7f307d93ed147fc831425189463d92e50d5c7566 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 14 Apr 2016 06:52:26 +0900 Subject: ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always load u-boot.img whether CONFIG_OF_SEPARATE is defined or not. Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index a3e4aec..82ece0d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -315,11 +315,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#ifdef CONFIG_OF_SEPARATE -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* Disable dcache for SPL just for sure */ -- cgit v0.10.2 From a6b9587bad47749118229da32c7cc3c25a16d962 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 4 Mar 2016 15:56:50 +0100 Subject: gpio: zynq: Add support for reading gpio pin state Add zynq_gpio_get_function() which return status on gpio pin. This function enables gpio status command. Signed-off-by: Michal Simek diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 3a995f6..4ab2356 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -299,11 +299,33 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, return 0; } +static int zynq_gpio_get_function(struct udevice *dev, unsigned offset) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(offset, dev) < 0) + return -1; + + zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev); + + /* set the GPIO pin as output */ + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg &= BIT(bank_pin_num); + if (reg) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + static const struct dm_gpio_ops gpio_zynq_ops = { .direction_input = zynq_gpio_direction_input, .direction_output = zynq_gpio_direction_output, .get_value = zynq_gpio_get_value, .set_value = zynq_gpio_set_value, + .get_function = zynq_gpio_get_function, + }; static const struct udevice_id zynq_gpio_ids[] = { -- cgit v0.10.2 From 621a93e14068787fe07dd31079da9fdf0b312dea Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 25 Apr 2016 12:14:43 +0900 Subject: ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus Commit 9f56917ab88a ("dm: core: make simple-bus compatible to simple-mfd") made possible to import the following commit: Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1 The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus. "simple-mfd" seems a more suitable compatible string than "simple-bus". Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index a327557..b618a3f 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -251,7 +251,7 @@ slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; + compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { -- cgit v0.10.2 From af3b4cd6b5ca548105ace3b593a745775347951c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 13:04:42 +0200 Subject: ARM64: zynqmp: Enable HUSH parser for all zynqmp targets Enable HUSH for all zynqmp boards which don't have it. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index cc08b03..9b40b1f 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 14d24a0..af122f7 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index e1e11b7..dcc5dd2 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 6f1cff8..98aaee6 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index a8982a0..482013f 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y -- cgit v0.10.2 From a1207de0e6d6526e470361fac42f2c077b43a0ad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 14:28:17 +0200 Subject: ARM64: zynqmp: Enable missing distro default options Enable all options which distros requires. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 6b8e3ea..f41a2cb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -65,6 +65,7 @@ #define CONFIG_CMD_ENV #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION +#define CONFIG_ISO_PARTITION #define CONFIG_MP /* BOOTP options */ @@ -74,6 +75,19 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL #define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Diff from config_distro_defaults.h */ +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_AUTO_COMPLETE + +/* PXE */ +#define CONFIG_CMD_PXE +#define CONFIG_MENU #if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC -- cgit v0.10.2 From 6919b4bf36357463b419c4b848b5778d7ba0874e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 11:48:49 +0200 Subject: ARM64: zynqmp: Add support for reading MAC from eeprom Add support for on board eeprom with programmed MAC for using in u-boot to have uniq address for every board. Most of the time uniq MAC address is on a label on the board. If address is not programmed use these command to program it. On zcu102: ZynqMP> mm.b 0 00000000: 00 ? 00 00000001: a0 ? 0a 00000002: 35 ? 35 00000003: 02 ? 02 00000004: 00 ? ef 00000005: 00 ? 67 00000006: 00 ? q i2c dev 5 i2c write 0 54 20 6 i2c md 54 20 Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 132d724..4623cd4 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,22 @@ int board_early_init_r(void) return 0; } +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ + defined(CONFIG_ZYNQ_EEPROM_BUS) + i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); + + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} + #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) /* * fdt_get_reg - Fill buffer by information from DT diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 30db2e4..81079fe 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -48,6 +48,12 @@ #define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102" +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_CMD_EEPROM +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 +#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 + #define CONFIG_KERNEL_FDT_OFST_SIZE \ "kernel_offset=0x180000\0" \ "fdt_offset=0x100000\0" \ -- cgit v0.10.2 From 926782cdf8be8769ae2f9a40ec7a62af1b91ac77 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 26 Apr 2016 16:03:42 +0200 Subject: ARM64: zynqmp: Enable eMMC boot partitions commands Enable some additional features of the eMMC boot partitions. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f41a2cb..e36dde6 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -92,6 +92,7 @@ #if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC # define CONFIG_GENERIC_MMC +# define CONFIG_SUPPORT_EMMC_BOOT # define CONFIG_SDHCI # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 -- cgit v0.10.2 From 73dc3fa6fe37baed8fc5ddeedea7295efd9bbd17 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2016 08:50:45 +0200 Subject: ARM64: zynqmp: Wire up debug_uart setup It has to be enabled by debug_uart_init(). Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index b185593..dbf4906 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -46,6 +46,11 @@ CONFIG_ZYNQ_SDHCI=y CONFIG_NAND_ARASAN=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 98aaee6..1ebadd2 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -39,6 +39,11 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 482013f..59e1cf1 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -39,6 +39,11 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -- cgit v0.10.2 From 9a23f458cbddfbfb67033a2aa60397821698a8a7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 3 May 2016 14:20:17 +0200 Subject: ARM: zynq: Add support for SPL_LOAD_FIT Enable minimal function to be able to compile SPL_LOAD_FIT. Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 723019d..9988965 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -90,3 +90,13 @@ __weak void ps7_init(void) * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. */ } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif -- cgit v0.10.2 From 013642c2d4a652878a4e7583fe125ea76582ce55 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 29 Apr 2016 13:04:02 +0200 Subject: ARM64: zynqmp: Remove CONFIG_PREBOOT CONFIG_PREBOOT variable is breaking ./test/py framework. Remove it. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e36dde6..e6c38a5 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -159,7 +159,6 @@ "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO -#define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 -- cgit v0.10.2 From 71eb243be3edffdc32f3c7b577e86d9f76f6f289 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 17 Mar 2016 23:02:37 +0100 Subject: ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108 Add missing SPI flash options. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index dbf4906..903dc48 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -44,6 +44,8 @@ CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_NAND_ARASAN=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y -- cgit v0.10.2 From bd483780d3925d62dc896cc9bf1351b8a8c01ed8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 May 2016 12:33:22 +0200 Subject: ARM64: zynqmp: Add debug uart for zc1751-dc1 It is helpful for debugging. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 9b40b1f..77a508e 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -41,6 +41,11 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_USB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -- cgit v0.10.2 From 3a3b9147892cb47f96dff1075f1494dca17b6eaf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2016 07:54:20 +0200 Subject: spl: Introduce new function spl_board_prepare_for_boot Call this function before passing control from SPL. For fpga case it is necessary to enable for example level shifters when bitstream is programmed. Signed-off-by: Michal Simek Reviewed-by: Simon Glass diff --git a/common/spl/spl.c b/common/spl/spl.c index 93f9bd1..caaf135 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -64,6 +64,11 @@ __weak void spl_board_prepare_for_linux(void) /* Nothing to do! */ } +__weak void spl_board_prepare_for_boot(void) +{ + /* Nothing to do! */ +} + void spl_set_header_raw_uboot(void) { spl_image.size = CONFIG_SYS_MONITOR_LEN; @@ -404,6 +409,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif debug("loaded - jumping to U-Boot..."); + spl_board_prepare_for_boot(); jump_to_image_no_args(&spl_image); } diff --git a/include/spl.h b/include/spl.h index 7edfab4..335b76a 100644 --- a/include/spl.h +++ b/include/spl.h @@ -58,6 +58,7 @@ u32 spl_boot_mode(void); void spl_set_header_raw_uboot(void); int spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); +void spl_board_prepare_for_boot(void); void __noreturn jump_to_image_linux(void *arg); int spl_start_uboot(void); void spl_display_print(void); -- cgit v0.10.2 From 27640fda55bf998d1eb5109b3410bf62e445e191 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2016 09:50:35 +0200 Subject: ARM64: zynqmp: Enable option to overwrite default variables Enable overwriting variables out of main config file. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e6c38a5..1a1892d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -148,6 +148,7 @@ #endif /* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ @@ -158,6 +159,7 @@ "load mmc $sdbootdev:$partid $kernel_addr Image && " \ "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO +#endif #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 -- cgit v0.10.2 From f44e603f73ea43268f0858b9aa4daf962f1eb347 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 May 2016 07:55:52 +0200 Subject: ARM: zynq: Call ps7_post_config() for SPL If ps7_post_config() is defined call it. It is enabling for example level shifters for PL bitstreams. Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 9988965..6c5415a 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -91,6 +91,21 @@ __weak void ps7_init(void) */ } +__weak int ps7_post_config(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. + */ + return 0; +} + +void spl_board_prepare_for_boot(void) +{ + ps7_post_config(); + debug("SPL bye\n"); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { -- cgit v0.10.2 From 8d16e1d5931bb1323ef5307204563b7afcb3b6c3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 28 Apr 2016 09:54:16 +0200 Subject: SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode Support loading FIT in SPL for RAM bootmode. CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored in memory. Signed-off-by: Michal Simek Reviewed-by: Simon Glass Reviewed-by: Lokesh Vutla diff --git a/common/spl/spl.c b/common/spl/spl.c index caaf135..bdde716 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -140,20 +140,47 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry(); } +#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS +# define CONFIG_SPL_LOAD_FIT_ADDRESS 0 +#endif + #ifdef CONFIG_SPL_RAM_DEVICE +static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + debug("%s: sector %lx, count %lx, buf %lx\n", + __func__, sector, count, (ulong)buf); + memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count); + return count; +} + static int spl_ram_load_image(void) { - const struct image_header *header; + struct image_header *header; - /* - * Get the header. It will point to an address defined by handoff - * which will tell where the image located inside the flash. For - * now, it will temporary fixed to address pointed by U-Boot. - */ - header = (struct image_header *) - (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header)); + header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS; - spl_parse_image_header(header); + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.bl_len = 1; + load.read = spl_ram_load_read; + spl_load_simple_fit(&load, 0, header); + } else { + debug("Legacy image\n"); + /* + * Get the header. It will point to an address defined by + * handoff which will tell where the image located inside + * the flash. For now, it will temporary fixed to address + * pointed by U-Boot. + */ + header = (struct image_header *) + (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header)); + + spl_parse_image_header(header); + } return 0; } -- cgit v0.10.2 From d9b58b303120fb8fe0b7c9799e2b7682da4bec16 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Apr 2016 14:03:29 +0200 Subject: tools: zynqmpimage: Add Xilinx ZynqMP boot header generation Add support for the zynqmpimage to mkimage. Only basic functionality is supported without encryption and register initialization with one partition which is filled by U-Boot SPL. For more detail information look at Xilinx ZynqMP TRM. Signed-off-by: Michal Simek Reviewed-by: Simon Glass diff --git a/common/image.c b/common/image.c index 26d6c9a..9824685 100644 --- a/common/image.c +++ b/common/image.c @@ -159,6 +159,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, + { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index f9ee564..a8488f2 100644 --- a/include/image.h +++ b/include/image.h @@ -246,8 +246,9 @@ struct lmb; #define IH_TYPE_RKSD 24 /* Rockchip SD card */ #define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ #define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ +#define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */ -#define IH_TYPE_COUNT 27 /* Number of image types */ +#define IH_TYPE_COUNT 28 /* Number of image types */ /* * Compression Types diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ec8d8f1..6d2017d 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -129,7 +129,12 @@ endif boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) else +ifdef CONFIG_ARCH_ZYNQ MKIMAGEFLAGS_boot.bin = -T zynqimage +endif +ifdef CONFIG_ARCH_ZYNQMP +MKIMAGEFLAGS_boot.bin = -T zynqmpimage +endif spl/boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) @@ -157,6 +162,8 @@ ifdef CONFIG_ARCH_ZYNQ ALL-y += $(obj)/boot.bin endif +ALL-(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin + all: $(ALL-y) quiet_cmd_cat = CAT $@ diff --git a/tools/Makefile b/tools/Makefile index da50e1b..63355aa 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \ common/hash.o \ ublimage.o \ zynqimage.o \ + zynqmpimage.o \ $(LIBFDT_OBJS) \ $(RSA_OBJS-y) diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c new file mode 100644 index 0000000..3f28eb4 --- /dev/null +++ b/tools/zynqmpimage.c @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2016 Michal Simek + * Copyright (C) 2015 Nathan Rossi + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The following Boot Header format/structures and values are defined in the + * following documents: + * * ug1085 ZynqMP TRM (Chapter 9, Table 9-3) + * + * Expected Header Size = 0x9C0 + * Forced as 'little' endian, 32-bit words + * + * 0x 0 - Interrupt table (8 words) + * ... (Default value = 0xeafffffe) + * 0x 1f + * 0x 20 - Width detection + * * DEFAULT_WIDTHDETECTION 0xaa995566 + * 0x 24 - Image identifier + * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58 + * 0x 28 - Encryption + * * 0x00000000 - None + * * 0xa5c3c5a3 - eFuse + * * 0xa5c3c5a7 - obfuscated key in eFUSE + * * 0x3a5c3c5a - bbRam + * * 0xa35c7ca5 - obfuscated key in boot header + * 0x 2C - Image load + * 0x 30 - Image offset + * 0x 34 - PFW image length + * 0x 38 - Total PFW image length + * 0x 3C - Image length + * 0x 40 - Total image length + * 0x 44 - Image attributes + * 0x 48 - Header checksum + * 0x 4c - Obfuscated key + * ... + * 0x 68 + * 0x 6c - Reserved + * 0x 70 - User defined + * ... + * 0x 9c + * 0x a0 - Secure header initialization vector + * ... + * 0x a8 + * 0x ac - Obfuscated key initialization vector + * ... + * 0x b4 + * 0x b8 - Register Initialization, 511 Address and Data word pairs + * * List is terminated with an address of 0xffffffff or + * ... * at the max number of entries + * 0x8b4 + * 0x8b8 - Reserved + * ... + * 0x9bf + * 0x9c0 - Data/Image starts here or above + */ + +#include "imagetool.h" +#include "mkimage.h" +#include + +#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe)) +#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff)) +#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566)) +#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58)) + +enum { + ENCRYPTION_EFUSE = 0xa5c3c5a3, + ENCRYPTION_OEFUSE = 0xa5c3c5a7, + ENCRYPTION_BBRAM = 0x3a5c3c5a, + ENCRYPTION_OBBRAM = 0xa35c7ca5, + ENCRYPTION_NONE = 0x0, +}; + +struct zynqmp_reginit { + uint32_t address; + uint32_t data; +}; + +#define HEADER_INTERRUPT_VECTORS 8 +#define HEADER_REGINITS 256 + +struct zynqmp_header { + uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */ + uint32_t width_detection; /* 0x20 */ + uint32_t image_identifier; /* 0x24 */ + uint32_t encryption; /* 0x28 */ + uint32_t image_load; /* 0x2c */ + uint32_t image_offset; /* 0x30 */ + uint32_t pfw_image_length; /* 0x34 */ + uint32_t total_pfw_image_length; /* 0x38 */ + uint32_t image_size; /* 0x3c */ + uint32_t image_stored_size; /* 0x40 */ + uint32_t image_attributes; /* 0x44 */ + uint32_t checksum; /* 0x48 */ + uint32_t __reserved1[27]; /* 0x4c */ + struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */ + uint32_t __reserved4[66]; /* 0x9c0 */ +}; + +static struct zynqmp_header zynqmpimage_header; + +static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr) +{ + uint32_t checksum = 0; + + if (ptr == NULL) + return 0; + + checksum += le32_to_cpu(ptr->width_detection); + checksum += le32_to_cpu(ptr->image_identifier); + checksum += le32_to_cpu(ptr->encryption); + checksum += le32_to_cpu(ptr->image_load); + checksum += le32_to_cpu(ptr->image_offset); + checksum += le32_to_cpu(ptr->pfw_image_length); + checksum += le32_to_cpu(ptr->total_pfw_image_length); + checksum += le32_to_cpu(ptr->image_size); + checksum += le32_to_cpu(ptr->image_stored_size); + checksum += le32_to_cpu(ptr->image_attributes); + checksum = ~checksum; + + return cpu_to_le32(checksum); +} + +static void zynqmpimage_default_header(struct zynqmp_header *ptr) +{ + int i; + + if (ptr == NULL) + return; + + ptr->width_detection = HEADER_WIDTHDETECTION; + ptr->image_attributes = 0x800; + ptr->image_identifier = HEADER_IMAGEIDENTIFIER; + ptr->encryption = cpu_to_le32(ENCRYPTION_NONE); + + /* Setup not-supported/constant/reserved fields */ + for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) + ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT; + + for (i = 0; i < HEADER_REGINITS; i++) { + ptr->register_init[i].address = HEADER_REGINIT_NULL; + ptr->register_init[i].data = 0; + } + + /* + * Certain reserved fields are required to be set to 0, ensure they are + * set as such. + */ + ptr->pfw_image_length = 0x0; + ptr->total_pfw_image_length = 0x0; +} + +/* mkimage glue functions */ +static int zynqmpimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; + + if (image_size < sizeof(struct zynqmp_header)) + return -1; + + if (zynqhdr->width_detection != HEADER_WIDTHDETECTION) + return -1; + if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER) + return -1; + + if (zynqmpimage_checksum(zynqhdr) != zynqhdr->checksum) + return -1; + + return 0; +} + +static void zynqmpimage_print_header(const void *ptr) +{ + struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; + int i; + + printf("Image Type : Xilinx Zynq Boot Image support\n"); + printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset)); + printf("Image Size : %lu bytes (%lu bytes packed)\n", + (unsigned long)le32_to_cpu(zynqhdr->image_size), + (unsigned long)le32_to_cpu(zynqhdr->image_stored_size)); + printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load)); + printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum)); + + for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) { + if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT) + continue; + + printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i, + le32_to_cpu(zynqhdr->interrupt_vectors[i])); + } + + for (i = 0; i < HEADER_REGINITS; i++) { + if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL) + break; + + if (i == 0) + printf("Custom Register Initialization:\n"); + + printf(" @ 0x%08x -> 0x%08x\n", + le32_to_cpu(zynqhdr->register_init[i].address), + le32_to_cpu(zynqhdr->register_init[i].data)); + } +} + +static int zynqmpimage_check_params(struct image_tool_params *params) +{ + if (!params) + return 0; + + if (params->addr != 0x0) { + fprintf(stderr, "Error: Load Address cannot be specified.\n"); + return -1; + } + + /* + * If the entry point is specified ensure it is 64 byte aligned. + */ + if (params->eflag && (params->ep % 64 != 0)) { + fprintf(stderr, + "Error: Entry Point must be aligned to a 64-byte boundary.\n"); + return -1; + } + + return !(params->lflag || params->dflag); +} + +static int zynqmpimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_ZYNQMPIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr; + zynqmpimage_default_header(zynqhdr); + + /* place image directly after header */ + zynqhdr->image_offset = + cpu_to_le32((uint32_t)sizeof(struct zynqmp_header)); + zynqhdr->image_size = cpu_to_le32(params->file_size - + sizeof(struct zynqmp_header)); + zynqhdr->image_stored_size = zynqhdr->image_size; + zynqhdr->image_load = 0xfffc0000; + if (params->eflag) + zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep); + + zynqhdr->checksum = zynqmpimage_checksum(zynqhdr); +} + +U_BOOT_IMAGE_TYPE( + zynqmpimage, + "Xilinx ZynqMP Boot Image support", + sizeof(struct zynqmp_header), + (void *)&zynqmpimage_header, + zynqmpimage_check_params, + zynqmpimage_verify_header, + zynqmpimage_print_header, + zynqmpimage_set_header, + NULL, + zynqmpimage_check_image_types, + NULL, + NULL +); -- cgit v0.10.2 From 0a8c4f67f3783eaf5330953b957e232dde747331 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Thu, 12 May 2016 13:44:01 +0200 Subject: ARM64: zynqmp: Align gic ranges for 64k in device tree The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index fb95b48..c6ba872 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -253,9 +253,9 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf902f000 0x2000>, + <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, - <0x0 0xf906f000 0x2000>; + <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; -- cgit v0.10.2 From c9811e14cfee68e3df054fd1597064f58c4e7e27 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 22 Feb 2016 09:57:27 +0100 Subject: ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI Add missing u-boot,dm-pre-reloc to get IPs initialized. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index c6ba872..619450e 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -264,6 +264,7 @@ amba: amba { compatible = "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; @@ -674,6 +675,7 @@ }; sdhci0: sdhci@ff160000 { + u-boot,dm-pre-reloc; compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -685,6 +687,7 @@ }; sdhci1: sdhci@ff170000 { + u-boot,dm-pre-reloc; compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -776,6 +779,7 @@ }; uart0: serial@ff000000 { + u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; @@ -786,6 +790,7 @@ }; uart1: serial@ff010000 { + u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; -- cgit v0.10.2 From e6a9ed04e78cf87ec97e306fa4e7a1669ef98df6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 Nov 2015 13:17:22 +0100 Subject: ARM64: zynqmp: Add SPL support support Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin cp atf.ub cp u-boot.bin 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin cp u-boot*.img 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e..729b181 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -594,6 +594,7 @@ config ARCH_ZYNQMP select DM select OF_CONTROL select DM_SERIAL + select SUPPORT_SPL config TEGRA bool "NVIDIA Tegra" diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index d0ed222..be8673a 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -9,3 +9,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-y += slcr.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c new file mode 100644 index 0000000..e3e2a4f --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -0,0 +1,107 @@ +/* + * Copyright 2015 - 2016 Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include +#include +#include + +void board_init_f(ulong dummy) +{ + psu_init(); + board_early_init_r(); + +#ifdef CONFIG_DEBUG_UART + /* Uart debug for sure */ + debug_uart_init(); + puts("Debug uart enabled\n"); /* or printch() */ +#endif + /* Delay is required for clocks to be propagated */ + udelay(1000000); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* No need to call timer init - it is empty for ZynqMP */ + board_init_r(NULL, 0); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + preloader_console_init(); + board_init(); +} +#endif + +u32 spl_boot_device(void) +{ + u32 reg = 0; + u8 bootmode; + + reg = readl(&crlapb_base->boot_mode); + bootmode = reg & BOOT_MODES_MASK; + + switch (bootmode) { + case JTAG_MODE: + return BOOT_DEVICE_RAM; +#ifdef CONFIG_SPL_MMC_SUPPORT + case EMMC_MODE: + case SD_MODE: + case SD_MODE1: + return BOOT_DEVICE_MMC1; +#endif + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_RAM: + return 0; + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FS; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +__weak void psu_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. + */ +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 021626d..1db2bd6 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -17,4 +17,6 @@ int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); +void psu_init(void); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 2ab3f19..90f00c6 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -1,8 +1,29 @@ # -# (C) Copyright 2014 - 2015 Xilinx, Inc. +# (C) Copyright 2014 - 2016 Xilinx, Inc. # Michal Simek # # SPDX-License-Identifier: GPL-2.0+ # obj-y := zynqmp.o + +hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME)) + +init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\ + $(hw-platform-y)/psu_init_gpl.o) + +ifeq ($(init-objs),) +ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),) +init-objs := psu_init_gpl.o +$(if $(CONFIG_SPL_BUILD),\ +$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/)) +endif +endif + +obj-$(CONFIG_SPL_BUILD) += $(init-objs) + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes + +# To include xil_io.h +CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src) diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h new file mode 100644 index 0000000..57ca4ad --- /dev/null +++ b/board/xilinx/zynqmp/xil_io.h @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H + +/* FIXME remove this when vivado is fixed */ +#include + +#define xil_printf(...) + +void Xil_ICacheEnable(void) +{} + +void Xil_DCacheEnable(void) +{} + +void Xil_ICacheDisable(void) +{} + +void Xil_DCacheDisable(void) +{} + +void Xil_Out32(unsigned long addr, unsigned long val) +{ + writel(val, addr); +} + +int Xil_In32(unsigned long addr) +{ + return readl(addr); +} + +#endif /* XIL_IO_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 1a1892d..b2fa164 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -41,7 +41,7 @@ # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR 0xfffffffc /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ #if !defined(COUNTER_FREQUENCY) @@ -65,7 +65,9 @@ #define CONFIG_CMD_ENV #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION -#define CONFIG_ISO_PARTITION +#ifndef CONFIG_SPL_BUILD +# define CONFIG_ISO_PARTITION +#endif #define CONFIG_MP /* BOOTP options */ @@ -228,4 +230,41 @@ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_CLOCKS +#define CONFIG_SPL_TEXT_BASE 0xfffc0000 +#define CONFIG_SPL_MAX_SIZE 0x20000 + +/* Just random location in OCM */ +#define CONFIG_SPL_BSS_START_ADDR 0x1000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000000 + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE + +#define CONFIG_SPL_OS_BOOT +/* u-boot is like dtb */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 + +/* ATF is my kernel image */ +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf.ub" + +/* FIT load address for RAM boot */ +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 + +/* MMC support */ +#ifdef CONFIG_ZYNQ_SDHCI +# define CONFIG_SPL_MMC_SUPPORT +# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ +# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ +# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */ +# define CONFIG_SPL_LIBDISK_SUPPORT +# define CONFIG_SPL_FAT_SUPPORT +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + #endif /* __XILINX_ZYNQMP_H */ -- cgit v0.10.2 From 293271cbc3080a3d23afe48adafbfba271cd6761 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 May 2016 13:33:11 +0200 Subject: ARM64: zynqmp: Enable CLK framework ZynqMP is using fixed clocks now that's why enabling it to be available for drivers. Signed-off-by: Michal Simek diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 903dc48..37b8052 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 77a508e..fa761e5 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index af122f7..2811d4b 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_NAND_ARASAN=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index dcc5dd2..3711084 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 1ebadd2..46a5dd0 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 59e1cf1..96a2be1 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y -- cgit v0.10.2 From 905bca6c2d65fc639cffdca42004602e041eb97a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 May 2016 14:32:00 +0200 Subject: fpga: Fix typo in function comment Trivial patch. Signed-off-by: Michal Simek diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index d94eb5c..7e2f3e1 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -120,7 +120,7 @@ static int fpga_dev_info(int devnum) } /* - * fgpa_init is usually called from misc_init_r() and MUST be called + * fpga_init is usually called from misc_init_r() and MUST be called * before any of the other fpga functions are used. */ void fpga_init(void) -- cgit v0.10.2 From ed0cea7c5271cbfd37089f3a6392ba383eda06f7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 May 2016 13:58:44 +0200 Subject: mkimage: Report information about fpga Add FIT_FPGA_PROP that user can identify an optional entry for fpga. Signed-off-by: Michal Simek Reviewed-by: Simon Glass diff --git a/common/image-fit.c b/common/image-fit.c index c86b7c6..8a0ca2a 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1483,6 +1483,10 @@ void fit_conf_print(const void *fit, int noffset, const char *p) if (uname) printf("%s FDT: %s\n", p, uname); + uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL); + if (uname) + printf("%s FPGA: %s\n", p, uname); + /* Print out all of the specified loadables */ for (loadables_index = 0; fdt_get_string_index(fit, noffset, diff --git a/common/image.c b/common/image.c index 9824685..ec78b7e 100644 --- a/common/image.c +++ b/common/image.c @@ -160,6 +160,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, + { IH_TYPE_FPGA, "fpga", "FPGA Image" }, { -1, "", "", }, }; diff --git a/doc/uImage.FIT/multi-with-fpga.its b/doc/uImage.FIT/multi-with-fpga.its new file mode 100644 index 0000000..0cdb31f --- /dev/null +++ b/doc/uImage.FIT/multi-with-fpga.its @@ -0,0 +1,67 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + * This example makes use of the 'loadables' field + */ + +/dts-v1/; + +/ { + description = "Configuration to load fpga before Kernel"; + #address-cells = <1>; + + images { + fdt@1 { + description = "zc706"; + data = /incbin/("/tftpboot/devicetree.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + load = <0x10000000>; + hash@1 { + algo = "md5"; + }; + }; + + fpga@1 { + description = "FPGA"; + data = /incbin/("/tftpboot/download.bit"); + type = "fpga"; + arch = "arm"; + compression = "none"; + load = <0x30000000>; + hash@1 { + algo = "md5"; + }; + }; + + linux_kernel@1 { + description = "Linux"; + data = /incbin/("/tftpboot/zImage"); + type = "kernel"; + arch = "arm"; + os = "linux"; + compression = "none"; + load = <0x8000>; + entry = <0x8000>; + hash@1 { + algo = "md5"; + }; + }; + }; + + configurations { + default = "config@2"; + config@1 { + description = "Linux"; + kernel = "linux_kernel@1"; + fdt = "fdt@1"; + }; + + config@2 { + description = "Linux with fpga"; + kernel = "linux_kernel@1"; + fdt = "fdt@1"; + fpga = "fpga@1"; + }; + }; +}; diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 9c527c3..3f54180 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -236,6 +236,7 @@ o config@1 |- kernel = "kernel sub-node unit name" |- ramdisk = "ramdisk sub-node unit name" |- fdt = "fdt sub-node unit-name" + |- fpga = "fpga sub-node unit-name" |- loadables = "loadables sub-node unit-name" @@ -251,6 +252,8 @@ o config@1 "fdt type"). - setup : Unit name of the corresponding setup binary (used for booting an x86 kernel). This contains the setup.bin file built by the kernel. + - fpga : Unit name of the corresponding fpga bitstream blob + (component image node of a "fpga type"). - loadables : Unit name containing a list of additional binaries to be loaded at their given locations. "loadables" is a comma-separated list of strings. U-Boot will load each binary at its given start-address. diff --git a/include/image.h b/include/image.h index a8488f2..e2a90ca 100644 --- a/include/image.h +++ b/include/image.h @@ -247,8 +247,9 @@ struct lmb; #define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ #define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ #define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */ +#define IH_TYPE_FPGA 28 /* FPGA Image */ -#define IH_TYPE_COUNT 28 /* Number of image types */ +#define IH_TYPE_COUNT 29 /* Number of image types */ /* * Compression Types @@ -810,6 +811,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end); #define FIT_LOADABLE_PROP "loadables" #define FIT_DEFAULT_PROP "default" #define FIT_SETUP_PROP "setup" +#define FIT_FPGA_PROP "fpga" #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE -- cgit v0.10.2 From 55259e7cda875bff3e0fcfd5fc61478f40872841 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2016 12:37:22 +0200 Subject: net: xilinx: Handle error value from phy_startup() Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek Acked-by: Stephen Warren diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 5862bf0..7b85aa0 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -250,7 +250,7 @@ static void emaclite_stop(struct udevice *dev) static int setup_phy(struct udevice *dev) { - int i; + int i, ret; u16 phyreg; struct xemaclite *emaclite = dev_get_priv(dev); struct phy_device *phydev; @@ -302,7 +302,9 @@ static int setup_phy(struct udevice *dev) phydev->advertising = supported; emaclite->phydev = phydev; phy_config(phydev); - phy_startup(phydev); + ret = phy_startup(phydev); + if (ret) + return ret; if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index aec8077..3704ce0 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -360,6 +360,7 @@ static int zynq_phy_init(struct udevice *dev) static int zynq_gem_init(struct udevice *dev) { u32 i, nwconfig; + int ret; unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; @@ -427,7 +428,9 @@ static int zynq_gem_init(struct udevice *dev) priv->init++; } - phy_startup(priv->phydev); + ret = phy_startup(priv->phydev); + if (ret) + return ret; if (!priv->phydev->link) { printf("%s: No link.\n", priv->phydev->dev->name); -- cgit v0.10.2 From ef5e821bd89aa059a20841e041221dadbf60aa7d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2016 12:48:57 +0200 Subject: phy: Return correct error code when timeout happens Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek Acked-by: Stephen Warren diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b8b1157..d24451b 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -103,7 +103,7 @@ static int m88e1011s_config(struct phy_device *phydev) /* Parse the 88E1011's status register for speed and duplex * information */ -static uint m88e1xxx_parse_status(struct phy_device *phydev) +static int m88e1xxx_parse_status(struct phy_device *phydev) { unsigned int speed; unsigned int mii_reg; @@ -120,7 +120,7 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev) if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts(" TIMEOUT !\n"); phydev->link = 0; - break; + return -ETIMEDOUT; } if ((i++ % 1000) == 0) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 23c82bb..68e752e 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -248,7 +248,7 @@ int genphy_update_link(struct phy_device *phydev) if (i > PHY_ANEG_TIMEOUT) { printf(" TIMEOUT !\n"); phydev->link = 0; - return 0; + return -ETIMEDOUT; } if (ctrlc()) { -- cgit v0.10.2 From b733c278d7adc48c71bd06faf359db3d9e385185 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2016 12:46:12 +0200 Subject: net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek Acked-by: Stephen Warren diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 4b2808e..9871cc3 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -84,11 +84,14 @@ static int bcm54xx_parse_status(struct phy_device *phydev) static int bcm54xx_startup(struct phy_device *phydev) { + int ret; + /* Read the Status (2x to make sure link is right) */ - genphy_update_link(phydev); - bcm54xx_parse_status(phydev); + ret = genphy_update_link(phydev); + if (ret) + return ret; - return 0; + return bcm54xx_parse_status(phydev); } /* Broadcom BCM5482S */ @@ -139,11 +142,14 @@ static int bcm5482_config(struct phy_device *phydev) static int bcm_cygnus_startup(struct phy_device *phydev) { + int ret; + /* Read the Status (2x to make sure link is right) */ - genphy_update_link(phydev); - genphy_parse_link(phydev); + ret = genphy_update_link(phydev); + if (ret) + return ret; - return 0; + return genphy_parse_link(phydev); } static int bcm_cygnus_config(struct phy_device *phydev) @@ -239,17 +245,21 @@ static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev) */ static int bcm5482_startup(struct phy_device *phydev) { + int ret; + if (bcm5482_is_serdes(phydev)) { bcm5482_parse_serdes_sr(phydev); phydev->port = PORT_FIBRE; - } else { - /* Wait for auto-negotiation to complete or fail */ - genphy_update_link(phydev); - /* Parse BCM54xx copper aux status register */ - bcm54xx_parse_status(phydev); + return 0; } - return 0; + /* Wait for auto-negotiation to complete or fail */ + ret = genphy_update_link(phydev); + if (ret) + return ret; + + /* Parse BCM54xx copper aux status register */ + return bcm54xx_parse_status(phydev); } static struct phy_driver BCM5461S_driver = { diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c index 0c039fe..0a6e410 100644 --- a/drivers/net/phy/davicom.c +++ b/drivers/net/phy/davicom.c @@ -60,10 +60,13 @@ static int dm9161_parse_status(struct phy_device *phydev) static int dm9161_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - dm9161_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return dm9161_parse_status(phydev); } static struct phy_driver DM9161_driver = { diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c index 70c15e2..2fe0132 100644 --- a/drivers/net/phy/et1011c.c +++ b/drivers/net/phy/et1011c.c @@ -79,9 +79,13 @@ static int et1011c_parse_status(struct phy_device *phydev) static int et1011c_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - et1011c_parse_status(phydev); - return 0; + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return et1011c_parse_status(phydev); } static struct phy_driver et1011c_driver = { diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c index 91838ce..9abc2a8 100644 --- a/drivers/net/phy/lxt.c +++ b/drivers/net/phy/lxt.c @@ -49,10 +49,13 @@ static int lxt971_parse_status(struct phy_device *phydev) static int lxt971_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - lxt971_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return lxt971_parse_status(phydev); } static struct phy_driver LXT971_driver = { diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index d24451b..64713fb 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -162,10 +162,13 @@ static int m88e1xxx_parse_status(struct phy_device *phydev) static int m88e1011s_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - m88e1xxx_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return m88e1xxx_parse_status(phydev); } /* Marvell 88E1111S */ @@ -358,13 +361,16 @@ static int m88e1118_config(struct phy_device *phydev) static int m88e1118_startup(struct phy_device *phydev) { + int ret; + /* Change Page Number */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); - genphy_update_link(phydev); - m88e1xxx_parse_status(phydev); + ret = genphy_update_link(phydev); + if (ret) + return ret; - return 0; + return m88e1xxx_parse_status(phydev); } /* Marvell 88E1121R */ @@ -421,12 +427,15 @@ static int m88e1145_config(struct phy_device *phydev) static int m88e1145_startup(struct phy_device *phydev) { - genphy_update_link(phydev); + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, MIIM_88E1145_PHY_LED_DIRECT); - m88e1xxx_parse_status(phydev); - - return 0; + return m88e1xxx_parse_status(phydev); } /* Marvell 88E1149S */ diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 8fcf737..b08788a 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -181,7 +181,12 @@ static struct phy_driver KS8721_driver = { static int ksz90xx_startup(struct phy_device *phydev) { unsigned phy_ctl; - genphy_update_link(phydev); + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX) diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c index d2e4c3c..1592e9b 100644 --- a/drivers/net/phy/natsemi.c +++ b/drivers/net/phy/natsemi.c @@ -93,10 +93,13 @@ static int dp83865_parse_status(struct phy_device *phydev) static int dp83865_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - dp83865_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return dp83865_parse_status(phydev); } @@ -134,10 +137,13 @@ static int dp83848_parse_status(struct phy_device *phydev) static int dp83848_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - dp83848_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return dp83848_parse_status(phydev); } static struct phy_driver DP83848_driver = { diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 68e752e..98986bb 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -431,10 +431,13 @@ int genphy_config(struct phy_device *phydev) int genphy_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - genphy_parse_link(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return genphy_parse_link(phydev); } int genphy_shutdown(struct phy_device *phydev) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 9d7f55b..7a99cb0 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -208,28 +208,38 @@ static int rtl8211f_parse_status(struct phy_device *phydev) static int rtl8211x_startup(struct phy_device *phydev) { + int ret; + /* Read the Status (2x to make sure link is right) */ - genphy_update_link(phydev); - rtl8211x_parse_status(phydev); + ret = genphy_update_link(phydev); + if (ret) + return ret; - return 0; + return rtl8211x_parse_status(phydev); } static int rtl8211e_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - genphy_parse_link(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return genphy_parse_link(phydev); } static int rtl8211f_startup(struct phy_device *phydev) { + int ret; + + /* Read the Status (2x to make sure link is right) */ + ret = genphy_update_link(phydev); + if (ret) + return ret; /* Read the Status (2x to make sure link is right) */ - genphy_update_link(phydev); - rtl8211f_parse_status(phydev); - return 0; + return rtl8211f_parse_status(phydev); } /* Support for RTL8211B PHY */ diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index 34986a2..313fcdf 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -34,9 +34,13 @@ static int smsc_parse_status(struct phy_device *phydev) static int smsc_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - smsc_parse_status(phydev); - return 0; + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return smsc_parse_status(phydev); } static struct phy_driver lan8700_driver = { diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 941d076..2635b82 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -112,10 +112,12 @@ static int vitesse_parse_status(struct phy_device *phydev) static int vitesse_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - vitesse_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + return vitesse_parse_status(phydev); } static int cis8204_config(struct phy_device *phydev) -- cgit v0.10.2 From 62afc601883e788f3f22291202d5b2a23c1a8b06 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 17 May 2016 14:03:50 +0200 Subject: image: Add boot_get_fpga() to load fpga with bootm Add function boot_get_fpga() which find and load bitstream to programmable logic if fpga entry is present. Function is supported on Xilinx devices for full and partial bitstreams in BIN and BIT format. Signed-off-by: Michal Simek Remove additional blankline in image.h diff --git a/common/bootm.c b/common/bootm.c index c965326..4941414 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -246,6 +246,16 @@ int bootm_find_images(int flag, int argc, char * const argv[]) #endif #if IMAGE_ENABLE_FIT +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX) + /* find bitstreams */ + ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT, + NULL, NULL); + if (ret) { + printf("FPGA image is corrupted or invalid\n"); + return 1; + } +#endif + /* find all of the loadables */ ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT, NULL, NULL); diff --git a/common/image-fit.c b/common/image-fit.c index 8a0ca2a..9873957 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -422,7 +422,8 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) } if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) || - (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) { + (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK) || + (type == IH_TYPE_FPGA)) { ret = fit_image_get_load(fit, image_noffset, &load); printf("%s Load Address: ", p); if (ret) @@ -1571,6 +1572,8 @@ static const char *fit_get_image_type_property(int type) return FIT_SETUP_PROP; case IH_TYPE_LOADABLE: return FIT_LOADABLE_PROP; + case IH_TYPE_FPGA: + return FIT_FPGA_PROP; } return "unknown"; @@ -1685,7 +1688,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD)); - os_ok = image_type == IH_TYPE_FLATDT || + os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA || fit_image_check_os(fit, noffset, IH_OS_LINUX) || fit_image_check_os(fit, noffset, IH_OS_OPENRTOS); diff --git a/common/image.c b/common/image.c index ec78b7e..0be09e5 100644 --- a/common/image.c +++ b/common/image.c @@ -32,6 +32,8 @@ #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT #include #include +#include +#include #endif #include @@ -1212,6 +1214,96 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch, } #if IMAGE_ENABLE_FIT +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX) +int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len) +{ + ulong tmp_img_addr, img_data, img_len; + void *buf; + int conf_noffset; + int fit_img_result; + char *uname, *name; + int err; + int devnum = 0; /* TODO support multi fpga platforms */ + const fpga_desc * const desc = fpga_get_desc(devnum); + xilinx_desc *desc_xilinx = desc->devdesc; + + /* Check to see if the images struct has a FIT configuration */ + if (!genimg_has_config(images)) { + debug("## FIT configuration was not specified\n"); + return 0; + } + + /* + * Obtain the os FIT header from the images struct + * copy from dataflash if needed + */ + tmp_img_addr = map_to_sysmem(images->fit_hdr_os); + tmp_img_addr = genimg_get_image(tmp_img_addr); + buf = map_sysmem(tmp_img_addr, 0); + /* + * Check image type. For FIT images get FIT node + * and attempt to locate a generic binary. + */ + switch (genimg_get_format(buf)) { + case IMAGE_FORMAT_FIT: + conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg); + + err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0, + (const char **)&uname); + if (err < 0) { + debug("## FPGA image is not specified\n"); + return 0; + } + fit_img_result = fit_image_load(images, + tmp_img_addr, + (const char **)&uname, + &(images->fit_uname_cfg), + arch, + IH_TYPE_FPGA, + BOOTSTAGE_ID_FPGA_INIT, + FIT_LOAD_OPTIONAL_NON_ZERO, + &img_data, &img_len); + + debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n", + uname, img_data, img_len); + + if (fit_img_result < 0) { + /* Something went wrong! */ + return fit_img_result; + } + + if (img_len >= desc_xilinx->size) { + name = "full"; + err = fpga_loadbitstream(devnum, (char *)img_data, + img_len, BIT_FULL); + if (err) + err = fpga_load(devnum, (const void *)img_data, + img_len, BIT_FULL); + } else { + name = "partial"; + err = fpga_loadbitstream(devnum, (char *)img_data, + img_len, BIT_PARTIAL); + if (err) + err = fpga_load(devnum, (const void *)img_data, + img_len, BIT_PARTIAL); + } + + printf(" Programming %s bitstream... ", name); + if (err) + printf("failed\n"); + else + printf("OK\n"); + break; + default: + printf("The given image format is not supported (corrupt?)\n"); + return 1; + } + + return 0; +} +#endif + int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, const ulong *ld_start, ulong * const ld_len) { diff --git a/include/bootstage.h b/include/bootstage.h index 9765360..0880a68 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -198,6 +198,7 @@ enum bootstage_id { BOOTSTAGE_ID_ACCUM_SCSI, BOOTSTAGE_ID_ACCUM_SPI, BOOTSTAGE_ID_ACCUM_DECOMP, + BOOTSTAGE_ID_FPGA_INIT, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, diff --git a/include/image.h b/include/image.h index e2a90ca..a8f6bd1 100644 --- a/include/image.h +++ b/include/image.h @@ -496,6 +496,8 @@ int genimg_get_format(const void *img_addr); int genimg_has_config(bootm_headers_t *images); ulong genimg_get_image(ulong img_addr); +int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len); int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, ulong *rd_start, ulong *rd_end); -- cgit v0.10.2 From 7a673f0b0642fc542b464a91957bdd44179296b2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2016 14:37:23 +0200 Subject: phy: Wire return value from phy_config() Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 98986bb..4b6c09f 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -879,9 +879,7 @@ __weak int board_phy_config(struct phy_device *phydev) int phy_config(struct phy_device *phydev) { /* Invoke an optional board-specific helper */ - board_phy_config(phydev); - - return 0; + return board_phy_config(phydev); } int phy_shutdown(struct phy_device *phydev) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 3704ce0..4d9c296 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -352,9 +352,8 @@ static int zynq_phy_init(struct udevice *dev) priv->phydev->supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; priv->phydev->advertising = priv->phydev->supported; - phy_config(priv->phydev); - return 0; + return phy_config(priv->phydev); } static int zynq_gem_init(struct udevice *dev) -- cgit v0.10.2 From 1b008fdb06848c7c84e7c1a4a9b2b76239550555 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 May 2016 14:46:28 +0200 Subject: phy: marvell: Do not reset phy after negotiation The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 64713fb..d2e68d4 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -352,11 +352,7 @@ static int m88e1118_config(struct phy_device *phydev) /* Change Page Number */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); - genphy_config_aneg(phydev); - - phy_reset(phydev); - - return 0; + return genphy_config_aneg(phydev); } static int m88e1118_startup(struct phy_device *phydev) -- cgit v0.10.2 From ad5b5801264e573bfbf17a20b04c546985c5bfc1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 20 May 2016 14:59:33 +0200 Subject: ARM: zynq: Simplify zynq configuration Extending Kconfig for adding new platform is a lot of work for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and remove all dependencies on TARGET_ZYNQ_* options including SPL. As a side-effect it also remove custom init folder for ps7_init_gpl.* files. Folder is chosen based on device-tree file. Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index d396a13..db3c579 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,41 +1,5 @@ if ARCH_ZYNQ -config ZYNQ_CUSTOM_INIT - bool "Use custom ps7_init provided by Xilinx tool" - help - U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants. - If you want to override them with customized ones - or ps7_init code for your board is missing, please say Y here - and add ones into board/xilinx/zynq/custom_hw_platform/ directory. - -choice - prompt "Xilinx Zynq board select" - default TARGET_ZYNQ_ZC702 - -config TARGET_ZYNQ_ZED - bool "Zynq ZedBoard" - -config TARGET_ZYNQ_MICROZED - bool "Zynq MicroZed" - -config TARGET_ZYNQ_PICOZED - bool "Zynq PicoZed" - -config TARGET_ZYNQ_ZC702 - bool "Zynq ZC702 Board" - -config TARGET_ZYNQ_ZC706 - bool "Zynq ZC706 Board" - -config TARGET_ZYNQ_ZC770 - bool "Zynq ZC770 Board" - select ZYNQ_CUSTOM_INIT - -config TARGET_ZYNQ_ZYBO - bool "Zynq Zybo Board" - -endchoice - config SYS_BOARD default "zynq" @@ -46,11 +10,11 @@ config SYS_SOC default "zynq" config SYS_CONFIG_NAME - default "zynq_zed" if TARGET_ZYNQ_ZED - default "zynq_microzed" if TARGET_ZYNQ_MICROZED - default "zynq_picozed" if TARGET_ZYNQ_PICOZED - default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 - default "zynq_zc770" if TARGET_ZYNQ_ZC770 - default "zynq_zybo" if TARGET_ZYNQ_ZYBO + string "Board configuration name" + default "zynq-common" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. endif diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index eab9303..7de0212 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -7,17 +7,7 @@ obj-y := board.o -# Copied from Xilinx SDK 2014.4 -hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform -hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform -# If you want to use customized ps7_init_gpl.c/h, -# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/. -# This line must be placed at the bottom of the list because -# it takes precedence over the default ones. -hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT) := custom_hw_platform +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\ $(hw-platform-y)/ps7_init_gpl.o) diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c deleted file mode 100644 index eb29002..0000000 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c +++ /dev/null @@ -1,12963 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000170[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000180[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x1e - // .. ==> 0XF8000190[13:8] = 0x0000001EU - // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xb0 - // .. .. ==> 0XF800612C[19:10] = 0x000000B0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xb1 - // .. .. ==> 0XF8006130[19:10] = 0x000000B1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006134[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xbc - // .. .. ==> 0XF8006134[19:10] = 0x000000BCU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006138[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xbb - // .. .. ==> 0XF8006138[19:10] = 0x000000BBU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 - // .. .. ==> 0XF8006154[9:0] = 0x00000077U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 - // .. .. ==> 0XF8006158[9:0] = 0x00000077U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF800615C[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006160[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x105 - // .. .. ==> 0XF8006168[10:0] = 0x00000105U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x106 - // .. .. ==> 0XF800616C[10:0] = 0x00000106U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x111 - // .. .. ==> 0XF8006170[10:0] = 0x00000111U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x110 - // .. .. ==> 0XF8006174[10:0] = 0x00000110U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), - // .. .. reg_phy_wr_data_slave_ratio = 0xb7 - // .. .. ==> 0XF800617C[9:0] = 0x000000B7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xb7 - // .. .. ==> 0XF8006180[9:0] = 0x000000B7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006184[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006188[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800073C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 50 - // .. ==> 0XF8000830[5:0] = 0x00000032U - // .. ==> MASK : 0x0000003FU VAL : 0x00000032U - // .. SDIO0_CD_SEL = 46 - // .. ==> 0XF8000830[21:16] = 0x0000002EU - // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000170[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000180[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x1e - // .. ==> 0XF8000190[13:8] = 0x0000001EU - // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xb0 - // .. .. ==> 0XF800612C[19:10] = 0x000000B0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xb1 - // .. .. ==> 0XF8006130[19:10] = 0x000000B1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006134[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xbc - // .. .. ==> 0XF8006134[19:10] = 0x000000BCU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006138[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xbb - // .. .. ==> 0XF8006138[19:10] = 0x000000BBU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 - // .. .. ==> 0XF8006154[9:0] = 0x00000077U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 - // .. .. ==> 0XF8006158[9:0] = 0x00000077U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF800615C[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006160[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x105 - // .. .. ==> 0XF8006168[10:0] = 0x00000105U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x106 - // .. .. ==> 0XF800616C[10:0] = 0x00000106U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x111 - // .. .. ==> 0XF8006170[10:0] = 0x00000111U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x110 - // .. .. ==> 0XF8006174[10:0] = 0x00000110U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), - // .. .. reg_phy_wr_data_slave_ratio = 0xb7 - // .. .. ==> 0XF800617C[9:0] = 0x000000B7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xb7 - // .. .. ==> 0XF8006180[9:0] = 0x000000B7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006184[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006188[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800073C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 50 - // .. ==> 0XF8000830[5:0] = 0x00000032U - // .. ==> MASK : 0x0000003FU VAL : 0x00000032U - // .. SDIO0_CD_SEL = 46 - // .. ==> 0XF8000830[21:16] = 0x0000002EU - // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000170[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000180[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x1e - // .. ==> 0XF8000190[13:8] = 0x0000001EU - // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xb0 - // .. .. ==> 0XF800612C[19:10] = 0x000000B0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xb1 - // .. .. ==> 0XF8006130[19:10] = 0x000000B1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006134[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xbc - // .. .. ==> 0XF8006134[19:10] = 0x000000BCU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006138[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xbb - // .. .. ==> 0XF8006138[19:10] = 0x000000BBU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 - // .. .. ==> 0XF8006154[9:0] = 0x00000077U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 - // .. .. ==> 0XF8006158[9:0] = 0x00000077U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF800615C[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006160[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x105 - // .. .. ==> 0XF8006168[10:0] = 0x00000105U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x106 - // .. .. ==> 0XF800616C[10:0] = 0x00000106U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x111 - // .. .. ==> 0XF8006170[10:0] = 0x00000111U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x110 - // .. .. ==> 0XF8006174[10:0] = 0x00000110U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), - // .. .. reg_phy_wr_data_slave_ratio = 0xb7 - // .. .. ==> 0XF800617C[9:0] = 0x000000B7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xb7 - // .. .. ==> 0XF8006180[9:0] = 0x000000B7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006184[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006188[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800073C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 50 - // .. ==> 0XF8000830[5:0] = 0x00000032U - // .. ==> MASK : 0x0000003FU VAL : 0x00000032U - // .. SDIO0_CD_SEL = 46 - // .. ==> 0XF8000830[21:16] = 0x0000002EU - // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h deleted file mode 100644 index bdea5a0..0000000 --- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h +++ /dev/null @@ -1,117 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 100000000 -#define FPGA2_FREQ 33333336 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c deleted file mode 100644 index abfd911..0000000 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c +++ /dev/null @@ -1,13296 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x5 - // .. ==> 0XF8000140[25:20] = 0x00000005U - // .. ==> MASK : 0x03F00000U VAL : 0x00500000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF800015C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF800015C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF800015C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xe - // .. ==> 0XF800015C[13:8] = 0x0000000EU - // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF800015C[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), - // .. CAN0_MUX = 0x0 - // .. ==> 0XF8000160[5:0] = 0x00000000U - // .. ==> MASK : 0x0000003FU VAL : 0x00000000U - // .. CAN0_REF_SEL = 0x0 - // .. ==> 0XF8000160[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. CAN1_MUX = 0x0 - // .. ==> 0XF8000160[21:16] = 0x00000000U - // .. ==> MASK : 0x003F0000U VAL : 0x00000000U - // .. CAN1_REF_SEL = 0x0 - // .. ==> 0XF8000160[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000170[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000180[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[16:16] = 0x00000001U - // .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x10 - // .. .. ==> 0XF8006018[15:10] = 0x00000010U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x4 - // .. .. ==> 0XF8006020[7:5] = 0x00000004U - // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x1d - // .. .. ==> 0XF800612C[9:0] = 0x0000001DU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU - // .. .. reg_phy_gatelvl_init_ratio = 0xf2 - // .. .. ==> 0XF800612C[19:10] = 0x000000F2U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), - // .. .. reg_phy_wrlvl_init_ratio = 0x12 - // .. .. ==> 0XF8006130[9:0] = 0x00000012U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U - // .. .. reg_phy_gatelvl_init_ratio = 0xd8 - // .. .. ==> 0XF8006130[19:10] = 0x000000D8U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), - // .. .. reg_phy_wrlvl_init_ratio = 0xc - // .. .. ==> 0XF8006134[9:0] = 0x0000000CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU - // .. .. reg_phy_gatelvl_init_ratio = 0xde - // .. .. ==> 0XF8006134[19:10] = 0x000000DEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), - // .. .. reg_phy_wrlvl_init_ratio = 0x21 - // .. .. ==> 0XF8006138[9:0] = 0x00000021U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF8006138[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d - // .. .. ==> 0XF8006154[9:0] = 0x0000009DU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 - // .. .. ==> 0XF8006158[9:0] = 0x00000092U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c - // .. .. ==> 0XF800615C[9:0] = 0x0000008CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 - // .. .. ==> 0XF8006160[9:0] = 0x000000A1U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x147 - // .. .. ==> 0XF8006168[10:0] = 0x00000147U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x12d - // .. .. ==> 0XF800616C[10:0] = 0x0000012DU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), - // .. .. reg_phy_fifo_we_slave_ratio = 0x133 - // .. .. ==> 0XF8006170[10:0] = 0x00000133U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x143 - // .. .. ==> 0XF8006174[10:0] = 0x00000143U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), - // .. .. reg_phy_wr_data_slave_ratio = 0xdd - // .. .. ==> 0XF800617C[9:0] = 0x000000DDU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), - // .. .. reg_phy_wr_data_slave_ratio = 0xd2 - // .. .. ==> 0XF8006180[9:0] = 0x000000D2U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), - // .. .. reg_phy_wr_data_slave_ratio = 0xcc - // .. .. ==> 0XF8006184[9:0] = 0x000000CCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xe1 - // .. .. ==> 0XF8006188[9:0] = 0x000000E1U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. VREF_EN = 0x1 - // .. ==> 0XF8000B00[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x0 - // .. ==> 0XF8000B00[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000700[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000700[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000700[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000704[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000704[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000708[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800070C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000710[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000714[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000718[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800071C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000720[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000724[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000724[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000728[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000728[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800072C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800072C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000730[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000730[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000734[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000734[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000738[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000738[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800073C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800073C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800073C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000740[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000740[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000744[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000744[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000748[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000748[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800074C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF800074C[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000750[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000750[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000754[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000754[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000758[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800075C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000760[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000764[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000768[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800076C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 1 - // .. ==> 0XF80007B8[7:5] = 0x00000001U - // .. ==> MASK : 0x000000E0U VAL : 0x00000020U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007B8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 1 - // .. ==> 0XF80007BC[7:5] = 0x00000001U - // .. ==> MASK : 0x000000E0U VAL : 0x00000020U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007BC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007C8[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007C8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007CC[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007CC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 15 - // .. ==> 0XF8000830[5:0] = 0x0000000FU - // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU - // .. SDIO0_CD_SEL = 0 - // .. ==> 0XF8000830[21:16] = 0x00000000U - // .. ==> MASK : 0x003F0000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x800 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x800 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x800 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x800 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. DIRECTION_0 = 0x2000 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. OP_ENABLE_0 = 0x2000 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x5 - // .. ==> 0XF8000140[25:20] = 0x00000005U - // .. ==> MASK : 0x03F00000U VAL : 0x00500000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF800015C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF800015C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF800015C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xe - // .. ==> 0XF800015C[13:8] = 0x0000000EU - // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF800015C[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), - // .. CAN0_MUX = 0x0 - // .. ==> 0XF8000160[5:0] = 0x00000000U - // .. ==> MASK : 0x0000003FU VAL : 0x00000000U - // .. CAN0_REF_SEL = 0x0 - // .. ==> 0XF8000160[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. CAN1_MUX = 0x0 - // .. ==> 0XF8000160[21:16] = 0x00000000U - // .. ==> MASK : 0x003F0000U VAL : 0x00000000U - // .. CAN1_REF_SEL = 0x0 - // .. ==> 0XF8000160[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000170[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000180[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[16:16] = 0x00000001U - // .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x10 - // .. .. ==> 0XF8006018[15:10] = 0x00000010U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x4 - // .. .. ==> 0XF8006020[7:5] = 0x00000004U - // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x1d - // .. .. ==> 0XF800612C[9:0] = 0x0000001DU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU - // .. .. reg_phy_gatelvl_init_ratio = 0xf2 - // .. .. ==> 0XF800612C[19:10] = 0x000000F2U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), - // .. .. reg_phy_wrlvl_init_ratio = 0x12 - // .. .. ==> 0XF8006130[9:0] = 0x00000012U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U - // .. .. reg_phy_gatelvl_init_ratio = 0xd8 - // .. .. ==> 0XF8006130[19:10] = 0x000000D8U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), - // .. .. reg_phy_wrlvl_init_ratio = 0xc - // .. .. ==> 0XF8006134[9:0] = 0x0000000CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU - // .. .. reg_phy_gatelvl_init_ratio = 0xde - // .. .. ==> 0XF8006134[19:10] = 0x000000DEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), - // .. .. reg_phy_wrlvl_init_ratio = 0x21 - // .. .. ==> 0XF8006138[9:0] = 0x00000021U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF8006138[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d - // .. .. ==> 0XF8006154[9:0] = 0x0000009DU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 - // .. .. ==> 0XF8006158[9:0] = 0x00000092U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c - // .. .. ==> 0XF800615C[9:0] = 0x0000008CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 - // .. .. ==> 0XF8006160[9:0] = 0x000000A1U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x147 - // .. .. ==> 0XF8006168[10:0] = 0x00000147U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x12d - // .. .. ==> 0XF800616C[10:0] = 0x0000012DU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), - // .. .. reg_phy_fifo_we_slave_ratio = 0x133 - // .. .. ==> 0XF8006170[10:0] = 0x00000133U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x143 - // .. .. ==> 0XF8006174[10:0] = 0x00000143U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), - // .. .. reg_phy_wr_data_slave_ratio = 0xdd - // .. .. ==> 0XF800617C[9:0] = 0x000000DDU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), - // .. .. reg_phy_wr_data_slave_ratio = 0xd2 - // .. .. ==> 0XF8006180[9:0] = 0x000000D2U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), - // .. .. reg_phy_wr_data_slave_ratio = 0xcc - // .. .. ==> 0XF8006184[9:0] = 0x000000CCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xe1 - // .. .. ==> 0XF8006188[9:0] = 0x000000E1U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. VREF_EN = 0x1 - // .. ==> 0XF8000B00[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. CLK_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. SRSTN_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000700[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000700[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000700[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000704[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000704[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000708[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800070C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000710[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000714[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000718[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800071C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000720[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000724[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000724[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000728[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000728[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800072C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800072C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000730[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000730[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000734[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000734[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000738[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000738[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800073C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800073C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800073C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000740[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000740[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000744[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000744[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000748[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000748[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800074C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF800074C[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000750[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000750[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000754[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000754[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000758[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800075C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000760[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000764[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000768[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800076C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 1 - // .. ==> 0XF80007B8[7:5] = 0x00000001U - // .. ==> MASK : 0x000000E0U VAL : 0x00000020U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007B8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 1 - // .. ==> 0XF80007BC[7:5] = 0x00000001U - // .. ==> MASK : 0x000000E0U VAL : 0x00000020U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007BC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007C8[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007C8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007CC[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007CC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 15 - // .. ==> 0XF8000830[5:0] = 0x0000000FU - // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU - // .. SDIO0_CD_SEL = 0 - // .. ==> 0XF8000830[21:16] = 0x00000000U - // .. ==> MASK : 0x003F0000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x800 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x800 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x800 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x800 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. DIRECTION_0 = 0x2000 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. OP_ENABLE_0 = 0x2000 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x5 - // .. ==> 0XF8000140[25:20] = 0x00000005U - // .. ==> MASK : 0x03F00000U VAL : 0x00500000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF800015C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF800015C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF800015C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xe - // .. ==> 0XF800015C[13:8] = 0x0000000EU - // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF800015C[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), - // .. CAN0_MUX = 0x0 - // .. ==> 0XF8000160[5:0] = 0x00000000U - // .. ==> MASK : 0x0000003FU VAL : 0x00000000U - // .. CAN0_REF_SEL = 0x0 - // .. ==> 0XF8000160[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. CAN1_MUX = 0x0 - // .. ==> 0XF8000160[21:16] = 0x00000000U - // .. ==> MASK : 0x003F0000U VAL : 0x00000000U - // .. CAN1_REF_SEL = 0x0 - // .. ==> 0XF8000160[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000170[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000180[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[16:16] = 0x00000001U - // .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x10 - // .. .. ==> 0XF8006018[15:10] = 0x00000010U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x4 - // .. .. ==> 0XF8006020[7:5] = 0x00000004U - // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x1d - // .. .. ==> 0XF800612C[9:0] = 0x0000001DU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU - // .. .. reg_phy_gatelvl_init_ratio = 0xf2 - // .. .. ==> 0XF800612C[19:10] = 0x000000F2U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), - // .. .. reg_phy_wrlvl_init_ratio = 0x12 - // .. .. ==> 0XF8006130[9:0] = 0x00000012U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U - // .. .. reg_phy_gatelvl_init_ratio = 0xd8 - // .. .. ==> 0XF8006130[19:10] = 0x000000D8U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), - // .. .. reg_phy_wrlvl_init_ratio = 0xc - // .. .. ==> 0XF8006134[9:0] = 0x0000000CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU - // .. .. reg_phy_gatelvl_init_ratio = 0xde - // .. .. ==> 0XF8006134[19:10] = 0x000000DEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), - // .. .. reg_phy_wrlvl_init_ratio = 0x21 - // .. .. ==> 0XF8006138[9:0] = 0x00000021U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF8006138[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d - // .. .. ==> 0XF8006154[9:0] = 0x0000009DU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 - // .. .. ==> 0XF8006158[9:0] = 0x00000092U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c - // .. .. ==> 0XF800615C[9:0] = 0x0000008CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 - // .. .. ==> 0XF8006160[9:0] = 0x000000A1U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x147 - // .. .. ==> 0XF8006168[10:0] = 0x00000147U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x12d - // .. .. ==> 0XF800616C[10:0] = 0x0000012DU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), - // .. .. reg_phy_fifo_we_slave_ratio = 0x133 - // .. .. ==> 0XF8006170[10:0] = 0x00000133U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x143 - // .. .. ==> 0XF8006174[10:0] = 0x00000143U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), - // .. .. reg_phy_wr_data_slave_ratio = 0xdd - // .. .. ==> 0XF800617C[9:0] = 0x000000DDU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), - // .. .. reg_phy_wr_data_slave_ratio = 0xd2 - // .. .. ==> 0XF8006180[9:0] = 0x000000D2U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), - // .. .. reg_phy_wr_data_slave_ratio = 0xcc - // .. .. ==> 0XF8006184[9:0] = 0x000000CCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xe1 - // .. .. ==> 0XF8006188[9:0] = 0x000000E1U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. VREF_EN = 0x1 - // .. ==> 0XF8000B00[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. CLK_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. SRSTN_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000700[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000700[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000700[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000704[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000704[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000708[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800070C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000710[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000714[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000718[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800071C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000720[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000724[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000724[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000728[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000728[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800072C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800072C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000730[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000730[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000734[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000734[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000738[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000738[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800073C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800073C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800073C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000740[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000740[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000744[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000744[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000748[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000748[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800074C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF800074C[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000750[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000750[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000754[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000754[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000758[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800075C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000760[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000764[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000768[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800076C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 1 - // .. ==> 0XF80007B8[7:5] = 0x00000001U - // .. ==> MASK : 0x000000E0U VAL : 0x00000020U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007B8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 1 - // .. ==> 0XF80007BC[7:5] = 0x00000001U - // .. ==> MASK : 0x000000E0U VAL : 0x00000020U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007BC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007C8[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007C8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007CC[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007CC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 15 - // .. ==> 0XF8000830[5:0] = 0x0000000FU - // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU - // .. SDIO0_CD_SEL = 0 - // .. ==> 0XF8000830[21:16] = 0x00000000U - // .. ==> MASK : 0x003F0000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x800 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x800 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x800 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xf7ff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U - // .. .. .. .. DATA_0_LSW = 0x800 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. DIRECTION_0 = 0x2000 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. OP_ENABLE_0 = 0x2000 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xdfff - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U - // .. .. .. .. DATA_0_LSW = 0x2000 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h deleted file mode 100644 index 16fa810..0000000 --- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h +++ /dev/null @@ -1,117 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 25000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 23809523 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 -#define FPGA1_FREQ 50000000 -#define FPGA2_FREQ 50000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c deleted file mode 100644 index 77fd949..0000000 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c +++ /dev/null @@ -1,13203 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x5 - // .. ==> 0XF8000140[25:20] = 0x00000005U - // .. ==> MASK : 0x03F00000U VAL : 0x00500000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000170[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000180[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x10 - // .. .. ==> 0XF8006018[15:10] = 0x00000010U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x4 - // .. .. ==> 0XF8006020[7:5] = 0x00000004U - // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x1e - // .. .. ==> 0XF800612C[9:0] = 0x0000001EU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF800612C[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), - // .. .. reg_phy_wrlvl_init_ratio = 0x25 - // .. .. ==> 0XF8006130[9:0] = 0x00000025U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U - // .. .. reg_phy_gatelvl_init_ratio = 0x10d - // .. .. ==> 0XF8006130[19:10] = 0x0000010DU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), - // .. .. reg_phy_wrlvl_init_ratio = 0x19 - // .. .. ==> 0XF8006134[9:0] = 0x00000019U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U - // .. .. reg_phy_gatelvl_init_ratio = 0xf3 - // .. .. ==> 0XF8006134[19:10] = 0x000000F3U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), - // .. .. reg_phy_wrlvl_init_ratio = 0x2a - // .. .. ==> 0XF8006138[9:0] = 0x0000002AU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU - // .. .. reg_phy_gatelvl_init_ratio = 0x109 - // .. .. ==> 0XF8006138[19:10] = 0x00000109U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e - // .. .. ==> 0XF8006154[9:0] = 0x0000009EU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5 - // .. .. ==> 0XF8006158[9:0] = 0x000000A5U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x99 - // .. .. ==> 0XF800615C[9:0] = 0x00000099U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa - // .. .. ==> 0XF8006160[9:0] = 0x000000AAU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU), - // .. .. reg_phy_fifo_we_slave_ratio = 0x143 - // .. .. ==> 0XF8006168[10:0] = 0x00000143U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x162 - // .. .. ==> 0XF800616C[10:0] = 0x00000162U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x148 - // .. .. ==> 0XF8006170[10:0] = 0x00000148U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x15e - // .. .. ==> 0XF8006174[10:0] = 0x0000015EU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU), - // .. .. reg_phy_wr_data_slave_ratio = 0xde - // .. .. ==> 0XF800617C[9:0] = 0x000000DEU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU), - // .. .. reg_phy_wr_data_slave_ratio = 0xe5 - // .. .. ==> 0XF8006180[9:0] = 0x000000E5U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U), - // .. .. reg_phy_wr_data_slave_ratio = 0xd9 - // .. .. ==> 0XF8006184[9:0] = 0x000000D9U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U), - // .. .. reg_phy_wr_data_slave_ratio = 0xea - // .. .. ==> 0XF8006188[9:0] = 0x000000EAU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. VREF_EN = 0x1 - // .. ==> 0XF8000B00[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x0 - // .. ==> 0XF8000B00[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000700[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000700[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000700[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000704[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000704[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000708[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800070C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000710[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000714[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000718[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800071C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000720[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000724[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000724[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000724[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000728[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000728[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000728[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800072C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800072C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800072C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000730[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000730[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000730[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000734[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000734[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000734[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000738[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000738[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000738[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800073C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800073C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800073C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000740[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000740[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000744[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000744[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000748[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000748[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800074C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF800074C[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000750[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000750[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000754[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000754[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000758[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800075C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000760[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000764[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000768[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800076C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007B8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007BC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007C8[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007C8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007CC[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007CC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 15 - // .. ==> 0XF8000830[5:0] = 0x0000000FU - // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU - // .. SDIO0_CD_SEL = 14 - // .. ==> 0XF8000830[21:16] = 0x0000000EU - // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. DIRECTION_1 = 0x8000 - // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. OP_ENABLE_1 = 0x8000 - // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x0 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. DIRECTION_1 = 0x4000 - // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. OP_ENABLE_1 = 0x4000 - // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x0 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x5 - // .. ==> 0XF8000140[25:20] = 0x00000005U - // .. ==> MASK : 0x03F00000U VAL : 0x00500000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000170[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000180[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x10 - // .. .. ==> 0XF8006018[15:10] = 0x00000010U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x4 - // .. .. ==> 0XF8006020[7:5] = 0x00000004U - // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x1e - // .. .. ==> 0XF800612C[9:0] = 0x0000001EU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF800612C[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), - // .. .. reg_phy_wrlvl_init_ratio = 0x25 - // .. .. ==> 0XF8006130[9:0] = 0x00000025U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U - // .. .. reg_phy_gatelvl_init_ratio = 0x10d - // .. .. ==> 0XF8006130[19:10] = 0x0000010DU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), - // .. .. reg_phy_wrlvl_init_ratio = 0x19 - // .. .. ==> 0XF8006134[9:0] = 0x00000019U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U - // .. .. reg_phy_gatelvl_init_ratio = 0xf3 - // .. .. ==> 0XF8006134[19:10] = 0x000000F3U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), - // .. .. reg_phy_wrlvl_init_ratio = 0x2a - // .. .. ==> 0XF8006138[9:0] = 0x0000002AU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU - // .. .. reg_phy_gatelvl_init_ratio = 0x109 - // .. .. ==> 0XF8006138[19:10] = 0x00000109U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e - // .. .. ==> 0XF8006154[9:0] = 0x0000009EU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5 - // .. .. ==> 0XF8006158[9:0] = 0x000000A5U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x99 - // .. .. ==> 0XF800615C[9:0] = 0x00000099U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa - // .. .. ==> 0XF8006160[9:0] = 0x000000AAU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU), - // .. .. reg_phy_fifo_we_slave_ratio = 0x143 - // .. .. ==> 0XF8006168[10:0] = 0x00000143U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x162 - // .. .. ==> 0XF800616C[10:0] = 0x00000162U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x148 - // .. .. ==> 0XF8006170[10:0] = 0x00000148U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x15e - // .. .. ==> 0XF8006174[10:0] = 0x0000015EU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU), - // .. .. reg_phy_wr_data_slave_ratio = 0xde - // .. .. ==> 0XF800617C[9:0] = 0x000000DEU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU), - // .. .. reg_phy_wr_data_slave_ratio = 0xe5 - // .. .. ==> 0XF8006180[9:0] = 0x000000E5U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U), - // .. .. reg_phy_wr_data_slave_ratio = 0xd9 - // .. .. ==> 0XF8006184[9:0] = 0x000000D9U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U), - // .. .. reg_phy_wr_data_slave_ratio = 0xea - // .. .. ==> 0XF8006188[9:0] = 0x000000EAU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. VREF_EN = 0x1 - // .. ==> 0XF8000B00[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. CLK_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. SRSTN_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000700[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000700[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000700[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000704[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000704[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000708[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800070C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000710[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000714[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000718[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800071C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000720[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000724[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000724[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000724[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000728[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000728[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000728[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800072C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800072C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800072C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000730[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000730[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000730[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000734[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000734[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000734[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000738[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000738[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000738[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800073C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800073C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800073C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000740[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000740[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000744[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000744[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000748[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000748[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800074C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF800074C[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000750[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000750[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000754[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000754[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000758[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800075C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000760[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000764[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000768[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800076C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007B8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007BC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007C8[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007C8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007CC[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007CC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 15 - // .. ==> 0XF8000830[5:0] = 0x0000000FU - // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU - // .. SDIO0_CD_SEL = 14 - // .. ==> 0XF8000830[21:16] = 0x0000000EU - // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. DIRECTION_1 = 0x8000 - // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. OP_ENABLE_1 = 0x8000 - // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x0 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. DIRECTION_1 = 0x4000 - // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. OP_ENABLE_1 = 0x4000 - // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x0 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x5 - // .. ==> 0XF8000140[25:20] = 0x00000005U - // .. ==> MASK : 0x03F00000U VAL : 0x00500000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000170[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000180[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x10 - // .. .. ==> 0XF8006018[15:10] = 0x00000010U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x4 - // .. .. ==> 0XF8006020[7:5] = 0x00000004U - // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x1e - // .. .. ==> 0XF800612C[9:0] = 0x0000001EU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU - // .. .. reg_phy_gatelvl_init_ratio = 0xee - // .. .. ==> 0XF800612C[19:10] = 0x000000EEU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), - // .. .. reg_phy_wrlvl_init_ratio = 0x25 - // .. .. ==> 0XF8006130[9:0] = 0x00000025U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U - // .. .. reg_phy_gatelvl_init_ratio = 0x10d - // .. .. ==> 0XF8006130[19:10] = 0x0000010DU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), - // .. .. reg_phy_wrlvl_init_ratio = 0x19 - // .. .. ==> 0XF8006134[9:0] = 0x00000019U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U - // .. .. reg_phy_gatelvl_init_ratio = 0xf3 - // .. .. ==> 0XF8006134[19:10] = 0x000000F3U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), - // .. .. reg_phy_wrlvl_init_ratio = 0x2a - // .. .. ==> 0XF8006138[9:0] = 0x0000002AU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU - // .. .. reg_phy_gatelvl_init_ratio = 0x109 - // .. .. ==> 0XF8006138[19:10] = 0x00000109U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e - // .. .. ==> 0XF8006154[9:0] = 0x0000009EU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5 - // .. .. ==> 0XF8006158[9:0] = 0x000000A5U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x99 - // .. .. ==> 0XF800615C[9:0] = 0x00000099U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa - // .. .. ==> 0XF8006160[9:0] = 0x000000AAU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU), - // .. .. reg_phy_fifo_we_slave_ratio = 0x143 - // .. .. ==> 0XF8006168[10:0] = 0x00000143U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x162 - // .. .. ==> 0XF800616C[10:0] = 0x00000162U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x148 - // .. .. ==> 0XF8006170[10:0] = 0x00000148U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x15e - // .. .. ==> 0XF8006174[10:0] = 0x0000015EU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU), - // .. .. reg_phy_wr_data_slave_ratio = 0xde - // .. .. ==> 0XF800617C[9:0] = 0x000000DEU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU), - // .. .. reg_phy_wr_data_slave_ratio = 0xe5 - // .. .. ==> 0XF8006180[9:0] = 0x000000E5U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U), - // .. .. reg_phy_wr_data_slave_ratio = 0xd9 - // .. .. ==> 0XF8006184[9:0] = 0x000000D9U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U), - // .. .. reg_phy_wr_data_slave_ratio = 0xea - // .. .. ==> 0XF8006188[9:0] = 0x000000EAU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. VREF_EN = 0x1 - // .. ==> 0XF8000B00[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. CLK_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. SRSTN_PULLUP_EN = 0x0 - // .. ==> 0XF8000B00[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000700[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000700[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000700[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000704[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000704[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000708[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800070C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000710[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000714[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000718[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800071C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000720[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000724[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000724[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000724[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000728[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000728[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000728[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800072C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800072C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800072C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000730[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000730[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000730[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000734[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000734[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000734[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000738[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000738[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF8000738[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800073C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800073C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF800073C[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000740[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000740[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000744[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000744[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000748[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000748[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800074C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF800074C[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000750[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000750[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000754[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 1 - // .. ==> 0XF8000754[13:13] = 0x00000001U - // .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000758[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800075C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000760[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000764[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF8000768[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 4 - // .. ==> 0XF800076C[11:9] = 0x00000004U - // .. ==> MASK : 0x00000E00U VAL : 0x00000800U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007B8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007BC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007C8[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007C8[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 2 - // .. ==> 0XF80007CC[7:5] = 0x00000002U - // .. ==> MASK : 0x000000E0U VAL : 0x00000040U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 1 - // .. ==> 0XF80007CC[12:12] = 0x00000001U - // .. ==> MASK : 0x00001000U VAL : 0x00001000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 15 - // .. ==> 0XF8000830[5:0] = 0x0000000FU - // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU - // .. SDIO0_CD_SEL = 14 - // .. ==> 0XF8000830[21:16] = 0x0000000EU - // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. DIRECTION_1 = 0x8000 - // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. OP_ENABLE_1 = 0x8000 - // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x0 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0x7fff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U - // .. .. .. .. DATA_1_LSW = 0x8000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. DIRECTION_1 = 0x4000 - // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. OP_ENABLE_1 = 0x4000 - // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x0 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. MASK_1_LSW = 0xbfff - // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U - // .. .. .. .. DATA_1_LSW = 0x4000 - // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h deleted file mode 100644 index 8527eef..0000000 --- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h +++ /dev/null @@ -1,117 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 25000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 -#define FPGA1_FREQ 50000000 -#define FPGA2_FREQ 50000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/custom_hw_platform/.gitignore b/board/xilinx/zynq/custom_hw_platform/.gitignore deleted file mode 100644 index c455361..0000000 --- a/board/xilinx/zynq/custom_hw_platform/.gitignore +++ /dev/null @@ -1 +0,0 @@ -ps7_init_gpl.[ch] diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c deleted file mode 100644 index f4f45be..0000000 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c +++ /dev/null @@ -1,12861 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000170[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x7 - // .. ==> 0XF8000180[13:8] = 0x00000007U - // .. ==> MASK : 0x00003F00U VAL : 0x00000700U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x18 - // .. .. ==> 0XF8006018[15:10] = 0x00000018U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0xf - // .. .. ==> 0XF8006044[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF800612C[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xcf - // .. .. ==> 0XF800612C[19:10] = 0x000000CFU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006130[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xd0 - // .. .. ==> 0XF8006130[19:10] = 0x000000D0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006134[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xbd - // .. .. ==> 0XF8006134[19:10] = 0x000000BDU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006138[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xc1 - // .. .. ==> 0XF8006138[19:10] = 0x000000C1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006154[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006158[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f - // .. .. ==> 0XF800615C[9:0] = 0x0000007FU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x78 - // .. .. ==> 0XF8006160[9:0] = 0x00000078U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x124 - // .. .. ==> 0XF8006168[10:0] = 0x00000124U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x125 - // .. .. ==> 0XF800616C[10:0] = 0x00000125U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x112 - // .. .. ==> 0XF8006170[10:0] = 0x00000112U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x116 - // .. .. ==> 0XF8006174[10:0] = 0x00000116U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF800617C[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006180[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbf - // .. .. ==> 0XF8006184[9:0] = 0x000000BFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU), - // .. .. reg_phy_wr_data_slave_ratio = 0xb8 - // .. .. ==> 0XF8006188[9:0] = 0x000000B8U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000704[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000708[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800070C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000710[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000714[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000718[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000720[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000720[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800073C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000740[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000744[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000748[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800074C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000750[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000754[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000758[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800075C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000760[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000764[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000768[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800076C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000770[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000774[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000778[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800077C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000780[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000784[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000788[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800078C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000790[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000794[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000798[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800079C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A0[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A4[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A8[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007AC[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007B0[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007B4[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007BC[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007CC[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 46 - // .. ==> 0XF8000830[5:0] = 0x0000002EU - // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU - // .. SDIO0_CD_SEL = 47 - // .. ==> 0XF8000830[21:16] = 0x0000002FU - // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000170[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x7 - // .. ==> 0XF8000180[13:8] = 0x00000007U - // .. ==> MASK : 0x00003F00U VAL : 0x00000700U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x18 - // .. .. ==> 0XF8006018[15:10] = 0x00000018U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0xf - // .. .. ==> 0XF8006044[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF800612C[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xcf - // .. .. ==> 0XF800612C[19:10] = 0x000000CFU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006130[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xd0 - // .. .. ==> 0XF8006130[19:10] = 0x000000D0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006134[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xbd - // .. .. ==> 0XF8006134[19:10] = 0x000000BDU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006138[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xc1 - // .. .. ==> 0XF8006138[19:10] = 0x000000C1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006154[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006158[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f - // .. .. ==> 0XF800615C[9:0] = 0x0000007FU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x78 - // .. .. ==> 0XF8006160[9:0] = 0x00000078U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x124 - // .. .. ==> 0XF8006168[10:0] = 0x00000124U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x125 - // .. .. ==> 0XF800616C[10:0] = 0x00000125U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x112 - // .. .. ==> 0XF8006170[10:0] = 0x00000112U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x116 - // .. .. ==> 0XF8006174[10:0] = 0x00000116U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF800617C[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006180[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbf - // .. .. ==> 0XF8006184[9:0] = 0x000000BFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU), - // .. .. reg_phy_wr_data_slave_ratio = 0xb8 - // .. .. ==> 0XF8006188[9:0] = 0x000000B8U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x3 - // .. ==> 0XF8000B6C[11:10] = 0x00000003U - // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000704[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000708[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800070C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000710[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000714[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000718[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000720[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000720[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800073C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000740[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000744[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000748[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800074C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000750[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000754[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000758[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800075C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000760[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000764[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000768[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800076C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000770[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000774[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000778[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800077C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000780[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000784[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000788[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800078C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000790[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000794[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000798[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800079C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A0[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A4[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A8[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007AC[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007B0[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007B4[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007BC[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007CC[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 46 - // .. ==> 0XF8000830[5:0] = 0x0000002EU - // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU - // .. SDIO0_CD_SEL = 47 - // .. ==> 0XF8000830[21:16] = 0x0000002FU - // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000110[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x28 - // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x2 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0xc - // .. .. ==> 0XF8000118[7:4] = 0x0000000CU - // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x145 - // .. .. ==> 0XF8000118[21:12] = 0x00000145U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x1e - // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x8 - // .. ==> 0XF8000140[13:8] = 0x00000008U - // .. ==> MASK : 0x00003F00U VAL : 0x00000800U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF800014C[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000150[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000150[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000150[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x14 - // .. ==> 0XF8000154[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000168[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000168[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x5 - // .. ==> 0XF8000168[13:8] = 0x00000005U - // .. ==> MASK : 0x00003F00U VAL : 0x00000500U - // .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000170[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0xa - // .. ==> 0XF8000170[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000170[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000180[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x7 - // .. ==> 0XF8000180[13:8] = 0x00000007U - // .. ==> MASK : 0x00003F00U VAL : 0x00000700U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000180[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), - // .. SRCSEL = 0x0 - // .. ==> 0XF8000190[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF8000190[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000190[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), - // .. SRCSEL = 0x0 - // .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR0 = 0x14 - // .. ==> 0XF80001A0[13:8] = 0x00000014U - // .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), - // .. CLK_621_TRUE = 0x1 - // .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. DMA_CPU_2XCLKACT = 0x1 - // .. ==> 0XF800012C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. USB0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USB1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. GEM0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[6:6] = 0x00000001U - // .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. GEM1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. SDI0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[10:10] = 0x00000001U - // .. ==> MASK : 0x00000400U VAL : 0x00000400U - // .. SDI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. SPI0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. SPI1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[15:15] = 0x00000000U - // .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. CAN0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. CAN1_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. I2C0_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[18:18] = 0x00000001U - // .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. I2C1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. UART0_CPU_1XCLKACT = 0x0 - // .. ==> 0XF800012C[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. UART1_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[21:21] = 0x00000001U - // .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. GPIO_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[22:22] = 0x00000001U - // .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. LQSPI_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[23:23] = 0x00000001U - // .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. SMC_CPU_1XCLKACT = 0x1 - // .. ==> 0XF800012C[24:24] = 0x00000001U - // .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1b - // .. .. ==> 0XF8006014[5:0] = 0x0000001BU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU - // .. .. reg_ddrc_t_rfc_min = 0x56 - // .. .. ==> 0XF8006014[13:6] = 0x00000056U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x18 - // .. .. ==> 0XF8006018[15:10] = 0x00000018U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x14 - // .. .. ==> 0XF8006018[26:22] = 0x00000014U - // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0xf - // .. .. ==> 0XF8006044[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF800612C[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xcf - // .. .. ==> 0XF800612C[19:10] = 0x000000CFU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U), - // .. .. reg_phy_wrlvl_init_ratio = 0x3 - // .. .. ==> 0XF8006130[9:0] = 0x00000003U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U - // .. .. reg_phy_gatelvl_init_ratio = 0xd0 - // .. .. ==> 0XF8006130[19:10] = 0x000000D0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006134[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xbd - // .. .. ==> 0XF8006134[19:10] = 0x000000BDU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006138[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xc1 - // .. .. ==> 0XF8006138[19:10] = 0x000000C1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006154[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 - // .. .. ==> 0XF8006158[9:0] = 0x00000083U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f - // .. .. ==> 0XF800615C[9:0] = 0x0000007FU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x78 - // .. .. ==> 0XF8006160[9:0] = 0x00000078U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x124 - // .. .. ==> 0XF8006168[10:0] = 0x00000124U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x125 - // .. .. ==> 0XF800616C[10:0] = 0x00000125U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x112 - // .. .. ==> 0XF8006170[10:0] = 0x00000112U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x116 - // .. .. ==> 0XF8006174[10:0] = 0x00000116U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF800617C[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc3 - // .. .. ==> 0XF8006180[9:0] = 0x000000C3U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbf - // .. .. ==> 0XF8006184[9:0] = 0x000000BFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU), - // .. .. reg_phy_wr_data_slave_ratio = 0xb8 - // .. .. ==> 0XF8006188[9:0] = 0x000000B8U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000704[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000708[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800070C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000710[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000714[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000718[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000720[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000720[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000728[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800072C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000730[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000734[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000738[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800073C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000740[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000744[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000748[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800074C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000750[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000754[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000758[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800075C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000760[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000764[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000768[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800076C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000770[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000774[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000778[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800077C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000780[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000784[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000788[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800078C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000790[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000794[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF8000798[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 1 - // .. ==> 0XF800079C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A0[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A4[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007A8[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007A8[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007AC[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007AC[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007B0[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007B4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 1 - // .. ==> 0XF80007B4[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007B8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007BC[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C8[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007CC[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO0_WP_SEL = 46 - // .. ==> 0XF8000830[5:0] = 0x0000002EU - // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU - // .. SDIO0_CD_SEL = 47 - // .. ==> 0XF8000830[21:16] = 0x0000002FU - // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U - // .. - EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h deleted file mode 100644 index 9b41e28..0000000 --- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h +++ /dev/null @@ -1,117 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 142857132 -#define FPGA2_FREQ 50000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c deleted file mode 100644 index 83daf7b..0000000 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c +++ /dev/null @@ -1,13045 +0,0 @@ -/* - * Copyright (c) Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: PLL SLCR REGISTERS */ - /* .. .. START: ARM PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x177 */ - /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x1a */ - /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. ARM_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. .. SRCSEL = 0x0 */ - /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. .. DIVISOR = 0x2 */ - /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ - /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ - /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ - /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ - /* .. .. .. CPU_2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ - /* .. .. .. CPU_1XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ - /* .. .. .. CPU_PERI_CLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), - /* .. .. FINISH: ARM PLL INIT */ - /* .. .. START: DDR PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x1db */ - /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x15 */ - /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. DDR_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. .. DDR_3XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. DDR_2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ - /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ - /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ - /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ - /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), - /* .. .. FINISH: DDR PLL INIT */ - /* .. .. START: IO PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x1f4 */ - /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x14 */ - /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. IO_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. FINISH: IO PLL INIT */ - /* .. FINISH: PLL SLCR REGISTERS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_clock_init_data_3_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: CLOCK CONTROL SLCR REGISTERS */ - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000128[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. DIVISOR0 = 0x34 */ - /* .. ==> 0XF8000128[13:8] = 0x00000034U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ - /* .. DIVISOR1 = 0x2 */ - /* .. ==> 0XF8000128[25:20] = 0x00000002U */ - /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000138[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000138[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000140[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000140[6:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. DIVISOR = 0x8 */ - /* .. ==> 0XF8000140[13:8] = 0x00000008U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ - /* .. DIVISOR1 = 0x1 */ - /* .. ==> 0XF8000140[25:20] = 0x00000001U */ - /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF800014C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF800014C[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x5 */ - /* .. ==> 0XF800014C[13:8] = 0x00000005U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. */ - EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), - /* .. CLKACT0 = 0x1 */ - /* .. ==> 0XF8000150[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. CLKACT1 = 0x0 */ - /* .. ==> 0XF8000150[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000150[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000150[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ - /* .. */ - EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), - /* .. CLKACT0 = 0x0 */ - /* .. ==> 0XF8000154[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. CLKACT1 = 0x1 */ - /* .. ==> 0XF8000154[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000154[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0xa */ - /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ - /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), - /* .. .. START: TRACE CLOCK */ - /* .. .. FINISH: TRACE CLOCK */ - /* .. .. CLKACT = 0x1 */ - /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR = 0x5 */ - /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x7 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x5 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x14 */ - /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), - /* .. .. CLK_621_TRUE = 0x1 */ - /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), - /* .. .. DMA_CPU_2XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. USB0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. .. USB1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ - /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ - /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ - /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. UART0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. UART1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ - /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ - /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ - /* .. .. SMC_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), - /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ - /* .. START: THIS SHOULD BE BLANK */ - /* .. FINISH: THIS SHOULD BE BLANK */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - /* START: top */ - /* .. START: DDR INITIALIZATION */ - /* .. .. START: LOCK DDR */ - /* .. .. reg_ddrc_soft_rstb = 0 */ - /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_powerdown_en = 0x0 */ - /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_data_bus_width = 0x0 */ - /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ - /* .. .. reg_ddrc_burst8_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ - /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ - /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), - /* .. .. FINISH: LOCK DDR */ - /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ - /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ - /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */ - /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ - /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ - /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU), - /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ - /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ - /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ - /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ - /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ - /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ - /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ - /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), - /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ - /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ - /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ - /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ - /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ - /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ - /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), - /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ - /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ - /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ - /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ - /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ - /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ - /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), - /* .. .. reg_ddrc_t_rc = 0x1a */ - /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ - /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ - /* .. .. reg_ddrc_t_rfc_min = 0x54 */ - /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ - /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ - /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ - /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ - /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), - /* .. .. reg_ddrc_wr2pre = 0x12 */ - /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ - /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ - /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ - /* .. .. reg_ddrc_t_faw = 0x15 */ - /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ - /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ - /* .. .. reg_ddrc_t_ras_max = 0x23 */ - /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ - /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ - /* .. .. reg_ddrc_t_ras_min = 0x13 */ - /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ - /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ - /* .. .. reg_ddrc_t_cke = 0x4 */ - /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), - /* .. .. reg_ddrc_write_latency = 0x5 */ - /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ - /* .. .. reg_ddrc_rd2wr = 0x7 */ - /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ - /* .. .. reg_ddrc_wr2rd = 0xe */ - /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ - /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ - /* .. .. reg_ddrc_t_xp = 0x4 */ - /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ - /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ - /* .. .. reg_ddrc_pad_pd = 0x0 */ - /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rd2pre = 0x4 */ - /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ - /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ - /* .. .. reg_ddrc_t_rcd = 0x7 */ - /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), - /* .. .. reg_ddrc_t_ccd = 0x4 */ - /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ - /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ - /* .. .. reg_ddrc_t_rrd = 0x6 */ - /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ - /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ - /* .. .. reg_ddrc_refresh_margin = 0x2 */ - /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. reg_ddrc_t_rp = 0x7 */ - /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ - /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ - /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ - /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ - /* .. .. reg_ddrc_mobile = 0x0 */ - /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */ - /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_read_latency = 0x7 */ - /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ - /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ - /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ - /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ - /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ - /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ - /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ - /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U), - /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ - /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_prefer_write = 0x0 */ - /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_wr = 0x0 */ - /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_addr = 0x0 */ - /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_data = 0x0 */ - /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ - /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ - /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_type = 0x0 */ - /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ - /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), - /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ - /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ - /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ - /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ - /* .. .. reg_ddrc_t_mrd = 0x4 */ - /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ - /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), - /* .. .. reg_ddrc_emr2 = 0x8 */ - /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ - /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ - /* .. .. reg_ddrc_emr3 = 0x0 */ - /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), - /* .. .. reg_ddrc_mr = 0x930 */ - /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ - /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ - /* .. .. reg_ddrc_emr = 0x4 */ - /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ - /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), - /* .. .. reg_ddrc_burst_rdwr = 0x4 */ - /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ - /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ - /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ - /* .. .. reg_ddrc_burstchop = 0x0 */ - /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), - /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ - /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_dq = 0x0 */ - /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), - /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ - /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ - /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ - /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ - /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ - /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ - /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ - /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ - /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), - /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ - /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ - /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ - /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ - /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ - /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ - /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ - /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ - /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ - /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ - /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), - /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ - /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ - /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ - /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ - /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ - /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ - /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ - /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ - /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ - /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ - /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ - /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ - /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ - /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), - /* .. .. reg_phy_rd_local_odt = 0x0 */ - /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_local_odt = 0x3 */ - /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ - /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ - /* .. .. reg_phy_idle_local_odt = 0x3 */ - /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ - /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ - /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */ - /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ - /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), - /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ - /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ - /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ - /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ - /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ - /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_phy_use_fixed_re = 0x1 */ - /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ - /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ - /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ - /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_phy_clk_stall_level = 0x0 */ - /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ - /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ - /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ - /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), - /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ - /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), - /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ - /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ - /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ - /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ - /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ - /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ - /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), - /* .. .. reg_ddrc_pageclose = 0x0 */ - /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ - /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ - /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ - /* .. .. reg_ddrc_auto_pre_en = 0x0 */ - /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. reg_ddrc_refresh_update_level = 0x0 */ - /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_wc = 0x0 */ - /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ - /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_ddrc_selfref_en = 0x0 */ - /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), - /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ - /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ - /* .. .. reg_arb_go2critical_en = 0x1 */ - /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), - /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ - /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ - /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ - /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ - /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ - /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ - /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), - /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ - /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ - /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ - /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), - /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ - /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ - /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ - /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ - /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ - /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ - /* .. .. reg_ddrc_t_cksre = 0x6 */ - /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ - /* .. .. reg_ddrc_t_cksrx = 0x6 */ - /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ - /* .. .. reg_ddrc_t_ckesr = 0x4 */ - /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), - /* .. .. reg_ddrc_t_ckpde = 0x2 */ - /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ - /* .. .. reg_ddrc_t_ckpdx = 0x2 */ - /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ - /* .. .. reg_ddrc_t_ckdpde = 0x2 */ - /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ - /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ - /* .. .. reg_ddrc_t_ckcsx = 0x3 */ - /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), - /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ - /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_ddr3 = 0x1 */ - /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. reg_ddrc_t_mod = 0x200 */ - /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ - /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ - /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ - /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ - /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ - /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ - /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), - /* .. .. t_zq_short_interval_x1024 = 0xc845 */ - /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ - /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ - /* .. .. dram_rstn_x1024 = 0x67 */ - /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ - /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), - /* .. .. deeppowerdown_en = 0x0 */ - /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. deeppowerdown_to_x1024 = 0xff */ - /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ - /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), - /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ - /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ - /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ - /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ - /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ - /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ - /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ - /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ - /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ - /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ - /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ - /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ - /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), - /* .. .. reg_ddrc_skip_ocd = 0x1 */ - /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), - /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ - /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ - /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ - /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ - /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ - /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ - /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ - /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), - /* .. .. START: RESET ECC ERROR */ - /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ - /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ - /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), - /* .. .. FINISH: RESET ECC ERROR */ - /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ - /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ - /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), - /* .. .. CORR_ECC_LOG_VALID = 0x0 */ - /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ - /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), - /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ - /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), - /* .. .. STAT_NUM_CORR_ERR = 0x0 */ - /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ - /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ - /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), - /* .. .. reg_ddrc_ecc_mode = 0x0 */ - /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_scrub = 0x1 */ - /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), - /* .. .. reg_phy_dif_on = 0x0 */ - /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_phy_dif_off = 0x0 */ - /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ - /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ - /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ - /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ - /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ - /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ - /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ - /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ - /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ - /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ - /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ - /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ - /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), - /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ - /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), - /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ - /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), - /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ - /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), - /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ - /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), - /* .. .. reg_phy_bl2 = 0x0 */ - /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_at_spd_atpg = 0x0 */ - /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_enable = 0x0 */ - /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_force_err = 0x0 */ - /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_mode = 0x0 */ - /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. .. reg_phy_invert_clkout = 0x1 */ - /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. .. reg_phy_sel_logic = 0x0 */ - /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ - /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ - /* .. .. reg_phy_ctrl_slave_force = 0x0 */ - /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ - /* .. .. reg_phy_lpddr = 0x0 */ - /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ - /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ - /* .. .. reg_phy_cmd_latency = 0x0 */ - /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ - /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), - /* .. .. reg_phy_wr_rl_delay = 0x2 */ - /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ - /* .. .. reg_phy_rd_rl_delay = 0x4 */ - /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ - /* .. .. reg_phy_dll_lock_diff = 0xf */ - /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ - /* .. .. reg_phy_use_wr_level = 0x1 */ - /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ - /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ - /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ - /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ - /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ - /* .. .. reg_phy_dis_calib_rst = 0x0 */ - /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), - /* .. .. reg_arb_page_addr_mask = 0x0 */ - /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_ddrc_lpddr2 = 0x0 */ - /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_derate_enable = 0x0 */ - /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr4_margin = 0x0 */ - /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), - /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ - /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), - /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ - /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ - /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ - /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ - /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ - /* .. .. reg_ddrc_t_mrw = 0x5 */ - /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), - /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ - /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ - /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ - /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ - /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), - /* .. .. START: POLL ON DCI STATUS */ - /* .. .. DONE = 1 */ - /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ - /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. .. */ - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - /* .. .. FINISH: POLL ON DCI STATUS */ - /* .. .. START: UNLOCK DDR */ - /* .. .. reg_ddrc_soft_rstb = 0x1 */ - /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_ddrc_powerdown_en = 0x0 */ - /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_data_bus_width = 0x0 */ - /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ - /* .. .. reg_ddrc_burst8_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ - /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ - /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), - /* .. .. FINISH: UNLOCK DDR */ - /* .. .. START: CHECK DDR STATUS */ - /* .. .. ddrc_reg_operating_mode = 1 */ - /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - /* .. .. FINISH: CHECK DDR STATUS */ - /* .. FINISH: DDR INITIALIZATION */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_mio_init_data_3_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: OCM REMAPPING */ - /* .. VREF_EN = 0x1 */ - /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. VREF_SEL = 0x0 */ - /* .. ==> 0XF8000B00[6:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U), - /* .. FINISH: OCM REMAPPING */ - /* .. START: DDRIOB SETTINGS */ - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCI_TYPE = 0x0 */ - /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCI_TYPE = 0x0 */ - /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x1 */ - /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCI_TYPE = 0x3 */ - /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x1 */ - /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCI_TYPE = 0x3 */ - /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x2 */ - /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCI_TYPE = 0x3 */ - /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x2 */ - /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCI_TYPE = 0x3 */ - /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), - /* .. reserved_INP_POWER = 0x0 */ - /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE_B = 0x0 */ - /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCI_TYPE = 0x0 */ - /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), - /* .. reserved_DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. reserved_DRIVE_N = 0xc */ - /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. reserved_SLEW_P = 0x3 */ - /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ - /* .. reserved_SLEW_N = 0x3 */ - /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ - /* .. reserved_GTL = 0x0 */ - /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. reserved_RTERM = 0x0 */ - /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), - /* .. reserved_DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. reserved_DRIVE_N = 0xc */ - /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. reserved_SLEW_P = 0x6 */ - /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. reserved_SLEW_N = 0x1f */ - /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. reserved_GTL = 0x0 */ - /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. reserved_RTERM = 0x0 */ - /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), - /* .. reserved_DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. reserved_DRIVE_N = 0xc */ - /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. reserved_SLEW_P = 0x6 */ - /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. reserved_SLEW_N = 0x1f */ - /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. reserved_GTL = 0x0 */ - /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. reserved_RTERM = 0x0 */ - /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), - /* .. reserved_DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. reserved_DRIVE_N = 0xc */ - /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. reserved_SLEW_P = 0x6 */ - /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. reserved_SLEW_N = 0x1f */ - /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. reserved_GTL = 0x0 */ - /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. reserved_RTERM = 0x0 */ - /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), - /* .. VREF_INT_EN = 0x0 */ - /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. VREF_SEL = 0x0 */ - /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ - /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ - /* .. VREF_EXT_EN = 0x3 */ - /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. reserved_VREF_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ - /* .. REFIO_EN = 0x1 */ - /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ - /* .. reserved_REFIO_TEST = 0x0 */ - /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ - /* .. reserved_REFIO_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. reserved_DRST_B_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. reserved_CKE_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ - /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), - /* .. .. START: ASSERT RESET */ - /* .. .. RESET = 1 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), - /* .. .. FINISH: ASSERT RESET */ - /* .. .. START: DEASSERT RESET */ - /* .. .. RESET = 0 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reserved_VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), - /* .. .. FINISH: DEASSERT RESET */ - /* .. .. RESET = 0x1 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. ENABLE = 0x1 */ - /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. reserved_VRP_TRI = 0x0 */ - /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reserved_VRN_TRI = 0x0 */ - /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reserved_VRP_OUT = 0x0 */ - /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reserved_VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. NREF_OPT1 = 0x0 */ - /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. .. NREF_OPT2 = 0x0 */ - /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ - /* .. .. NREF_OPT4 = 0x1 */ - /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ - /* .. .. PREF_OPT1 = 0x0 */ - /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ - /* .. .. PREF_OPT2 = 0x0 */ - /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ - /* .. .. UPDATE_CONTROL = 0x0 */ - /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. reserved_INIT_COMPLETE = 0x0 */ - /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. .. reserved_TST_CLK = 0x0 */ - /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. .. reserved_TST_HLN = 0x0 */ - /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. .. reserved_TST_HLP = 0x0 */ - /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. .. reserved_TST_RST = 0x0 */ - /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reserved_INT_DCI_EN = 0x0 */ - /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), - /* .. FINISH: DDRIOB SETTINGS */ - /* .. START: MIO PROGRAMMING */ - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000700[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000700[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000700[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000700[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000700[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000700[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000700[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000700[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000700[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000704[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000704[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000704[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000704[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000704[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000704[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000704[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000704[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000704[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000708[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000708[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000708[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000708[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000708[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000708[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000708[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000708[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000708[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800070C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800070C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800070C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800070C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800070C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800070C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800070C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800070C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800070C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000710[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000710[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000710[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000710[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000710[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000710[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000710[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000710[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000710[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000714[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000714[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000714[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000714[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000714[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000714[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000714[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000714[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000714[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000718[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000718[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000718[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000718[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000718[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000718[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000718[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000718[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000718[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800071C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800071C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800071C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800071C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800071C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800071C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800071C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800071C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800071C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000720[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000720[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000720[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000720[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000720[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000720[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000720[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000720[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000720[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000724[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000724[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000724[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000724[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000724[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000724[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000724[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000724[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000724[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000728[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000728[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000728[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000728[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000728[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000728[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000728[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000728[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000728[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800072C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800072C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800072C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800072C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800072C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800072C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800072C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF800072C[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800072C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000730[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000730[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000730[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000730[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000730[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000730[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000730[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000730[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000730[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000734[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000734[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000734[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000734[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000734[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000734[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000734[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000734[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000734[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000738[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000738[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000738[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000738[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000738[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000738[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000738[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000738[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000738[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800073C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800073C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800073C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800073C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800073C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800073C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800073C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF800073C[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800073C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000740[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000740[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000740[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000740[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000740[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000740[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000740[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000740[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000740[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000744[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000744[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000744[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000744[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000744[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000744[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000744[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000744[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000744[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000748[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000748[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000748[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000748[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000748[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000748[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000748[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000748[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000748[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800074C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800074C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800074C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800074C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800074C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800074C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800074C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800074C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF800074C[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000750[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000750[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000750[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000750[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000750[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000750[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000750[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000750[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000750[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000754[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000754[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000754[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000754[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000754[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000754[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000754[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000754[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000754[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000758[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000758[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000758[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000758[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000758[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000758[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000758[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000758[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000758[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800075C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800075C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800075C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800075C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800075C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800075C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800075C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800075C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800075C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000760[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000760[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000760[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000760[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000760[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000760[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000760[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000760[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000760[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000764[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000764[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000764[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000764[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000764[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000764[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000764[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000764[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000764[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000768[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000768[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000768[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000768[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000768[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000768[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000768[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000768[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000768[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800076C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800076C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800076C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800076C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800076C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800076C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800076C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800076C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800076C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000770[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000770[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000770[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000770[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000770[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000770[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000770[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000770[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000770[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000774[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000774[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000774[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000774[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000774[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000774[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000774[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000774[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000774[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000778[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000778[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000778[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000778[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000778[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000778[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000778[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000778[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000778[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800077C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800077C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800077C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800077C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800077C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800077C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800077C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800077C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800077C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000780[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000780[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000780[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000780[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000780[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000780[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000780[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000780[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000780[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000784[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000784[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000784[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000784[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000784[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000784[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000784[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000784[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000784[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000788[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000788[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000788[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000788[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000788[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000788[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000788[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000788[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000788[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800078C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800078C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800078C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800078C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800078C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800078C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800078C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800078C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800078C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000790[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000790[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000790[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000790[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000790[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000790[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000790[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000790[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000790[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000794[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000794[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000794[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000794[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000794[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000794[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000794[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000794[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000794[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000798[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000798[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000798[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000798[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000798[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000798[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000798[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000798[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000798[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800079C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800079C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800079C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800079C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800079C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800079C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800079C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800079C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800079C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 7 */ - /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 7 */ - /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), - /* .. SDIO0_WP_SEL = 55 */ - /* .. ==> 0XF8000830[5:0] = 0x00000037U */ - /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ - /* .. SDIO0_CD_SEL = 47 */ - /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ - /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), - /* .. FINISH: MIO PROGRAMMING */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), - /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* .. START: SRAM/NOR SET OPMODE */ - /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ - /* .. START: QSPI REGISTERS */ - /* .. Holdb_dr = 1 */ - /* .. ==> 0XE000D000[19:19] = 0x00000001U */ - /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. */ - EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), - /* .. FINISH: QSPI REGISTERS */ - /* .. START: PL POWER ON RESET REGISTERS */ - /* .. PCFG_POR_CNT_4K = 0 */ - /* .. ==> 0XF8007000[29:29] = 0x00000000U */ - /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), - /* .. FINISH: PL POWER ON RESET REGISTERS */ - /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ - /* .. .. START: NAND SET CYCLE */ - /* .. .. FINISH: NAND SET CYCLE */ - /* .. .. START: OPMODE */ - /* .. .. FINISH: OPMODE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: SRAM/NOR CS0 SET CYCLE */ - /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: NOR CS0 BASE ADDRESS */ - /* .. .. FINISH: NOR CS0 BASE ADDRESS */ - /* .. .. START: SRAM/NOR CS1 SET CYCLE */ - /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: NOR CS1 BASE ADDRESS */ - /* .. .. FINISH: NOR CS1 BASE ADDRESS */ - /* .. .. START: USB RESET */ - /* .. .. .. START: USB0 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. DIRECTION_1 = 0x4000 */ - /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x4000 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ - /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x0 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x4000 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: USB0 RESET */ - /* .. .. .. START: USB1 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: USB1 RESET */ - /* .. .. FINISH: USB RESET */ - /* .. .. START: ENET RESET */ - /* .. .. .. START: ENET0 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: ENET0 RESET */ - /* .. .. .. START: ENET1 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: ENET1 RESET */ - /* .. .. FINISH: ENET RESET */ - /* .. .. START: I2C RESET */ - /* .. .. .. START: I2C0 RESET */ - /* .. .. .. .. START: DIR MODE GPIO BANK0 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ - /* .. .. .. .. START: DIR MODE GPIO BANK1 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: I2C0 RESET */ - /* .. .. .. START: I2C1 RESET */ - /* .. .. .. .. START: DIR MODE GPIO BANK0 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ - /* .. .. .. .. START: DIR MODE GPIO BANK1 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: I2C1 RESET */ - /* .. .. FINISH: I2C RESET */ - /* .. .. START: NOR CHIP SELECT */ - /* .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. FINISH: NOR CHIP SELECT */ - /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_post_config_3_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: ENABLING LEVEL SHIFTER */ - /* .. USER_LVL_INP_EN_0 = 1 */ - /* .. ==> 0XF8000900[3:3] = 0x00000001U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. USER_LVL_OUT_EN_0 = 1 */ - /* .. ==> 0XF8000900[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. USER_LVL_INP_EN_1 = 1 */ - /* .. ==> 0XF8000900[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. USER_LVL_OUT_EN_1 = 1 */ - /* .. ==> 0XF8000900[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), - /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: FPGA RESETS TO 0 */ - /* .. reserved_3 = 0 */ - /* .. ==> 0XF8000240[31:25] = 0x00000000U */ - /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ - /* .. reserved_FPGA_ACP_RST = 0 */ - /* .. ==> 0XF8000240[24:24] = 0x00000000U */ - /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. reserved_FPGA_AXDS3_RST = 0 */ - /* .. ==> 0XF8000240[23:23] = 0x00000000U */ - /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. reserved_FPGA_AXDS2_RST = 0 */ - /* .. ==> 0XF8000240[22:22] = 0x00000000U */ - /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. reserved_FPGA_AXDS1_RST = 0 */ - /* .. ==> 0XF8000240[21:21] = 0x00000000U */ - /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. reserved_FPGA_AXDS0_RST = 0 */ - /* .. ==> 0XF8000240[20:20] = 0x00000000U */ - /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. reserved_2 = 0 */ - /* .. ==> 0XF8000240[19:18] = 0x00000000U */ - /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ - /* .. reserved_FSSW1_FPGA_RST = 0 */ - /* .. ==> 0XF8000240[17:17] = 0x00000000U */ - /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. reserved_FSSW0_FPGA_RST = 0 */ - /* .. ==> 0XF8000240[16:16] = 0x00000000U */ - /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. reserved_1 = 0 */ - /* .. ==> 0XF8000240[15:14] = 0x00000000U */ - /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ - /* .. reserved_FPGA_FMSW1_RST = 0 */ - /* .. ==> 0XF8000240[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. reserved_FPGA_FMSW0_RST = 0 */ - /* .. ==> 0XF8000240[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. reserved_FPGA_DMA3_RST = 0 */ - /* .. ==> 0XF8000240[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. reserved_FPGA_DMA2_RST = 0 */ - /* .. ==> 0XF8000240[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. reserved_FPGA_DMA1_RST = 0 */ - /* .. ==> 0XF8000240[9:9] = 0x00000000U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. reserved_FPGA_DMA0_RST = 0 */ - /* .. ==> 0XF8000240[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. reserved = 0 */ - /* .. ==> 0XF8000240[7:4] = 0x00000000U */ - /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. FPGA3_OUT_RST = 0 */ - /* .. ==> 0XF8000240[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. FPGA2_OUT_RST = 0 */ - /* .. ==> 0XF8000240[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. FPGA1_OUT_RST = 0 */ - /* .. ==> 0XF8000240[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. FPGA0_OUT_RST = 0 */ - /* .. ==> 0XF8000240[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), - /* .. FINISH: FPGA RESETS TO 0 */ - /* .. START: AFI REGISTERS */ - /* .. .. START: AFI0 REGISTERS */ - /* .. .. FINISH: AFI0 REGISTERS */ - /* .. .. START: AFI1 REGISTERS */ - /* .. .. FINISH: AFI1 REGISTERS */ - /* .. .. START: AFI2 REGISTERS */ - /* .. .. FINISH: AFI2 REGISTERS */ - /* .. .. START: AFI3 REGISTERS */ - /* .. .. FINISH: AFI3 REGISTERS */ - /* .. .. START: AFI2 SECURE REGISTER */ - /* .. .. FINISH: AFI2 SECURE REGISTER */ - /* .. FINISH: AFI REGISTERS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_debug_3_0[] = { - /* START: top */ - /* .. START: CROSS TRIGGER CONFIGURATIONS */ - /* .. .. START: UNLOCKING CTI REGISTERS */ - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: UNLOCKING CTI REGISTERS */ - /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_pll_init_data_2_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: PLL SLCR REGISTERS */ - /* .. .. START: ARM PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x177 */ - /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x1a */ - /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. ARM_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. .. SRCSEL = 0x0 */ - /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. .. DIVISOR = 0x2 */ - /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ - /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ - /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ - /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ - /* .. .. .. CPU_2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ - /* .. .. .. CPU_1XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ - /* .. .. .. CPU_PERI_CLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), - /* .. .. FINISH: ARM PLL INIT */ - /* .. .. START: DDR PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x1db */ - /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x15 */ - /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. DDR_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. .. DDR_3XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. DDR_2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ - /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ - /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ - /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ - /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), - /* .. .. FINISH: DDR PLL INIT */ - /* .. .. START: IO PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x1f4 */ - /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x14 */ - /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. IO_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. FINISH: IO PLL INIT */ - /* .. FINISH: PLL SLCR REGISTERS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_clock_init_data_2_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: CLOCK CONTROL SLCR REGISTERS */ - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000128[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. DIVISOR0 = 0x34 */ - /* .. ==> 0XF8000128[13:8] = 0x00000034U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ - /* .. DIVISOR1 = 0x2 */ - /* .. ==> 0XF8000128[25:20] = 0x00000002U */ - /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000138[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000138[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000140[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000140[6:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. DIVISOR = 0x8 */ - /* .. ==> 0XF8000140[13:8] = 0x00000008U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ - /* .. DIVISOR1 = 0x1 */ - /* .. ==> 0XF8000140[25:20] = 0x00000001U */ - /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF800014C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF800014C[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x5 */ - /* .. ==> 0XF800014C[13:8] = 0x00000005U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. */ - EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), - /* .. CLKACT0 = 0x1 */ - /* .. ==> 0XF8000150[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. CLKACT1 = 0x0 */ - /* .. ==> 0XF8000150[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000150[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000150[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ - /* .. */ - EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), - /* .. CLKACT0 = 0x0 */ - /* .. ==> 0XF8000154[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. CLKACT1 = 0x1 */ - /* .. ==> 0XF8000154[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000154[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0xa */ - /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ - /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), - /* .. .. START: TRACE CLOCK */ - /* .. .. FINISH: TRACE CLOCK */ - /* .. .. CLKACT = 0x1 */ - /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR = 0x5 */ - /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x7 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x5 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x14 */ - /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), - /* .. .. CLK_621_TRUE = 0x1 */ - /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), - /* .. .. DMA_CPU_2XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. USB0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. .. USB1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ - /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ - /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ - /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. UART0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. UART1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ - /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ - /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ - /* .. .. SMC_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), - /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ - /* .. START: THIS SHOULD BE BLANK */ - /* .. FINISH: THIS SHOULD BE BLANK */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - /* START: top */ - /* .. START: DDR INITIALIZATION */ - /* .. .. START: LOCK DDR */ - /* .. .. reg_ddrc_soft_rstb = 0 */ - /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_powerdown_en = 0x0 */ - /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_data_bus_width = 0x0 */ - /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ - /* .. .. reg_ddrc_burst8_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ - /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ - /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), - /* .. .. FINISH: LOCK DDR */ - /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ - /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ - /* .. .. reg_ddrc_active_ranks = 0x1 */ - /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ - /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ - /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_wr_odt_block = 0x1 */ - /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ - /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ - /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ - /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ - /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ - /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), - /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ - /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ - /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ - /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ - /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ - /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ - /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ - /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), - /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ - /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ - /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ - /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ - /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ - /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ - /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), - /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ - /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ - /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ - /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ - /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ - /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ - /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), - /* .. .. reg_ddrc_t_rc = 0x1a */ - /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ - /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ - /* .. .. reg_ddrc_t_rfc_min = 0x54 */ - /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ - /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ - /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ - /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ - /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), - /* .. .. reg_ddrc_wr2pre = 0x12 */ - /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ - /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ - /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ - /* .. .. reg_ddrc_t_faw = 0x15 */ - /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ - /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ - /* .. .. reg_ddrc_t_ras_max = 0x23 */ - /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ - /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ - /* .. .. reg_ddrc_t_ras_min = 0x13 */ - /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ - /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ - /* .. .. reg_ddrc_t_cke = 0x4 */ - /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), - /* .. .. reg_ddrc_write_latency = 0x5 */ - /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ - /* .. .. reg_ddrc_rd2wr = 0x7 */ - /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ - /* .. .. reg_ddrc_wr2rd = 0xe */ - /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ - /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ - /* .. .. reg_ddrc_t_xp = 0x4 */ - /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ - /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ - /* .. .. reg_ddrc_pad_pd = 0x0 */ - /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rd2pre = 0x4 */ - /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ - /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ - /* .. .. reg_ddrc_t_rcd = 0x7 */ - /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), - /* .. .. reg_ddrc_t_ccd = 0x4 */ - /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ - /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ - /* .. .. reg_ddrc_t_rrd = 0x6 */ - /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ - /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ - /* .. .. reg_ddrc_refresh_margin = 0x2 */ - /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. reg_ddrc_t_rp = 0x7 */ - /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ - /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ - /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ - /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ - /* .. .. reg_ddrc_sdram = 0x1 */ - /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ - /* .. .. reg_ddrc_mobile = 0x0 */ - /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_clock_stop_en = 0x0 */ - /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_read_latency = 0x7 */ - /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ - /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ - /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ - /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ - /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ - /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ - /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ - /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_loopback = 0x0 */ - /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ - /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), - /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ - /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_prefer_write = 0x0 */ - /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_max_rank_rd = 0xf */ - /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ - /* .. .. reg_ddrc_mr_wr = 0x0 */ - /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_addr = 0x0 */ - /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_data = 0x0 */ - /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ - /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ - /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_type = 0x0 */ - /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ - /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), - /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ - /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ - /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ - /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ - /* .. .. reg_ddrc_t_mrd = 0x4 */ - /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ - /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), - /* .. .. reg_ddrc_emr2 = 0x8 */ - /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ - /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ - /* .. .. reg_ddrc_emr3 = 0x0 */ - /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), - /* .. .. reg_ddrc_mr = 0x930 */ - /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ - /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ - /* .. .. reg_ddrc_emr = 0x4 */ - /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ - /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), - /* .. .. reg_ddrc_burst_rdwr = 0x4 */ - /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ - /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ - /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ - /* .. .. reg_ddrc_burstchop = 0x0 */ - /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), - /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ - /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_dq = 0x0 */ - /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_debug_mode = 0x0 */ - /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_level_start = 0x0 */ - /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_level_start = 0x0 */ - /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_phy_dq0_wait_t = 0x0 */ - /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), - /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ - /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ - /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ - /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ - /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ - /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ - /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ - /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ - /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), - /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ - /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ - /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ - /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ - /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ - /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ - /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ - /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ - /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ - /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ - /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), - /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ - /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ - /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ - /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ - /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ - /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ - /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ - /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ - /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ - /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ - /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ - /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ - /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ - /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), - /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ - /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ - /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ - /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ - /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ - /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ - /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. .. reg_phy_rd_local_odt = 0x0 */ - /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_local_odt = 0x3 */ - /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ - /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ - /* .. .. reg_phy_idle_local_odt = 0x3 */ - /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ - /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ - /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ - /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ - /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), - /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ - /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ - /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ - /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ - /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ - /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_phy_use_fixed_re = 0x1 */ - /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ - /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ - /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ - /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_phy_clk_stall_level = 0x0 */ - /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ - /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ - /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ - /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), - /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ - /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ - /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ - /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ - /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), - /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ - /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ - /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ - /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ - /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ - /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ - /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), - /* .. .. reg_ddrc_pageclose = 0x0 */ - /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ - /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ - /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ - /* .. .. reg_ddrc_auto_pre_en = 0x0 */ - /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. reg_ddrc_refresh_update_level = 0x0 */ - /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_wc = 0x0 */ - /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ - /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_ddrc_selfref_en = 0x0 */ - /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), - /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ - /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ - /* .. .. reg_arb_go2critical_en = 0x1 */ - /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), - /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ - /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ - /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ - /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ - /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ - /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ - /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), - /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ - /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ - /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ - /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), - /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ - /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ - /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ - /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ - /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ - /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ - /* .. .. reg_ddrc_t_cksre = 0x6 */ - /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ - /* .. .. reg_ddrc_t_cksrx = 0x6 */ - /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ - /* .. .. reg_ddrc_t_ckesr = 0x4 */ - /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), - /* .. .. reg_ddrc_t_ckpde = 0x2 */ - /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ - /* .. .. reg_ddrc_t_ckpdx = 0x2 */ - /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ - /* .. .. reg_ddrc_t_ckdpde = 0x2 */ - /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ - /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ - /* .. .. reg_ddrc_t_ckcsx = 0x3 */ - /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), - /* .. .. refresh_timer0_start_value_x32 = 0x0 */ - /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ - /* .. .. refresh_timer1_start_value_x32 = 0x8 */ - /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ - /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), - /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ - /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_ddr3 = 0x1 */ - /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. reg_ddrc_t_mod = 0x200 */ - /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ - /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ - /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ - /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ - /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ - /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ - /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), - /* .. .. t_zq_short_interval_x1024 = 0xc845 */ - /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ - /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ - /* .. .. dram_rstn_x1024 = 0x67 */ - /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ - /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), - /* .. .. deeppowerdown_en = 0x0 */ - /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. deeppowerdown_to_x1024 = 0xff */ - /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ - /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), - /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ - /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ - /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ - /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ - /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ - /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ - /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ - /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ - /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ - /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ - /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ - /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ - /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), - /* .. .. reg_ddrc_2t_delay = 0x0 */ - /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ - /* .. .. reg_ddrc_skip_ocd = 0x1 */ - /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ - /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ - /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), - /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ - /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ - /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ - /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ - /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ - /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ - /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ - /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), - /* .. .. START: RESET ECC ERROR */ - /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ - /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ - /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), - /* .. .. FINISH: RESET ECC ERROR */ - /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ - /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ - /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), - /* .. .. CORR_ECC_LOG_VALID = 0x0 */ - /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ - /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), - /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ - /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), - /* .. .. STAT_NUM_CORR_ERR = 0x0 */ - /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ - /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ - /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), - /* .. .. reg_ddrc_ecc_mode = 0x0 */ - /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_scrub = 0x1 */ - /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), - /* .. .. reg_phy_dif_on = 0x0 */ - /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_phy_dif_off = 0x0 */ - /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ - /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ - /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ - /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ - /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ - /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ - /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ - /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ - /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ - /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ - /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ - /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ - /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), - /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ - /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), - /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ - /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), - /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ - /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), - /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ - /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), - /* .. .. reg_phy_loopback = 0x0 */ - /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_phy_bl2 = 0x0 */ - /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_at_spd_atpg = 0x0 */ - /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_enable = 0x0 */ - /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_force_err = 0x0 */ - /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_mode = 0x0 */ - /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. .. reg_phy_invert_clkout = 0x1 */ - /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ - /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_phy_sel_logic = 0x0 */ - /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ - /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ - /* .. .. reg_phy_ctrl_slave_force = 0x0 */ - /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ - /* .. .. reg_phy_use_rank0_delays = 0x1 */ - /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. reg_phy_lpddr = 0x0 */ - /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ - /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ - /* .. .. reg_phy_cmd_latency = 0x0 */ - /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ - /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ - /* .. .. reg_phy_int_lpbk = 0x0 */ - /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ - /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), - /* .. .. reg_phy_wr_rl_delay = 0x2 */ - /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ - /* .. .. reg_phy_rd_rl_delay = 0x4 */ - /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ - /* .. .. reg_phy_dll_lock_diff = 0xf */ - /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ - /* .. .. reg_phy_use_wr_level = 0x1 */ - /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ - /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ - /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ - /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ - /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ - /* .. .. reg_phy_dis_calib_rst = 0x0 */ - /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), - /* .. .. reg_arb_page_addr_mask = 0x0 */ - /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_ddrc_lpddr2 = 0x0 */ - /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ - /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_derate_enable = 0x0 */ - /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr4_margin = 0x0 */ - /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), - /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ - /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), - /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ - /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ - /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ - /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ - /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ - /* .. .. reg_ddrc_t_mrw = 0x5 */ - /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), - /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ - /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ - /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ - /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ - /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), - /* .. .. START: POLL ON DCI STATUS */ - /* .. .. DONE = 1 */ - /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ - /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. .. */ - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - /* .. .. FINISH: POLL ON DCI STATUS */ - /* .. .. START: UNLOCK DDR */ - /* .. .. reg_ddrc_soft_rstb = 0x1 */ - /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_ddrc_powerdown_en = 0x0 */ - /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_data_bus_width = 0x0 */ - /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ - /* .. .. reg_ddrc_burst8_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ - /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ - /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), - /* .. .. FINISH: UNLOCK DDR */ - /* .. .. START: CHECK DDR STATUS */ - /* .. .. ddrc_reg_operating_mode = 1 */ - /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - /* .. .. FINISH: CHECK DDR STATUS */ - /* .. FINISH: DDR INITIALIZATION */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_mio_init_data_2_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: OCM REMAPPING */ - /* .. VREF_EN = 0x1 */ - /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. VREF_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. CLK_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. SRSTN_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), - /* .. FINISH: OCM REMAPPING */ - /* .. START: DDRIOB SETTINGS */ - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCR_TYPE = 0x0 */ - /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCR_TYPE = 0x0 */ - /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x1 */ - /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x1 */ - /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x2 */ - /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x2 */ - /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCR_TYPE = 0x0 */ - /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x3 */ - /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ - /* .. SLEW_N = 0x3 */ - /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x6 */ - /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. SLEW_N = 0x1f */ - /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x6 */ - /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. SLEW_N = 0x1f */ - /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x6 */ - /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. SLEW_N = 0x1f */ - /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), - /* .. VREF_INT_EN = 0x0 */ - /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. VREF_SEL = 0x0 */ - /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ - /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ - /* .. VREF_EXT_EN = 0x3 */ - /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. VREF_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ - /* .. REFIO_EN = 0x1 */ - /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ - /* .. REFIO_TEST = 0x0 */ - /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ - /* .. REFIO_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DRST_B_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. CKE_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ - /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), - /* .. .. START: ASSERT RESET */ - /* .. .. RESET = 1 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), - /* .. .. FINISH: ASSERT RESET */ - /* .. .. START: DEASSERT RESET */ - /* .. .. RESET = 0 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), - /* .. .. FINISH: DEASSERT RESET */ - /* .. .. RESET = 0x1 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. ENABLE = 0x1 */ - /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. VRP_TRI = 0x0 */ - /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. VRN_TRI = 0x0 */ - /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. VRP_OUT = 0x0 */ - /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. NREF_OPT1 = 0x0 */ - /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. .. NREF_OPT2 = 0x0 */ - /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ - /* .. .. NREF_OPT4 = 0x1 */ - /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ - /* .. .. PREF_OPT1 = 0x0 */ - /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ - /* .. .. PREF_OPT2 = 0x0 */ - /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ - /* .. .. UPDATE_CONTROL = 0x0 */ - /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. INIT_COMPLETE = 0x0 */ - /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. .. TST_CLK = 0x0 */ - /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. .. TST_HLN = 0x0 */ - /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. .. TST_HLP = 0x0 */ - /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. .. TST_RST = 0x0 */ - /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. INT_DCI_EN = 0x0 */ - /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), - /* .. FINISH: DDRIOB SETTINGS */ - /* .. START: MIO PROGRAMMING */ - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000700[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000700[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000700[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000700[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000700[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000700[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000700[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000700[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000700[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000704[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000704[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000704[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000704[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000704[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000704[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000704[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000704[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000704[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000708[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000708[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000708[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000708[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000708[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000708[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000708[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000708[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000708[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800070C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800070C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800070C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800070C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800070C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800070C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800070C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800070C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800070C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000710[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000710[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000710[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000710[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000710[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000710[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000710[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000710[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000710[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000714[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000714[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000714[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000714[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000714[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000714[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000714[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000714[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000714[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000718[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000718[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000718[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000718[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000718[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000718[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000718[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000718[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000718[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800071C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800071C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800071C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800071C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800071C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800071C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800071C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800071C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800071C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000720[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000720[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000720[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000720[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000720[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000720[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000720[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000720[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000720[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000724[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000724[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000724[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000724[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000724[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000724[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000724[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000724[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000724[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000728[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000728[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000728[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000728[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000728[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000728[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000728[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000728[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000728[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800072C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800072C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800072C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800072C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800072C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800072C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800072C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF800072C[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800072C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000730[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000730[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000730[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000730[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000730[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000730[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000730[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000730[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000730[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000734[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000734[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000734[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000734[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000734[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000734[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000734[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000734[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000734[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000738[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000738[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000738[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000738[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000738[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000738[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000738[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000738[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000738[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800073C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800073C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800073C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800073C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800073C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800073C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800073C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF800073C[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800073C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000740[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000740[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000740[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000740[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000740[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000740[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000740[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000740[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000740[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000744[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000744[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000744[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000744[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000744[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000744[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000744[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000744[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000744[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000748[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000748[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000748[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000748[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000748[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000748[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000748[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000748[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000748[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800074C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800074C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800074C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800074C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800074C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800074C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800074C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800074C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF800074C[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000750[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000750[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000750[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000750[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000750[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000750[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000750[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000750[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000750[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000754[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000754[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000754[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000754[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000754[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000754[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000754[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000754[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000754[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000758[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000758[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000758[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000758[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000758[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000758[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000758[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000758[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000758[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800075C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800075C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800075C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800075C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800075C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800075C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800075C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800075C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800075C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000760[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000760[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000760[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000760[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000760[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000760[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000760[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000760[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000760[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000764[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000764[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000764[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000764[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000764[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000764[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000764[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000764[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000764[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000768[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000768[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000768[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000768[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000768[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000768[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000768[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000768[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000768[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800076C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800076C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800076C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800076C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800076C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800076C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800076C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800076C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800076C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000770[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000770[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000770[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000770[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000770[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000770[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000770[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000770[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000770[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000774[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000774[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000774[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000774[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000774[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000774[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000774[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000774[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000774[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000778[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000778[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000778[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000778[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000778[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000778[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000778[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000778[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000778[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800077C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800077C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800077C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800077C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800077C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800077C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800077C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800077C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800077C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000780[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000780[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000780[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000780[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000780[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000780[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000780[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000780[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000780[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000784[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000784[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000784[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000784[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000784[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000784[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000784[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000784[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000784[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000788[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000788[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000788[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000788[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000788[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000788[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000788[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000788[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000788[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800078C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800078C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800078C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800078C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800078C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800078C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800078C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800078C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800078C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000790[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000790[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000790[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000790[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000790[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000790[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000790[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000790[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000790[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000794[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000794[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000794[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000794[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000794[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000794[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000794[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000794[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000794[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000798[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000798[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000798[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000798[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000798[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000798[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000798[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000798[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000798[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800079C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800079C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800079C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800079C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800079C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800079C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800079C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800079C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800079C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 7 */ - /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 7 */ - /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), - /* .. SDIO0_WP_SEL = 55 */ - /* .. ==> 0XF8000830[5:0] = 0x00000037U */ - /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ - /* .. SDIO0_CD_SEL = 47 */ - /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ - /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), - /* .. FINISH: MIO PROGRAMMING */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), - /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* .. START: SRAM/NOR SET OPMODE */ - /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. IRMODE = 0x0 */ - /* .. ==> 0XE0001004[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. UCLKEN = 0x0 */ - /* .. ==> 0XE0001004[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ - /* .. START: QSPI REGISTERS */ - /* .. Holdb_dr = 1 */ - /* .. ==> 0XE000D000[19:19] = 0x00000001U */ - /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. */ - EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), - /* .. FINISH: QSPI REGISTERS */ - /* .. START: PL POWER ON RESET REGISTERS */ - /* .. PCFG_POR_CNT_4K = 0 */ - /* .. ==> 0XF8007000[29:29] = 0x00000000U */ - /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), - /* .. FINISH: PL POWER ON RESET REGISTERS */ - /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ - /* .. .. START: NAND SET CYCLE */ - /* .. .. FINISH: NAND SET CYCLE */ - /* .. .. START: OPMODE */ - /* .. .. FINISH: OPMODE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: SRAM/NOR CS0 SET CYCLE */ - /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: NOR CS0 BASE ADDRESS */ - /* .. .. FINISH: NOR CS0 BASE ADDRESS */ - /* .. .. START: SRAM/NOR CS1 SET CYCLE */ - /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: NOR CS1 BASE ADDRESS */ - /* .. .. FINISH: NOR CS1 BASE ADDRESS */ - /* .. .. START: USB RESET */ - /* .. .. .. START: USB0 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. DIRECTION_1 = 0x4000 */ - /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x4000 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ - /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x0 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x4000 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: USB0 RESET */ - /* .. .. .. START: USB1 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: USB1 RESET */ - /* .. .. FINISH: USB RESET */ - /* .. .. START: ENET RESET */ - /* .. .. .. START: ENET0 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: ENET0 RESET */ - /* .. .. .. START: ENET1 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: ENET1 RESET */ - /* .. .. FINISH: ENET RESET */ - /* .. .. START: I2C RESET */ - /* .. .. .. START: I2C0 RESET */ - /* .. .. .. .. START: DIR MODE GPIO BANK0 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ - /* .. .. .. .. START: DIR MODE GPIO BANK1 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: I2C0 RESET */ - /* .. .. .. START: I2C1 RESET */ - /* .. .. .. .. START: DIR MODE GPIO BANK0 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ - /* .. .. .. .. START: DIR MODE GPIO BANK1 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: I2C1 RESET */ - /* .. .. FINISH: I2C RESET */ - /* .. .. START: NOR CHIP SELECT */ - /* .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. FINISH: NOR CHIP SELECT */ - /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_post_config_2_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: ENABLING LEVEL SHIFTER */ - /* .. USER_INP_ICT_EN_0 = 3 */ - /* .. ==> 0XF8000900[1:0] = 0x00000003U */ - /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ - /* .. USER_INP_ICT_EN_1 = 3 */ - /* .. ==> 0XF8000900[3:2] = 0x00000003U */ - /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ - /* .. */ - EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), - /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: FPGA RESETS TO 0 */ - /* .. reserved_3 = 0 */ - /* .. ==> 0XF8000240[31:25] = 0x00000000U */ - /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ - /* .. FPGA_ACP_RST = 0 */ - /* .. ==> 0XF8000240[24:24] = 0x00000000U */ - /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. FPGA_AXDS3_RST = 0 */ - /* .. ==> 0XF8000240[23:23] = 0x00000000U */ - /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. FPGA_AXDS2_RST = 0 */ - /* .. ==> 0XF8000240[22:22] = 0x00000000U */ - /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. FPGA_AXDS1_RST = 0 */ - /* .. ==> 0XF8000240[21:21] = 0x00000000U */ - /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. FPGA_AXDS0_RST = 0 */ - /* .. ==> 0XF8000240[20:20] = 0x00000000U */ - /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. reserved_2 = 0 */ - /* .. ==> 0XF8000240[19:18] = 0x00000000U */ - /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ - /* .. FSSW1_FPGA_RST = 0 */ - /* .. ==> 0XF8000240[17:17] = 0x00000000U */ - /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. FSSW0_FPGA_RST = 0 */ - /* .. ==> 0XF8000240[16:16] = 0x00000000U */ - /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. reserved_1 = 0 */ - /* .. ==> 0XF8000240[15:14] = 0x00000000U */ - /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ - /* .. FPGA_FMSW1_RST = 0 */ - /* .. ==> 0XF8000240[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. FPGA_FMSW0_RST = 0 */ - /* .. ==> 0XF8000240[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. FPGA_DMA3_RST = 0 */ - /* .. ==> 0XF8000240[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. FPGA_DMA2_RST = 0 */ - /* .. ==> 0XF8000240[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. FPGA_DMA1_RST = 0 */ - /* .. ==> 0XF8000240[9:9] = 0x00000000U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. FPGA_DMA0_RST = 0 */ - /* .. ==> 0XF8000240[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. reserved = 0 */ - /* .. ==> 0XF8000240[7:4] = 0x00000000U */ - /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. FPGA3_OUT_RST = 0 */ - /* .. ==> 0XF8000240[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. FPGA2_OUT_RST = 0 */ - /* .. ==> 0XF8000240[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. FPGA1_OUT_RST = 0 */ - /* .. ==> 0XF8000240[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. FPGA0_OUT_RST = 0 */ - /* .. ==> 0XF8000240[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), - /* .. FINISH: FPGA RESETS TO 0 */ - /* .. START: AFI REGISTERS */ - /* .. .. START: AFI0 REGISTERS */ - /* .. .. FINISH: AFI0 REGISTERS */ - /* .. .. START: AFI1 REGISTERS */ - /* .. .. FINISH: AFI1 REGISTERS */ - /* .. .. START: AFI2 REGISTERS */ - /* .. .. FINISH: AFI2 REGISTERS */ - /* .. .. START: AFI3 REGISTERS */ - /* .. .. FINISH: AFI3 REGISTERS */ - /* .. FINISH: AFI REGISTERS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_debug_2_0[] = { - /* START: top */ - /* .. START: CROSS TRIGGER CONFIGURATIONS */ - /* .. .. START: UNLOCKING CTI REGISTERS */ - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: UNLOCKING CTI REGISTERS */ - /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_pll_init_data_1_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: PLL SLCR REGISTERS */ - /* .. .. START: ARM PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x177 */ - /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x1a */ - /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. ARM_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. .. SRCSEL = 0x0 */ - /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. .. DIVISOR = 0x2 */ - /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ - /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ - /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ - /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ - /* .. .. .. CPU_2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ - /* .. .. .. CPU_1XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ - /* .. .. .. CPU_PERI_CLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), - /* .. .. FINISH: ARM PLL INIT */ - /* .. .. START: DDR PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x1db */ - /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x15 */ - /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. DDR_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. .. DDR_3XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. DDR_2XCLKACT = 0x1 */ - /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ - /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ - /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ - /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ - /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), - /* .. .. FINISH: DDR PLL INIT */ - /* .. .. START: IO PLL INIT */ - /* .. .. PLL_RES = 0xc */ - /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ - /* .. .. PLL_CP = 0x2 */ - /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. LOCK_CNT = 0x1f4 */ - /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), - /* .. .. .. START: UPDATE FB_DIV */ - /* .. .. .. PLL_FDIV = 0x14 */ - /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ - /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), - /* .. .. .. FINISH: UPDATE FB_DIV */ - /* .. .. .. START: BY PASS PLL */ - /* .. .. .. PLL_BYPASS_FORCE = 1 */ - /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), - /* .. .. .. FINISH: BY PASS PLL */ - /* .. .. .. START: ASSERT RESET */ - /* .. .. .. PLL_RESET = 1 */ - /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), - /* .. .. .. FINISH: ASSERT RESET */ - /* .. .. .. START: DEASSERT RESET */ - /* .. .. .. PLL_RESET = 0 */ - /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), - /* .. .. .. FINISH: DEASSERT RESET */ - /* .. .. .. START: CHECK PLL STATUS */ - /* .. .. .. IO_PLL_LOCK = 1 */ - /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ - /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. .. .. */ - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - /* .. .. .. FINISH: CHECK PLL STATUS */ - /* .. .. .. START: REMOVE PLL BY PASS */ - /* .. .. .. PLL_BYPASS_FORCE = 0 */ - /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ - /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. .. */ - EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), - /* .. .. .. FINISH: REMOVE PLL BY PASS */ - /* .. .. FINISH: IO PLL INIT */ - /* .. FINISH: PLL SLCR REGISTERS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_clock_init_data_1_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: CLOCK CONTROL SLCR REGISTERS */ - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000128[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. DIVISOR0 = 0x34 */ - /* .. ==> 0XF8000128[13:8] = 0x00000034U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ - /* .. DIVISOR1 = 0x2 */ - /* .. ==> 0XF8000128[25:20] = 0x00000002U */ - /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000138[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000138[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF8000140[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000140[6:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. DIVISOR = 0x8 */ - /* .. ==> 0XF8000140[13:8] = 0x00000008U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ - /* .. DIVISOR1 = 0x1 */ - /* .. ==> 0XF8000140[25:20] = 0x00000001U */ - /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), - /* .. CLKACT = 0x1 */ - /* .. ==> 0XF800014C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF800014C[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x5 */ - /* .. ==> 0XF800014C[13:8] = 0x00000005U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. */ - EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), - /* .. CLKACT0 = 0x1 */ - /* .. ==> 0XF8000150[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. CLKACT1 = 0x0 */ - /* .. ==> 0XF8000150[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000150[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000150[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ - /* .. */ - EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), - /* .. CLKACT0 = 0x0 */ - /* .. ==> 0XF8000154[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. CLKACT1 = 0x1 */ - /* .. ==> 0XF8000154[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. SRCSEL = 0x0 */ - /* .. ==> 0XF8000154[5:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0xa */ - /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ - /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), - /* .. .. START: TRACE CLOCK */ - /* .. .. FINISH: TRACE CLOCK */ - /* .. .. CLKACT = 0x1 */ - /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR = 0x5 */ - /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x7 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x5 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), - /* .. .. SRCSEL = 0x0 */ - /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0x14 */ - /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ - /* .. .. DIVISOR1 = 0x1 */ - /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), - /* .. .. CLK_621_TRUE = 0x1 */ - /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), - /* .. .. DMA_CPU_2XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. USB0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. .. USB1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ - /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ - /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ - /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. UART0_CPU_1XCLKACT = 0x0 */ - /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. UART1_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ - /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ - /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ - /* .. .. SMC_CPU_1XCLKACT = 0x1 */ - /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), - /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ - /* .. START: THIS SHOULD BE BLANK */ - /* .. FINISH: THIS SHOULD BE BLANK */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - /* START: top */ - /* .. START: DDR INITIALIZATION */ - /* .. .. START: LOCK DDR */ - /* .. .. reg_ddrc_soft_rstb = 0 */ - /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_powerdown_en = 0x0 */ - /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_data_bus_width = 0x0 */ - /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ - /* .. .. reg_ddrc_burst8_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ - /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ - /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), - /* .. .. FINISH: LOCK DDR */ - /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ - /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ - /* .. .. reg_ddrc_active_ranks = 0x1 */ - /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ - /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ - /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_wr_odt_block = 0x1 */ - /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ - /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ - /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ - /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ - /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ - /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), - /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ - /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ - /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ - /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ - /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ - /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ - /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ - /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), - /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ - /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ - /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ - /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ - /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ - /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ - /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), - /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ - /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ - /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ - /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ - /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ - /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ - /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), - /* .. .. reg_ddrc_t_rc = 0x1a */ - /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ - /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ - /* .. .. reg_ddrc_t_rfc_min = 0x54 */ - /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ - /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ - /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ - /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ - /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), - /* .. .. reg_ddrc_wr2pre = 0x12 */ - /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ - /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ - /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ - /* .. .. reg_ddrc_t_faw = 0x15 */ - /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ - /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ - /* .. .. reg_ddrc_t_ras_max = 0x23 */ - /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ - /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ - /* .. .. reg_ddrc_t_ras_min = 0x13 */ - /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ - /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ - /* .. .. reg_ddrc_t_cke = 0x4 */ - /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), - /* .. .. reg_ddrc_write_latency = 0x5 */ - /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ - /* .. .. reg_ddrc_rd2wr = 0x7 */ - /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ - /* .. .. reg_ddrc_wr2rd = 0xe */ - /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ - /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ - /* .. .. reg_ddrc_t_xp = 0x4 */ - /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ - /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ - /* .. .. reg_ddrc_pad_pd = 0x0 */ - /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rd2pre = 0x4 */ - /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ - /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ - /* .. .. reg_ddrc_t_rcd = 0x7 */ - /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), - /* .. .. reg_ddrc_t_ccd = 0x4 */ - /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ - /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ - /* .. .. reg_ddrc_t_rrd = 0x6 */ - /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ - /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ - /* .. .. reg_ddrc_refresh_margin = 0x2 */ - /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ - /* .. .. reg_ddrc_t_rp = 0x7 */ - /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ - /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ - /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ - /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ - /* .. .. reg_ddrc_sdram = 0x1 */ - /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ - /* .. .. reg_ddrc_mobile = 0x0 */ - /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_clock_stop_en = 0x0 */ - /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_read_latency = 0x7 */ - /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ - /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ - /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ - /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ - /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ - /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ - /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ - /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_loopback = 0x0 */ - /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ - /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), - /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ - /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_prefer_write = 0x0 */ - /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_max_rank_rd = 0xf */ - /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ - /* .. .. reg_ddrc_mr_wr = 0x0 */ - /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_addr = 0x0 */ - /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_data = 0x0 */ - /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ - /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ - /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_type = 0x0 */ - /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ - /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), - /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ - /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ - /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ - /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ - /* .. .. reg_ddrc_t_mrd = 0x4 */ - /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ - /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), - /* .. .. reg_ddrc_emr2 = 0x8 */ - /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ - /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ - /* .. .. reg_ddrc_emr3 = 0x0 */ - /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), - /* .. .. reg_ddrc_mr = 0x930 */ - /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ - /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ - /* .. .. reg_ddrc_emr = 0x4 */ - /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ - /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), - /* .. .. reg_ddrc_burst_rdwr = 0x4 */ - /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ - /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ - /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ - /* .. .. reg_ddrc_burstchop = 0x0 */ - /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), - /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ - /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_dq = 0x0 */ - /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_debug_mode = 0x0 */ - /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_level_start = 0x0 */ - /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_level_start = 0x0 */ - /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_phy_dq0_wait_t = 0x0 */ - /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), - /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ - /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ - /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ - /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ - /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ - /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ - /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ - /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ - /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), - /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ - /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ - /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ - /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ - /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ - /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ - /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ - /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ - /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ - /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ - /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), - /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ - /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ - /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ - /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ - /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ - /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ - /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ - /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ - /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ - /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ - /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ - /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ - /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ - /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ - /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), - /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ - /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ - /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ - /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ - /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ - /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ - /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. .. reg_phy_rd_local_odt = 0x0 */ - /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_local_odt = 0x3 */ - /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ - /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ - /* .. .. reg_phy_idle_local_odt = 0x3 */ - /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ - /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ - /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ - /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ - /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ - /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ - /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), - /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ - /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ - /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ - /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ - /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ - /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_phy_use_fixed_re = 0x1 */ - /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ - /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ - /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ - /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_phy_clk_stall_level = 0x0 */ - /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ - /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ - /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ - /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ - /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ - /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), - /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ - /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ - /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ - /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ - /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ - /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), - /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ - /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ - /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ - /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ - /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ - /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ - /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), - /* .. .. reg_ddrc_pageclose = 0x0 */ - /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ - /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ - /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ - /* .. .. reg_ddrc_auto_pre_en = 0x0 */ - /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. .. reg_ddrc_refresh_update_level = 0x0 */ - /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_wc = 0x0 */ - /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ - /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_ddrc_selfref_en = 0x0 */ - /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), - /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ - /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ - /* .. .. reg_arb_go2critical_en = 0x1 */ - /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), - /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ - /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ - /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ - /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ - /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ - /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ - /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), - /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ - /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ - /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ - /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), - /* .. .. refresh_timer0_start_value_x32 = 0x0 */ - /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ - /* .. .. refresh_timer1_start_value_x32 = 0x8 */ - /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ - /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), - /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ - /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_ddr3 = 0x1 */ - /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. reg_ddrc_t_mod = 0x200 */ - /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ - /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ - /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ - /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ - /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ - /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ - /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), - /* .. .. t_zq_short_interval_x1024 = 0xc845 */ - /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ - /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ - /* .. .. dram_rstn_x1024 = 0x67 */ - /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ - /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), - /* .. .. deeppowerdown_en = 0x0 */ - /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. deeppowerdown_to_x1024 = 0xff */ - /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ - /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), - /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ - /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ - /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ - /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ - /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ - /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ - /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ - /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ - /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ - /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ - /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ - /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ - /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ - /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ - /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), - /* .. .. reg_ddrc_2t_delay = 0x0 */ - /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ - /* .. .. reg_ddrc_skip_ocd = 0x1 */ - /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ - /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ - /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), - /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ - /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ - /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ - /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ - /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ - /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ - /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ - /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), - /* .. .. START: RESET ECC ERROR */ - /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ - /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ - /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), - /* .. .. FINISH: RESET ECC ERROR */ - /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ - /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ - /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), - /* .. .. CORR_ECC_LOG_VALID = 0x0 */ - /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ - /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), - /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ - /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), - /* .. .. STAT_NUM_CORR_ERR = 0x0 */ - /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ - /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ - /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), - /* .. .. reg_ddrc_ecc_mode = 0x0 */ - /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_scrub = 0x1 */ - /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), - /* .. .. reg_phy_dif_on = 0x0 */ - /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ - /* .. .. reg_phy_dif_off = 0x0 */ - /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_data_slice_in_use = 0x1 */ - /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ - /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_tx = 0x0 */ - /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_board_lpbk_rx = 0x0 */ - /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_shift_dq = 0x0 */ - /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_err_clr = 0x0 */ - /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ - /* .. .. reg_phy_dq_offset = 0x40 */ - /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ - /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ - /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ - /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ - /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), - /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ - /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ - /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ - /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ - /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ - /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ - /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ - /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ - /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), - /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ - /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ - /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ - /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ - /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ - /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ - /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), - /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ - /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ - /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ - /* .. .. reg_phy_fifo_we_in_force = 0x0 */ - /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ - /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ - /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), - /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ - /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), - /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ - /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), - /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ - /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), - /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ - /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ - /* .. .. reg_phy_wr_data_slave_force = 0x0 */ - /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ - /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), - /* .. .. reg_phy_loopback = 0x0 */ - /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_phy_bl2 = 0x0 */ - /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_phy_at_spd_atpg = 0x0 */ - /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_enable = 0x0 */ - /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_force_err = 0x0 */ - /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. reg_phy_bist_mode = 0x0 */ - /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. .. reg_phy_invert_clkout = 0x1 */ - /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ - /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. .. reg_phy_sel_logic = 0x0 */ - /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ - /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ - /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ - /* .. .. reg_phy_ctrl_slave_force = 0x0 */ - /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ - /* .. .. reg_phy_use_rank0_delays = 0x1 */ - /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ - /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ - /* .. .. reg_phy_lpddr = 0x0 */ - /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ - /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ - /* .. .. reg_phy_cmd_latency = 0x0 */ - /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ - /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ - /* .. .. reg_phy_int_lpbk = 0x0 */ - /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ - /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), - /* .. .. reg_phy_wr_rl_delay = 0x2 */ - /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ - /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ - /* .. .. reg_phy_rd_rl_delay = 0x4 */ - /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ - /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ - /* .. .. reg_phy_dll_lock_diff = 0xf */ - /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ - /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ - /* .. .. reg_phy_use_wr_level = 0x1 */ - /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ - /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ - /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ - /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ - /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ - /* .. .. reg_phy_dis_calib_rst = 0x0 */ - /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ - /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), - /* .. .. reg_arb_page_addr_mask = 0x0 */ - /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_wr_portn = 0x3ff */ - /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ - /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_rmw_portn = 0x1 */ - /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_arb_pri_rd_portn = 0x3ff */ - /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ - /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ - /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ - /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ - /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ - /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ - /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), - /* .. .. reg_ddrc_lpddr2 = 0x0 */ - /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ - /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_derate_enable = 0x0 */ - /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. reg_ddrc_mr4_margin = 0x0 */ - /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), - /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ - /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), - /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ - /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ - /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ - /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ - /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ - /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ - /* .. .. reg_ddrc_t_mrw = 0x5 */ - /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ - /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), - /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ - /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ - /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ - /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ - /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ - /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ - /* .. .. */ - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), - /* .. .. START: POLL ON DCI STATUS */ - /* .. .. DONE = 1 */ - /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ - /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. .. */ - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - /* .. .. FINISH: POLL ON DCI STATUS */ - /* .. .. START: UNLOCK DDR */ - /* .. .. reg_ddrc_soft_rstb = 0x1 */ - /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. reg_ddrc_powerdown_en = 0x0 */ - /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. .. reg_ddrc_data_bus_width = 0x0 */ - /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ - /* .. .. reg_ddrc_burst8_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ - /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ - /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ - /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ - /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ - /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ - /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ - /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ - /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), - /* .. .. FINISH: UNLOCK DDR */ - /* .. .. START: CHECK DDR STATUS */ - /* .. .. ddrc_reg_operating_mode = 1 */ - /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ - /* .. .. */ - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - /* .. .. FINISH: CHECK DDR STATUS */ - /* .. FINISH: DDR INITIALIZATION */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_mio_init_data_1_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: OCM REMAPPING */ - /* .. VREF_EN = 0x1 */ - /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. VREF_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. CLK_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. SRSTN_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), - /* .. FINISH: OCM REMAPPING */ - /* .. START: DDRIOB SETTINGS */ - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCR_TYPE = 0x0 */ - /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCR_TYPE = 0x0 */ - /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x1 */ - /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x1 */ - /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x2 */ - /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x2 */ - /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x1 */ - /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. DCR_TYPE = 0x3 */ - /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. IBUF_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0 */ - /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), - /* .. INP_POWER = 0x0 */ - /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. INP_TYPE = 0x0 */ - /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. DCI_UPDATE = 0x0 */ - /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. TERM_EN = 0x0 */ - /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. DCR_TYPE = 0x0 */ - /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ - /* .. IBUF_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. TERM_DISABLE_MODE = 0x0 */ - /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. OUTPUT_EN = 0x3 */ - /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ - /* .. PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x3 */ - /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ - /* .. SLEW_N = 0x3 */ - /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x6 */ - /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. SLEW_N = 0x1f */ - /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x6 */ - /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. SLEW_N = 0x1f */ - /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), - /* .. DRIVE_P = 0x1c */ - /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ - /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ - /* .. DRIVE_N = 0xc */ - /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ - /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ - /* .. SLEW_P = 0x6 */ - /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ - /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ - /* .. SLEW_N = 0x1f */ - /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ - /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ - /* .. GTL = 0x0 */ - /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ - /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ - /* .. RTERM = 0x0 */ - /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ - /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), - /* .. VREF_INT_EN = 0x0 */ - /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. VREF_SEL = 0x0 */ - /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ - /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ - /* .. VREF_EXT_EN = 0x3 */ - /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ - /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ - /* .. VREF_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ - /* .. REFIO_EN = 0x1 */ - /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ - /* .. REFIO_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DRST_B_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. CKE_PULLUP_EN = 0x0 */ - /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ - /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U), - /* .. .. START: ASSERT RESET */ - /* .. .. RESET = 1 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), - /* .. .. FINISH: ASSERT RESET */ - /* .. .. START: DEASSERT RESET */ - /* .. .. RESET = 0 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. .. VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), - /* .. .. FINISH: DEASSERT RESET */ - /* .. .. RESET = 0x1 */ - /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. .. ENABLE = 0x1 */ - /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. .. VRP_TRI = 0x0 */ - /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. .. VRN_TRI = 0x0 */ - /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. .. VRP_OUT = 0x0 */ - /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ - /* .. .. VRN_OUT = 0x1 */ - /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ - /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ - /* .. .. NREF_OPT1 = 0x0 */ - /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ - /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. .. NREF_OPT2 = 0x0 */ - /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ - /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ - /* .. .. NREF_OPT4 = 0x1 */ - /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ - /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ - /* .. .. PREF_OPT1 = 0x0 */ - /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ - /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ - /* .. .. PREF_OPT2 = 0x0 */ - /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ - /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ - /* .. .. UPDATE_CONTROL = 0x0 */ - /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ - /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. .. INIT_COMPLETE = 0x0 */ - /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ - /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. .. TST_CLK = 0x0 */ - /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ - /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. .. TST_HLN = 0x0 */ - /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ - /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. .. TST_HLP = 0x0 */ - /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ - /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. .. TST_RST = 0x0 */ - /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ - /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ - /* .. .. INT_DCI_EN = 0x0 */ - /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ - /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), - /* .. FINISH: DDRIOB SETTINGS */ - /* .. START: MIO PROGRAMMING */ - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000700[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000700[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000700[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000700[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000700[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000700[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000700[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000700[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000700[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000704[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000704[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000704[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000704[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000704[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000704[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000704[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000704[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000704[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000708[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000708[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000708[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000708[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000708[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000708[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000708[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000708[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000708[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800070C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800070C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800070C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800070C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800070C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800070C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800070C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800070C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800070C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000710[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000710[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000710[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000710[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000710[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000710[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000710[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000710[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000710[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000714[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000714[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000714[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000714[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000714[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000714[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000714[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000714[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000714[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000718[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000718[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000718[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000718[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000718[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000718[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000718[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000718[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000718[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800071C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800071C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800071C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800071C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800071C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800071C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800071C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800071C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800071C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000720[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000720[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000720[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000720[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000720[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000720[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000720[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000720[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000720[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000724[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000724[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000724[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000724[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000724[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000724[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000724[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000724[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000724[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000728[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000728[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000728[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000728[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000728[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000728[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000728[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000728[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000728[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800072C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800072C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800072C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800072C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800072C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800072C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800072C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF800072C[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800072C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000730[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000730[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000730[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000730[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000730[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000730[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000730[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000730[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000730[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000734[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000734[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000734[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000734[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000734[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000734[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000734[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000734[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000734[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000738[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000738[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000738[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000738[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000738[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF8000738[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF8000738[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF8000738[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000738[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800073C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800073C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800073C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800073C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800073C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF800073C[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 3 */ - /* .. ==> 0XF800073C[11:9] = 0x00000003U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF800073C[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800073C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000740[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000740[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000740[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000740[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000740[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000740[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000740[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000740[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000740[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000744[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000744[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000744[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000744[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000744[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000744[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000744[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000744[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000744[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000748[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000748[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000748[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000748[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000748[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000748[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000748[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000748[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000748[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800074C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800074C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800074C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800074C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800074C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800074C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800074C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800074C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF800074C[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000750[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000750[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000750[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000750[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000750[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000750[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000750[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000750[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000750[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000754[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000754[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000754[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000754[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000754[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000754[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000754[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000754[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 1 */ - /* .. ==> 0XF8000754[13:13] = 0x00000001U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000758[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000758[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000758[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000758[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000758[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000758[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000758[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000758[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000758[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800075C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800075C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800075C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800075C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800075C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800075C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800075C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800075C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800075C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000760[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000760[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000760[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000760[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000760[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000760[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000760[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000760[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000760[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000764[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000764[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000764[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000764[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000764[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000764[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000764[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000764[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000764[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000768[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF8000768[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF8000768[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000768[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000768[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000768[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF8000768[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000768[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000768[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800076C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 1 */ - /* .. ==> 0XF800076C[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF800076C[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800076C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800076C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800076C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 4 */ - /* .. ==> 0XF800076C[11:9] = 0x00000004U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800076C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800076C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000770[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000770[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000770[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000770[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000770[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000770[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000770[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000770[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000770[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000774[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000774[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000774[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000774[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000774[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000774[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000774[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000774[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000774[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000778[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000778[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000778[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000778[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000778[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000778[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000778[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000778[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000778[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF800077C[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800077C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800077C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800077C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800077C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800077C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800077C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800077C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800077C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000780[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000780[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000780[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000780[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000780[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000780[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000780[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000780[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000780[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000784[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000784[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000784[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000784[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000784[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000784[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000784[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000784[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000784[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000788[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000788[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000788[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000788[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000788[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000788[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000788[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000788[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000788[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800078C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800078C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800078C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800078C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800078C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800078C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800078C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800078C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800078C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF8000790[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000790[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000790[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000790[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000790[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000790[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000790[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000790[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000790[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000794[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000794[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000794[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000794[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000794[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000794[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000794[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000794[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000794[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF8000798[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF8000798[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF8000798[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF8000798[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF8000798[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF8000798[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF8000798[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF8000798[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF8000798[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF800079C[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF800079C[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 1 */ - /* .. ==> 0XF800079C[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF800079C[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF800079C[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 1 */ - /* .. ==> 0XF800079C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF800079C[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF800079C[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF800079C[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 1 */ - /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 1 */ - /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 7 */ - /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), - /* .. TRI_ENABLE = 1 */ - /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 7 */ - /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 0 */ - /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), - /* .. TRI_ENABLE = 0 */ - /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. L0_SEL = 0 */ - /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. L1_SEL = 0 */ - /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. L2_SEL = 0 */ - /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ - /* .. L3_SEL = 4 */ - /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ - /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ - /* .. Speed = 0 */ - /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. IO_Type = 1 */ - /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ - /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ - /* .. PULLUP = 0 */ - /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. DisableRcvr = 0 */ - /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), - /* .. SDIO0_WP_SEL = 55 */ - /* .. ==> 0XF8000830[5:0] = 0x00000037U */ - /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ - /* .. SDIO0_CD_SEL = 47 */ - /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ - /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), - /* .. FINISH: MIO PROGRAMMING */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), - /* .. IBUF_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ - /* .. TERM_DISABLE_MODE = 0x1 */ - /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ - /* .. */ - EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), - /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* .. START: SRAM/NOR SET OPMODE */ - /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. IRMODE = 0x0 */ - /* .. ==> 0XE0001004[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. UCLKEN = 0x0 */ - /* .. ==> 0XE0001004[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ - /* .. START: QSPI REGISTERS */ - /* .. Holdb_dr = 1 */ - /* .. ==> 0XE000D000[19:19] = 0x00000001U */ - /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ - /* .. */ - EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), - /* .. FINISH: QSPI REGISTERS */ - /* .. START: PL POWER ON RESET REGISTERS */ - /* .. PCFG_POR_CNT_4K = 0 */ - /* .. ==> 0XF8007000[29:29] = 0x00000000U */ - /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), - /* .. FINISH: PL POWER ON RESET REGISTERS */ - /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ - /* .. .. START: NAND SET CYCLE */ - /* .. .. FINISH: NAND SET CYCLE */ - /* .. .. START: OPMODE */ - /* .. .. FINISH: OPMODE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: SRAM/NOR CS0 SET CYCLE */ - /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: NOR CS0 BASE ADDRESS */ - /* .. .. FINISH: NOR CS0 BASE ADDRESS */ - /* .. .. START: SRAM/NOR CS1 SET CYCLE */ - /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ - /* .. .. START: DIRECT COMMAND */ - /* .. .. FINISH: DIRECT COMMAND */ - /* .. .. START: NOR CS1 BASE ADDRESS */ - /* .. .. FINISH: NOR CS1 BASE ADDRESS */ - /* .. .. START: USB RESET */ - /* .. .. .. START: USB0 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. DIRECTION_1 = 0x4000 */ - /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x4000 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ - /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x0 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. MASK_1_LSW = 0xbfff */ - /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ - /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ - /* .. .. .. .. DATA_1_LSW = 0x4000 */ - /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ - /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ - /* .. .. .. .. */ - EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: USB0 RESET */ - /* .. .. .. START: USB1 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: USB1 RESET */ - /* .. .. FINISH: USB RESET */ - /* .. .. START: ENET RESET */ - /* .. .. .. START: ENET0 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: ENET0 RESET */ - /* .. .. .. START: ENET1 RESET */ - /* .. .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. .. START: DIR MODE BANK 1 */ - /* .. .. .. .. FINISH: DIR MODE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: ENET1 RESET */ - /* .. .. FINISH: ENET RESET */ - /* .. .. START: I2C RESET */ - /* .. .. .. START: I2C0 RESET */ - /* .. .. .. .. START: DIR MODE GPIO BANK0 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ - /* .. .. .. .. START: DIR MODE GPIO BANK1 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: I2C0 RESET */ - /* .. .. .. START: I2C1 RESET */ - /* .. .. .. .. START: DIR MODE GPIO BANK0 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ - /* .. .. .. .. START: DIR MODE GPIO BANK1 */ - /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: OUTPUT ENABLE */ - /* .. .. .. .. FINISH: OUTPUT ENABLE */ - /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ - /* .. .. .. .. START: ADD 1 MS DELAY */ - /* .. .. .. .. */ - EMIT_MASKDELAY(0XF8F00200, 1), - /* .. .. .. .. FINISH: ADD 1 MS DELAY */ - /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ - /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ - /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ - /* .. .. .. FINISH: I2C1 RESET */ - /* .. .. FINISH: I2C RESET */ - /* .. .. START: NOR CHIP SELECT */ - /* .. .. .. START: DIR MODE BANK 0 */ - /* .. .. .. FINISH: DIR MODE BANK 0 */ - /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ - /* .. .. .. START: OUTPUT ENABLE BANK 0 */ - /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ - /* .. .. FINISH: NOR CHIP SELECT */ - /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_post_config_1_0[] = { - /* START: top */ - /* .. START: SLCR SETTINGS */ - /* .. UNLOCK_KEY = 0XDF0D */ - /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ - /* .. */ - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - /* .. FINISH: SLCR SETTINGS */ - /* .. START: ENABLING LEVEL SHIFTER */ - /* .. USER_INP_ICT_EN_0 = 3 */ - /* .. ==> 0XF8000900[1:0] = 0x00000003U */ - /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ - /* .. USER_INP_ICT_EN_1 = 3 */ - /* .. ==> 0XF8000900[3:2] = 0x00000003U */ - /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ - /* .. */ - EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), - /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: FPGA RESETS TO 0 */ - /* .. reserved_3 = 0 */ - /* .. ==> 0XF8000240[31:25] = 0x00000000U */ - /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ - /* .. FPGA_ACP_RST = 0 */ - /* .. ==> 0XF8000240[24:24] = 0x00000000U */ - /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ - /* .. FPGA_AXDS3_RST = 0 */ - /* .. ==> 0XF8000240[23:23] = 0x00000000U */ - /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ - /* .. FPGA_AXDS2_RST = 0 */ - /* .. ==> 0XF8000240[22:22] = 0x00000000U */ - /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ - /* .. FPGA_AXDS1_RST = 0 */ - /* .. ==> 0XF8000240[21:21] = 0x00000000U */ - /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ - /* .. FPGA_AXDS0_RST = 0 */ - /* .. ==> 0XF8000240[20:20] = 0x00000000U */ - /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ - /* .. reserved_2 = 0 */ - /* .. ==> 0XF8000240[19:18] = 0x00000000U */ - /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ - /* .. FSSW1_FPGA_RST = 0 */ - /* .. ==> 0XF8000240[17:17] = 0x00000000U */ - /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ - /* .. FSSW0_FPGA_RST = 0 */ - /* .. ==> 0XF8000240[16:16] = 0x00000000U */ - /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ - /* .. reserved_1 = 0 */ - /* .. ==> 0XF8000240[15:14] = 0x00000000U */ - /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ - /* .. FPGA_FMSW1_RST = 0 */ - /* .. ==> 0XF8000240[13:13] = 0x00000000U */ - /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ - /* .. FPGA_FMSW0_RST = 0 */ - /* .. ==> 0XF8000240[12:12] = 0x00000000U */ - /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ - /* .. FPGA_DMA3_RST = 0 */ - /* .. ==> 0XF8000240[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. FPGA_DMA2_RST = 0 */ - /* .. ==> 0XF8000240[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. FPGA_DMA1_RST = 0 */ - /* .. ==> 0XF8000240[9:9] = 0x00000000U */ - /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ - /* .. FPGA_DMA0_RST = 0 */ - /* .. ==> 0XF8000240[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. reserved = 0 */ - /* .. ==> 0XF8000240[7:4] = 0x00000000U */ - /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ - /* .. FPGA3_OUT_RST = 0 */ - /* .. ==> 0XF8000240[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. FPGA2_OUT_RST = 0 */ - /* .. ==> 0XF8000240[2:2] = 0x00000000U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ - /* .. FPGA1_OUT_RST = 0 */ - /* .. ==> 0XF8000240[1:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ - /* .. FPGA0_OUT_RST = 0 */ - /* .. ==> 0XF8000240[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), - /* .. FINISH: FPGA RESETS TO 0 */ - /* .. START: AFI REGISTERS */ - /* .. .. START: AFI0 REGISTERS */ - /* .. .. FINISH: AFI0 REGISTERS */ - /* .. .. START: AFI1 REGISTERS */ - /* .. .. FINISH: AFI1 REGISTERS */ - /* .. .. START: AFI2 REGISTERS */ - /* .. .. FINISH: AFI2 REGISTERS */ - /* .. .. START: AFI3 REGISTERS */ - /* .. .. FINISH: AFI3 REGISTERS */ - /* .. FINISH: AFI REGISTERS */ - /* .. START: LOCK IT BACK */ - /* .. LOCK_KEY = 0X767B */ - /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ - /* .. */ - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - /* .. FINISH: LOCK IT BACK */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -unsigned long ps7_debug_1_0[] = { - /* START: top */ - /* .. START: CROSS TRIGGER CONFIGURATIONS */ - /* .. .. START: UNLOCKING CTI REGISTERS */ - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: UNLOCKING CTI REGISTERS */ - /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char *getPS7MessageInfo(unsigned key) -{ - char *err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: - err_msg = "PS7 initialization successful"; - break; - case PS7_INIT_CORRUPT: - err_msg = "PS7 init Data Corrupted"; - break; - case PS7_INIT_TIMEOUT: - err_msg = "PS7 init mask poll timeout"; - break; - case PS7_POLL_FAILED_DDR_INIT: - err_msg = "Mask Poll failed for DDR Init"; - break; - case PS7_POLL_FAILED_DMA: - err_msg = "Mask Poll failed for PLL Init"; - break; - case PS7_POLL_FAILED_PLL: - err_msg = "Mask Poll failed for DMA done bit"; - break; - default: - err_msg = "Undefined error status"; - break; - } - - return err_msg; -} - -unsigned long ps7GetSiliconVersion(void) -{ - /* Read PS version from MCTRL register [31:28] */ - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long *)0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write(unsigned long add, unsigned long mask, unsigned long val) -{ - unsigned long *addr = (unsigned long *)add; - *addr = (val & mask) | (*addr & ~mask); -} - -int mask_poll(unsigned long add, unsigned long mask) -{ - volatile unsigned long *addr = (volatile unsigned long *)add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) - return -1; - i++; - } - return 1; -} - -unsigned long mask_read(unsigned long add, unsigned long mask) -{ - unsigned long *addr = (unsigned long *)add; - unsigned long val = (*addr & mask); - return val; -} - -int ps7_config(unsigned long *ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; /* current instruction .. */ - unsigned long args[16]; /* no opcode has so many args ... */ - int numargs; /* number of arguments of this instruction */ - int j; /* general purpose index */ - - volatile unsigned long *addr; /* some variable to make code readable */ - unsigned long val, mask; /* some variable to make code readable */ - - int finish = -1; /* loop while this is negative ! */ - int i = 0; /* Timeout variable */ - - while (finish < 0) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for (j = 0; j < numargs; j++) - args[j] = ptr[j + 1]; - ptr += numargs + 1; - - switch (opcode) { - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long *)args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long *)args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long *)args[0]; - mask = args[1]; - val = args[2]; - *addr = (val & mask) | (*addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long *)args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long *)args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) - ; - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int ps7_post_config(void) -{ - /* Get the PS_VERSION on run time */ - unsigned long si_ver = ps7GetSiliconVersion(); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config(ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config(ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } else { - ret = ps7_config(ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } - return PS7_INIT_SUCCESS; -} - -int ps7_debug(void) -{ - /* Get the PS_VERSION on run time */ - unsigned long si_ver = ps7GetSiliconVersion(); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config(ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config(ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } else { - ret = ps7_config(ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } - return PS7_INIT_SUCCESS; -} - -int ps7_init(void) -{ - /* Get the PS_VERSION on run time */ - unsigned long si_ver = ps7GetSiliconVersion(); - int ret; - /*int pcw_ver = 0; */ - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - /*pcw_ver = 1; */ - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - /*pcw_ver = 2; */ - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - /*pcw_ver = 3; */ - } - - /* MIO init */ - ret = ps7_config(ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) - return ret; - - /* PLL init */ - ret = ps7_config(ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) - return ret; - - /* Clock init */ - ret = ps7_config(ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) - return ret; - - /* DDR init */ - ret = ps7_config(ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) - return ret; - - /* Peripherals init */ - ret = ps7_config(ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) - return ret; - return PS7_INIT_SUCCESS; -} - -/* For delay calculation using global timer */ - -/* start timer */ -void perf_start_clock(void) -{ - *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */ - (1 << 3) | /* Auto-increment */ - (0 << 8) /* Pre-scale */ - ); -} - -/* stop timer and reset timer count regs */ -void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */ - return APU_FREQ * delay / (2 * 1000); -} - -/* stop timer */ -void perf_disable_clock(void) -{ - *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer(void) -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h deleted file mode 100644 index 22d9fd9..0000000 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/*typedef unsigned int u32; */ - -/** do we need to make this name more unique ? **/ -/*extern u32 ps7_init_data[]; */ -extern unsigned long *ps7_ddr_init_data; -extern unsigned long *ps7_mio_init_data; -extern unsigned long *ps7_pll_init_data; -extern unsigned long *ps7_clock_init_data; -extern unsigned long *ps7_peripherals_init_data; - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) -#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr -#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val -#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val -#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask -#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ -#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ -#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ -#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ -#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ -#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 650000000 -#define DDR_FREQ 525000000 -#define DCI_FREQ 10096154 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 100000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 108333336 -#define WDT_FREQ 108333336 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 142857132 -#define FPGA2_FREQ 200000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config(unsigned long *); -int ps7_init(void); -int ps7_post_config(void); -int ps7_debug(void); -char *getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(void); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c new file mode 100644 index 0000000..eb29002 --- /dev/null +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -0,0 +1,12963 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000170[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x1e + // .. ==> 0XF8000190[13:8] = 0x0000001EU + // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xb0 + // .. .. ==> 0XF800612C[19:10] = 0x000000B0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xb1 + // .. .. ==> 0XF8006130[19:10] = 0x000000B1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006134[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xbc + // .. .. ==> 0XF8006134[19:10] = 0x000000BCU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006138[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xbb + // .. .. ==> 0XF8006138[19:10] = 0x000000BBU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 + // .. .. ==> 0XF8006154[9:0] = 0x00000077U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 + // .. .. ==> 0XF8006158[9:0] = 0x00000077U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF800615C[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006160[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x105 + // .. .. ==> 0XF8006168[10:0] = 0x00000105U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x106 + // .. .. ==> 0XF800616C[10:0] = 0x00000106U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x111 + // .. .. ==> 0XF8006170[10:0] = 0x00000111U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x110 + // .. .. ==> 0XF8006174[10:0] = 0x00000110U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), + // .. .. reg_phy_wr_data_slave_ratio = 0xb7 + // .. .. ==> 0XF800617C[9:0] = 0x000000B7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xb7 + // .. .. ==> 0XF8006180[9:0] = 0x000000B7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006184[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006188[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 50 + // .. ==> 0XF8000830[5:0] = 0x00000032U + // .. ==> MASK : 0x0000003FU VAL : 0x00000032U + // .. SDIO0_CD_SEL = 46 + // .. ==> 0XF8000830[21:16] = 0x0000002EU + // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000170[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x1e + // .. ==> 0XF8000190[13:8] = 0x0000001EU + // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xb0 + // .. .. ==> 0XF800612C[19:10] = 0x000000B0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xb1 + // .. .. ==> 0XF8006130[19:10] = 0x000000B1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006134[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xbc + // .. .. ==> 0XF8006134[19:10] = 0x000000BCU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006138[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xbb + // .. .. ==> 0XF8006138[19:10] = 0x000000BBU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 + // .. .. ==> 0XF8006154[9:0] = 0x00000077U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 + // .. .. ==> 0XF8006158[9:0] = 0x00000077U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF800615C[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006160[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x105 + // .. .. ==> 0XF8006168[10:0] = 0x00000105U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x106 + // .. .. ==> 0XF800616C[10:0] = 0x00000106U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x111 + // .. .. ==> 0XF8006170[10:0] = 0x00000111U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x110 + // .. .. ==> 0XF8006174[10:0] = 0x00000110U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), + // .. .. reg_phy_wr_data_slave_ratio = 0xb7 + // .. .. ==> 0XF800617C[9:0] = 0x000000B7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xb7 + // .. .. ==> 0XF8006180[9:0] = 0x000000B7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006184[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006188[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 50 + // .. ==> 0XF8000830[5:0] = 0x00000032U + // .. ==> MASK : 0x0000003FU VAL : 0x00000032U + // .. SDIO0_CD_SEL = 46 + // .. ==> 0XF8000830[21:16] = 0x0000002EU + // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000170[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x1e + // .. ==> 0XF8000190[13:8] = 0x0000001EU + // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xb0 + // .. .. ==> 0XF800612C[19:10] = 0x000000B0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xb1 + // .. .. ==> 0XF8006130[19:10] = 0x000000B1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006134[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xbc + // .. .. ==> 0XF8006134[19:10] = 0x000000BCU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006138[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xbb + // .. .. ==> 0XF8006138[19:10] = 0x000000BBU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 + // .. .. ==> 0XF8006154[9:0] = 0x00000077U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x77 + // .. .. ==> 0XF8006158[9:0] = 0x00000077U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF800615C[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006160[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x105 + // .. .. ==> 0XF8006168[10:0] = 0x00000105U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x106 + // .. .. ==> 0XF800616C[10:0] = 0x00000106U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x111 + // .. .. ==> 0XF8006170[10:0] = 0x00000111U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x110 + // .. .. ==> 0XF8006174[10:0] = 0x00000110U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U), + // .. .. reg_phy_wr_data_slave_ratio = 0xb7 + // .. .. ==> 0XF800617C[9:0] = 0x000000B7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xb7 + // .. .. ==> 0XF8006180[9:0] = 0x000000B7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006184[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006188[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 50 + // .. ==> 0XF8000830[5:0] = 0x00000032U + // .. ==> MASK : 0x0000003FU VAL : 0x00000032U + // .. SDIO0_CD_SEL = 46 + // .. ==> 0XF8000830[21:16] = 0x0000002EU + // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h new file mode 100644 index 0000000..bdea5a0 --- /dev/null +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h @@ -0,0 +1,117 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 33333336 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c new file mode 100644 index 0000000..abfd911 --- /dev/null +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -0,0 +1,13296 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B00[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x800 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x800 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2000 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2000 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h new file mode 100644 index 0000000..16fa810 --- /dev/null +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h @@ -0,0 +1,117 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 25000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 23809523 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 50000000 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c new file mode 100644 index 0000000..77fd949 --- /dev/null +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -0,0 +1,13203 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1e + // .. .. ==> 0XF800612C[9:0] = 0x0000001EU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF800612C[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), + // .. .. reg_phy_wrlvl_init_ratio = 0x25 + // .. .. ==> 0XF8006130[9:0] = 0x00000025U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U + // .. .. reg_phy_gatelvl_init_ratio = 0x10d + // .. .. ==> 0XF8006130[19:10] = 0x0000010DU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), + // .. .. reg_phy_wrlvl_init_ratio = 0x19 + // .. .. ==> 0XF8006134[9:0] = 0x00000019U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U + // .. .. reg_phy_gatelvl_init_ratio = 0xf3 + // .. .. ==> 0XF8006134[19:10] = 0x000000F3U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), + // .. .. reg_phy_wrlvl_init_ratio = 0x2a + // .. .. ==> 0XF8006138[9:0] = 0x0000002AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU + // .. .. reg_phy_gatelvl_init_ratio = 0x109 + // .. .. ==> 0XF8006138[19:10] = 0x00000109U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e + // .. .. ==> 0XF8006154[9:0] = 0x0000009EU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5 + // .. .. ==> 0XF8006158[9:0] = 0x000000A5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x99 + // .. .. ==> 0XF800615C[9:0] = 0x00000099U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa + // .. .. ==> 0XF8006160[9:0] = 0x000000AAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006168[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x162 + // .. .. ==> 0XF800616C[10:0] = 0x00000162U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x148 + // .. .. ==> 0XF8006170[10:0] = 0x00000148U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x15e + // .. .. ==> 0XF8006174[10:0] = 0x0000015EU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU), + // .. .. reg_phy_wr_data_slave_ratio = 0xde + // .. .. ==> 0XF800617C[9:0] = 0x000000DEU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe5 + // .. .. ==> 0XF8006180[9:0] = 0x000000E5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xd9 + // .. .. ==> 0XF8006184[9:0] = 0x000000D9U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xea + // .. .. ==> 0XF8006188[9:0] = 0x000000EAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B00[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000700[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000724[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000728[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800072C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000730[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000734[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 14 + // .. ==> 0XF8000830[21:16] = 0x0000000EU + // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1e + // .. .. ==> 0XF800612C[9:0] = 0x0000001EU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF800612C[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), + // .. .. reg_phy_wrlvl_init_ratio = 0x25 + // .. .. ==> 0XF8006130[9:0] = 0x00000025U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U + // .. .. reg_phy_gatelvl_init_ratio = 0x10d + // .. .. ==> 0XF8006130[19:10] = 0x0000010DU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), + // .. .. reg_phy_wrlvl_init_ratio = 0x19 + // .. .. ==> 0XF8006134[9:0] = 0x00000019U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U + // .. .. reg_phy_gatelvl_init_ratio = 0xf3 + // .. .. ==> 0XF8006134[19:10] = 0x000000F3U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), + // .. .. reg_phy_wrlvl_init_ratio = 0x2a + // .. .. ==> 0XF8006138[9:0] = 0x0000002AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU + // .. .. reg_phy_gatelvl_init_ratio = 0x109 + // .. .. ==> 0XF8006138[19:10] = 0x00000109U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e + // .. .. ==> 0XF8006154[9:0] = 0x0000009EU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5 + // .. .. ==> 0XF8006158[9:0] = 0x000000A5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x99 + // .. .. ==> 0XF800615C[9:0] = 0x00000099U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa + // .. .. ==> 0XF8006160[9:0] = 0x000000AAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006168[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x162 + // .. .. ==> 0XF800616C[10:0] = 0x00000162U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x148 + // .. .. ==> 0XF8006170[10:0] = 0x00000148U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x15e + // .. .. ==> 0XF8006174[10:0] = 0x0000015EU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU), + // .. .. reg_phy_wr_data_slave_ratio = 0xde + // .. .. ==> 0XF800617C[9:0] = 0x000000DEU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe5 + // .. .. ==> 0XF8006180[9:0] = 0x000000E5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xd9 + // .. .. ==> 0XF8006184[9:0] = 0x000000D9U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xea + // .. .. ==> 0XF8006188[9:0] = 0x000000EAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000700[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000724[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000728[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800072C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000730[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000734[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 14 + // .. ==> 0XF8000830[21:16] = 0x0000000EU + // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1e + // .. .. ==> 0XF800612C[9:0] = 0x0000001EU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF800612C[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU), + // .. .. reg_phy_wrlvl_init_ratio = 0x25 + // .. .. ==> 0XF8006130[9:0] = 0x00000025U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U + // .. .. reg_phy_gatelvl_init_ratio = 0x10d + // .. .. ==> 0XF8006130[19:10] = 0x0000010DU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U), + // .. .. reg_phy_wrlvl_init_ratio = 0x19 + // .. .. ==> 0XF8006134[9:0] = 0x00000019U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U + // .. .. reg_phy_gatelvl_init_ratio = 0xf3 + // .. .. ==> 0XF8006134[19:10] = 0x000000F3U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U), + // .. .. reg_phy_wrlvl_init_ratio = 0x2a + // .. .. ==> 0XF8006138[9:0] = 0x0000002AU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU + // .. .. reg_phy_gatelvl_init_ratio = 0x109 + // .. .. ==> 0XF8006138[19:10] = 0x00000109U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e + // .. .. ==> 0XF8006154[9:0] = 0x0000009EU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5 + // .. .. ==> 0XF8006158[9:0] = 0x000000A5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x99 + // .. .. ==> 0XF800615C[9:0] = 0x00000099U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa + // .. .. ==> 0XF8006160[9:0] = 0x000000AAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006168[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x162 + // .. .. ==> 0XF800616C[10:0] = 0x00000162U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x148 + // .. .. ==> 0XF8006170[10:0] = 0x00000148U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x15e + // .. .. ==> 0XF8006174[10:0] = 0x0000015EU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU), + // .. .. reg_phy_wr_data_slave_ratio = 0xde + // .. .. ==> 0XF800617C[9:0] = 0x000000DEU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe5 + // .. .. ==> 0XF8006180[9:0] = 0x000000E5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xd9 + // .. .. ==> 0XF8006184[9:0] = 0x000000D9U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xea + // .. .. ==> 0XF8006188[9:0] = 0x000000EAU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000700[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000724[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000728[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800072C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000730[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000734[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 14 + // .. ==> 0XF8000830[21:16] = 0x0000000EU + // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. DIRECTION_1 = 0x8000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. OP_ENABLE_1 = 0x8000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0x7fff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U + // .. .. .. .. DATA_1_LSW = 0x8000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. DIRECTION_1 = 0x4000 + // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_1 = 0x4000 + // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x0 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. MASK_1_LSW = 0xbfff + // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U + // .. .. .. .. DATA_1_LSW = 0x4000 + // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U), + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h new file mode 100644 index 0000000..8527eef --- /dev/null +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h @@ -0,0 +1,117 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 25000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 50000000 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c new file mode 100644 index 0000000..f4f45be --- /dev/null +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -0,0 +1,12861 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000170[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF8000180[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x18 + // .. .. ==> 0XF8006018[15:10] = 0x00000018U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0xf + // .. .. ==> 0XF8006044[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF800612C[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xcf + // .. .. ==> 0XF800612C[19:10] = 0x000000CFU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006130[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xd0 + // .. .. ==> 0XF8006130[19:10] = 0x000000D0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xbd + // .. .. ==> 0XF8006134[19:10] = 0x000000BDU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xc1 + // .. .. ==> 0XF8006138[19:10] = 0x000000C1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006154[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006158[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f + // .. .. ==> 0XF800615C[9:0] = 0x0000007FU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x78 + // .. .. ==> 0XF8006160[9:0] = 0x00000078U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x124 + // .. .. ==> 0XF8006168[10:0] = 0x00000124U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x125 + // .. .. ==> 0XF800616C[10:0] = 0x00000125U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x112 + // .. .. ==> 0XF8006170[10:0] = 0x00000112U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x116 + // .. .. ==> 0XF8006174[10:0] = 0x00000116U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF800617C[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006180[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbf + // .. .. ==> 0XF8006184[9:0] = 0x000000BFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb8 + // .. .. ==> 0XF8006188[9:0] = 0x000000B8U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000704[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000708[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800070C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000710[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000714[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000718[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000720[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A0[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A4[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A8[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007AC[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007B0[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007B4[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007CC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 46 + // .. ==> 0XF8000830[5:0] = 0x0000002EU + // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000170[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF8000180[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x18 + // .. .. ==> 0XF8006018[15:10] = 0x00000018U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0xf + // .. .. ==> 0XF8006044[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF800612C[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xcf + // .. .. ==> 0XF800612C[19:10] = 0x000000CFU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006130[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xd0 + // .. .. ==> 0XF8006130[19:10] = 0x000000D0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xbd + // .. .. ==> 0XF8006134[19:10] = 0x000000BDU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xc1 + // .. .. ==> 0XF8006138[19:10] = 0x000000C1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006154[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006158[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f + // .. .. ==> 0XF800615C[9:0] = 0x0000007FU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x78 + // .. .. ==> 0XF8006160[9:0] = 0x00000078U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x124 + // .. .. ==> 0XF8006168[10:0] = 0x00000124U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x125 + // .. .. ==> 0XF800616C[10:0] = 0x00000125U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x112 + // .. .. ==> 0XF8006170[10:0] = 0x00000112U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x116 + // .. .. ==> 0XF8006174[10:0] = 0x00000116U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF800617C[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006180[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbf + // .. .. ==> 0XF8006184[9:0] = 0x000000BFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb8 + // .. .. ==> 0XF8006188[9:0] = 0x000000B8U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000704[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000708[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800070C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000710[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000714[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000718[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000720[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A0[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A4[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A8[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007AC[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007B0[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007B4[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007CC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 46 + // .. ==> 0XF8000830[5:0] = 0x0000002EU + // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xa + // .. ==> 0XF8000170[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF8000180[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x18 + // .. .. ==> 0XF8006018[15:10] = 0x00000018U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0xf + // .. .. ==> 0XF8006044[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF800612C[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xcf + // .. .. ==> 0XF800612C[19:10] = 0x000000CFU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U), + // .. .. reg_phy_wrlvl_init_ratio = 0x3 + // .. .. ==> 0XF8006130[9:0] = 0x00000003U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U + // .. .. reg_phy_gatelvl_init_ratio = 0xd0 + // .. .. ==> 0XF8006130[19:10] = 0x000000D0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xbd + // .. .. ==> 0XF8006134[19:10] = 0x000000BDU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xc1 + // .. .. ==> 0XF8006138[19:10] = 0x000000C1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006154[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x83 + // .. .. ==> 0XF8006158[9:0] = 0x00000083U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f + // .. .. ==> 0XF800615C[9:0] = 0x0000007FU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x78 + // .. .. ==> 0XF8006160[9:0] = 0x00000078U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x124 + // .. .. ==> 0XF8006168[10:0] = 0x00000124U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x125 + // .. .. ==> 0XF800616C[10:0] = 0x00000125U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x112 + // .. .. ==> 0XF8006170[10:0] = 0x00000112U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x116 + // .. .. ==> 0XF8006174[10:0] = 0x00000116U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF800617C[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc3 + // .. .. ==> 0XF8006180[9:0] = 0x000000C3U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbf + // .. .. ==> 0XF8006184[9:0] = 0x000000BFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU), + // .. .. reg_phy_wr_data_slave_ratio = 0xb8 + // .. .. ==> 0XF8006188[9:0] = 0x000000B8U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000704[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000708[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800070C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000710[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000714[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000718[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000720[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800073C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000770[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000774[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000778[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800077C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000780[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000784[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000788[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800078C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000790[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000794[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000798[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800079C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A0[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A4[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007A8[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007AC[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007B0[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 1 + // .. ==> 0XF80007B4[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007BC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007CC[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 46 + // .. ==> 0XF8000830[5:0] = 0x0000002EU + // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU + // .. SDIO0_CD_SEL = 47 + // .. ==> 0XF8000830[21:16] = 0x0000002FU + // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h new file mode 100644 index 0000000..9b41e28 --- /dev/null +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h @@ -0,0 +1,117 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* SPDX-License-Identifier: GPL-2.0+ +* +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 142857132 +#define FPGA2_FREQ 50000000 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c new file mode 100644 index 0000000..83daf7b --- /dev/null +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c @@ -0,0 +1,13045 @@ +/* + * Copyright (c) Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ + /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ + /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ + /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_t_cksre = 0x6 */ + /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_t_cksrx = 0x6 */ + /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_t_ckesr = 0x4 */ + /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + /* .. .. reg_ddrc_t_ckpde = 0x2 */ + /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_ckpdx = 0x2 */ + /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ + /* .. .. reg_ddrc_t_ckdpde = 0x2 */ + /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ + /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ + /* .. .. reg_ddrc_t_ckcsx = 0x3 */ + /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B00[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. reserved_SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. reserved_VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. reserved_REFIO_TEST = 0x0 */ + /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ + /* .. reserved_REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. reserved_DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. reserved_CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reserved_VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reserved_VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reserved_VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reserved_VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reserved_VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reserved_INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reserved_TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reserved_TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reserved_TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. reserved_TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reserved_INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_LVL_INP_EN_0 = 1 */ + /* .. ==> 0XF8000900[3:3] = 0x00000001U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. USER_LVL_OUT_EN_0 = 1 */ + /* .. ==> 0XF8000900[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. USER_LVL_INP_EN_1 = 1 */ + /* .. ==> 0XF8000900[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. USER_LVL_OUT_EN_1 = 1 */ + /* .. ==> 0XF8000900[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. reserved_FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. reserved_FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. reserved_FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. reserved_FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. reserved_FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. .. START: AFI2 SECURE REGISTER */ + /* .. .. FINISH: AFI2 SECURE REGISTER */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_3_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_pll_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_block = 0x1 */ + /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ + /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ + /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ + /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ + /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_sdram = 0x1 */ + /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_clock_stop_en = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_loopback = 0x0 */ + /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_max_rank_rd = 0xf */ + /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_debug_mode = 0x0 */ + /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_dq0_wait_t = 0x0 */ + /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ + /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ + /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ + /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ + /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ + /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_t_cksre = 0x6 */ + /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_t_cksrx = 0x6 */ + /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_t_ckesr = 0x4 */ + /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + /* .. .. reg_ddrc_t_ckpde = 0x2 */ + /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_ckpdx = 0x2 */ + /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ + /* .. .. reg_ddrc_t_ckdpde = 0x2 */ + /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ + /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ + /* .. .. reg_ddrc_t_ckcsx = 0x3 */ + /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + /* .. .. refresh_timer0_start_value_x32 = 0x0 */ + /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ + /* .. .. refresh_timer1_start_value_x32 = 0x8 */ + /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_2t_delay = 0x0 */ + /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ + /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_loopback = 0x0 */ + /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ + /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_rank0_delays = 0x1 */ + /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_phy_int_lpbk = 0x0 */ + /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ + /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. CLK_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. SRSTN_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. REFIO_TEST = 0x0 */ + /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ + /* .. REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. IRMODE = 0x0 */ + /* .. ==> 0XE0001004[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. UCLKEN = 0x0 */ + /* .. ==> 0XE0001004[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_INP_ICT_EN_0 = 3 */ + /* .. ==> 0XF8000900[1:0] = 0x00000003U */ + /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ + /* .. USER_INP_ICT_EN_1 = 3 */ + /* .. ==> 0XF8000900[3:2] = 0x00000003U */ + /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_2_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_pll_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_block = 0x1 */ + /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ + /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ + /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ + /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ + /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_sdram = 0x1 */ + /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_clock_stop_en = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_loopback = 0x0 */ + /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_max_rank_rd = 0xf */ + /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_debug_mode = 0x0 */ + /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_dq0_wait_t = 0x0 */ + /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ + /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ + /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. refresh_timer0_start_value_x32 = 0x0 */ + /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ + /* .. .. refresh_timer1_start_value_x32 = 0x8 */ + /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_2t_delay = 0x0 */ + /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ + /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_loopback = 0x0 */ + /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ + /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_rank0_delays = 0x1 */ + /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_phy_int_lpbk = 0x0 */ + /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ + /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. CLK_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. SRSTN_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. IRMODE = 0x0 */ + /* .. ==> 0XE0001004[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. UCLKEN = 0x0 */ + /* .. ==> 0XE0001004[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_INP_ICT_EN_0 = 3 */ + /* .. ==> 0XF8000900[1:0] = 0x00000003U */ + /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ + /* .. USER_INP_ICT_EN_1 = 3 */ + /* .. ==> 0XF8000900[3:2] = 0x00000003U */ + /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_1_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char *getPS7MessageInfo(unsigned key) +{ + char *err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: + err_msg = "PS7 initialization successful"; + break; + case PS7_INIT_CORRUPT: + err_msg = "PS7 init Data Corrupted"; + break; + case PS7_INIT_TIMEOUT: + err_msg = "PS7 init mask poll timeout"; + break; + case PS7_POLL_FAILED_DDR_INIT: + err_msg = "Mask Poll failed for DDR Init"; + break; + case PS7_POLL_FAILED_DMA: + err_msg = "Mask Poll failed for PLL Init"; + break; + case PS7_POLL_FAILED_PLL: + err_msg = "Mask Poll failed for DMA done bit"; + break; + default: + err_msg = "Undefined error status"; + break; + } + + return err_msg; +} + +unsigned long ps7GetSiliconVersion(void) +{ + /* Read PS version from MCTRL register [31:28] */ + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long *)0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write(unsigned long add, unsigned long mask, unsigned long val) +{ + unsigned long *addr = (unsigned long *)add; + *addr = (val & mask) | (*addr & ~mask); +} + +int mask_poll(unsigned long add, unsigned long mask) +{ + volatile unsigned long *addr = (volatile unsigned long *)add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) + return -1; + i++; + } + return 1; +} + +unsigned long mask_read(unsigned long add, unsigned long mask) +{ + unsigned long *addr = (unsigned long *)add; + unsigned long val = (*addr & mask); + return val; +} + +int ps7_config(unsigned long *ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; /* current instruction .. */ + unsigned long args[16]; /* no opcode has so many args ... */ + int numargs; /* number of arguments of this instruction */ + int j; /* general purpose index */ + + volatile unsigned long *addr; /* some variable to make code readable */ + unsigned long val, mask; /* some variable to make code readable */ + + int finish = -1; /* loop while this is negative ! */ + int i = 0; /* Timeout variable */ + + while (finish < 0) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for (j = 0; j < numargs; j++) + args[j] = ptr[j + 1]; + ptr += numargs + 1; + + switch (opcode) { + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long *)args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long *)args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long *)args[0]; + mask = args[1]; + val = args[2]; + *addr = (val & mask) | (*addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long *)args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long *)args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) + ; + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int ps7_post_config(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config(ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config(ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else { + ret = ps7_config(ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } + return PS7_INIT_SUCCESS; +} + +int ps7_debug(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config(ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config(ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else { + ret = ps7_config(ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } + return PS7_INIT_SUCCESS; +} + +int ps7_init(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret; + /*int pcw_ver = 0; */ + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + /*pcw_ver = 1; */ + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + /*pcw_ver = 2; */ + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + /*pcw_ver = 3; */ + } + + /* MIO init */ + ret = ps7_config(ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* PLL init */ + ret = ps7_config(ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* Clock init */ + ret = ps7_config(ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* DDR init */ + ret = ps7_config(ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* Peripherals init */ + ret = ps7_config(ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} + +/* For delay calculation using global timer */ + +/* start timer */ +void perf_start_clock(void) +{ + *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */ + (1 << 3) | /* Auto-increment */ + (0 << 8) /* Pre-scale */ + ); +} + +/* stop timer and reset timer count regs */ +void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */ + return APU_FREQ * delay / (2 * 1000); +} + +/* stop timer */ +void perf_disable_clock(void) +{ + *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer(void) +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h new file mode 100644 index 0000000..22d9fd9 --- /dev/null +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*typedef unsigned int u32; */ + +/** do we need to make this name more unique ? **/ +/*extern u32 ps7_init_data[]; */ +extern unsigned long *ps7_ddr_init_data; +extern unsigned long *ps7_mio_init_data; +extern unsigned long *ps7_pll_init_data; +extern unsigned long *ps7_clock_init_data; +extern unsigned long *ps7_peripherals_init_data; + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) +#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr +#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val +#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val +#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask +#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ +#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ +#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ +#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ +#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ +#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 650000000 +#define DDR_FREQ 525000000 +#define DCI_FREQ 10096154 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 108333336 +#define WDT_FREQ 108333336 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 142857132 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config(unsigned long *); +int ps7_init(void); +int ps7_post_config(void); +int ps7_debug(void); +char *getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(void); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 7c66247..d0b1ec9 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_microzed" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_MICROZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index b46ab44..3624424 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_picozed" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_PICOZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SPL=y CONFIG_HUSH_PARSER=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 052679a..e1b1fc9 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" CONFIG_SPL=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 3539f05..63d32d9 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZC706=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 6a4726c..6ccbb8c 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc770" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 46dd6be..e6c646b 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc770" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 12f0e2c..a8cfeb8 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc770" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 8c7efe5..f2d00ca 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zc770" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 7976e07..7783eeb 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zed" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" CONFIG_SPL=y CONFIG_FIT=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index cd222c5..9236c5e 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="zynq_zybo" CONFIG_ARCH_ZYNQ=y -CONFIG_TARGET_ZYNQ_ZYBO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" CONFIG_SPL=y CONFIG_FIT=y -- cgit v0.10.2