From 28747f9bb1623d8333c419ae679b914bcabd4836 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 20 Jan 2011 16:34:41 +0530 Subject: powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index cbb0fc6..628e1cf 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -87,9 +87,11 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1010) += p1010_serdes.o COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o +COBJS-$(CONFIG_P1014) += p1010_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c new file mode 100644 index 0000000..e8a0387 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -0,0 +1,75 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, + [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {NONE, NONE}, + [0x01] = {SATA1, SATA2}, + [0x02] = {SATA1, SATA2}, + [0x03] = {PCIE1, PCIE2}, +}; + + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6bd83ba..49f5b6b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1874,8 +1874,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 #else +#if defined(CONFIG_P1010) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#endif /* if defined(CONFIG_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -- cgit v0.10.2 From d789b5f5bc18199fe617878efaa32756f481e7c8 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Thu, 20 Jan 2011 16:29:35 +0530 Subject: powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat Acked-by: Scott Wood Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1aad2ba..49ea6cc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -280,7 +281,8 @@ int cpu_mmc_init(bd_t *bis) /* * Print out the state of various machine registers. - * Currently prints out LAWs, BR0/OR0, and TLBs + * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing + * parameters for IFC and TLBs */ void mpc85xx_reginfo(void) { @@ -289,6 +291,9 @@ void mpc85xx_reginfo(void) #if defined(CONFIG_FSL_LBC) print_lbc_regs(); #endif +#ifdef CONFIG_FSL_IFC + print_ifc_regs(); +#endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 5dfd65b..4ae26e4 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -15,6 +15,7 @@ COBJS-y += cpu.o endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o COBJS-$(CONFIG_SYS_SRIO) += srio.o diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c new file mode 100644 index 0000000..39a4556 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -0,0 +1,84 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); + + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#endif + +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); + + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); +#endif + +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); + + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); + +#endif + +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); + + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); +#endif +} diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 2b6b233..536f142 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -75,8 +75,10 @@ /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) +#if !defined(CONFIG_FSL_IFC) #define CONFIG_FSL_LBC #endif +#endif /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h new file mode 100644 index 0000000..d4d9809 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -0,0 +1,957 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_PPC_FSL_IFC_H +#define __ASM_PPC_FSL_IFC_H + +#include +#include + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ +/* + * FTIM0 - NAND Flash Mode + */ +#define FTIM0_NAND 0x7EFF3F3F +#define FTIM0_NAND_TCCST_SHIFT 25 +#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) +#define FTIM0_NAND_TWP_SHIFT 16 +#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) +#define FTIM0_NAND_TWCHT_SHIFT 8 +#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) +#define FTIM0_NAND_TWH_SHIFT 0 +#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) +/* + * FTIM1 - NAND Flash Mode + */ +#define FTIM1_NAND 0xFFFF3FFF +#define FTIM1_NAND_TADLE_SHIFT 24 +#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) +#define FTIM1_NAND_TWBE_SHIFT 16 +#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) +#define FTIM1_NAND_TRR_SHIFT 8 +#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) +#define FTIM1_NAND_TRP_SHIFT 0 +#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) +/* + * FTIM2 - NAND Flash Mode + */ +#define FTIM2_NAND 0x1FE1F8FF +#define FTIM2_NAND_TRAD_SHIFT 21 +#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) +#define FTIM2_NAND_TREH_SHIFT 11 +#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) +#define FTIM2_NAND_TWHRE_SHIFT 0 +#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) +/* + * FTIM3 - NAND Flash Mode + */ +#define FTIM3_NAND 0xFF000000 +#define FTIM3_NAND_TWW_SHIFT 24 +#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Chip Select Register (NAND_CSEL) + */ +#define IFC_NAND_CSEL 0x0C000000 +#define IFC_NAND_CSEL_SHIFT 26 +#define IFC_NAND_CSEL_CS0 0x00000000 +#define IFC_NAND_CSEL_CS1 0x04000000 +#define IFC_NAND_CSEL_CS2 0x08000000 +#define IFC_NAND_CSEL_CS3 0x0C000000 + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + + +#ifndef __ASSEMBLY__ +#include + +extern void print_ifc_regs(void); +extern void init_early_memctl_regs(void); + +#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + +#define FSL_IFC_BANK_COUNT 4 + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + u32 ncfgr; + u32 res1[0x4]; + u32 nand_fcr0; + u32 nand_fcr1; + u32 res2[0x8]; + u32 row0; + u32 res3; + u32 col0; + u32 res4; + u32 row1; + u32 res5; + u32 col1; + u32 res6; + u32 row2; + u32 res7; + u32 col2; + u32 res8; + u32 row3; + u32 res9; + u32 col3; + u32 res10[0x24]; + u32 nand_fbcr; + u32 res11; + u32 nand_fir0; + u32 nand_fir1; + u32 nand_fir2; + u32 res12[0x10]; + u32 nand_csel; + u32 res13; + u32 nandseq_strt; + u32 res14; + u32 nand_evter_stat; + u32 res15; + u32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + u32 nand_evter_en; + u32 res17[0x2]; + u32 nand_evter_intr_en; + u32 res18[0x2]; + u32 nand_erattr0; + u32 nand_erattr1; + u32 res19[0x10]; + u32 nand_fsr; + u32 res20; + u32 nand_eccstat0; + u32 nand_eccstat1; + u32 nand_eccstat2; + u32 nand_eccstat3; + u32 res21[0x20]; + u32 nanndcr; + u32 res22[0x2]; + u32 nand_autoboot_trgr; + u32 res23; + u32 nand_mdr; + u32 res24[0x5C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + u32 nor_evter_stat; + u32 res1[0x2]; + u32 nor_evter_en; + u32 res2[0x2]; + u32 nor_evter_intr_en; + u32 res3[0x2]; + u32 nor_erattr0; + u32 nor_erattr1; + u32 nor_erattr2; + u32 res4[0x4]; + u32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + u32 gpcm_evter_stat; + u32 res1[0x2]; + u32 gpcm_evter_en; + u32 res2[0x2]; + u32 gpcm_evter_intr_en; + u32 res3[0x2]; + u32 gpcm_erattr0; + u32 gpcm_erattr1; + u32 gpcm_erattr2; + u32 gpcm_stat; + u32 res4[0x1F3]; +}; + + +/* + * IFC Controller Registers + */ +struct fsl_ifc { + u32 ifc_rev; + u32 res1[0x3]; + struct { + u32 cspr; + u32 res2[0x2]; + } cspr_cs[FSL_IFC_BANK_COUNT]; + u32 res3[0x18]; + struct { + u32 amask; + u32 res4[0x2]; + } amask_cs[FSL_IFC_BANK_COUNT]; + u32 res5[0x18]; + struct { + u32 csor; + u32 res6[0x2]; + } csor_cs[FSL_IFC_BANK_COUNT]; + u32 res7[0x18]; + struct { + u32 ftim[4]; + u32 res8[0x8]; + } ftim_cs[FSL_IFC_BANK_COUNT]; + u32 res9[0x60]; + u32 rb_stat; + u32 res10[0x2]; + u32 ifc_gcr; + u32 res11[0x2]; + u32 cm_evter_stat; + u32 res12[0x2]; + u32 cm_evter_en; + u32 res13[0x2]; + u32 cm_evter_intr_en; + u32 res14[0x2]; + u32 cm_erattr0; + u32 cm_erattr1; + u32 res15[0x2]; + u32 ifc_ccr; + u32 ifc_csr; + u32 res16[0x2EB]; + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 6a4279c..ae45f9b 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -91,6 +91,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 49f5b6b..f239e59 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -2232,6 +2233,7 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 @@ -2274,6 +2276,8 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_IFC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ -- cgit v0.10.2 From aa8d3fb8f4d383e7371f8f678ca3db1ca7d0ae32 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 21 Jan 2011 16:03:57 -0600 Subject: p1022ds: allow for board-specific ngPIXIS functions The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC SOCs. Although programming the ngPIXIS is mostly standard on all boards that have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in "indirect" mode whenever the video display (DIU) is active. To support indirect mode, and to make it easier to support other quirks on future reference boards, the low-level ngPIXIS functions are all marked as weak, so that board-specific code can override any of them. We take advantage of this feature on the P1022DS, so that we can properly reset the board when the DIU is active. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index a135fbe..4e01e5a 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -1,5 +1,5 @@ /** - * Copyright 2010 Freescale Semiconductor + * Copyright 2010-2011 Freescale Semiconductor * Author: Timur Tabi * * This program is free software; you can redistribute it and/or modify it @@ -35,61 +35,89 @@ #include #include -#include -#include #include #include "ngpixis.h" +static u8 __pixis_read(unsigned int reg) +{ + void *p = (void *)PIXIS_BASE; + + return in_8(p + reg); +} +u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read"))); + +static void __pixis_write(unsigned int reg, u8 value) +{ + void *p = (void *)PIXIS_BASE; + + out_8(p + reg, value); +} +void pixis_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__pixis_write"))); + /* * Reset the board. This ignores the ENx registers. */ -void pixis_reset(void) +void __pixis_reset(void) { - out_8(&pixis->rst, 0); + PIXIS_WRITE(rst, 0); while (1); } +void pixis_reset(void) __attribute__((weak, alias("__pixis_reset"))); /* * Reset the board. Like pixis_reset(), but it honors the ENx registers. */ -void pixis_bank_reset(void) +void __pixis_bank_reset(void) { - out_8(&pixis->vctl, 0); - out_8(&pixis->vctl, 1); + PIXIS_WRITE(vctl, 0); + PIXIS_WRITE(vctl, 1); while (1); } +void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset"))); /** * Set the boot bank to the power-on default bank */ -void clear_altbank(void) +void __clear_altbank(void) { + u8 reg; + /* Tell the ngPIXIS to use this the bits in the physical switch for the * boot bank value, instead of the SWx register. We need to be careful * only to set the bits in SWx that correspond to the boot bank. */ - clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK); + reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en); + reg &= ~PIXIS_LBMAP_MASK; + PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg); } +void clear_altbank(void) __attribute__((weak, alias("__clear_altbank"))); /** * Set the boot bank to the alternate bank */ -void set_altbank(void) +void __set_altbank(void) { + u8 reg; + /* Program the alternate bank number into the SWx register. */ - clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK, - PIXIS_LBMAP_ALTBANK); + reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw); + reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK; + PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg); /* Tell the ngPIXIS to use this the bits in the SWx register for the * boot bank value, instead of the physical switch. We need to be * careful only to set the bits in SWx that correspond to the boot bank. */ - setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK); + reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en); + reg |= PIXIS_LBMAP_MASK; + PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg); } +void set_altbank(void) __attribute__((weak, alias("__set_altbank"))); int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 089408b..681b0d0 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -1,5 +1,5 @@ /** - * Copyright 2010 Freescale Semiconductor + * Copyright 2010-2011 Freescale Semiconductor * Author: Timur Tabi * * This program is free software; you can redistribute it and/or modify it @@ -55,3 +55,9 @@ typedef struct ngpixis { /* The PIXIS EN register that corresponds to board switch X, where x >= 1 */ #define PIXIS_EN(x) (pixis->s[(x) - 1].en) + +u8 pixis_read(unsigned int reg); +void pixis_write(unsigned int reg, u8 value); + +#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg)) +#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c index 8f5305c..b37e0e2 100644 --- a/board/freescale/p1022ds/diu.c +++ b/board/freescale/p1022ds/diu.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * Authors: Timur Tabi * * FSL DIU Framebuffer driver @@ -139,8 +139,6 @@ int platform_diu_init(unsigned int *xres, unsigned int *yres) return fsl_diu_init(*xres, pixel_format, 0); } -#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS - /* * set_mux_to_lbc - disable the DIU so that we can read/write to elbc * @@ -211,6 +209,68 @@ static void set_mux_to_diu(void) in_be32(&gur->pmuxcr); } +/* + * pixis_read - board-specific function to read from the PIXIS + * + * This function overrides the generic pixis_read() function, so that it can + * use PIXIS indirect mode if necessary. + */ +u8 pixis_read(unsigned int reg) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Use indirect mode if the mux is currently set to DIU mode */ + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != + PMUXCR_ELBCDIU_NOR16) { + out_8(lbc_lcs0_ba, reg); + return in_8(lbc_lcs1_ba); + } else { + void *p = (void *)PIXIS_BASE; + + return in_8(p + reg); + } +} + +/* + * pixis_write - board-specific function to write to the PIXIS + * + * This function overrides the generic pixis_write() function, so that it can + * use PIXIS indirect mode if necessary. + */ +void pixis_write(unsigned int reg, u8 value) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Use indirect mode if the mux is currently set to DIU mode */ + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != + PMUXCR_ELBCDIU_NOR16) { + out_8(lbc_lcs0_ba, reg); + out_8(lbc_lcs1_ba, value); + /* Do a read-back to ensure the write completed */ + in_8(lbc_lcs1_ba); + } else { + void *p = (void *)PIXIS_BASE; + + out_8(p + reg, value); + } +} + +void pixis_bank_reset(void) +{ + /* + * For some reason, a PIXIS bank reset does not work if the PIXIS is + * in indirect mode, so switch to direct mode first. + */ + set_mux_to_lbc(); + + out_8(&pixis->vctl, 0); + out_8(&pixis->vctl, 1); + + while (1); +} + +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + void flash_write8(u8 value, void *addr) { int sw = set_mux_to_lbc(); -- cgit v0.10.2 From 5cfbc458d4957a186d1433cf1c14e8f4e6d4431f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 24 Jan 2011 23:36:17 -0600 Subject: powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init Rather than having #defines DATARATE_*_MHZ, lets just match what we do on the SPD code and convert the DDR frequency into MHZ and just compare with a constant. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 07b950f..844eb1d 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -31,19 +31,21 @@ extern fixed_ddr_parm_t fixed_ddr_parm_1[]; phys_size_t fixed_sdram(void) { int i; - sys_info_t sysinfo; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; phys_size_t ddr_size; unsigned int lawbar1_target_id; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; - get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, ddr_freq)); for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) && - (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, sizeof(ddr_cfg_regs)); @@ -53,7 +55,7 @@ phys_size_t fixed_sdram(void) if (fixed_ddr_parm_0[i].max_freq == 0) panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, ddr_freq)); ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index 4ad89ff..ccb9da8 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,12 +9,6 @@ #include #include -#define DATARATE_800MHZ 800000000 -#define DATARATE_900MHZ 900000000 -#define DATARATE_1000MHZ 1000000000 -#define DATARATE_1200MHZ 1200000000 -#define DATARATE_1300MHZ 1300000000 - #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 #define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 @@ -340,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { }; fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800}, - {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900}, - {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000}, - {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200}, + {800, 900, &ddr_cfg_regs_800}, + {900, 1000, &ddr_cfg_regs_900}, + {1000, 1200, &ddr_cfg_regs_1000}, + {1200, 1300, &ddr_cfg_regs_1200}, {0, 0, NULL} }; fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd}, - {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd}, - {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd}, - {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd}, + {800, 900, &ddr_cfg_regs_800_2nd}, + {900, 1000, &ddr_cfg_regs_900_2nd}, + {1000, 1200, &ddr_cfg_regs_1000_2nd}, + {1200, 1300, &ddr_cfg_regs_1200_2nd}, {0, 0, NULL} }; diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index e54fde2..fbc46b1 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009, 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -33,11 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); -#define DATARATE_400MHZ 400000000 -#define DATARATE_533MHZ 533333333 -#define DATARATE_667MHZ 666666666 -#define DATARATE_800MHZ 800000000 - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -204,27 +199,29 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { phys_size_t fixed_sdram (void) { - sys_info_t sysinfo; char buf[32]; fsl_ddr_cfg_regs_t ddr_cfg_regs; size_t ddr_size; struct cpu_type *cpu; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; - get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, ddr_freq)); - if(sysinfo.freqDDRBus <= DATARATE_400MHZ) + if(ddr_freq_mhz <= 400) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); - else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) + else if(ddr_freq_mhz <= 533) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); - else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) + else if(ddr_freq_mhz <= 667) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); - else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) + else if(ddr_freq_mhz <= 800) memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); else panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, ddr_freq)); cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ -- cgit v0.10.2 From f0f899432e8e901844c3d98483d89d4612f13d98 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 25 Jan 2011 01:48:03 -0600 Subject: powerpc/85xx: Declare fsl_ddr_set_memctl_regs in Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 02a1f5d..b5b1efe 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -271,6 +271,8 @@ typedef struct memctl_options_s { extern phys_size_t fsl_ddr_sdram(void); extern int fsl_use_spd(void); +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); /* * The 85xx boards have a common prototype for fixed_sdram so put the diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 844eb1d..ee08abb 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -16,9 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); - /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index fbc46b1..44faec3 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -- cgit v0.10.2 From eea9a123449c34fa1631e7869aae94dbe3b61dbd Mon Sep 17 00:00:00 2001 From: Pankaj Chauhan Date: Tue, 25 Jan 2011 14:44:57 +0530 Subject: powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2" In a manner similar to passing ethernet stashing parameters into device tree for "gianfar", extend the support to the "fsl,etsec2" as well. Signed-off-by: Pankaj Chauhan Signed-off-by: Sandeep Gopalpet Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 00fa752..6ed0284 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -338,6 +338,9 @@ void fdt_add_enet_stashing(void *fdt) do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); + do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); } #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) -- cgit v0.10.2 From fbee0f7f09e94c0967ac118d41388c3edb0c226d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 25 Jan 2011 12:42:32 -0600 Subject: powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020 Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6c16681..53703f6 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -156,11 +156,18 @@ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -191,11 +198,19 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 #else #error Processor type not defined for this platform -- cgit v0.10.2 From 9c4d8767ed672f995bf2d6b7cb2e83823bae9d76 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Mon, 24 Jan 2011 17:09:53 +0000 Subject: powerpc/85xx: Add eSDHC support on P2020DS We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang Signed-off-by: Jin Qing Signed-off-by: Kumar Gala diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 8546aa9..16e9206 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -44,6 +44,19 @@ DECLARE_GLOBAL_DATA_PTR; +int board_early_init_f(void) +{ +#ifdef CONFIG_MMC + ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); +#endif + + return 0; +} + int checkboard(void) { u8 sw; diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b32a997..d4770f2 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -78,6 +78,8 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + #define CONFIG_ENABLE_36BIT_PHYS 1 #ifdef CONFIG_PHYS_64BIT @@ -605,15 +607,36 @@ /* * USB */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ /* + * SDHC/MMC + */ +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -- cgit v0.10.2 From ccc4a8d89f8abcd30c25ac67a5aa5e57ac2eb515 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 24 Jan 2011 17:09:52 +0000 Subject: powerpc/85xx: Update P2020DS default env settings Read MAC address from EEPROM. Add hwconfig settings. Modified the default othbootargs to include the cache-sram-size parameter. This parameter is needed as the L2 as SRAM is ON by default in the P2020RDB kernel and used by the Gianfar driver. Also cleanup some of the boot commands. Signed-off-by: Li Yang Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index d4770f2..6648d6e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -674,13 +674,8 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif #define CONFIG_IPADDR 192.168.1.254 @@ -703,8 +698,8 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "perf_mode=stable\0" \ - "memctl_intlv_ctl=2\0" \ + "perf_mode=performance\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ @@ -713,18 +708,25 @@ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ + "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2020ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ + "othbootargs=cache-sram-size=0x10000\0" \ "fdtfile=p2020ds/p2020ds.dtb\0" \ - "bdev=sda3\0" + "bdev=sda3\0" \ + "partition=scsi 0:0\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ + "ext2load $partition $loadaddr $bootfile;" \ + "ext2load $partition $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_NFSBOOTCOMMAND \ -- cgit v0.10.2 From 561e710a979c86a0c647dd70d143cafc123bcd64 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 15:51:20 -0600 Subject: powerpc: Move cpu specific lmb reserve to arch_lmb_reserve We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 116d81b..c7f3d08 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -33,6 +33,7 @@ #include #include #include +#include #if defined(CONFIG_OF_LIBFDT) #include @@ -166,6 +167,10 @@ void arch_lmb_reserve(struct lmb *lmb) sp -= 4096; lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); +#ifdef CONFIG_MP + cpu_mp_lmb_reserve(lmb); +#endif + return ; } diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 232dc72..3db93c3 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -39,8 +39,6 @@ extern void pci_of_setup(void *blob, bd_t *bd); DECLARE_GLOBAL_DATA_PTR; -void cpu_mp_lmb_reserve(struct lmb *lmb); - int checkboard (void) { u8 sw; @@ -186,13 +184,6 @@ int misc_init_r(void) return 0; } -#ifdef CONFIG_MP -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif - void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 4b2ef4e..f444805 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -259,12 +259,3 @@ void ft_board_setup(void *blob, bd_t *bd) #endif } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 166ff0c..cd2ce4b 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2007, 2010 Freescale Semiconductor. + * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -261,12 +261,3 @@ void board_reset(void) while (1) ; } - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 0ea0bdf..62beafa 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan * Timur Tabi * @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -302,10 +301,3 @@ void ft_board_setup(void *blob, bd_t *bd) ft_codec_setup(blob, "wlf,wm8776"); } #endif - -#ifdef CONFIG_MP -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 0780942..806d90e 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -229,12 +229,3 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 16e9206..238b4d9 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -36,7 +36,6 @@ #include #include #include -#include #include #include "../common/ngpixis.h" @@ -262,10 +261,3 @@ void ft_board_setup(void *blob, bd_t *bd) #endif } #endif - -#ifdef CONFIG_MP -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 5c30b26..dd58541 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -273,12 +273,3 @@ void board_reset(void) __asm__ __volatile__ ("rfi"); #endif } - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 61443aa..179b238 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -93,12 +93,3 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c index d074495..9d9afae 100644 --- a/board/xes/xpedite537x/xpedite537x.c +++ b/board/xes/xpedite537x/xpedite537x.c @@ -96,12 +96,3 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c index 6f91c83..24b2b0e 100644 --- a/board/xes/xpedite550x/xpedite550x.c +++ b/board/xes/xpedite550x/xpedite550x.c @@ -96,12 +96,3 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); } #endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif -- cgit v0.10.2 From 00203c64648bb2a7e20dac8cde850de6c1044db6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 15:57:01 -0600 Subject: powerpc/85xx: Remove config.mk for nand linker script Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk deleted file mode 100644 index 228d8c0..0000000 --- a/board/freescale/mpc8536ds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2008, 2011 Freescale Semiconductor. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8536ds board -# -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk deleted file mode 100644 index 54b2eb1..0000000 --- a/board/freescale/mpc8569mds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (C) 2009 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8569mds board -# -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk deleted file mode 100644 index 9fd30f9..0000000 --- a/board/freescale/mpc8572ds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8572ds board -# -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk deleted file mode 100644 index 0769804..0000000 --- a/board/freescale/p1_p2_rdb/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright 2009, 2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# p1_p2rdb board -# - -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 13300de..333a1ea 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9e24e12..b815ed0 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -72,6 +72,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bf2fdd6..4224229 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 95b85e3..b67f70f 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -50,6 +50,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif -- cgit v0.10.2 From 5df4b0ad0dff3cef1bd6660bcc8cba028c80adcb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 20:36:02 -0600 Subject: powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index cefabe7..ee7ef0f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = fsl_ddr_get_mem_data_rate(); + unsigned int data_rate = get_ddr_freq(0); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index c7c12c1..1e866fe 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); -extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 1e2d921..815c5e3 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -11,8 +11,6 @@ #include "ddr.h" -unsigned int fsl_ddr_get_mem_data_rate(void); - /* * Round mclk_ps to nearest 10 ps in memory controller code. * @@ -24,7 +22,7 @@ unsigned int get_memory_clk_period_ps(void) { unsigned int mclk_ps; - mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate(); + mclk_ps = 2000000000000ULL / get_ddr_freq(0); /* round to nearest 10 ps */ return 10 * ((mclk_ps + 5) / 10); } @@ -40,7 +38,7 @@ unsigned int picos_to_mclk(unsigned int picos) if (!picos) return 0; - clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos; + clks = get_ddr_freq(0) * (unsigned long long) picos; clks_temp = clks; clks = clks / ULL_2e12; if (clks_temp % ULL_2e12) { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index ee08abb..d83b9bf 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -118,11 +118,6 @@ static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) } } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index 2bad787..565e213 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -17,11 +17,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 93d1100..64a3ee1 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index c84a6cb..ce08af1 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index b8330eb..87f0a22 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index ab64fa8..bc6e71a 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index c84a6cb..ce08af1 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 93d1100..64a3ee1 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 482fd91..9a4c5c9 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -18,12 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e3f5b4a..bedbedd 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -18,12 +18,6 @@ get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index cdde6ec..52c7d73 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -17,11 +17,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 0117d13..5523c0e 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 8dc249b..07bb92f 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { @@ -144,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Get clk_adjust, cpo, write_data_delay, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ - ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000; + ddr_freq = get_ddr_freq(0) / 1000000; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { if (pdimm[j].n_ranks > 0) { for (i = 0; i < num_params; i++) { diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index 7ecfb3e..80c1d63 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -15,11 +15,6 @@ #include #include -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { int ret; diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 9a1b075..b52582f 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -17,11 +17,6 @@ static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index ab64fa8..bc6e71a 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c index 7850794..f7e956a 100644 --- a/board/sbc8560/ddr.c +++ b/board/sbc8560/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index 23497f9..bed94bf 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 2b62b84..4558326 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 93d1100..64a3ee1 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 93d1100..64a3ee1 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c index 1d57d09..981bf41 100644 --- a/board/xes/xpedite517x/ddr.c +++ b/board/xes/xpedite517x/ddr.c @@ -32,11 +32,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { @@ -144,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int datarate; get_sys_info(&sysinfo); - datarate = fsl_ddr_get_mem_data_rate() / 1000000; + datarate = get_ddr_freq(0) / 1000000; for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { if ((bopts[i].datarate_mhz_low <= datarate) && diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index c5616d5..f8d945a 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -27,11 +27,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) } } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index 4d3f255..307f875 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -33,11 +33,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 38a4597..9e69649 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -46,11 +46,6 @@ void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, } } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - /* * There are traditionally three board-specific SDRAM timing parameters * which must be calculated based on the particular PCB artwork. These are: diff --git a/include/common.h b/include/common.h index 893af5c..54503ed 100644 --- a/include/common.h +++ b/include/common.h @@ -538,6 +538,10 @@ ulong get_ddr_freq (ulong); #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +static inline ulong get_ddr_freq(ulong dummy) +{ + return get_bus_freq(dummy); +} #endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) -- cgit v0.10.2 From c39f44dc6f5ae843d5def511f6e71d4b012dc598 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 22:18:47 -0600 Subject: powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index bb96d66..c8fa123 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -13,6 +13,7 @@ */ #include +#include #include #include "ddr.h" @@ -26,9 +27,65 @@ extern void fsl_ddr_set_lawbar( extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); +#if defined(SPD_EEPROM_ADDRESS) || \ + defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ + defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) +#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS, +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ +}; +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +__attribute__((weak, alias("__get_spd"))) +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); + +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + i2c_address = spd_i2c_addr[ctrl_num][i]; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} +#else +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ +} +#endif /* SPD_EEPROM_ADDRESSx */ /* * ASSUMPTIONS: diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index d83b9bf..98024c7 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -107,33 +107,6 @@ phys_size_t fixed_sdram(void) return ddr_size; } -static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) -{ - int ret; - - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); - if (ret) { - debug("DDR: failed to read SPD from address %u\n", i2c_address); - memset(spd, 0, sizeof(ddr3_spd_eeprom_t)); - } -} - -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - else if (ctrl_num == 1 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS2; - - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index 565e213..d10370c 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 64a3ee1..5711374 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index ce08af1..78d73b0 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index 87f0a22..94219b9 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index bc6e71a..996ffe2 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index ce08af1..78d73b0 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 64a3ee1..5711374 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 9a4c5c9..b1f4f1f 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index bedbedd..68f686b 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - if (ctrl_num == 0 && i == 1) - i2c_address = SPD_EEPROM_ADDRESS2; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index 52c7d73..ab471af 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -7,33 +7,10 @@ */ #include -#include #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - if (ctrl_num == 1 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS2; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 5523c0e..94219b9 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 07bb92f..bd0b299 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -7,40 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - if (ctrl_num == 0 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; - } - if (ctrl_num == 1 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS3; - } - if (ctrl_num == 1 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS4; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index 80c1d63..20b996e 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -10,28 +10,10 @@ */ #include -#include #include #include -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) -{ - int ret; - - /* - * The P1022 has only one DDR controller, and the board has only one - * DIMM slot. - */ - ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd, - sizeof(ddr3_spd_eeprom_t)); - if (ret) { - debug("DDR: failed to read SPD from address %u\n", - SPD_EEPROM_ADDRESS1); - memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t)); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b52582f..9bf7d2f 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -7,29 +7,10 @@ */ #include -#include #include #include -static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index bc6e71a..996ffe2 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c index f7e956a..e9babc6 100644 --- a/board/sbc8560/ddr.c +++ b/board/sbc8560/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index bed94bf..996ffe2 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -7,40 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - if (ctrl_num == 0 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; - } - if (ctrl_num == 1 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS3; - } - if (ctrl_num == 1 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS4; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 4558326..e9db476 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 64a3ee1..5711374 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 64a3ee1..56c87b2 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -12,27 +12,6 @@ #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c index 981bf41..3a6e297 100644 --- a/board/xes/xpedite517x/ddr.c +++ b/board/xes/xpedite517x/ddr.c @@ -26,35 +26,12 @@ #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; -#ifdef SPD_EEPROM_ADDRESS2 - } else if (ctrl_num == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; -#endif - } else { - /* An inalid ctrl number was give, use default SPD */ - printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num); - i2c_address = SPD_EEPROM_ADDRESS1; - } - - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - /* * There are four board-specific SDRAM timing parameters which must be * calculated based on the particular PCB artwork. These are: diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index f8d945a..3671cb8 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -12,8 +12,7 @@ #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); @@ -27,20 +26,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) } } -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index 307f875..d0662b0 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -27,27 +27,12 @@ #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - if (ctrl_num == 1) - i2c_address = SPD_EEPROM_ADDRESS2; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - /* * There are four board-specific SDRAM timing parameters which must be * calculated based on the particular PCB artwork. These are: diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 9e69649..3b6e08b 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -27,25 +27,12 @@ #include #include -static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address) { i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - /* * There are traditionally three board-specific SDRAM timing parameters * which must be calculated based on the particular PCB artwork. These are: diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b815ed0..5f80425 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -139,8 +139,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) /* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 03ee394..7b25e07 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -108,7 +108,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 84b7e1d..5f47d1a 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -87,7 +87,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* * Memory map diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 6648d6e..1815191 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -130,7 +130,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index a051913..17aab5a 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -67,7 +67,7 @@ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x54 +#define SPD_EEPROM_ADDRESS 0x54 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -- cgit v0.10.2 From fdb4dad31e2b0c7991595c9cedaf76c033a31115 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 23:09:25 -0600 Subject: powerpc/85xx: Cleanup some QE related defines Move some processor specific QE defines into config_mpc85xx.h and use QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct. Also fixed up some comment style issues in immap_qe.h Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 53703f6..b014ec6 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -67,11 +67,17 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define QE_MURAM_SIZE 0x10000UL +#define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define QE_MURAM_SIZE 0x20000UL +#define MAX_QE_RISC 4 +#define QE_NUM_OF_SNUM 46 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 531cfc8..9be9dca 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -3,7 +3,7 @@ * The Internal Memory Map for devices with QE on them. This * is the superset of all QE devices (8360, etc.). * - * Copyright (c) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc. * Author: Shlomi Gridih * * This program is free software; you can redistribute it and/or modify it @@ -15,8 +15,19 @@ #ifndef __IMMAP_QE_H__ #define __IMMAP_QE_H__ -/* QE I-RAM -*/ +#ifdef CONFIG_MPC83xx +#if defined(CONFIG_MPC8360) +#define QE_MURAM_SIZE 0xc000UL +#define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 +#elif defined(CONFIG_MPC832x) +#define QE_MURAM_SIZE 0x4000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#endif +#endif + +/* QE I-RAM */ typedef struct qe_iram { u32 iadd; /* I-RAM Address Register */ u32 idata; /* I-RAM Data Register */ @@ -25,8 +36,7 @@ typedef struct qe_iram { u8 res1[0x70]; } __attribute__ ((packed)) qe_iram_t; -/* QE Interrupt Controller -*/ +/* QE Interrupt Controller */ typedef struct qe_ic { u32 qicr; u32 qivec; @@ -49,8 +59,7 @@ typedef struct qe_ic { u8 res3[0x1C]; } __attribute__ ((packed)) qe_ic_t; -/* Communications Processor -*/ +/* Communications Processor */ typedef struct cp_qe { u32 cecr; /* QE command register */ u32 ceccr; /* QE controller configuration register */ @@ -87,8 +96,7 @@ typedef struct cp_qe { u8 res13[0x280]; } __attribute__ ((packed)) cp_qe_t; -/* QE Multiplexer -*/ +/* QE Multiplexer */ typedef struct qe_mux { u32 cmxgcr; /* CMX general clock route register */ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ @@ -102,8 +110,7 @@ typedef struct qe_mux { u8 res0[0x1C]; } __attribute__ ((packed)) qe_mux_t; -/* QE Timers -*/ +/* QE Timers */ typedef struct qe_timers { u8 gtcfr1; /* Timer 1 2 global configuration register */ u8 res0[0x3]; @@ -133,8 +140,7 @@ typedef struct qe_timers { u8 res2[0x46]; } __attribute__ ((packed)) qe_timers_t; -/* BRG -*/ +/* BRG */ typedef struct qe_brg { u32 brgc1; /* BRG1 configuration register */ u32 brgc2; /* BRG2 configuration register */ @@ -155,8 +161,7 @@ typedef struct qe_brg { u8 res0[0x40]; } __attribute__ ((packed)) qe_brg_t; -/* SPI -*/ +/* SPI */ typedef struct spi { u8 res0[0x20]; u32 spmode; /* SPI mode register */ @@ -174,8 +179,7 @@ typedef struct spi { u8 res7[0x8]; } __attribute__ ((packed)) spi_t; -/* SI -*/ +/* SI */ typedef struct si1 { u16 siamr1; /* SI1 TDMA mode register */ u16 sibmr1; /* SI1 TDMB mode register */ @@ -222,16 +226,14 @@ typedef struct si1 { u8 res9[0xBB]; } __attribute__ ((packed)) si1_t; -/* SI Routing Tables -*/ +/* SI Routing Tables */ typedef struct sir { u8 tx[0x400]; u8 rx[0x400]; u8 res0[0x800]; } __attribute__ ((packed)) sir_t; -/* USB Controller. -*/ +/* USB Controller. */ typedef struct usb_ctlr { u8 usb_usmod; u8 usb_usadr; @@ -253,8 +255,7 @@ typedef struct usb_ctlr { u8 res6[0x22]; } __attribute__ ((packed)) usb_t; -/* MCC -*/ +/* MCC */ typedef struct mcc { u32 mcce; /* MCC event register */ u32 mccm; /* MCC mask register */ @@ -263,8 +264,7 @@ typedef struct mcc { u8 res0[0xF0]; } __attribute__ ((packed)) mcc_t; -/* QE UCC Slow -*/ +/* QE UCC Slow */ typedef struct ucc_slow { u32 gumr_l; /* UCCx general mode register (low) */ u32 gumr_h; /* UCCx general mode register (high) */ @@ -368,8 +368,7 @@ typedef struct ucc_ethernet { u8 res5[0x200 - 0x1c4]; } __attribute__ ((packed)) uec_t; -/* QE UCC Fast -*/ +/* QE UCC Fast */ typedef struct ucc_fast { u32 gumr; /* UCCx general mode register */ u32 upsmr; /* UCCx protocol-specific mode register */ @@ -403,8 +402,7 @@ typedef struct ucc_fast { uec_t ucc_eth; } __attribute__ ((packed)) ucc_fast_t; -/* QE UCC -*/ +/* QE UCC */ typedef struct ucc_common { u8 res1[0x90]; u8 guemr; @@ -419,8 +417,7 @@ typedef struct ucc { }; } __attribute__ ((packed)) ucc_t; -/* MultiPHY UTOPIA POS Controllers (UPC) -*/ +/* MultiPHY UTOPIA POS Controllers (UPC) */ typedef struct upc { u32 upgcr; /* UTOPIA/POS general configuration register */ u32 uplpa; /* UTOPIA/POS last PHY address */ @@ -476,8 +473,7 @@ typedef struct upc { u8 res2[0x150]; } __attribute__ ((packed)) upc_t; -/* SDMA -*/ +/* SDMA */ typedef struct sdma { u32 sdsr; /* Serial DMA status register */ u32 sdmr; /* Serial DMA mode register */ @@ -497,8 +493,7 @@ typedef struct sdma { u8 res2[0x38]; } __attribute__ ((packed)) sdma_t; -/* Debug Space -*/ +/* Debug Space */ typedef struct dbg { u32 bpdcr; /* Breakpoint debug command register */ u32 bpdsr; /* Breakpoint debug status register */ @@ -582,40 +577,9 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -#if defined(CONFIG_MPC8568) - u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ - u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ -#elif defined(CONFIG_MPC8569) - u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */ - u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */ -#else - u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ -#endif + u8 muram[QE_MURAM_SIZE]; } __attribute__ ((packed)) qe_map_t; extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8568) -#define QE_MURAM_SIZE 0x10000UL -#elif defined(CONFIG_MPC8569) -#define QE_MURAM_SIZE 0x20000UL -#elif defined(CONFIG_MPC8360) -#define QE_MURAM_SIZE 0xc000UL -#elif defined(CONFIG_MPC832x) -#define QE_MURAM_SIZE 0x4000UL -#endif - -#if defined(CONFIG_MPC8323) -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC8569) -#define MAX_QE_RISC 4 -#define QE_NUM_OF_SNUM 46 -#else -#define MAX_QE_RISC 2 -#define QE_NUM_OF_SNUM 28 -#endif - #endif /* __IMMAP_QE_H__ */ -- cgit v0.10.2 From f9a33f1c6158ce3fa119d94109d4347cf2e0aa4a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Feb 2011 11:23:50 -0600 Subject: powerpc: Add cpu_secondary_init_r to allow for initialization post env setup We can simplify some cpu/SoC level initialization by moving it to be after the environment and non-volatile storage is setup as there might be dependancies on such things in various boot configurations. For example for FSL SoC's with QE if we boot from NAND we need it setup to extra the ucode image to initialize the QE. If we always do this after environment & non-volatile storage is working we can have the code be the same regardless of NOR, NAND, SPI, MMC boot. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 8ece970..215b7b3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -384,12 +384,6 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE - uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ - qe_init(qe_base); - qe_reset(); -#endif - /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); @@ -449,3 +443,12 @@ int sata_initialize(void) return 1; } #endif + +void cpu_secondary_init_r(void) +{ +#ifdef CONFIG_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); +#endif +} diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 4719f8c..83fb074 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -186,6 +186,12 @@ int __board_flash_wp_on(void) } int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on"))); +void __cpu_secondary_init_r(void) +{ +} +void cpu_secondary_init_r(void) +__attribute__((weak, alias("__cpu_secondary_init_r"))); + static int init_func_ram (void) { #ifdef CONFIG_BOARD_TYPES @@ -798,6 +804,14 @@ void board_init_r (gd_t *id, ulong dest_addr) env_relocate (); /* + * after non-volatile devices & environment is setup and cpu code have + * another round to deal with any initialization that might require + * full access to the environment or loading of some image (firmware) + * from a non-volatile device + */ + cpu_secondary_init_r(); + + /* * Fill in missing fields of bd_info. * We do this here, where we have "normal" access to the * environment; we used to do this still running from ROM, -- cgit v0.10.2 From ebc73943bab9d61a67ac466eb63c433a17799cbb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Feb 2011 20:21:42 -0600 Subject: powerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPL Slim down NAND SPL build a bit as we don't need read_tlbcam_entry. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 31143ba..295f175 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -55,6 +55,7 @@ void init_tlbs(void) return ; } +#ifndef CONFIG_NAND_SPL void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -73,7 +74,6 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, #endif } -#ifndef CONFIG_NAND_SPL void print_tlbcam(void) { int i; -- cgit v0.10.2 From 67a719da2e5cfdfa461c5a35c1c5a6a2c5e82d73 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Thu, 3 Feb 2011 22:14:19 -0600 Subject: powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 628e1cf..cc16db3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -92,9 +92,11 @@ COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o COBJS-$(CONFIG_P1014) += p1010_serdes.o +COBJS-$(CONFIG_P1017) += p1023_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o +COBJS-$(CONFIG_P1023) += p1023_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c new file mode 100644 index 0000000..c8ab5d6 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -0,0 +1,53 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Roy Zang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {PCIE1, PCIE2, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, PCIE3, NONE}, + [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2}, + [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + return ret; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 4335fb4..d2baaf0 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -71,15 +71,19 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1012, P1012, 1), CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1013, P1013_E, 1), + CPU_TYPE_ENTRY(P1017, P1017, 1), + CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), CPU_TYPE_ENTRY(P1021, P1021_E, 2), CPU_TYPE_ENTRY(P1022, P1022, 2), CPU_TYPE_ENTRY(P1022, P1022_E, 2), + CPU_TYPE_ENTRY(P1023, P1023, 2), + CPU_TYPE_ENTRY(P1023, P1023_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b014ec6..9437301 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -121,6 +121,16 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#elif defined(CONFIG_P1017) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_QMAN_NUM_PORTALS 3 +#define CONFIG_SYS_BMAN_NUM_PORTALS 3 + #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -144,6 +154,16 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#elif defined(CONFIG_P1023) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_QMAN_NUM_PORTALS 3 +#define CONFIG_SYS_BMAN_NUM_PORTALS 3 + #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index ae45f9b..13caffd 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -83,6 +83,7 @@ enum law_trgt_if { LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, + LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ }; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index f239e59..ce27fec 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1865,8 +1865,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORBMSR_HA_SHIFT 16 u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ +#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 +#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 +#else #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 +#endif #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 @@ -1874,6 +1879,9 @@ typedef struct ccsr_gur { #if defined(CONFIG_P1013) || defined(CONFIG_P1022) #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 +#elif defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #if defined(CONFIG_P1010) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 @@ -2247,6 +2255,12 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 +#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fcee1a2..d8b8f34 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,12 +1048,16 @@ #define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 #define SVR_P1014_E 0x80F901 +#define SVR_P1017 0x80F700 +#define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 #define SVR_P1021_E 0x80EC01 #define SVR_P1022 0x80E600 #define SVR_P1022_E 0x80EE00 +#define SVR_P1023 0x80F600 +#define SVR_P1023_E 0x80FE00 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -- cgit v0.10.2 From 24995d829aecc6abca0f1b41443ae0cd9b4fde5a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 20 Jan 2011 22:26:31 +0000 Subject: powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index cc16db3..5791be0 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -69,7 +69,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_FSL_CORENET) += portals.o +COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 01aec6e..e8d53bb 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,18 +30,13 @@ #include #include -static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; void setup_portals(void) { +#ifdef CONFIG_FSL_CORENET int i; - /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ -#ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); -#endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; @@ -53,6 +48,13 @@ void setup_portals(void) /* set frame liodn */ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } +#endif + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); } /* Update portal containter to match LAW setup of portal in phy map */ @@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char *container, static int fdt_qportal(void *blob, int off, int id, char *name, enum fsl_dpaa_dev dev, int create) { - int childoff, dev_off, num, ret = 0; + int childoff, dev_off, ret = 0; uint32_t dev_handle; +#ifdef CONFIG_FSL_CORENET + int num; u32 liodns[2]; +#endif childoff = fdt_subnode_offset(blob, off, name); if (create) { @@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name, if (ret < 0) return ret; +#ifdef CONFIG_FSL_CORENET num = get_dpaa_liodn(dev, &liodns[0], id); ret = fdt_setprop(blob, childoff, "fsl,liodn", &liodns[0], sizeof(u32) * num); +#endif } else { return childoff; } @@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { +#ifdef CONFIG_FSL_CORENET u32 liodns[2]; +#endif const int *ci = fdt_getprop(blob, off, "cell-index", NULL); int j, i = *ci; @@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET liodns[0] = qp_info[i].dliodn; liodns[1] = qp_info[i].fliodn; @@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob) &liodns, sizeof(u32) * 2); if (err < 0) goto err; +#endif i++; @@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_DPAA_PME err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); if (err < 0) @@ -214,6 +226,8 @@ void fdt_fixup_qportals(void *blob) #else fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); #endif +#endif + #ifdef CONFIG_SYS_DPAA_FMAN for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d0..9d749c3 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -162,7 +162,6 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif -#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -170,6 +169,15 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#ifdef CONFIG_SYS_DPAA_FMAN + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#endif /* CONFIG_FSL_CORENET */ + #if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 4c17fe2..f76676c 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -85,13 +85,13 @@ extern void fdt_fixup_liodn(void *blob); #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) + CONFIG_SYS_FSL_QMAN_OFFSET, \ + CONFIG_SYS_FSL_QMAN_OFFSET) #define SET_BMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) + CONFIG_SYS_FSL_BMAN_OFFSET, \ + CONFIG_SYS_FSL_BMAN_OFFSET) #define SET_PME_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index ce27fec..d26d648 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2204,8 +2204,8 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 -#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2268,10 +2268,10 @@ typedef struct ccsr_pme { #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_FSL_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) +#define CONFIG_SYS_FSL_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bff212e..7bafa05 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -357,6 +357,7 @@ #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -- cgit v0.10.2 From b6ccd2c9dee758a70e761403a41e60c31a1cfcec Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 4 Feb 2011 09:00:43 +0530 Subject: fsl_pci: Add support for FSL PCIe controllers v2.x FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 0a98bde..82d75be 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,6 +25,9 @@ #include #include +#define PEX_IP_BLK_REV_2_2 0x02080202 +#define PEX_IP_BLK_REV_2_3 0x02080203 + int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_config_unlock(struct pci_controller *hose); @@ -73,7 +76,8 @@ typedef struct ccsr_pci { u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ u32 config; /* 0x014 - PCIE CONFIG Register */ - char res2[8]; + u32 int_status; /* 0x018 - PCIE interrupt status register */ + char res2[4]; u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ @@ -83,8 +87,11 @@ typedef struct ccsr_pci { u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ - u32 res5[64]; - pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ + u32 res5[24]; + pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */ + u32 res6[24]; + pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */ + #define PIT3 0 #define PIT2 1 #define PIT1 2 @@ -158,6 +165,11 @@ typedef struct ccsr_pci { u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ char res24[252]; } ccsr_fsl_pci_t; +#define PCIE_CONFIG_PC 0x00020000 +#define PCIE_CONFIG_OB_CK 0x00002000 +#define PCIE_CONFIG_SAC 0x00000010 +#define PCIE_CONFIG_SP 0x80000002 +#define PCIE_CONFIG_SCC 0x80000001 struct fsl_pci_info { unsigned long regs; diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index dc34bd6..ab461b4 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -223,6 +223,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; u16 temp16; u32 temp32; + u32 block_rev; int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; @@ -232,13 +233,20 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* Initialize ATMU registers based on hose regions and flags */ volatile pot_t *po = &pci->pot[1]; /* skip 0 */ - volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ + volatile pit_t *pi; u64 out_hi = 0, out_lo = -1ULL; u32 pcicsrbar, pcicsrbar_sz; pci_setup_indirect(hose, cfg_addr, cfg_data); + block_rev = in_be32(&pci->block_rev1); + if (PEX_IP_BLK_REV_2_2 <= block_rev) { + pi = &pci->pit[2]; /* 0xDC0 */ + } else { + pi = &pci->pit[3]; /* 0xDE0 */ + } + /* Handle setup of outbound windows first */ for (r = 0; r < hose->region_count; r++) { unsigned long flags = hose->regions[r].flags; -- cgit v0.10.2 From 7639675131673e8f1582d760203a9af34fba9e79 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Feb 2011 09:02:13 -0600 Subject: powerpc/8xxx: Fix LAW init to respect pre-initialized entries If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW entries consider them good and mark them used. In the NAND SPL case we skip re-initializing based on the law_table since the SPL phase already did that. Signed-off-by: Kumar Gala diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 031c974..3233ff2 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -24,6 +24,7 @@ */ #include +#include #include #include @@ -246,6 +247,25 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif + /* + * Any LAWs that were set up before we booted assume they are meant to + * be around and mark them used. + */ + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u32 lawar = in_be32(LAWAR_ADDR(i)); + + if (lawar & LAW_EN) + gd->used_laws |= (1 << i); + } + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * in NAND boot we've already parsed the law_table and setup those LAWs + * so don't do it again. + */ + return; +#endif + for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, -- cgit v0.10.2 From dea8bd627c26bb2d17d7079b374352301af4a028 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 4 Feb 2011 13:57:59 -0800 Subject: powerpc/85xx: Update fixed DDR3 timing table for P4080DS Most of time U-boot doesn't get an exact clock number. For example, clock 900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the table to align the desired clocks in the middle. Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index ccb9da8..844e1d7 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -334,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { }; fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {800, 900, &ddr_cfg_regs_800}, - {900, 1000, &ddr_cfg_regs_900}, - {1000, 1200, &ddr_cfg_regs_1000}, - {1200, 1300, &ddr_cfg_regs_1200}, + {750, 850, &ddr_cfg_regs_800}, + {850, 950, &ddr_cfg_regs_900}, + {950, 1050, &ddr_cfg_regs_1000}, + {1050, 1250, &ddr_cfg_regs_1200}, {0, 0, NULL} }; fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {800, 900, &ddr_cfg_regs_800_2nd}, - {900, 1000, &ddr_cfg_regs_900_2nd}, - {1000, 1200, &ddr_cfg_regs_1000_2nd}, - {1200, 1300, &ddr_cfg_regs_1200_2nd}, + {750, 850, &ddr_cfg_regs_800_2nd}, + {850, 950, &ddr_cfg_regs_900_2nd}, + {950, 1050, &ddr_cfg_regs_1000_2nd}, + {1050, 1250, &ddr_cfg_regs_1200_2nd}, {0, 0, NULL} }; -- cgit v0.10.2 From c399765d9cb46e8e20739251d5f3151a5608328d Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 4 Feb 2011 13:58:00 -0800 Subject: powerpc/8xxx: Display DIMM model Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers embedded in SPD. Signed-off-by: York Sun Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 8b31ec0..00f3d6c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -207,10 +207,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, temp1 = temp2 = 0; for (i = 0; i < number_of_dimms; i++) { if (dimm_params[i].n_ranks) { - if (dimm_params[i].registered_dimm) + if (dimm_params[i].registered_dimm) { temp1 = 1; - if (!dimm_params[i].registered_dimm) + printf("Detected RDIMM %s\n", + dimm_params[i].mpart); + } else { temp2 = 1; + printf("Detected UDIMM %s\n", + dimm_params[i].mpart); + } } } @@ -218,10 +223,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->all_DIMMs_unbuffered = 0; if (temp1 && !temp2) { outpdimm->all_DIMMs_registered = 1; - printf("Detected RDIMM(s)\n"); } else if (!temp1 && temp2) { outpdimm->all_DIMMs_unbuffered = 1; - printf("Detected UDIMM(s)\n"); } else { printf("ERROR: Mix of registered buffered and unbuffered " "DIMMs detected!\n"); -- cgit v0.10.2 From 09f9ee1695136045f293dacda915d94c2891d4f0 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Mon, 7 Feb 2011 15:08:29 +0530 Subject: powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b67f70f..a217bcd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -264,7 +264,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< Date: Mon, 7 Feb 2011 15:09:51 +0530 Subject: fsl_ddr: Adds 16 bit DDR Data width option Signed-off-by: Poonam Aggrwal Cc: York Sun Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 815c5e3..b9a5a69 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -139,6 +139,8 @@ void board_add_ram_info(int use_default) if (sdram_cfg & SDRAM_CFG_32_BE) puts(", 32-bit"); + else if (sdram_cfg & SDRAM_CFG_16_BE) + puts(", 16-bit"); else puts(", 64-bit"); diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index b5b1efe..99dddb4 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 -- cgit v0.10.2 From a7b1e1b706a78f9208cb4128be9692e97f58e5ac Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Mon, 7 Feb 2011 16:14:15 -0500 Subject: powerpc/85xx: load ucode from nand flash before qe_init In the case the QE's microcode is stored in nand flash, we need to load it from NAND flash to ddr first then the qe_init can get the ucode correctly. Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 215b7b3..5642cd7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,10 @@ #include #include #include "mp.h" +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -448,6 +452,19 @@ void cpu_secondary_init_r(void) { #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#ifdef CONFIG_SYS_QE_FW_IN_NAND + int ret; + size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + + /* load QE firmware from NAND flash to DDR first */ + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + + if (ret && ret == -EUCLEAN) { + printf ("NAND read for QE firmware at offset %x failed %d\n", + CONFIG_SYS_QE_FW_IN_NAND, ret); + } +#endif qe_init(qe_base); qe_reset(); #endif -- cgit v0.10.2 From 298f8af17b5056fd4135708c1745572f351bd339 Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Sun, 13 Mar 2011 10:00:40 -0500 Subject: echi: add ULI1575 PCI ID Add ULI1575 EHCI controller to the list of the supported devices. Signed-off-by: Zhao Chenhui Acked-by: Remy Bohmer Signed-off-by: Kumar Gala diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index cff3438..bf490b0 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -29,6 +29,7 @@ static struct pci_device_id ehci_pci_ids[] = { /* Please add supported PCI EHCI controller ids here */ {0x1033, 0x00E0}, + {0x10b9, 0x5239}, /* ULI1575 PCI EHCI module ids */ {0, 0} }; #endif -- cgit v0.10.2 From 093cffbe9a692bd6bb47b0775d015545b1628af8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 5 Feb 2011 13:45:07 -0600 Subject: powerpc/85xx: Support for Freescale P1024/P1025 processor Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors. P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core. Added comments in config_mpc85xx.h to denote single core versions of processors. Signed-off-by: Jin Qing Signed-off-by: Li Yang Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 5791be0..d61d34c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1014) += ddr-gen3.o +COBJS-$(CONFIG_P1015) += ddr-gen3.o +COBJS-$(CONFIG_P1016) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o +COBJS-$(CONFIG_P1024) += ddr-gen3.o +COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o @@ -92,11 +96,15 @@ COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o COBJS-$(CONFIG_P1014) += p1010_serdes.o +COBJS-$(CONFIG_P1015) += p1021_serdes.o +COBJS-$(CONFIG_P1016) += p1021_serdes.o COBJS-$(CONFIG_P1017) += p1023_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_P1023) += p1023_serdes.o +COBJS-$(CONFIG_P1024) += p1021_serdes.o +COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index d2baaf0..39b304a 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -74,6 +74,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), + CPU_TYPE_ENTRY(P1015, P1015_E, 1), + CPU_TYPE_ENTRY(P1015, P1015, 1), + CPU_TYPE_ENTRY(P1016, P1016_E, 1), + CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), @@ -84,6 +88,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P1023, P1023, 2), CPU_TYPE_ENTRY(P1023, P1023_E, 2), + CPU_TYPE_ENTRY(P1024, P1024, 2), + CPU_TYPE_ENTRY(P1024, P1024_E, 2), + CPU_TYPE_ENTRY(P1025, P1025, 2), + CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9437301..040e71b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -92,20 +92,27 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +/* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +/* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +/* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -121,6 +128,27 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +/* P1015 is single core version of P1024 */ +#elif defined(CONFIG_P1015) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1016 is single core version of P1025 */ +#elif defined(CONFIG_P1016) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -137,6 +165,8 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -144,6 +174,8 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -164,6 +196,27 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +/* P1024 is lower end variant of P1020 */ +#elif defined(CONFIG_P1024) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1025 is lower end variant of P1021 */ +#elif defined(CONFIG_P1025) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P2010 is single core version of P2020 */ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -220,6 +273,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +/* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index d8b8f34..f5bf4dd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,6 +1048,10 @@ #define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 #define SVR_P1014_E 0x80F901 +#define SVR_P1015 0x80E502 +#define SVR_P1015_E 0x80ED02 +#define SVR_P1016 0x80E503 +#define SVR_P1016_E 0x80ED03 #define SVR_P1017 0x80F700 #define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 @@ -1058,6 +1062,10 @@ #define SVR_P1022_E 0x80EE00 #define SVR_P1023 0x80F600 #define SVR_P1023_E 0x80FE00 +#define SVR_P1024 0x80E402 +#define SVR_P1024_E 0x80EC02 +#define SVR_P1025 0x80E403 +#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -- cgit v0.10.2 From 1fbf3483b75f93c86b94439d4e0181d1b0546c92 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Sun, 6 Feb 2011 11:31:44 +0530 Subject: powerpc/85xx: Adds some P1010/P1014 SoC configuration defines Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 040e71b..ac304f3 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -91,6 +91,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -127,6 +131,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* P1015 is single core version of P1024 */ #elif defined(CONFIG_P1015) -- cgit v0.10.2 From 7d640e9bdf5e38f7f40f8becc47dc4036943f01a Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Feb 2011 15:45:25 +0530 Subject: powerpc/85xx: Corrected sdhc clock value for P1010 SDHC clock is equal to CCB on P1010 and P1014 not CCB/2. Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9d749c3..faca451 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -262,7 +262,8 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_MPC8569 +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) gd->sdhc_clk = gd->bus_clk; #else gd->sdhc_clk = gd->bus_clk / 2; -- cgit v0.10.2 From c657d898bcf95d5af15f081ed9f03e0ea5b1a16e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 4 Feb 2011 00:43:34 -0600 Subject: powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ac304f3..0529632 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -166,6 +166,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -203,6 +204,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -246,6 +248,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -255,11 +258,13 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -271,6 +276,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -290,6 +296,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -299,6 +306,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #else #error Processor type not defined for this platform -- cgit v0.10.2 From f098c9c880f08c7b090a4c5bcb924eef1663a32e Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 9 Feb 2011 02:00:09 +0000 Subject: fsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1 The NXID EEPROM format comes in two versions, v0 and v1. The only difference is in the number of MAC addresses that can be stored. NXID v0 supports eight addresses, and NXID v1 supports 23. Rather than allow a board to choose which version to support, NXID v0 is now considered deprecated. The EEPROM code is updated to support only NXID v1, but it can still read EEPROMs formatted with v0. In these cases, the EEPROM data is loaded and the CRC is verified, but the data is stored into a v1 data structure. If the EEPROM data is written back, it is written in v1 format. This allows existing v0-formatted EEPROMs to continue providing MAC addresses, but any changes to the data will force an upgrade to the v1 format, while retaining all data. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3ecfb06..d2ed036 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2008-2009 Freescale Semiconductor + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor * York Sun (yorksun@freescale.com) * Haiying Wang (haiying.wang@freescale.com) * Timur Tabi (timur@freescale.com) @@ -34,12 +34,6 @@ #endif #ifdef CONFIG_SYS_I2C_EEPROM_NXID -#define MAX_NUM_PORTS 8 -#define NXID_VERSION 0 -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1 -#define CONFIG_SYS_I2C_EEPROM_NXID #define MAX_NUM_PORTS 23 #define NXID_VERSION 1 #endif @@ -428,11 +422,16 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * This ensures that any user-saved variables are never overwritten. * * This function must be called after relocation. + * + * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 + * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is + * located at a different offset. */ int mac_read_from_eeprom(void) { unsigned int i; - u32 crc; + u32 crc, crc_offset = offsetof(struct eeprom, crc); + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ puts("EEPROM: "); @@ -447,12 +446,32 @@ int mac_read_from_eeprom(void) return -1; } - crc = crc32(0, (void *)&e, sizeof(e) - 4); - if (crc != be32_to_cpu(e.crc)) { +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * If we've read an NXID v0 EEPROM, then we need to set the CRC offset + * to where it is in v0. + */ + if (e.version == 0) + crc_offset = 0x72; +#endif + + crc = crc32(0, (void *)&e, crc_offset); + crcp = (void *)&e + crc_offset; + if (crc != be32_to_cpu(*crcp)) { printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); return -1; } +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * MAC address #9 in v1 occupies the same position as the CRC in v0. + * Erase it so that it's not mistaken for a MAC address. We'll + * update the CRC later. + */ + if (e.version == 0) + memset(e.mac[8], 0xff, 6); +#endif + for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { @@ -482,6 +501,17 @@ int mac_read_from_eeprom(void) printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * Now we need to upconvert the data into v1 format. We do this last so + * that at boot time, U-Boot will still say "NXID v0". + */ + if (e.version == 0) { + e.version = NXID_VERSION; + update_crc(); + } +#endif + return 0; } -- cgit v0.10.2 From 0c871e952e77fe9f3b88d52778d2b5d82da4d884 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Feb 2011 13:13:15 +0530 Subject: powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 44faec3..853044e 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -202,6 +202,17 @@ phys_size_t fixed_sdram (void) struct cpu_type *cpu; ulong ddr_freq, ddr_freq_mhz; + cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } else { + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + } +#if defined(CONFIG_SYS_RAMBOOT) + return ddr_size; +#endif ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; @@ -220,16 +231,12 @@ phys_size_t fixed_sdram (void) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); - cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; - ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } - else - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index a46b1b5..9b166b2 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -80,15 +80,10 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1G, 1) #endif }; diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a217bcd..53ec56f 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -57,14 +57,14 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifndef CONFIG_SYS_TEXT_BASE -- cgit v0.10.2 From cac29f25fdda1fcbc962629825d309da87618faf Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Feb 2011 13:18:34 +0530 Subject: powerpc/85xx: Read board switch settings on p1_p2_rdb PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width. On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI] switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width. Signed-off-by: Priyanka Jain Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 806d90e..9f57a21 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -142,6 +143,30 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int orig_bus = i2c_get_bus_num(); + u8 i2c_data; + + i2c_set_bus_num(1); + if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, + 1, &i2c_data, sizeof(i2c_data)) == 0) { + if (i2c_data & 0x2) + puts("NOR Flash Bank : Secondary\n"); + else + puts("NOR Flash Bank : Primary\n"); + + if (i2c_data & 0x1) { + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + puts("SD/MMC : 8-bit Mode\n"); + puts("eSPI : Disabled\n"); + } else { + puts("SD/MMC : 4-bit Mode\n"); + puts("eSPI : Enabled\n"); + } + } else { + puts("Failed reading I2C Chip 0x18 on bus 1\n"); + } + i2c_set_bus_num(orig_bus); /* * Remap Boot flash region to caching-inhibited diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 53ec56f..6f2088e 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -362,6 +362,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 + #define CONFIG_RTC_DS1337 #define CONFIG_SYS_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -- cgit v0.10.2 From 3313b20b950060723e6897870f793db7d3582084 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 9 Feb 2011 23:24:11 +0530 Subject: powerpc/85xx: Removed P1/P2 RDB RevB support RevB boards never really made it outside of Freescale and have been replaced with RevC & RevD which had various board bug fixes. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 9f57a21..d4b4b68 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -55,38 +55,25 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSCLK_MASK 0x00200000 #define BOARDREV_MASK 0x10100000 -#define BOARDREV_B 0x10100000 #define BOARDREV_C 0x00100000 #define BOARDREV_D 0x00000000 #define SYSCLK_66 66666666 -#define SYSCLK_50 50000000 #define SYSCLK_100 100000000 unsigned long get_board_sys_clk(ulong dummy) { volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio, board_rev_gpio; + u32 val_gpdat, sysclk_gpio; val_gpdat = in_be32(&pgpio->gpdat); sysclk_gpio = val_gpdat & SYSCLK_MASK; - board_rev_gpio = val_gpdat & BOARDREV_MASK; - if (board_rev_gpio == BOARDREV_C) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } else if (board_rev_gpio == BOARDREV_B) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_50; - } else if (board_rev_gpio == BOARDREV_D) { - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - } + + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_100; + return 0; } @@ -113,8 +100,6 @@ int checkboard (void) board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; - else if (board_rev_gpio == BOARDREV_B) - board_rev = 'B'; else if (board_rev_gpio == BOARDREV_D) board_rev = 'D'; else -- cgit v0.10.2 From 66c74fca18aab4c4182be486641d7a374689c4c3 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Mon, 7 Feb 2011 17:17:28 +0530 Subject: powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 853044e..71c6088 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -74,13 +74,13 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 #define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 #define CONFIG_SYS_DDR_MODE_1_800 0x00040852 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, -- cgit v0.10.2 From e0082f7cb4985b7fbf3a69fbf884a85bd15af87a Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 9 Feb 2011 20:05:29 +0000 Subject: powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Kumar Gala diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index d4b4b68..307c3e2 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -107,6 +107,9 @@ int checkboard (void) cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) \n"); +#endif setbits_be32(&pgpio->gpdir, GPIO_DIR); /* diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 9b166b2..1847935 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -25,19 +25,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), diff --git a/boards.cfg b/boards.cfg index 45c3102..263c1e6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -509,15 +509,24 @@ MPC8572DS powerpc mpc85xx mpc8572ds freesca MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB +P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT +P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD +P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB +P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT +P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD +P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB +P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT +P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD +P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH @@ -525,6 +534,9 @@ P2020DS powerpc mpc85xx p2020ds freesca P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB +P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT +P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD +P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6f2088e..4103e8b 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + #ifdef CONFIG_P1011RDB #define CONFIG_P1011 #endif @@ -123,6 +127,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -144,7 +153,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ @@ -197,13 +210,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -231,6 +248,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ @@ -242,10 +271,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE 0xfff00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -292,7 +331,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#else #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#endif #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ | BR_PS_8 | BR_V) @@ -376,23 +419,41 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- cgit v0.10.2 From 1a66f289160c265a27fba29225aae6c0a1d9116a Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Wed, 2 Mar 2011 16:44:36 +0800 Subject: powerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DS Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 4224229..2b0e58b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -741,7 +741,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "memctl_intlv_ctl=2\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ -- cgit v0.10.2 From 5103d7aa23b33b9c4c5b6221248109eb6672c7b1 Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Wed, 2 Mar 2011 16:44:52 +0800 Subject: powerpc/85xx: Disable ECC in considering performance on MPC8572DS Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2b0e58b..0f419c5 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -741,7 +741,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=bank\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ -- cgit v0.10.2 From 863a3eac23362e70f12a456e6b563c416cbc43fc Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Fri, 4 Mar 2011 16:31:41 +0800 Subject: powerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DS MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage device support using PCI EHCI module. Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 0f419c5..8c0d06a 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -672,6 +672,20 @@ #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI_PCI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_STORAGE +#define CONFIG_PCI_EHCI_DEVICE 0 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#endif + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* -- cgit v0.10.2 From b5c8753fa173d6372d86dcd11f83ef23c911b0de Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Feb 2011 02:03:29 -0600 Subject: powerpc/85xx: Fixup determining PME, FMan freq On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index faca451..f26de6c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,25 +107,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0529632..4228161 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -243,6 +243,7 @@ #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -252,6 +253,7 @@ #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -262,12 +264,14 @@ #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -290,6 +294,7 @@ /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -300,6 +305,7 @@ #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 -- cgit v0.10.2 From 939cdcdc622840d43dd01b6a9509abcb6f4c24f6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Mar 2011 06:09:20 -0600 Subject: powerpc/85xx: Fix determining Fman freq on P1023 On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2 of it. Also we only have one Fman so no need for the code to deal with a second. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f26de6c..e530494 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -190,10 +190,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif #ifdef CONFIG_SYS_DPAA_FMAN - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; -#if (CONFIG_SYS_NUM_FMAN) == 2 - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; -#endif + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; #endif #endif /* CONFIG_FSL_CORENET */ -- cgit v0.10.2 From f5feb5afb2d4cd02480056c37ebc111de3ee04fc Mon Sep 17 00:00:00 2001 From: bhaskar upadhaya Date: Wed, 2 Feb 2011 14:44:28 +0000 Subject: powerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree Fix up the device tree property associated with the IEEE 1588 timer source frequency. Currently we only support the IEEE 1588 timer source being the internal eTSEC system clock (for those SoCs with IEEE 1588 support). The eTSEC clock is ccb_clk/2. Signed-off-by: Bhaskar Upadhaya Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6ed0284..642f6c5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -486,4 +486,13 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_SRIO ft_srio_setup(blob); #endif + + /* + * system-clock = CCB clock/2 + * Here gd->bus_clk = CCB clock + * We are using the system clock as 1588 Timer reference + * clock source select + */ + do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", + "timer-frequency", gd->bus_clk/2, 1); } -- cgit v0.10.2 From 19d68d202786efe7400dc2a6412c2d06b2ab38ec Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 27 Jan 2011 19:02:50 +0800 Subject: tsec: add AR8021 PHY support Signed-off-by: Li Yang diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9c8fe62..9a91b9e 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1810,6 +1810,28 @@ static struct phy_info phy_info_rtl8211b = { }, }; +struct phy_info phy_info_AR8021 = { + 0x4dd04, + "AR8021", + 4, + (struct phy_cmd[]) { /* config */ + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL}, + {0x1d, 0x05, NULL}, + {0x1e, 0x3D47, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, &mii_parse_link}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + } +}; + static struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_cis8201, @@ -1832,6 +1854,7 @@ static struct phy_info *phy_info[] = { &phy_info_VSC8221, &phy_info_dp83865, &phy_info_rtl8211b, + &phy_info_AR8021, &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ NULL }; -- cgit v0.10.2 From 9899ac1951331b855152f8b5d9a8b540936ee947 Mon Sep 17 00:00:00 2001 From: Jiang Yutang Date: Mon, 24 Jan 2011 18:21:15 +0800 Subject: powerpc/85xx: Add 36-bit address map support to P1022DS Signed-off-by: Jiang Yutang Signed-off-by: Kumar Gala diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 62beafa..6f20dc3 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -53,6 +53,9 @@ int checkboard(void) u8 sw; puts("Board: P1022DS "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); diff --git a/boards.cfg b/boards.cfg index 263c1e6..2622f78 100644 --- a/boards.cfg +++ b/boards.cfg @@ -523,6 +523,7 @@ P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale +P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5f47d1a..c15cb8d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -14,6 +14,10 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -39,10 +43,11 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PHYS_64BIT +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif #define CONFIG_FSL_LAW /* Use common FSL init code */ @@ -65,7 +70,11 @@ */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* DDR Setup */ @@ -111,7 +120,11 @@ * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) @@ -145,7 +158,11 @@ #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) @@ -241,32 +258,59 @@ /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI -- cgit v0.10.2 From 33e683541eb12e898524f85803abae659af7be54 Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Tue, 15 Mar 2011 16:37:36 +0200 Subject: powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020 We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by: Laurentiu TUDOR Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index febbee9..1255898 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index df25048..fd155c8 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -44,9 +44,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 156), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), + SET_PCI_LIODN("fsl,p4080-pcie", 1, 193), + SET_PCI_LIODN("fsl,p4080-pcie", 2, 194), + SET_PCI_LIODN("fsl,p4080-pcie", 3, 195), SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index febbee9..1255898 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index f76676c..0ec5c0a 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -70,8 +70,8 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) -#define SET_PCI_LIODN(pciNum, liodn) \ - SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\ +#define SET_PCI_LIODN(compat, pciNum, liodn) \ + SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ -- cgit v0.10.2 From e820a131f4084397a212c6ffe3ed8ea0ce43631f Mon Sep 17 00:00:00 2001 From: Kyle Moffett Date: Tue, 15 Mar 2011 11:23:47 -0400 Subject: fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies. Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily restructure the computation to use the "do_div()" function to perform 64-bit/32-bit divide operations. On 64-bit this change is basically a no-op, because do_div is implemented as a literal 64-bit divide operation and the instruction scheduling works out almost the same. On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is over 1.1kB of code and thousands of heavily dependent cycles to compute, all of which is linked from libgcc. Another 1.2kB of code comes in for the function __umoddi3. It should be noted that nothing else in U-Boot or the Linux kernel seems to require a full 64-bit divide on my 32-bit PowerPC. Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection. Signed-off-by: Kyle Moffett Acked-by: York Sun Cc: Andy Fleming Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index b9a5a69..02908b4 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -8,9 +8,17 @@ #include #include +#include #include "ddr.h" +/* To avoid 64-bit full-divides, we factor this here */ +#define ULL_2e12 2000000000000ULL +#define UL_5pow12 244140625UL +#define UL_2pow13 (1UL << 13) + +#define ULL_8Fs 0xFFFFFFFFULL + /* * Round mclk_ps to nearest 10 ps in memory controller code. * @@ -20,35 +28,51 @@ */ unsigned int get_memory_clk_period_ps(void) { - unsigned int mclk_ps; + unsigned int data_rate = get_ddr_freq(0); + unsigned int result; + + /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ + unsigned long long mclk_ps = ULL_2e12; - mclk_ps = 2000000000000ULL / get_ddr_freq(0); - /* round to nearest 10 ps */ - return 10 * ((mclk_ps + 5) / 10); + /* Add 5*data_rate, for rounding */ + mclk_ps += 5*(unsigned long long)data_rate; + + /* Now perform the big divide, the result fits in 32-bits */ + do_div(mclk_ps, data_rate); + result = mclk_ps; + + /* We still need to round to 10ps */ + return 10 * (result/10); } /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ unsigned int picos_to_mclk(unsigned int picos) { - const unsigned long long ULL_2e12 = 2000000000000ULL; - const unsigned long long ULL_8Fs = 0xFFFFFFFFULL; - unsigned long long clks; - unsigned long long clks_temp; + unsigned long long clks, clks_rem; + /* Short circuit for zero picos */ if (!picos) return 0; - clks = get_ddr_freq(0) * (unsigned long long) picos; - clks_temp = clks; - clks = clks / ULL_2e12; - if (clks_temp % ULL_2e12) { + /* First multiply the time by the data rate (32x32 => 64) */ + clks = picos * (unsigned long long)get_ddr_freq(0); + + /* + * Now divide by 5^12 and track the 32-bit remainder, then divide + * by 2*(2^12) using shifts (and updating the remainder). + */ + clks_rem = do_div(clks, UL_5pow12); + clks_rem <<= 13; + clks_rem |= clks & (UL_2pow13-1); + clks >>= 13; + + /* If we had a remainder, then round up */ + if (clks_rem) clks++; - } - if (clks > ULL_8Fs) { + /* Clamp to the maximum representable value */ + if (clks > ULL_8Fs) clks = ULL_8Fs; - } - return (unsigned int) clks; } -- cgit v0.10.2 From c7fd27ccfb3225ffaf2ad88c44a89eeccc1008ac Mon Sep 17 00:00:00 2001 From: Kyle Moffett Date: Mon, 28 Mar 2011 11:35:48 -0400 Subject: mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett Cc: Andy Fleming Cc: Kim Phillips Acked-by: York Sun Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index dcb37ce..b565e33 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -250,24 +250,27 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, pdimm->primary_sdram_width = spd->primw; pdimm->ec_sdram_width = spd->ecw; - /* FIXME: what about registered SO-DIMM? */ + /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ switch (spd->dimm_type) { - case 0x01: /* RDIMM */ - case 0x10: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + case DDR2_SPD_DIMMTYPE_RDIMM: + case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: + case DDR2_SPD_DIMMTYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; break; - case 0x02: /* UDIMM */ - case 0x04: /* SO-DIMM */ - case 0x08: /* Micro-DIMM */ - case 0x20: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + case DDR2_SPD_DIMMTYPE_UDIMM: + case DDR2_SPD_DIMMTYPE_SO_DIMM: + case DDR2_SPD_DIMMTYPE_MICRO_DIMM: + case DDR2_SPD_DIMMTYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + pdimm->registered_dimm = 0; break; + case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: default: printf("unknown dimm_type 0x%02X\n", spd->dimm_type); return 1; - break; } /* SDRAM device parameters */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 29cea53..756b15f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -128,24 +128,32 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; - switch (spd->module_type & 0xf) { - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + /* These are the types defined by the JEDEC DDR3 SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { + case DDR3_SPD_MODULETYPE_RDIMM: + case DDR3_SPD_MODULETYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; for (i = 0; i < 16; i += 2) { - pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F; - pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F; + u8 rcw = spd->mod_section.registered.rcw[i/2]; + pdimm->rcw[i] = (rcw >> 0) & 0x0F; + pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; } break; - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + + case DDR3_SPD_MODULETYPE_UDIMM: + case DDR3_SPD_MODULETYPE_SO_DIMM: + case DDR3_SPD_MODULETYPE_MICRO_DIMM: + case DDR3_SPD_MODULETYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; break; default: - printf("unknown dimm_type 0x%02X\n", spd->module_type); + printf("unknown module_type 0x%02X\n", spd->module_type); return 1; } @@ -303,16 +311,5 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) * mtb_ps; - /* - * We need check the address mirror for unbuffered DIMM - * If SPD indicate the address map mirror, The DDR controller - * need care it. - */ - if ((spd->module_type == SPD_MODULETYPE_UDIMM) || - (spd->module_type == SPD_MODULETYPE_SODIMM) || - (spd->module_type == SPD_MODULETYPE_MICRODIMM) || - (spd->module_type == SPD_MODULETYPE_MINIUDIMM)) - pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1; - return 0; } diff --git a/common/ddr_spd.c b/common/ddr_spd.c index a7a30de..7a388bb 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -18,7 +18,7 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) /* * Check SPD revision supported - * Rev 1.2 or less supported by this code + * Rev 1.X or less supported by this code */ if (spd_rev >= 0x20) { printf("SPD revision %02X not supported by this code\n", diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 710e528..e895d61 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -304,14 +304,24 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) -/* - * Byte 3 Key Byte / Module Type for DDR3 SPD - */ -#define SPD_MODULETYPE_RDIMM (0x01) -#define SPD_MODULETYPE_UDIMM (0x02) -#define SPD_MODULETYPE_SODIMM (0x03) -#define SPD_MODULETYPE_MICRODIMM (0x04) -#define SPD_MODULETYPE_MINIRDIMM (0x05) -#define SPD_MODULETYPE_MINIUDIMM (0x06) +/* DIMM Type for DDR2 SPD (according to v1.3) */ +#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) +#define DDR2_SPD_DIMMTYPE_RDIMM (0x01) +#define DDR2_SPD_DIMMTYPE_UDIMM (0x02) +#define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) +#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) +#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) +#define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) +#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) +#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) + +/* Byte 3 Key Byte / Module Type for DDR3 SPD */ +#define DDR3_SPD_MODULETYPE_MASK (0x0f) +#define DDR3_SPD_MODULETYPE_RDIMM (0x01) +#define DDR3_SPD_MODULETYPE_UDIMM (0x02) +#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) +#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) #endif /* _DDR_SPD_H_ */ -- cgit v0.10.2 From c2a63f48fb6cc5e242133dacb5a9bcb8c29db53e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 18 Mar 2011 11:53:06 -0500 Subject: powerpc/8xxx: Fix typo for address hashing message Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index ee7ef0f..02d069c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1305,7 +1305,7 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { if (popts->addr_hash) { ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Addess hashing enabled.\n"); + puts("Address hashing enabled.\n"); } } -- cgit v0.10.2 From 97039ab98c551c7860bc0977d684ef686159e0d7 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 24 Jan 2011 17:09:55 +0000 Subject: env_mmc: Allow board code to override the environment address On some boards the environment may not be located at a fixed address in the MMC/SDHC card. This allows those boards to implement their own means to report what address the environment is located at. Signed-off-by: Mingkai Hu Signed-off-by: Jerry Huang Signed-off-by: Zhao Chenhui Acked-by: Andy Fleming Signed-off-by: Kumar Gala diff --git a/common/env_mmc.c b/common/env_mmc.c index 71dcc4c..83f40f4 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * (C) Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,19 @@ static void use_default(void); DECLARE_GLOBAL_DATA_PTR; +#if !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0 +#endif + +static int __mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) +{ + *env_addr = CONFIG_ENV_OFFSET; + return 0; +} +__attribute__((weak, alias("__mmc_get_env_addr"))) +int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr); + + uchar env_get_char_spec(int index) { return *((uchar *)(gd->env_addr + index)); @@ -102,10 +115,14 @@ int saveenv(void) ssize_t len; char *res; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + u32 offset; if (init_mmc_for_env(mmc)) return 1; + if(mmc_get_env_addr(mmc, &offset)) + return 1; + res = (char *)&env_new.data; len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { @@ -114,7 +131,7 @@ int saveenv(void) } env_new.crc = crc32(0, env_new.data, ENV_SIZE); printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV); - if (write_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)&env_new)) { + if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)&env_new)) { puts("failed\n"); return 1; } @@ -141,16 +158,22 @@ inline int read_env(struct mmc *mmc, unsigned long size, void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) - char buf[CONFIG_ENV_SIZE]; + char buf[CONFIG_ENV_SIZE]; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + u32 offset; if (init_mmc_for_env(mmc)) { use_default(); return; } - if (read_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf)) { + if(mmc_get_env_addr(mmc, &offset)) { + use_default(); + return ; + } + + if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) { use_default(); return; } -- cgit v0.10.2 From 1ac63e4094eee321266d5e5129077a3247d9439a Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Mon, 24 Jan 2011 17:09:54 +0000 Subject: powerpc/85xx: Enable eSDHC boot support on P2020 DS We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by: Jerry Huang Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 1abd3e5..8ea5acb 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -36,6 +36,7 @@ COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o +COBJS-$(CONFIG_ENV_IS_IN_MMC) += sdhc_boot.o COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c new file mode 100644 index 0000000..964c6b8 --- /dev/null +++ b/board/freescale/common/sdhc_boot.c @@ -0,0 +1,64 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * The environment variables are written to just after the u-boot image + * on SDCard, so we must read the MBR to get the start address and code + * length of the u-boot image, then calculate the address of the env. + */ +#define ESDHC_BOOT_IMAGE_SIZE 0x48 +#define ESDHC_BOOT_IMAGE_ADDR 0x50 + +int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) +{ + u8 *tmp_buf; + u32 blklen, code_offset, code_len, n; + + blklen = mmc->read_bl_len; + tmp_buf = malloc(blklen); + if (!tmp_buf) + return 1; + + /* read out the first block, get the config data information */ + n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf); + if (!n) { + free(tmp_buf); + return 1; + } + + /* Get the Source Address, from offset 0x50 */ + code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR); + + /* Get the code size from offset 0x48 */ + code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); + + *env_addr = code_offset + code_len; + + free(tmp_buf); + + return 0; +} + diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index 824b3b2..fd914a1 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_4K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 2622f78..a96e7cf 100644 --- a/boards.cfg +++ b/boards.cfg @@ -534,6 +534,7 @@ P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020DS powerpc mpc85xx p2020ds freescale P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 +P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 1815191..30da7b1 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -33,6 +33,13 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -93,6 +100,18 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L2 Cache + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ @@ -571,6 +590,11 @@ /* * Environment */ +#if defined(CONFIG_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 @@ -579,6 +603,7 @@ #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit v0.10.2 From 7d3053fbf16caad4745f42f7ae3e38e9d3e964b5 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 15 Feb 2011 17:09:19 -0600 Subject: powerpc: clean up DIU macro definitions for Freescale reference boards Clean up the macro defintions used to enable DIU (video) support on the MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS, which is newer. Add software cursor support to all three boards. Also document the CONFIG_FSL_DIU_FB in the README. Signed-off-by: Timur Tabi Acked-by: Anatolij Gustschin Signed-off-by: Kumar Gala diff --git a/README b/README index 21cd71b..bd03523 100644 --- a/README +++ b/README @@ -1074,6 +1074,28 @@ The following options need to be configured: and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP or CONFIG_VIDEO_SED13806_16BPP + CONFIG_FSL_DIU_FB + Enable the Freescale DIU video driver. Reference boards for + SOCs that have a DIU should define this macro to enable DIU + support, and should also define these other macros: + + CONFIG_SYS_DIU_ADDR + CONFIG_VIDEO + CONFIG_CMD_BMP + CONFIG_CFB_CONSOLE + CONFIG_VIDEO_SW_CURSOR + CONFIG_VGA_AS_SINGLE_DEVICE + CONFIG_VIDEO_LOGO + CONFIG_VIDEO_BMP_LOGO + + The DIU driver will look for the 'monitor' environment variable, + and if defined, enable the DIU as a console during boot. This + variable should be set to one of these values: + + '0' Output video to the DVI connector + '1' Output video to the LVDS connector + '2' Output video to the Dual-Link LVDS connector + - Keyboard Support: CONFIG_KEYBOARD diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 7b25e07..efe0313 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -21,14 +21,14 @@ #define CONFIG_SYS_TEXT_BASE 0xfff00000 -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ /* video */ -#undef CONFIG_VIDEO - -#ifdef CONFIG_VIDEO +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) +#define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -88,8 +88,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE @@ -494,9 +492,6 @@ #define CONFIG_WATCHDOG /* watchdog enabled */ #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ -/*DIU Configuration*/ -#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ - /* * Miscellaneous configurable options */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index c15cb8d..e78bcc5 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -202,13 +202,12 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Video */ -#undef CONFIG_FSL_DIU_FB - #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) #define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index f966325..e7ef298 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -46,16 +46,16 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* video */ -#undef CONFIG_VIDEO - -#ifdef CONFIG_VIDEO +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) +#define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -74,7 +74,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -- cgit v0.10.2