From d57259b95078accec01e58a63f783010b782ece4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 20 Apr 2017 20:36:25 +0200 Subject: u-boot.elf: remove hard-coded arm64 flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is needed in order to allow building it for other archs. Move relocation comment to a better place. Remove no longer needed dts FIXME. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Tom Rini diff --git a/Makefile b/Makefile index 600a4d6..d129e16 100644 --- a/Makefile +++ b/Makefile @@ -747,6 +747,9 @@ BOARD_SIZE_CHECK = endif # Statically apply RELA-style relocations (currently arm64 only) +# This is useful for arm64 where static relocation needs to be performed on +# the raw binary, but certain simulators only accept an ELF file (but don't +# do the relocation). ifneq ($(CONFIG_STATIC_RELA),) # $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base DO_STATIC_RELA = \ @@ -1180,14 +1183,9 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,pad_cat) -# Create a new ELF from a raw binary file. This is useful for arm64 -# where static relocation needs to be performed on the raw binary, -# but certain simulators only accept an ELF file (but don't do the -# relocation). -# FIXME refactor dts/Makefile to share target/arch detection +# Create a new ELF from a raw binary file. u-boot.elf: u-boot.bin - @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ - $< u-boot-elf.o + @$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o @$(LD) u-boot-elf.o -o $@ \ --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 2143633..a5eebb9 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -30,6 +30,12 @@ PLATFORM_RELFLAGS += $(LLVM_RELFLAGS) PLATFORM_CPPFLAGS += -D__ARM__ +ifdef CONFIG_ARM64 +PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64 +else +PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm +endif + # Choose between ARM/Thumb instruction sets ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) -- cgit v0.10.2 From 96ee1ada5dce6e193f68a2cd235cb3e8147178ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 20 Apr 2017 20:36:26 +0200 Subject: u-boot.elf: allow overriding entry symbol MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LD gives the following warning when trying to process u-boot-elf.o warning: cannot find entry symbol __start; defaulting to 0000000080010000 According to gnu-libc the entry symbol for mips is __start and not _start: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/mips/dl-machine.h;h=ed47513ccc1d23d23d32ee640053d2f351f3990b;hb=HEAD#l258 Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Tom Rini diff --git a/Makefile b/Makefile index d129e16..fd9d201 100644 --- a/Makefile +++ b/Makefile @@ -1184,10 +1184,13 @@ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,pad_cat) # Create a new ELF from a raw binary file. +ifndef PLATFORM_ELFENTRY + PLATFORM_ELFENTRY = "_start" +endif u-boot.elf: u-boot.bin @$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o @$(LD) u-boot-elf.o -o $@ \ - --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ + --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) # Rule to link u-boot -- cgit v0.10.2 From 47cf465c25d4c121d4b2befc67aabfa044a52389 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 20 Apr 2017 20:36:27 +0200 Subject: MIPS: add support for generating u-boot.elf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf Signed-off-by: Álvaro Fernández Rojas diff --git a/arch/mips/config.mk b/arch/mips/config.mk index dcd3460..2c72c15 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -36,6 +36,8 @@ OBJCOPYFLAGS += -O $(64bit-bfd) endif PLATFORM_CPPFLAGS += -D__MIPS__ +PLATFORM_ELFENTRY = "__start" +PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS) # # From Linux arch/mips/Makefile -- cgit v0.10.2 From e69945ee8a30676bfafb9b7956026bd11733f9b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 20 Apr 2017 20:36:28 +0200 Subject: u-boot.elf: add quiet_cmd_u-boot-elf and cmd_u-boot-elf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This way we can see output about u-boot.elf being built or not. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Tom Rini diff --git a/Makefile b/Makefile index fd9d201..57fa6ec 100644 --- a/Makefile +++ b/Makefile @@ -1187,11 +1187,13 @@ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE ifndef PLATFORM_ELFENTRY PLATFORM_ELFENTRY = "_start" endif +quiet_cmd_u-boot-elf ?= LD $@ + cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \ + --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ + -Ttext=$(CONFIG_SYS_TEXT_BASE) u-boot.elf: u-boot.bin - @$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o - @$(LD) u-boot-elf.o -o $@ \ - --defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \ - -Ttext=$(CONFIG_SYS_TEXT_BASE) + $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o + $(call if_changed,u-boot-elf) # Rule to link u-boot # May be overridden by arch/$(ARCH)/config.mk -- cgit v0.10.2 From 7b12ebe407794fb7b2ab3668b21969502bddd227 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 24 Apr 2017 19:03:31 +0200 Subject: MIPS: QCA AP121: remove debug_uart_init call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to add a generic MIPS debug_uart_init call right before the call to board_early_init_f, we need to remove all calls to debug_uart_init from every MIPS boards. Signed-off-by: Álvaro Fernández Rojas diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c index e245faa..ac9be35 100644 --- a/board/qca/ap121/ap121.c +++ b/board/qca/ap121/ap121.c @@ -43,9 +43,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif ddr_init(); ath79_eth_reset(); return 0; -- cgit v0.10.2 From 79f90ab1d255dc4417113bc9c8f3f46478aeb660 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 24 Apr 2017 19:03:32 +0200 Subject: MIPS: QCA AP143: remove debug_uart_init call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to add a generic MIPS debug_uart_init call right before the call to board_early_init_f, we need to remove all calls to debug_uart_init from every MIPS boards. Signed-off-by: Álvaro Fernández Rojas diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c index e921ea5..19b55ac 100644 --- a/board/qca/ap143/ap143.c +++ b/board/qca/ap143/ap143.c @@ -59,9 +59,6 @@ void board_debug_uart_init(void) int board_early_init_f(void) { -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); -#endif ddr_init(); ath79_eth_reset(); return 0; -- cgit v0.10.2 From fa9aee3aa379d15d4fbb225bc3d6b48521678182 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 24 Apr 2017 19:03:33 +0200 Subject: MIPS: tl-wdr4300: remove debug_uart_init call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to add a generic MIPS debug_uart_init call right before the call to board_early_init_f, we need to remove all calls to debug_uart_init from every MIPS boards. WDR4300 doesn't provide a board_debug_uart_init and configures pinmux in board_early_init_f instead. Since I have no idead of what's the needed uart pinmux config, I copied the whole pinmux config to a new function that is called from board_early_init_f if CONFIG_DEBUG_UART_BOARD_INIT is not enabled. Signed-off-by: Álvaro Fernández Rojas diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c index 6e070fd..0f59648 100644 --- a/board/tplink/wdr4300/wdr4300.c +++ b/board/tplink/wdr4300/wdr4300.c @@ -34,8 +34,7 @@ static void wdr4300_usb_start(void) static inline void wdr4300_usb_start(void) {} #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) +void wdr4300_pinmux_config(void) { void __iomem *regs; @@ -56,9 +55,20 @@ int board_early_init_f(void) writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3); writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4); writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5); +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + wdr4300_pinmux_config(); +} +#endif -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifndef CONFIG_DEBUG_UART_BOARD_INIT + wdr4300_pinmux_config(); #endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT -- cgit v0.10.2 From 0d159d6852e2bafc453206a327e267124704a30e Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Mon, 24 Apr 2017 19:03:34 +0200 Subject: MIPS: call debug_uart_init right before board_init_f MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All MIPS boards that support debug uart are calling debug_uart_init right at the beginning of board_early_init_f. Instead of doing that, let's provide a generic call to debug_uart_init right before the call to board_init_f if debug uart is enabled for boards without stack in SRAM. On the other hand, boards with stack in SRAM can call earlier (right before low level init). Signed-off-by: Daniel Schwierzeck Signed-off-by: Álvaro Fernández Rojas diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6740fdf..a6b7a04 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -237,6 +237,13 @@ wr_done: #ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM /* Set up initial stack and global data */ setup_stack_gd + +# ifdef CONFIG_DEBUG_UART + /* Earliest point to set up debug uart */ + PTR_LA t9, debug_uart_init + jalr t9 + nop +# endif #endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT @@ -263,6 +270,13 @@ wr_done: #ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM /* Set up initial stack and global data */ setup_stack_gd + +# ifdef CONFIG_DEBUG_UART + /* Earliest point to set up debug uart */ + PTR_LA t9, debug_uart_init + jalr t9 + nop +# endif #endif move a0, zero # a0 <-- boot_flags = 0 -- cgit v0.10.2 From 22c2c17915ba3f18d958bbf2c2f2c7facf2194cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:13 +0200 Subject: cmd: cpu: fix NULL cpu feature prints MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 740d5d3 added two new features but only one feature name, which results in NULL prints when device_id feature is selected. Before: HG556a # cpu detail -1: cpu@0 BCM6358A1 ID = 0, freq = 300 MHz: L1 cache, MMU, NULL Device ID 0x2a010 -1: cpu@1 BCM6358A1 ID = 1, freq = 300 MHz: L1 cache, MMU, NULL Device ID 0x2a010 After: HG556a # cpu detail -1: cpu@0 BCM6358A1 ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID Device ID 0x2a010 -1: cpu@1 BCM6358A1 ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID Device ID 0x2a010 Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass Reviewed-by: Tom Rini diff --git a/cmd/cpu.c b/cmd/cpu.c index bc4dc5c..adfd54a 100644 --- a/cmd/cpu.c +++ b/cmd/cpu.c @@ -15,6 +15,7 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = { "L1 cache", "MMU", "Microcode", + "Device ID", }; static int print_cpu_list(bool detail) -- cgit v0.10.2 From e388969178a471fed636f127faa49b141bd18aab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:14 +0200 Subject: sysreset: add syscon-reboot driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c, which provides a generic driver for platforms that only require writing a mask to a regmap offset. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 9664630..b2f7464 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -23,4 +23,12 @@ config SYSRESET_PSCI must be running on your system. endif + +config SYSRESET_SYSCON + bool "Enable support for mfd syscon reboot driver" + select REGMAP + select SYSCON + help + Reboot support for generic SYSCON mapped register reset. + endmenu diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 7bb8406..bd352e7 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o +obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c new file mode 100644 index 0000000..3818fae --- /dev/null +++ b/drivers/sysreset/sysreset_syscon.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/power/reset/syscon-reboot.c: + * Copyright (C) 2013, Applied Micro Circuits Corporation + * Author: Feng Kan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct syscon_reboot_priv { + struct regmap *regmap; + unsigned int offset; + unsigned int mask; +}; + +static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) +{ + struct syscon_reboot_priv *priv = dev_get_priv(dev); + + regmap_write(priv->regmap, priv->offset, priv->mask); + + return -EINPROGRESS; +} + +static struct sysreset_ops syscon_reboot_ops = { + .request = syscon_reboot_request, +}; + +int syscon_reboot_probe(struct udevice *dev) +{ + struct udevice *syscon; + struct syscon_reboot_priv *priv = dev_get_priv(dev); + int err; + + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "regmap", &syscon); + if (err) { + error("unable to find syscon device\n"); + return err; + } + + priv->regmap = syscon_get_regmap(syscon); + if (!priv->regmap) { + error("unable to find regmap\n"); + return -ENODEV; + } + + priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "offset", 0); + priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "mask", 0); + + return 0; +} + +static const struct udevice_id syscon_reboot_ids[] = { + { .compatible = "syscon-reboot" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(syscon_reboot) = { + .name = "syscon_reboot", + .id = UCLASS_SYSRESET, + .of_match = syscon_reboot_ids, + .probe = syscon_reboot_probe, + .priv_auto_alloc_size = sizeof(struct syscon_reboot_priv), + .ops = &syscon_reboot_ops, +}; -- cgit v0.10.2 From 5e36546c53abe9712193ed303edbfd47c660d121 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:15 +0200 Subject: MIPS: allow using generic sysreset drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c index 1b919ed..55e6498 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -12,6 +12,7 @@ #include #include +#ifndef CONFIG_SYSRESET void __weak _machine_restart(void) { fprintf(stderr, "*** reset failed ***\n"); @@ -26,6 +27,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#endif void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { -- cgit v0.10.2 From 3058104056f4d3b9ca382d64fd5f73fc16aa5590 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:16 +0200 Subject: serial: add serial driver for BCM6345 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is based on linux/drivers/tty/serial/bcm63xx_uart.c Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5832066..7249945 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -145,6 +145,14 @@ config DEBUG_UART_ATMEL will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_BCM6345 + bool "BCM6345 UART" + depends on BCM6345_SERIAL + help + Select this to enable a debug UART on BCM6345 SoCs. You + will need to provide parameters to make this work. The driver will + be available until the real driver model serial is running. + config DEBUG_UART_NS16550 bool "ns16550" help @@ -350,6 +358,12 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node. +config BCM6345_SERIAL + bool "Support for BCM6345 UART" + depends on DM_SERIAL && ARCH_BMIPS + help + Select this to enable UART on BCM6345 SoCs. + config FSL_LPUART bool "Freescale LPUART support" help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 4382cf9..dca31b2 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o +obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c new file mode 100644 index 0000000..db270e3 --- /dev/null +++ b/drivers/serial/serial_bcm6345.c @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/tty/serial/bcm63xx_uart.c: + * Copyright (C) 2008 Maxime Bizon + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +/* UART Control register */ +#define UART_CTL_REG 0x0 +#define UART_CTL_RXTIMEOUT_MASK 0x1f +#define UART_CTL_RXTIMEOUT_5 0x5 +#define UART_CTL_RSTRXFIFO_SHIFT 6 +#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) +#define UART_CTL_RSTTXFIFO_SHIFT 7 +#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) +#define UART_CTL_STOPBITS_SHIFT 8 +#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_BITSPERSYM_SHIFT 12 +#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) +#define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT) +#define UART_CTL_XMITBRK_SHIFT 14 +#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) +#define UART_CTL_RSVD_SHIFT 15 +#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) +#define UART_CTL_RXPAREVEN_SHIFT 16 +#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) +#define UART_CTL_RXPAREN_SHIFT 17 +#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) +#define UART_CTL_TXPAREVEN_SHIFT 18 +#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) +#define UART_CTL_TXPAREN_SHIFT 19 +#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) +#define UART_CTL_LOOPBACK_SHIFT 20 +#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) +#define UART_CTL_RXEN_SHIFT 21 +#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) +#define UART_CTL_TXEN_SHIFT 22 +#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) +#define UART_CTL_BRGEN_SHIFT 23 +#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) + +/* UART Baudword register */ +#define UART_BAUD_REG 0x4 + +/* UART FIFO Config register */ +#define UART_FIFO_CFG_REG 0x8 +#define UART_FIFO_CFG_RX_SHIFT 8 +#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT) +#define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT) +#define UART_FIFO_CFG_TX_SHIFT 12 +#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT) +#define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT) + +/* UART Interrupt register */ +#define UART_IR_REG 0x10 +#define UART_IR_STAT(x) (1 << (x)) +#define UART_IR_TXEMPTY 5 +#define UART_IR_RXOVER 7 +#define UART_IR_RXNOTEMPTY 11 + +/* UART FIFO register */ +#define UART_FIFO_REG 0x14 +#define UART_FIFO_VALID_MASK 0xff +#define UART_FIFO_FRAMEERR_SHIFT 8 +#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) +#define UART_FIFO_PARERR_SHIFT 9 +#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) +#define UART_FIFO_BRKDET_SHIFT 10 +#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) +#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ + UART_FIFO_PARERR_MASK | \ + UART_FIFO_BRKDET_MASK) + +struct bcm6345_serial_priv { + void __iomem *base; + ulong uartclk; +}; + +/* enable rx & tx operation on uart */ +static void bcm6345_serial_enable(void __iomem *base) +{ + setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | + UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); +} + +/* disable rx & tx operation on uart */ +static void bcm6345_serial_disable(void __iomem *base) +{ + clrbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | + UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); +} + +/* clear all unread data in rx fifo and unsent data in tx fifo */ +static void bcm6345_serial_flush(void __iomem *base) +{ + /* empty rx and tx fifo */ + setbits_be32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | + UART_CTL_RSTTXFIFO_MASK); + + /* read any pending char to make sure all irq status are cleared */ + readl_be(base + UART_FIFO_REG); +} + +static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{ + u32 val; + + /* mask all irq and flush port */ + bcm6345_serial_disable(base); + bcm6345_serial_flush(base); + + /* set uart control config */ + clrsetbits_be32(base + UART_CTL_REG, + /* clear rx timeout */ + UART_CTL_RXTIMEOUT_MASK | + /* clear stop bits */ + UART_CTL_STOPBITS_MASK | + /* clear bits per symbol */ + UART_CTL_BITSPERSYM_MASK | + /* clear xmit break */ + UART_CTL_XMITBRK_MASK | + /* clear reserved bit */ + UART_CTL_RSVD_MASK | + /* disable parity */ + UART_CTL_RXPAREN_MASK | + UART_CTL_TXPAREN_MASK | + /* disable loopback */ + UART_CTL_LOOPBACK_MASK, + /* set timeout to 5 */ + UART_CTL_RXTIMEOUT_5 | + /* set 8 bits/symbol */ + UART_CTL_BITSPERSYM_8 | + /* set parity to even */ + UART_CTL_RXPAREVEN_MASK | + UART_CTL_TXPAREVEN_MASK); + + /* set uart fifo config */ + clrsetbits_be32(base + UART_FIFO_CFG_REG, + /* clear fifo config */ + UART_FIFO_CFG_RX_MASK | + UART_FIFO_CFG_TX_MASK, + /* set fifo config to 4 */ + UART_FIFO_CFG_RX_4 | + UART_FIFO_CFG_TX_4); + + /* set baud rate */ + val = (clk / baudrate) / 16; + if (val & 0x1) + val = val; + else + val = val / 2 - 1; + writel_be(val, base + UART_BAUD_REG); + + /* clear interrupts */ + writel_be(0, base + UART_IR_REG); + + /* enable uart */ + bcm6345_serial_enable(base); + + return 0; +} + +static int bcm6345_serial_pending(struct udevice *dev, bool input) +{ + struct bcm6345_serial_priv *priv = dev_get_priv(dev); + u32 val = readl_be(priv->base + UART_IR_REG); + + if (input) + return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)); + else + return !(val & UART_IR_STAT(UART_IR_TXEMPTY)); +} + +static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct bcm6345_serial_priv *priv = dev_get_priv(dev); + + return bcm6345_serial_init(priv->base, priv->uartclk, baudrate); +} + +static int bcm6345_serial_putc(struct udevice *dev, const char ch) +{ + struct bcm6345_serial_priv *priv = dev_get_priv(dev); + u32 val; + + val = readl_be(priv->base + UART_IR_REG); + if (!(val & UART_IR_STAT(UART_IR_TXEMPTY))) + return -EAGAIN; + + writel_be(ch, priv->base + UART_FIFO_REG); + + return 0; +} + +static int bcm6345_serial_getc(struct udevice *dev) +{ + struct bcm6345_serial_priv *priv = dev_get_priv(dev); + u32 val; + + val = readl_be(priv->base + UART_IR_REG); + if (val & UART_IR_STAT(UART_IR_RXOVER)) + setbits_be32(priv->base + UART_CTL_REG, + UART_CTL_RSTRXFIFO_MASK); + if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY))) + return -EAGAIN; + + val = readl_be(priv->base + UART_FIFO_REG); + if (val & UART_FIFO_ANYERR_MASK) + return -EAGAIN; + + return val & UART_FIFO_VALID_MASK; +} + +static int bcm6345_serial_probe(struct udevice *dev) +{ + struct bcm6345_serial_priv *priv = dev_get_priv(dev); + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + /* get address */ + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = ioremap(addr, size); + + /* get clock rate */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + priv->uartclk = clk_get_rate(&clk) / 2; + clk_free(&clk); + + /* initialize serial */ + return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); +} + +static const struct dm_serial_ops bcm6345_serial_ops = { + .putc = bcm6345_serial_putc, + .pending = bcm6345_serial_pending, + .getc = bcm6345_serial_getc, + .setbrg = bcm6345_serial_setbrg, +}; + +static const struct udevice_id bcm6345_serial_ids[] = { + { .compatible = "brcm,bcm6345-uart" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6345_serial) = { + .name = "bcm6345-uart", + .id = UCLASS_SERIAL, + .of_match = bcm6345_serial_ids, + .probe = bcm6345_serial_probe, + .priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv), + .ops = &bcm6345_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_BCM6345 +static inline void _debug_uart_init(void) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void wait_xfered(void __iomem *base) +{ + do { + u32 val = readl_be(base + UART_IR_REG); + if (val & UART_IR_STAT(UART_IR_TXEMPTY)) + break; + } while (1); +} + +static inline void _debug_uart_putc(int ch) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + wait_xfered(base); + writel_be(ch, base + UART_FIFO_REG); + wait_xfered(base); +} + +DEBUG_UART_FUNCS +#endif -- cgit v0.10.2 From 320eca5cf77ebab347adab4f9bbdb5417b2da81d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:17 +0200 Subject: cmd: cpu: refactor to ensure devices are probed and improve code style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use uclass_first_device and uclass_next_device in order to avoid exceptions for drivers that aren't probed when cpu ops are requested. Improve code style and fix indentations. Fix incorrect line break when cpu info is not available. Remove unneeded brackets. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/cmd/cpu.c b/cmd/cpu.c index adfd54a..6213c72 100644 --- a/cmd/cpu.c +++ b/cmd/cpu.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2015 Google, Inc * Written by Simon Glass + * Copyright (c) 2017 Álvaro Fernández Rojas * * SPDX-License-Identifier: GPL-2.0+ */ @@ -21,20 +22,15 @@ static const char *cpu_feature_name[CPU_FEAT_COUNT] = { static int print_cpu_list(bool detail) { struct udevice *dev; - struct uclass *uc; char buf[100]; - int ret; - ret = uclass_get(UCLASS_CPU, &uc); - if (ret) { - printf("Cannot find CPU uclass\n"); - return ret; - } - uclass_foreach_dev(dev, uc) { + for (uclass_first_device(UCLASS_CPU, &dev); + dev; + uclass_next_device(&dev)) { struct cpu_platdata *plat = dev_get_parent_platdata(dev); struct cpu_info info; - bool first; - int i; + bool first = true; + int ret, i; ret = cpu_get_desc(dev, buf, sizeof(buf)); printf("%3d: %-10s %s\n", dev->seq, dev->name, @@ -45,13 +41,12 @@ static int print_cpu_list(bool detail) if (ret) { printf("\t(no detail available"); if (ret != -ENOSYS) - printf(": err=%d\n", ret); + printf(": err=%d", ret); printf(")\n"); continue; } printf("\tID = %d, freq = ", plat->cpu_id); print_freq(info.cpu_freq, ""); - first = true; for (i = 0; i < CPU_FEAT_COUNT; i++) { if (info.features & (1 << i)) { printf("%s%s", first ? ": " : ", ", @@ -60,10 +55,9 @@ static int print_cpu_list(bool detail) } } printf("\n"); - if (info.features & (1 << CPU_FEAT_UCODE)) { + if (info.features & (1 << CPU_FEAT_UCODE)) printf("\tMicrocode version %#x\n", plat->ucode_version); - } if (info.features & (1 << CPU_FEAT_DEVICE_ID)) printf("\tDevice ID %#lx\n", plat->device_id); } @@ -71,7 +65,8 @@ static int print_cpu_list(bool detail) return 0; } -static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) { if (print_cpu_list(false)) return CMD_RET_FAILURE; @@ -97,7 +92,7 @@ static cmd_tbl_t cmd_cpu_sub[] = { * Process a cpu sub-command */ static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) + char * const argv[]) { cmd_tbl_t *c = NULL; @@ -106,7 +101,8 @@ static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc, argv++; if (argc) - c = find_cmd_tbl(argv[0], cmd_cpu_sub, ARRAY_SIZE(cmd_cpu_sub)); + c = find_cmd_tbl(argv[0], cmd_cpu_sub, + ARRAY_SIZE(cmd_cpu_sub)); if (c) return c->cmd(cmdtp, flag, argc, argv); -- cgit v0.10.2 From 10e320483f9282c893efe7ed1ac4aaf4617f1787 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:18 +0200 Subject: cpu: add CPU driver for Broadcom MIPS SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index 8710160..db515f6 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -5,3 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # obj-$(CONFIG_CPU) += cpu-uclass.o + +obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c new file mode 100644 index 0000000..379acf2 --- /dev/null +++ b/drivers/cpu/bmips_cpu.c @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/bcm63xx/cpu.c: + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2009 Florian Fainelli + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define REV_CHIPID_SHIFT 16 +#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) +#define REV_LONG_CHIPID_SHIFT 12 +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) +#define REV_REVID_SHIFT 0 +#define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + +#define REG_BCM6328_OTP 0x62c +#define BCM6328_TP1_DISABLED BIT(9) + +#define REG_BCM6328_MISC_STRAPBUS 0x1a40 +#define STRAPBUS_6328_FCVO_SHIFT 7 +#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) + +#define REG_BCM6358_DDR_DMIPSPLLCFG 0x12b8 +#define DMIPSPLLCFG_6358_M1_SHIFT 0 +#define DMIPSPLLCFG_6358_M1_MASK (0xff << DMIPSPLLCFG_6358_M1_SHIFT) +#define DMIPSPLLCFG_6358_N1_SHIFT 23 +#define DMIPSPLLCFG_6358_N1_MASK (0x3f << DMIPSPLLCFG_6358_N1_SHIFT) +#define DMIPSPLLCFG_6358_N2_SHIFT 29 +#define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) + +#define REG_BCM63268_MISC_STRAPBUS 0x1814 +#define STRAPBUS_63268_FCVO_SHIFT 21 +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) + +struct bmips_cpu_priv; + +struct bmips_cpu_hw { + int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size); + ulong (*get_cpu_freq)(struct bmips_cpu_priv *); + int (*get_cpu_count)(struct bmips_cpu_priv *); +}; + +struct bmips_cpu_priv { + void __iomem *regs; + const struct bmips_cpu_hw *hw; +}; + +/* Specific CPU Ops */ +static int bcm6358_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf, + int size) +{ + unsigned short cpu_id; + unsigned char cpu_rev; + u32 val; + + val = readl_be(priv->regs); + cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; + + snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev); + + return 0; +} + +static int bcm6328_get_cpu_desc(struct bmips_cpu_priv *priv, char *buf, + int size) +{ + unsigned int cpu_id; + unsigned char cpu_rev; + u32 val; + + val = readl_be(priv->regs); + cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT; + cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT; + + snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev); + + return 0; +} + +static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int mips_pll_fcvo; + + mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS); + mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK) + >> STRAPBUS_6328_FCVO_SHIFT; + + switch (mips_pll_fcvo) { + case 0x12: + case 0x14: + case 0x19: + return 160000000; + case 0x1c: + return 192000000; + case 0x13: + case 0x15: + return 200000000; + case 0x1a: + return 384000000; + case 0x16: + return 400000000; + default: + return 320000000; + } +} + +static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int tmp, n1, n2, m1; + + tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG); + n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT; + n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT; + m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT; + + return (16 * 1000000 * n1 * n2) / m1; +} + +static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int mips_pll_fcvo; + + mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS); + mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK) + >> STRAPBUS_63268_FCVO_SHIFT; + + switch (mips_pll_fcvo) { + case 0x3: + case 0xe: + return 320000000; + case 0xa: + return 333000000; + case 0x2: + case 0xb: + case 0xf: + return 400000000; + default: + return 0; + } +} + +static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) +{ + u32 val = readl_be(priv->regs + REG_BCM6328_OTP); + + if (val & BCM6328_TP1_DISABLED) + return 1; + else + return 2; +} + +static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv) +{ + return 2; +} + +static const struct bmips_cpu_hw bmips_cpu_bcm6328 = { + .get_cpu_desc = bcm6328_get_cpu_desc, + .get_cpu_freq = bcm6328_get_cpu_freq, + .get_cpu_count = bcm6328_get_cpu_count, +}; + +static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { + .get_cpu_desc = bcm6358_get_cpu_desc, + .get_cpu_freq = bcm6358_get_cpu_freq, + .get_cpu_count = bcm6358_get_cpu_count, +}; + +static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { + .get_cpu_desc = bcm6328_get_cpu_desc, + .get_cpu_freq = bcm63268_get_cpu_freq, + .get_cpu_count = bcm6358_get_cpu_count, +}; + +/* Generic CPU Ops */ +static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) +{ + struct bmips_cpu_priv *priv = dev_get_priv(dev); + const struct bmips_cpu_hw *hw = priv->hw; + + return hw->get_cpu_desc(priv, buf, size); +} + +static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info) +{ + struct bmips_cpu_priv *priv = dev_get_priv(dev); + const struct bmips_cpu_hw *hw = priv->hw; + + info->cpu_freq = hw->get_cpu_freq(priv); + info->features = BIT(CPU_FEAT_L1_CACHE); + info->features |= BIT(CPU_FEAT_MMU); + info->features |= BIT(CPU_FEAT_DEVICE_ID); + + return 0; +} + +static int bmips_cpu_get_count(struct udevice *dev) +{ + struct bmips_cpu_priv *priv = dev_get_priv(dev); + const struct bmips_cpu_hw *hw = priv->hw; + + return hw->get_cpu_count(priv); +} + +static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size) +{ + snprintf(buf, size, "Broadcom"); + + return 0; +} + +static const struct cpu_ops bmips_cpu_ops = { + .get_desc = bmips_cpu_get_desc, + .get_info = bmips_cpu_get_info, + .get_count = bmips_cpu_get_count, + .get_vendor = bmips_cpu_get_vendor, +}; + +/* BMIPS CPU driver */ +int bmips_cpu_bind(struct udevice *dev) +{ + struct cpu_platdata *plat = dev_get_parent_platdata(dev); + + plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "reg", -1); + plat->device_id = read_c0_prid(); + + return 0; +} + +int bmips_cpu_probe(struct udevice *dev) +{ + struct bmips_cpu_priv *priv = dev_get_priv(dev); + const struct bmips_cpu_hw *hw = + (const struct bmips_cpu_hw *)dev_get_driver_data(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->hw = hw; + + return 0; +} + +static const struct udevice_id bmips_cpu_ids[] = { + { + .compatible = "brcm,bcm6328-cpu", + .data = (ulong)&bmips_cpu_bcm6328, + }, { + .compatible = "brcm,bcm6358-cpu", + .data = (ulong)&bmips_cpu_bcm6358, + }, { + .compatible = "brcm,bcm63268-cpu", + .data = (ulong)&bmips_cpu_bcm63268, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bmips_cpu_drv) = { + .name = "bmips_cpu", + .id = UCLASS_CPU, + .of_match = bmips_cpu_ids, + .bind = bmips_cpu_bind, + .probe = bmips_cpu_probe, + .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv), + .ops = &bmips_cpu_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + struct cpu_info cpu; + struct udevice *dev; + int err; + char desc[100]; + + err = uclass_get_device(UCLASS_CPU, 0, &dev); + if (err) + return 0; + + err = cpu_get_info(dev, &cpu); + if (err) + return 0; + + err = cpu_get_desc(dev, desc, sizeof(desc)); + if (err) + return 0; + + printf("Chip ID: %s, MIPS: ", desc); + print_freq(cpu.cpu_freq, "\n"); + + return 0; +} +#endif -- cgit v0.10.2 From 193030e5916960f101e1ba406510980452bc47b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:19 +0200 Subject: ram: add RAM driver for Broadcom MIPS SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index ecb036d..c409c48 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o +obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c new file mode 100644 index 0000000..9c0b23b --- /dev/null +++ b/drivers/ram/bmips_ram.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/bcm63xx/cpu.c: + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2009 Florian Fainelli + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MEMC_CFG_REG 0x4 +#define MEMC_CFG_32B_SHIFT 1 +#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) +#define MEMC_CFG_COL_SHIFT 3 +#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) +#define MEMC_CFG_ROW_SHIFT 6 +#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) + +#define DDR_CSEND_REG 0x8 + +struct bmips_ram_priv; + +struct bmips_ram_hw { + ulong (*get_ram_size)(struct bmips_ram_priv *); +}; + +struct bmips_ram_priv { + void __iomem *regs; + const struct bmips_ram_hw *hw; +}; + +static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv) +{ + return readl_be(priv->regs + DDR_CSEND_REG) << 24; +} + +static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv) +{ + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + + val = readl_be(priv->regs + MEMC_CFG_REG); + rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; + cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; + is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; + banks = 2; + + /* 0 => 11 address bits ... 2 => 13 address bits */ + rows += 11; + + /* 0 => 8 address bits ... 2 => 10 address bits */ + cols += 8; + + return 1 << (cols + rows + (is_32bits + 1) + banks); +} + +static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info) +{ + struct bmips_ram_priv *priv = dev_get_priv(dev); + const struct bmips_ram_hw *hw = priv->hw; + + info->base = 0x80000000; + info->size = hw->get_ram_size(priv); + + return 0; +} + +static const struct ram_ops bmips_ram_ops = { + .get_info = bmips_ram_get_info, +}; + +static const struct bmips_ram_hw bmips_ram_bcm6328 = { + .get_ram_size = bcm6328_get_ram_size, +}; + +static const struct bmips_ram_hw bmips_ram_bcm6358 = { + .get_ram_size = bcm6358_get_ram_size, +}; + +static const struct udevice_id bmips_ram_ids[] = { + { + .compatible = "brcm,bcm6328-mc", + .data = (ulong)&bmips_ram_bcm6328, + }, { + .compatible = "brcm,bcm6358-mc", + .data = (ulong)&bmips_ram_bcm6358, + }, { + .compatible = "brcm,bcm63268-mc", + .data = (ulong)&bmips_ram_bcm6328, + }, + { /* sentinel */ } +}; + +static int bmips_ram_probe(struct udevice *dev) +{ + struct bmips_ram_priv *priv = dev_get_priv(dev); + const struct bmips_ram_hw *hw = + (const struct bmips_ram_hw *)dev_get_driver_data(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->hw = hw; + + return 0; +} + +U_BOOT_DRIVER(bmips_ram) = { + .name = "bmips-mc", + .id = UCLASS_RAM, + .of_match = bmips_ram_ids, + .probe = bmips_ram_probe, + .priv_auto_alloc_size = sizeof(struct bmips_ram_priv), + .ops = &bmips_ram_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v0.10.2 From ee422142f454d54f0ed39a2cbf083ff12e98a3e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:20 +0200 Subject: MIPS: add initial infrastructure for Broadcom MIPS SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d97930e..c97ea41 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -75,6 +75,15 @@ config ARCH_ATH79 select OF_CONTROL select DM +config ARCH_BMIPS + bool "Support BMIPS SoCs" + select OF_CONTROL + select DM + select CLK + select CPU + select RAM + select SYSRESET + config MACH_PIC32 bool "Support Microchip PIC32" select OF_CONTROL @@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index efe7e44..c30d4ef 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 machine-$(CONFIG_ARCH_ATH79) += ath79 +machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index a6b7a04..d01ee9f 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -151,8 +151,13 @@ reset: mfc0 t0, CP0_GLOBALNUMBER #endif +#ifdef CONFIG_ARCH_BMIPS +1: mfc0 t0, CP0_DIAGNOSTIC, 3 + and t0, t0, (1 << 31) +#else 1: mfc0 t0, CP0_EBASE and t0, t0, EBASE_CPUNUM +#endif /* Hang if this isn't the first CPU in the system */ 2: beqz t0, 4f diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig new file mode 100644 index 0000000..4f4d351 --- /dev/null +++ b/arch/mips/mach-bmips/Kconfig @@ -0,0 +1,23 @@ +menu "Broadcom MIPS platforms" + depends on ARCH_BMIPS + +config SYS_SOC + default "none" + +choice + prompt "Boot mode" + +config BMIPS_BOOT_RAM + bool "RAM boot" + depends on BMIPS_SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a RAM address. It can be used + for booting from CFE via TFTP using an ELF image, but it can also be + booted from RAM by other bootloaders using a BIN image. + +endchoice + +config BMIPS_SUPPORTS_BOOT_RAM + bool + +endmenu diff --git a/arch/mips/mach-bmips/Makefile b/arch/mips/mach-bmips/Makefile new file mode 100644 index 0000000..f432acc --- /dev/null +++ b/arch/mips/mach-bmips/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dram.o diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c new file mode 100644 index 0000000..b19b28a --- /dev/null +++ b/arch/mips/mach-bmips/dram.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2016 Daniel Schwierzeck + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int err; + + err = uclass_get_device(UCLASS_RAM, 0, &dev); + if (err) { + debug("DRAM init failed: %d\n", err); + return 0; + } + + err = ram_get_info(dev, &ram); + if (err) { + debug("Cannot get DRAM size: %d\n", err); + return 0; + } + + debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h new file mode 100644 index 0000000..d2b05d4 --- /dev/null +++ b/include/configs/bmips_common.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_COMMON_H +#define __CONFIG_BMIPS_COMMON_H + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0xa0000000 +#define CONFIG_SYS_MEMTEST_END 0xa2000000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#endif /* __CONFIG_BMIPS_COMMON_H */ -- cgit v0.10.2 From e30d2bd40eaed27c5cead1b6e337e66f2b84d30e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:21 +0200 Subject: MIPS: add support for Broadcom MIPS BCM6358 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi new file mode 100644 index 0000000..48322fb --- /dev/null +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6358"; + + cpus { + reg = <0xfffe0000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@fffe0008 { + compatible = "syscon"; + reg = <0xfffe0008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@fffe0100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@fffe0120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@fffe1200 { + compatible = "brcm,bcm6358-mc"; + reg = <0xfffe1200 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 4f4d351..03cba72 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -2,7 +2,23 @@ menu "Broadcom MIPS platforms" depends on ARCH_BMIPS config SYS_SOC - default "none" + default "bcm6358" if SOC_BMIPS_BCM6358 + +choice + prompt "Broadcom MIPS SoC select" + +config SOC_BMIPS_BCM6358 + bool "BMIPS BCM6358 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6358 family including BCM6358 and BCM6359. + +endchoice choice prompt "Boot mode" diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h new file mode 100644 index 0000000..404690e --- /dev/null +++ b/arch/mips/mach-bmips/include/ioremap.h @@ -0,0 +1,45 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_MACH_BMIPS_IOREMAP_H +#define __ASM_MACH_BMIPS_IOREMAP_H + +#include + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_bmips_internal_registers(phys_addr_t offset) +{ +#if defined(CONFIG_SOC_BMIPS_BCM6358) + if (offset >= 0xfffe0000) + return 1; +#endif + + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_bmips_internal_registers(offset)) + return (void __iomem *)offset; + + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_bmips_internal_registers((unsigned long)addr); +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_BMIPS_IOREMAP_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h new file mode 100644 index 0000000..5d018a3 --- /dev/null +++ b/include/configs/bmips_bcm6358.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6358_H +#define __CONFIG_BMIPS_BCM6358_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 + +#endif /* __CONFIG_BMIPS_BCM6358_H */ -- cgit v0.10.2 From 4a2b2724a214de764cc9250d85043f32cdd43ab9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:22 +0200 Subject: MIPS: add BMIPS Huawei HG556a board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 30fcc2b..1843b77 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts new file mode 100644 index 0000000..6775909 --- /dev/null +++ b/arch/mips/dts/huawei,hg556a.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "Huawei EchoLife HG556a"; + compatible = "huawei,hg556a", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 03cba72..0300ae3 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -21,6 +21,16 @@ config SOC_BMIPS_BCM6358 endchoice choice + prompt "Board select" + +config BOARD_HUAWEI_HG556A + bool "Huawei EchoLife HG556a" + depends on SOC_BMIPS_BCM6358 + select BMIPS_SUPPORTS_BOOT_RAM + +endchoice + +choice prompt "Boot mode" config BMIPS_BOOT_RAM @@ -36,4 +46,6 @@ endchoice config BMIPS_SUPPORTS_BOOT_RAM bool +source "board/huawei/hg556a/Kconfig" + endmenu diff --git a/board/huawei/hg556a/Kconfig b/board/huawei/hg556a/Kconfig new file mode 100644 index 0000000..88622d0 --- /dev/null +++ b/board/huawei/hg556a/Kconfig @@ -0,0 +1,12 @@ +if BOARD_HUAWEI_HG556A + +config SYS_BOARD + default "hg556a" + +config SYS_VENDOR + default "huawei" + +config SYS_CONFIG_NAME + default "huawei_hg556a" + +endif diff --git a/board/huawei/hg556a/MAINTAINERS b/board/huawei/hg556a/MAINTAINERS new file mode 100644 index 0000000..3ead7e4 --- /dev/null +++ b/board/huawei/hg556a/MAINTAINERS @@ -0,0 +1,6 @@ +HUAWEI HG556A BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/huawei/hg556a/ +F: include/configs/huawei_hg556a.h +F: configs/huawei_hg556a_ram_defconfig diff --git a/board/huawei/hg556a/Makefile b/board/huawei/hg556a/Makefile new file mode 100644 index 0000000..ace0ed3 --- /dev/null +++ b/board/huawei/hg556a/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += hg556a.o diff --git a/board/huawei/hg556a/hg556a.c b/board/huawei/hg556a/hg556a.c new file mode 100644 index 0000000..d181ca6 --- /dev/null +++ b/board/huawei/hg556a/hg556a.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig new file mode 100644 index 0000000..ca00c4d --- /dev/null +++ b/configs/huawei_hg556a_ram_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_HUAWEI_HG556A=y +CONFIG_CFI_FLASH=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_FLASH=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM6358=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_PROMPT="HG556a # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h new file mode 100644 index 0000000..ab64518 --- /dev/null +++ b/include/configs/huawei_hg556a.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 -- cgit v0.10.2 From 6471a225e708f550077d0f6c6c1b9e8773b5e9d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:23 +0200 Subject: MIPS: add support for Broadcom MIPS BCM6328 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi new file mode 100644 index 0000000..b287239 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6328"; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6328-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000068 { + compatible = "syscon"; + reg = <0x10000068 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 0300ae3..467ba5b 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -2,11 +2,23 @@ menu "Broadcom MIPS platforms" depends on ARCH_BMIPS config SYS_SOC + default "bcm6328" if SOC_BMIPS_BCM6328 default "bcm6358" if SOC_BMIPS_BCM6358 choice prompt "Broadcom MIPS SoC select" +config SOC_BMIPS_BCM6328 + bool "BMIPS BCM6328 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6328 family including BCM63281 and BCM63283. + config SOC_BMIPS_BCM6358 bool "BMIPS BCM6358 family" select SUPPORTS_BIG_ENDIAN diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h new file mode 100644 index 0000000..41c7838 --- /dev/null +++ b/include/configs/bmips_bcm6328.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6328_H +#define __CONFIG_BMIPS_BCM6328_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6328_H */ -- cgit v0.10.2 From 0642f485dc7b22e147ec85180af1f524c04b46ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:24 +0200 Subject: MIPS: add BMIPS Comtrend AR-5387un board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 1843b77..0805819 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb +dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts new file mode 100644 index 0000000..73f3be4 --- /dev/null +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6328.dtsi" + +/ { + model = "Comtrend AR-5387un"; + compatible = "comtrend,ar5387-un", "brcm,bcm6328"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 467ba5b..e3ffcb7 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -35,6 +35,11 @@ endchoice choice prompt "Board select" +config BOARD_COMTREND_AR5387UN + bool "Comtrend AR-5387un" + depends on SOC_BMIPS_BCM6328 + select BMIPS_SUPPORTS_BOOT_RAM + config BOARD_HUAWEI_HG556A bool "Huawei EchoLife HG556a" depends on SOC_BMIPS_BCM6358 @@ -58,6 +63,7 @@ endchoice config BMIPS_SUPPORTS_BOOT_RAM bool +source "board/comtrend/ar5387un/Kconfig" source "board/huawei/hg556a/Kconfig" endmenu diff --git a/board/comtrend/ar5387un/Kconfig b/board/comtrend/ar5387un/Kconfig new file mode 100644 index 0000000..45ab7e2 --- /dev/null +++ b/board/comtrend/ar5387un/Kconfig @@ -0,0 +1,12 @@ +if BOARD_COMTREND_AR5387UN + +config SYS_BOARD + default "ar5387un" + +config SYS_VENDOR + default "comtrend" + +config SYS_CONFIG_NAME + default "comtrend_ar5387un" + +endif diff --git a/board/comtrend/ar5387un/MAINTAINERS b/board/comtrend/ar5387un/MAINTAINERS new file mode 100644 index 0000000..bcaac64 --- /dev/null +++ b/board/comtrend/ar5387un/MAINTAINERS @@ -0,0 +1,6 @@ +COMTREND AR-5387UN BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/comtrend/ar-5387un/ +F: include/configs/comtrend_ar5387un.h +F: configs/comtrend_ar5387un_ram_defconfig diff --git a/board/comtrend/ar5387un/Makefile b/board/comtrend/ar5387un/Makefile new file mode 100644 index 0000000..9de1cd2 --- /dev/null +++ b/board/comtrend/ar5387un/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ar-5387un.o diff --git a/board/comtrend/ar5387un/ar-5387un.c b/board/comtrend/ar5387un/ar-5387un.c new file mode 100644 index 0000000..d181ca6 --- /dev/null +++ b/board/comtrend/ar5387un/ar-5387un.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig new file mode 100644 index 0000000..c95a369 --- /dev/null +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_COMTREND_AR5387UN=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM6328=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_NO_FLASH=y +CONFIG_SYS_PROMPT="AR-5387un # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h new file mode 100644 index 0000000..5d8f968 --- /dev/null +++ b/include/configs/comtrend_ar5387un.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP -- cgit v0.10.2 From 6a235bb87bfe4a80554c07b2da3679f12167083d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:25 +0200 Subject: MIPS: add support for Broadcom MIPS BCM63268 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi new file mode 100644 index 0000000..3d81047 --- /dev/null +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63268"; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm63268-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + uart0: serial@10000180 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000180 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@100001a0 { + compatible = "brcm,bcm6345-uart"; + reg = <0x100001a0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x1000>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e3ffcb7..b461b79 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -4,6 +4,7 @@ menu "Broadcom MIPS platforms" config SYS_SOC default "bcm6328" if SOC_BMIPS_BCM6328 default "bcm6358" if SOC_BMIPS_BCM6358 + default "bcm63268" if SOC_BMIPS_BCM63268 choice prompt "Broadcom MIPS SoC select" @@ -30,6 +31,18 @@ config SOC_BMIPS_BCM6358 help This supports BMIPS BCM6358 family including BCM6358 and BCM6359. +config SOC_BMIPS_BCM63268 + bool "BMIPS BCM63268 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM63268 family including BCM63168, BCM63169, + BCM63268 and BCM63269. + endchoice choice diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h new file mode 100644 index 0000000..ac0a670 --- /dev/null +++ b/include/configs/bmips_bcm63268.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM63268_H +#define __CONFIG_BMIPS_BCM63268_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM63268_H */ -- cgit v0.10.2 From 77ca99d1a0d9fd46046d417b4247edb4e1b05d4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 25 Apr 2017 00:39:26 +0200 Subject: MIPS: add BMIPS Comtrend VR-3032u board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 0805819..4c02c48 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb +dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts new file mode 100644 index 0000000..6715304 --- /dev/null +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm63268.dtsi" + +/ { + model = "Comtrend VR-3032u"; + compatible = "comtrend,vr-3032u", "brcm,bcm63268"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index b461b79..d168448 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -53,6 +53,11 @@ config BOARD_COMTREND_AR5387UN depends on SOC_BMIPS_BCM6328 select BMIPS_SUPPORTS_BOOT_RAM +config BOARD_COMTREND_VR3032U + bool "Comtrend VR-3032u board" + depends on SOC_BMIPS_BCM63268 + select BMIPS_SUPPORTS_BOOT_RAM + config BOARD_HUAWEI_HG556A bool "Huawei EchoLife HG556a" depends on SOC_BMIPS_BCM6358 @@ -77,6 +82,7 @@ config BMIPS_SUPPORTS_BOOT_RAM bool source "board/comtrend/ar5387un/Kconfig" +source "board/comtrend/vr3032u/Kconfig" source "board/huawei/hg556a/Kconfig" endmenu diff --git a/board/comtrend/vr3032u/Kconfig b/board/comtrend/vr3032u/Kconfig new file mode 100644 index 0000000..6f552cf --- /dev/null +++ b/board/comtrend/vr3032u/Kconfig @@ -0,0 +1,12 @@ +if BOARD_COMTREND_VR3032U + +config SYS_BOARD + default "vr3032u" + +config SYS_VENDOR + default "comtrend" + +config SYS_CONFIG_NAME + default "comtrend_vr3032u" + +endif diff --git a/board/comtrend/vr3032u/MAINTAINERS b/board/comtrend/vr3032u/MAINTAINERS new file mode 100644 index 0000000..833d7da --- /dev/null +++ b/board/comtrend/vr3032u/MAINTAINERS @@ -0,0 +1,6 @@ +COMTREND VR-3032U BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/comtrend/vr-3032u/ +F: include/configs/comtrend_vr-3032u.h +F: configs/comtrend_vr3032u_ram_defconfig diff --git a/board/comtrend/vr3032u/Makefile b/board/comtrend/vr3032u/Makefile new file mode 100644 index 0000000..9e62031 --- /dev/null +++ b/board/comtrend/vr3032u/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += vr-3032u.o diff --git a/board/comtrend/vr3032u/vr-3032u.c b/board/comtrend/vr3032u/vr-3032u.c new file mode 100644 index 0000000..d181ca6 --- /dev/null +++ b/board/comtrend/vr3032u/vr-3032u.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig new file mode 100644 index 0000000..c62ef0c --- /dev/null +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_COMTREND_VR3032U=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM63268=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_NO_FLASH=y +CONFIG_SYS_PROMPT="VR-3032u # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h new file mode 100644 index 0000000..d45f8b3 --- /dev/null +++ b/include/configs/comtrend_vr3032u.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP -- cgit v0.10.2 From e64bdb2fcfce7e002964e72f2732920ecda4b74c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:30 +0200 Subject: dm: gpio: add BCM6345 gpio driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver is based on linux/arch/mips/bcm63xx/gpio.c, simplified to allow defining one or two independent banks for each Broadcom SoC. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 9951611..325d053 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -21,6 +21,12 @@ config ALTERA_PIO Select this to enable PIO for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config BCM6345_GPIO + bool "BCM6345 GPIO driver" + depends on DM_GPIO && ARCH_BMIPS + help + This driver supports the GPIO banks on BCM6345 SoCs. + config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 0ca845f..03df558 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DM_74X164) += 74x164_gpio.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o +obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o diff --git a/drivers/gpio/bcm6345_gpio.c b/drivers/gpio/bcm6345_gpio.c new file mode 100644 index 0000000..1c46020 --- /dev/null +++ b/drivers/gpio/bcm6345_gpio.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/bcm63xx/gpio.c: + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008-2011 Florian Fainelli + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct bcm6345_gpio_priv { + void __iomem *reg_dirout; + void __iomem *reg_data; +}; + +static int bcm6345_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + + return !!(readl_be(priv->reg_data) & BIT(offset)); +} + +static int bcm6345_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + + if (value) + setbits_be32(priv->reg_data, BIT(offset)); + else + clrbits_be32(priv->reg_data, BIT(offset)); + + return 0; +} + +static int bcm6345_gpio_set_direction(void __iomem *dirout, unsigned offset, + bool input) +{ + if (input) + clrbits_be32(dirout, BIT(offset)); + else + setbits_be32(dirout, BIT(offset)); + + return 0; +} + +static int bcm6345_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + + return bcm6345_gpio_set_direction(priv->reg_dirout, offset, 1); +} + +static int bcm6345_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + + return bcm6345_gpio_set_direction(priv->reg_dirout, offset, 0); +} + +static int bcm6345_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + + if (readl_be(priv->reg_dirout) & BIT(offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops bcm6345_gpio_ops = { + .direction_input = bcm6345_gpio_direction_input, + .direction_output = bcm6345_gpio_direction_output, + .get_value = bcm6345_gpio_get_value, + .set_value = bcm6345_gpio_set_value, + .get_function = bcm6345_gpio_get_function, +}; + +static int bcm6345_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct bcm6345_gpio_priv *priv = dev_get_priv(dev); + fdt_addr_t data_addr, dirout_addr; + fdt_size_t data_size, dirout_size; + + dirout_addr = dev_get_addr_size_index(dev, 0, &dirout_size); + if (dirout_addr == FDT_ADDR_T_NONE) + return -EINVAL; + + data_addr = dev_get_addr_size_index(dev, 1, &data_size); + if (data_addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->reg_data = ioremap(data_addr, data_size); + priv->reg_dirout = ioremap(dirout_addr, dirout_size); + + uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "ngpios", 32); + uc_priv->bank_name = dev->name; + + return 0; +} + +static const struct udevice_id bcm6345_gpio_ids[] = { + { .compatible = "brcm,bcm6345-gpio" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6345_gpio) = { + .name = "bcm6345-gpio", + .id = UCLASS_GPIO, + .of_match = bcm6345_gpio_ids, + .ops = &bcm6345_gpio_ops, + .priv_auto_alloc_size = sizeof(struct bcm6345_gpio_priv), + .probe = bcm6345_gpio_probe, +}; -- cgit v0.10.2 From 2507f69c41d8b4f9140e3668f3a4c76a43bb76d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:31 +0200 Subject: mips: bmips: add bcm6345-gpio driver support for BCM6358 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This SoC has one gpio bank divided into two 32 bit registers, with a total of 40 GPIOs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 48322fb..4c94555 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -73,6 +73,25 @@ mask = <0x1>; }; + gpio1: gpio-controller@fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + + status = "disabled"; + }; + + gpio0: gpio-controller@fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial@fffe0100 { compatible = "brcm,bcm6345-uart"; reg = <0xfffe0100 0x18>; -- cgit v0.10.2 From 320186f4768a6a8445909031fa4646e455940862 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:32 +0200 Subject: mips: bmips: add bcm6345-gpio driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This SoC has one gpio bank with a total of 32 GPIOs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index b287239..30c2ee8 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -63,6 +63,15 @@ mask = <0x1>; }; + gpio: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial@10000100 { compatible = "brcm,bcm6345-uart"; reg = <0x10000100 0x18>; -- cgit v0.10.2 From c9c94d5d7e8ca6a9578732cecc15710bad0cb319 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:33 +0200 Subject: mips: bmips: add bcm6345-gpio driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This SoC has one gpio bank divided into two 32 bit registers, with a total of 52 GPIOs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 3d81047..3eda77d 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -63,6 +63,25 @@ mask = <0x1>; }; + gpio1: gpio-controller@100000c0 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c0 0x4>, <0x100000c8 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + + status = "disabled"; + }; + + gpio0: gpio-controller@100000c4 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c4 0x4>, <0x100000cc 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + uart0: serial@10000180 { compatible = "brcm,bcm6345-uart"; reg = <0x10000180 0x18>; -- cgit v0.10.2 From 2791f8db5e2285a6bf6c6a7dad3ea517be72c592 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:09:34 +0200 Subject: mips: bmips: add Huawei HG556a gpio-leds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This board has several LEDs attached to gpio0. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts index 6775909..31c7d7e 100644 --- a/arch/mips/dts/huawei,hg556a.dts +++ b/arch/mips/dts/huawei,hg556a.dts @@ -19,6 +19,79 @@ chosen { stdout-path = "serial0:115200n8"; }; + + gpio-leds { + compatible = "gpio-leds"; + + message_red { + label = "HG556a:red:message"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + hspa_red { + label = "HG556a:red:hspa"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_red { + label = "HG556a:red:dsl"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + power_red { + label = "HG556a:red:power"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + all_red { + label = "HG556a:red:all"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + lan1_green { + label = "HG556a:green:lan1"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + lan1_red { + label = "HG556a:red:lan1"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + lan2_green { + label = "HG556a:green:lan2"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + lan2_red { + label = "HG556a:red:lan2"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + lan3_green { + label = "HG556a:green:lan3"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + lan3_red { + label = "HG556a:red:lan3"; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + lan4_green { + label = "HG556a:green:lan4"; + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + }; + + lan4_red { + label = "HG556a:red:lan4"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; }; &pflash { diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index ca00c4d..ccfdf1d 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_HUAWEI_HG556A=y @@ -17,6 +18,7 @@ CONFIG_CMD_FLASH=y # CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y CONFIG_CMD_LICENSE=y CONFIG_CMD_LOADB=y # CONFIG_CMD_LOADS is not set @@ -32,6 +34,8 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_MIPS=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set -- cgit v0.10.2 From 28300dc5263b26365d8210b92d8acf097dc5e942 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:10:24 +0200 Subject: dm: led: add BCM6328 led driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c, simplified to remove HW leds and blink fallbacks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/doc/device-tree-bindings/leds/leds-bcm6328.txt b/doc/device-tree-bindings/leds/leds-bcm6328.txt new file mode 100644 index 0000000..7f5597b --- /dev/null +++ b/doc/device-tree-bindings/leds/leds-bcm6328.txt @@ -0,0 +1,106 @@ +LEDs connected to Broadcom BCM6328 controller + +This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268. +In these SoCs it's possible to control LEDs both as GPIOs or by hardware. +However, on some devices there are Serial LEDs (LEDs connected to a 74x164 +controller), which can either be controlled by software (exporting the 74x164 +as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +by hardware using this driver. +Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and +exporting the 74x164 as spi-gpio prevents those LEDs to be hardware +controlled, so the only chance to keep them working is by using this driver. + +Required properties: + - compatible : should be "brcm,bcm6328-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6328 LED controller address and size. + +Optional properties: + - brcm,serial-leds : Boolean, enables Serial LEDs. + Default : false + - brcm,serial-mux : Boolean, enables Serial LEDs multiplexing. + Default : false + - brcm,serial-clk-low : Boolean, makes clock signal active low. + Default : false + - brcm,serial-dat-low : Boolean, makes data signal active low. + Default : false + - brcm,serial-shift-inv : Boolean, inverts Serial LEDs shift direction. + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6328-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 23 are valid). + +LED sub-node optional properties: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + +Examples: +Scenario 1 : BCM6328 with 4 GPIO LEDs + leds0: led-controller@10000800 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10000800 0x24>; + + alarm_red@2 { + reg = <2>; + active-low; + label = "red:alarm"; + }; + inet_green@3 { + reg = <3>; + active-low; + label = "green:inet"; + }; + power_green@4 { + reg = <4>; + active-low; + label = "green:power"; + }; + }; + +Scenario 2 : BCM63268 with Serial LEDs + leds0: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001900 0x24>; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + + inet_red@2 { + reg = <2>; + active-low; + label = "red:inet"; + }; + dsl_green@3 { + reg = <3>; + active-low; + label = "green:dsl"; + }; + usb_green@4 { + reg = <4>; + active-low; + label = "green:usb"; + }; + wps_green@7 { + reg = <7>; + active-low; + label = "green:wps"; + }; + inet_green@8 { + reg = <8>; + active-low; + label = "green:inet"; + }; + power_green@20 { + reg = <20>; + active-low; + label = "green:power"; + }; + }; diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 309372a..dc19f4f 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -9,6 +9,17 @@ config LED can provide access to board-specific LEDs. Use of the device tree for configuration is encouraged. +config LED_BCM6328 + bool "LED Support for BCM6328" + depends on LED && ARCH_BMIPS + help + This option enables support for LEDs connected to the BCM6328 + LED HW controller accessed via MMIO registers. + HW blinking is supported and up to 24 LEDs can be controlled. + All LEDs can blink at the same time but the delay is shared, which + means that if one LED is set to blink at 100ms and then a different + LED is set to blink at 200ms, both will blink at 200ms. + config LED_BLINK bool "Support LED blinking" depends on LED diff --git a/drivers/led/Makefile b/drivers/led/Makefile index 02367fd..d371ed5 100644 --- a/drivers/led/Makefile +++ b/drivers/led/Makefile @@ -6,4 +6,5 @@ # obj-y += led-uclass.o +obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o diff --git a/drivers/led/led_bcm6328.c b/drivers/led/led_bcm6328.c new file mode 100644 index 0000000..ef8c6a7 --- /dev/null +++ b/drivers/led/led_bcm6328.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define LEDS_MAX 24 + +/* LED Init register */ +#define LED_INIT_REG 0x00 +#define LED_INIT_FASTINTV_MS 20 +#define LED_INIT_FASTINTV_SHIFT 6 +#define LED_INIT_FASTINTV_MASK (0x3f << LED_INIT_FASTINTV_SHIFT) +#define LED_INIT_SLEDEN_SHIFT 12 +#define LED_INIT_SLEDEN_MASK (1 << LED_INIT_SLEDEN_SHIFT) +#define LED_INIT_SLEDMUX_SHIFT 13 +#define LED_INIT_SLEDMUX_MASK (1 << LED_INIT_SLEDMUX_SHIFT) +#define LED_INIT_SLEDCLKNPOL_SHIFT 14 +#define LED_INIT_SLEDCLKNPOL_MASK (1 << LED_INIT_SLEDCLKNPOL_SHIFT) +#define LED_INIT_SLEDDATAPPOL_SHIFT 15 +#define LED_INIT_SLEDDATANPOL_MASK (1 << LED_INIT_SLEDDATAPPOL_SHIFT) +#define LED_INIT_SLEDSHIFTDIR_SHIFT 16 +#define LED_INIT_SLEDSHIFTDIR_MASK (1 << LED_INIT_SLEDSHIFTDIR_SHIFT) + +/* LED Mode registers */ +#define LED_MODE_REG_HI 0x04 +#define LED_MODE_REG_LO 0x08 +#define LED_MODE_ON 0 +#define LED_MODE_FAST 1 +#define LED_MODE_BLINK 2 +#define LED_MODE_OFF 3 +#define LED_MODE_MASK 0x3 + +DECLARE_GLOBAL_DATA_PTR; + +struct bcm6328_led_priv { + void __iomem *regs; + void __iomem *mode; + uint8_t shift; + bool active_low; +}; + +static unsigned long bcm6328_led_get_mode(struct bcm6328_led_priv *priv) +{ + return ((readl_be(priv->mode) >> priv->shift) & LED_MODE_MASK); +} + +static int bcm6328_led_set_mode(struct bcm6328_led_priv *priv, uint8_t mode) +{ + clrsetbits_be32(priv->mode, (LED_MODE_MASK << priv->shift), + (mode << priv->shift)); + + return 0; +} + +static enum led_state_t bcm6328_led_get_state(struct udevice *dev) +{ + struct bcm6328_led_priv *priv = dev_get_priv(dev); + enum led_state_t state = LEDST_OFF; + + switch (bcm6328_led_get_mode(priv)) { +#ifdef CONFIG_LED_BLINK + case LED_MODE_BLINK: + case LED_MODE_FAST: + state = LEDST_BLINK; + break; +#endif + case LED_MODE_OFF: + state = (priv->active_low ? LEDST_ON : LEDST_OFF); + break; + case LED_MODE_ON: + state = (priv->active_low ? LEDST_OFF : LEDST_ON); + break; + } + + return state; +} + +static int bcm6328_led_set_state(struct udevice *dev, enum led_state_t state) +{ + struct bcm6328_led_priv *priv = dev_get_priv(dev); + unsigned long mode; + + switch (state) { +#ifdef CONFIG_LED_BLINK + case LEDST_BLINK: + mode = LED_MODE_BLINK; + break; +#endif + case LEDST_OFF: + mode = (priv->active_low ? LED_MODE_ON : LED_MODE_OFF); + break; + case LEDST_ON: + mode = (priv->active_low ? LED_MODE_OFF : LED_MODE_ON); + break; + case LEDST_TOGGLE: + if (bcm6328_led_get_state(dev) == LEDST_OFF) + return bcm6328_led_set_state(dev, LEDST_ON); + else + return bcm6328_led_set_state(dev, LEDST_OFF); + break; + default: + return -ENOSYS; + } + + return bcm6328_led_set_mode(priv, mode); +} + +#ifdef CONFIG_LED_BLINK +static unsigned long bcm6328_blink_delay(int delay) +{ + unsigned long bcm6328_delay = delay; + + bcm6328_delay += (LED_INIT_FASTINTV_MS / 2); + bcm6328_delay /= LED_INIT_FASTINTV_MS; + bcm6328_delay <<= LED_INIT_FASTINTV_SHIFT; + + if (bcm6328_delay > LED_INIT_FASTINTV_MASK) + return LED_INIT_FASTINTV_MASK; + else + return bcm6328_delay; +} + +static int bcm6328_led_set_period(struct udevice *dev, int period_ms) +{ + struct bcm6328_led_priv *priv = dev_get_priv(dev); + + clrsetbits_be32(priv->regs + LED_INIT_REG, LED_INIT_FASTINTV_MASK, + bcm6328_blink_delay(period_ms)); + + return 0; +} +#endif + +static const struct led_ops bcm6328_led_ops = { + .get_state = bcm6328_led_get_state, + .set_state = bcm6328_led_set_state, +#ifdef CONFIG_LED_BLINK + .set_period = bcm6328_led_set_period, +#endif +}; + +static int bcm6328_led_probe(struct udevice *dev) +{ + struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev); + fdt_addr_t addr; + fdt_size_t size; + + /* Top-level LED node */ + if (!uc_plat->label) { + void __iomem *regs; + u32 set_bits = 0; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = ioremap(addr, size); + + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "brcm,serial-leds")) + set_bits |= LED_INIT_SLEDEN_MASK; + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "brcm,serial-mux")) + set_bits |= LED_INIT_SLEDMUX_MASK; + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "brcm,serial-clk-low")) + set_bits |= LED_INIT_SLEDCLKNPOL_MASK; + if (!fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "brcm,serial-dat-low")) + set_bits |= LED_INIT_SLEDDATANPOL_MASK; + if (!fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "brcm,serial-shift-inv")) + set_bits |= LED_INIT_SLEDSHIFTDIR_MASK; + + clrsetbits_be32(regs + LED_INIT_REG, ~0, set_bits); + } else { + struct bcm6328_led_priv *priv = dev_get_priv(dev); + unsigned int pin; + + addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pin = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "reg", + LEDS_MAX); + if (pin >= LEDS_MAX) + return -EINVAL; + + priv->regs = ioremap(addr, size); + if (pin < 8) { + /* LEDs 0-7 (bits 47:32) */ + priv->mode = priv->regs + LED_MODE_REG_HI; + priv->shift = (pin << 1); + } else { + /* LEDs 8-23 (bits 31:0) */ + priv->mode = priv->regs + LED_MODE_REG_LO; + priv->shift = ((pin - 8) << 1); + } + + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "active-low")) + priv->active_low = true; + } + + return 0; +} + +static int bcm6328_led_bind(struct udevice *parent) +{ + const void *blob = gd->fdt_blob; + int node; + + for (node = fdt_first_subnode(blob, dev_of_offset(parent)); + node > 0; + node = fdt_next_subnode(blob, node)) { + struct led_uc_plat *uc_plat; + struct udevice *dev; + const char *label; + int ret; + + label = fdt_getprop(blob, node, "label", NULL); + if (!label) { + debug("%s: node %s has no label\n", __func__, + fdt_get_name(blob, node, NULL)); + return -EINVAL; + } + + ret = device_bind_driver_to_node(parent, "bcm6328-led", + fdt_get_name(blob, node, NULL), + node, &dev); + if (ret) + return ret; + + uc_plat = dev_get_uclass_platdata(dev); + uc_plat->label = label; + } + + return 0; +} + +static const struct udevice_id bcm6328_led_ids[] = { + { .compatible = "brcm,bcm6328-leds" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6328_led) = { + .name = "bcm6328-led", + .id = UCLASS_LED, + .of_match = bcm6328_led_ids, + .ops = &bcm6328_led_ops, + .bind = bcm6328_led_bind, + .probe = bcm6328_led_probe, + .priv_auto_alloc_size = sizeof(struct bcm6328_led_priv), +}; -- cgit v0.10.2 From e0f1fd2b3702efe08e23939d8c3a3c425fa4d8b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:10:25 +0200 Subject: mips: bmips: add bcm6328-led driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 24 LEDs and supports HW blinking and serial leds. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 30c2ee8..a5b43ae 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -88,6 +88,15 @@ status = "disabled"; }; + leds: led-controller@10000800 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10000800 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x1000>; -- cgit v0.10.2 From 65a7c955fa6504afdc24164cbc60525d1452ca5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:10:26 +0200 Subject: mips: bmips: add bcm6328-led driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 24 LEDs and supports HW blinking and serial leds. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 3eda77d..11c6729 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -98,6 +98,15 @@ status = "disabled"; }; + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x1000>; -- cgit v0.10.2 From 6def1b24d537e9444b2d63bde0862b3572ca9d05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:10:27 +0200 Subject: mips: bmips: add Comtrend AR-5387un bcm6328-leds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This board has several LEDs attached to its BCM6328 led controller. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index 73f3be4..73f2b49 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -21,6 +21,36 @@ }; }; +&leds { + status = "okay"; + + led@1 { + reg = <1>; + label = "AR-5387un:red:inet"; + }; + + led@4 { + reg = <4>; + label = "AR-5387un:red:power"; + }; + + led@7 { + reg = <7>; + label = "AR-5387un:green:inet"; + }; + + led@8 { + reg = <8>; + label = "AR-5387un:green:power"; + }; + + led@11 { + reg = <11>; + active-low; + label = "AR-5387un:green:dsl"; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index c95a369..f8656c4 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y CONFIG_CMD_LICENSE=y CONFIG_CMD_LOADB=y # CONFIG_CMD_LOADS is not set @@ -31,6 +32,9 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y CONFIG_MIPS=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set -- cgit v0.10.2 From 09e2a571505b8f5abbb8fbf7feabd5400e6a6969 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:10:28 +0200 Subject: mips: bmips: add Comtrend VR-3032u bcm6328-leds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This board has several LEDs attached to its BCM6328 led controller. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts index 6715304..54e738c 100644 --- a/arch/mips/dts/comtrend,vr-3032u.dts +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -21,6 +21,49 @@ }; }; +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + + led@2 { + reg = <2>; + active-low; + label = "VR-3032u:red:inet"; + }; + + led@3 { + reg = <3>; + active-low; + label = "VR-3032u:green:dsl"; + }; + + led@4 { + reg = <4>; + active-low; + label = "VR-3032u:green:usb"; + }; + + led@7 { + reg = <7>; + active-low; + label = "VR-3032u:green:wps"; + }; + + led@8 { + reg = <8>; + active-low; + label = "VR-3032u:green:inet"; + }; + + led@20 { + reg = <20>; + active-low; + label = "VR-3032u:green:power"; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index c62ef0c..a04b0e5 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_GPIO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y CONFIG_CMD_LICENSE=y CONFIG_CMD_LOADB=y # CONFIG_CMD_LOADS is not set @@ -31,6 +32,9 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y CONFIG_MIPS=y # CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set -- cgit v0.10.2 From 632889cfe5205b68b2d0fc597011adb051bd938b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:11:30 +0200 Subject: dm: led: add BCM6358 led driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/doc/device-tree-bindings/leds/leds-bcm6358.txt b/doc/device-tree-bindings/leds/leds-bcm6358.txt new file mode 100644 index 0000000..e394d9e --- /dev/null +++ b/doc/device-tree-bindings/leds/leds-bcm6358.txt @@ -0,0 +1,141 @@ +LEDs connected to Broadcom BCM6358 controller + +This controller is present on BCM6358 and BCM6368. +In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), +which can either be controlled by software (exporting the 74x164 as spi-gpio. +See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or +by hardware using this driver. + +Required properties: + - compatible : should be "brcm,bcm6358-leds". + - #address-cells : must be 1. + - #size-cells : must be 0. + - reg : BCM6358 LED controller address and size. + +Optional properties: + - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8. + Default : 1 + - brcm,clk-dat-low : Boolean, makes clock and data signals active low. + Default : false + +Each LED is represented as a sub-node of the brcm,bcm6358-leds device. + +LED sub-node required properties: + - reg : LED pin number (only LEDs 0 to 31 are valid). + +LED sub-node optional properties: + - label : see Documentation/devicetree/bindings/leds/common.txt + - active-low : Boolean, makes LED active low. + Default : false + +Examples: +Scenario 1 : BCM6358 + leds0: led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe00d0 0x8>; + + alarm_white { + reg = <0>; + active-low; + label = "white:alarm"; + }; + tv_white { + reg = <2>; + active-low; + label = "white:tv"; + }; + tel_white { + reg = <3>; + active-low; + label = "white:tel"; + }; + adsl_white { + reg = <4>; + active-low; + label = "white:adsl"; + }; + }; + +Scenario 2 : BCM6368 + leds0: led-controller@100000d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100000d0 0x8>; + brcm,pol-low; + brcm,clk-div = <4>; + + power_red { + reg = <0>; + active-low; + label = "red:power"; + }; + power_green { + reg = <1>; + active-low; + label = "green:power"; + default-state = "on"; + }; + power_blue { + reg = <2>; + label = "blue:power"; + }; + broadband_red { + reg = <3>; + active-low; + label = "red:broadband"; + }; + broadband_green { + reg = <4>; + label = "green:broadband"; + }; + broadband_blue { + reg = <5>; + active-low; + label = "blue:broadband"; + }; + wireless_red { + reg = <6>; + active-low; + label = "red:wireless"; + }; + wireless_green { + reg = <7>; + active-low; + label = "green:wireless"; + }; + wireless_blue { + reg = <8>; + label = "blue:wireless"; + }; + phone_red { + reg = <9>; + active-low; + label = "red:phone"; + }; + phone_green { + reg = <10>; + active-low; + label = "green:phone"; + }; + phone_blue { + reg = <11>; + label = "blue:phone"; + }; + upgrading_red { + reg = <12>; + active-low; + label = "red:upgrading"; + }; + upgrading_green { + reg = <13>; + active-low; + label = "green:upgrading"; + }; + upgrading_blue { + reg = <14>; + label = "blue:upgrading"; + }; + }; diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index dc19f4f..5da5c4a 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -20,6 +20,14 @@ config LED_BCM6328 means that if one LED is set to blink at 100ms and then a different LED is set to blink at 200ms, both will blink at 200ms. +config LED_BCM6358 + bool "LED Support for BCM6358" + depends on LED && ARCH_BMIPS + help + This option enables support for LEDs connected to the BCM6358 + LED HW controller accessed via MMIO registers. + HW has no blinking capabilities and up to 32 LEDs can be controlled. + config LED_BLINK bool "Support LED blinking" depends on LED diff --git a/drivers/led/Makefile b/drivers/led/Makefile index d371ed5..9d079f8 100644 --- a/drivers/led/Makefile +++ b/drivers/led/Makefile @@ -7,4 +7,5 @@ obj-y += led-uclass.o obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o +obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o diff --git a/drivers/led/led_bcm6358.c b/drivers/led/led_bcm6358.c new file mode 100644 index 0000000..11caecd --- /dev/null +++ b/drivers/led/led_bcm6358.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define LEDS_MAX 32 +#define LEDS_WAIT 100 + +/* LED Mode register */ +#define LED_MODE_REG 0x0 +#define LED_MODE_OFF 0 +#define LED_MODE_ON 1 +#define LED_MODE_MASK 1 + +/* LED Control register */ +#define LED_CTRL_REG 0x4 +#define LED_CTRL_CLK_MASK 0x3 +#define LED_CTRL_CLK_1 0 +#define LED_CTRL_CLK_2 1 +#define LED_CTRL_CLK_4 2 +#define LED_CTRL_CLK_8 3 +#define LED_CTRL_POL_SHIFT 2 +#define LED_CTRL_POL_MASK (1 << LED_CTRL_POL_SHIFT) +#define LED_CTRL_BUSY_SHIFT 3 +#define LED_CTRL_BUSY_MASK (1 << LED_CTRL_BUSY_SHIFT) + +DECLARE_GLOBAL_DATA_PTR; + +struct bcm6358_led_priv { + void __iomem *regs; + uint8_t pin; + bool active_low; +}; + +static void bcm6358_led_busy(void __iomem *regs) +{ + while (readl_be(regs + LED_CTRL_REG) & LED_CTRL_BUSY_MASK) + udelay(LEDS_WAIT); +} + +static unsigned long bcm6358_led_get_mode(struct bcm6358_led_priv *priv) +{ + bcm6358_led_busy(priv->regs); + + return (readl_be(priv->regs + LED_MODE_REG) >> priv->pin) & + LED_MODE_MASK; +} + +static int bcm6358_led_set_mode(struct bcm6358_led_priv *priv, uint8_t mode) +{ + bcm6358_led_busy(priv->regs); + + clrsetbits_be32(priv->regs + LED_MODE_REG, + (LED_MODE_MASK << priv->pin), + (mode << priv->pin)); + + return 0; +} + +static enum led_state_t bcm6358_led_get_state(struct udevice *dev) +{ + struct bcm6358_led_priv *priv = dev_get_priv(dev); + enum led_state_t state = LEDST_OFF; + + switch (bcm6358_led_get_mode(priv)) { + case LED_MODE_OFF: + state = (priv->active_low ? LEDST_ON : LEDST_OFF); + break; + case LED_MODE_ON: + state = (priv->active_low ? LEDST_OFF : LEDST_ON); + break; + } + + return state; +} + +static int bcm6358_led_set_state(struct udevice *dev, enum led_state_t state) +{ + struct bcm6358_led_priv *priv = dev_get_priv(dev); + unsigned long mode; + + switch (state) { + case LEDST_OFF: + mode = (priv->active_low ? LED_MODE_ON : LED_MODE_OFF); + break; + case LEDST_ON: + mode = (priv->active_low ? LED_MODE_OFF : LED_MODE_ON); + break; + case LEDST_TOGGLE: + if (bcm6358_led_get_state(dev) == LEDST_OFF) + return bcm6358_led_set_state(dev, LEDST_ON); + else + return bcm6358_led_set_state(dev, LEDST_OFF); + break; + default: + return -ENOSYS; + } + + return bcm6358_led_set_mode(priv, mode); +} + +static const struct led_ops bcm6358_led_ops = { + .get_state = bcm6358_led_get_state, + .set_state = bcm6358_led_set_state, +}; + +static int bcm6358_led_probe(struct udevice *dev) +{ + struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev); + fdt_addr_t addr; + fdt_size_t size; + + /* Top-level LED node */ + if (!uc_plat->label) { + void __iomem *regs; + unsigned int clk_div; + u32 set_bits = 0; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = ioremap(addr, size); + + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "brcm,clk-dat-low")) + set_bits |= LED_CTRL_POL_MASK; + clk_div = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "brcm,clk-div", LED_CTRL_CLK_1); + switch (clk_div) { + case 8: + set_bits |= LED_CTRL_CLK_8; + break; + case 4: + set_bits |= LED_CTRL_CLK_4; + break; + case 2: + set_bits |= LED_CTRL_CLK_2; + break; + default: + set_bits |= LED_CTRL_CLK_1; + break; + } + + bcm6358_led_busy(regs); + clrsetbits_be32(regs + LED_CTRL_REG, + LED_CTRL_POL_MASK | LED_CTRL_CLK_MASK, + set_bits); + } else { + struct bcm6358_led_priv *priv = dev_get_priv(dev); + unsigned int pin; + + addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pin = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "reg", + LEDS_MAX); + if (pin >= LEDS_MAX) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->pin = pin; + + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "active-low")) + priv->active_low = true; + } + + return 0; +} + +static int bcm6358_led_bind(struct udevice *parent) +{ + const void *blob = gd->fdt_blob; + int node; + + for (node = fdt_first_subnode(blob, dev_of_offset(parent)); + node > 0; + node = fdt_next_subnode(blob, node)) { + struct led_uc_plat *uc_plat; + struct udevice *dev; + const char *label; + int ret; + + label = fdt_getprop(blob, node, "label", NULL); + if (!label) { + debug("%s: node %s has no label\n", __func__, + fdt_get_name(blob, node, NULL)); + return -EINVAL; + } + + ret = device_bind_driver_to_node(parent, "bcm6358-led", + fdt_get_name(blob, node, NULL), + node, &dev); + if (ret) + return ret; + + uc_plat = dev_get_uclass_platdata(dev); + uc_plat->label = label; + } + + return 0; +} + +static const struct udevice_id bcm6358_led_ids[] = { + { .compatible = "brcm,bcm6358-leds" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcm6358_led) = { + .name = "bcm6358-led", + .id = UCLASS_LED, + .of_match = bcm6358_led_ids, + .bind = bcm6358_led_bind, + .probe = bcm6358_led_probe, + .priv_auto_alloc_size = sizeof(struct bcm6358_led_priv), + .ops = &bcm6358_led_ops, +}; -- cgit v0.10.2 From 4d6a519c68c4abc6e7ac0dc267625814668f7aee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:11:31 +0200 Subject: mips: bmips: add bcm6358-led driver support for BCM6358 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 serial leds. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 4c94555..edd0002 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -92,6 +92,15 @@ status = "disabled"; }; + leds: led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + reg = <0xfffe00d0 0x8>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart0: serial@fffe0100 { compatible = "brcm,bcm6345-uart"; reg = <0xfffe0100 0x18>; -- cgit v0.10.2 From a186d2630bd92d952c953f24c412b492265289ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:11:32 +0200 Subject: mips: bmips: add NeufBox 4 (Sercomm) board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This serves as an example for bcm6358-leds. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts new file mode 100644 index 0000000..f2092e9 --- /dev/null +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6358.dtsi" + +/ { + model = "SFR NeufBox 4 (Sercomm) Board"; + compatible = "sfr,nb4-ser", "brcm,bcm6358"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + traffic_white { + label = "NB4-SER:white:traffic"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + service_blue { + label = "NB4-SER:blue:service"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + }; + + wifi_white { + label = "NB4-SER:white:wifi"; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + service_red { + label = "NB4-SER:red:service"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + service_green { + label = "NB4-SER:green:service"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,clk-div = <1>; + + led@0 { + reg = <0>; + active-low; + label = "NB4-SER:white:alarm"; + }; + + led@2 { + reg = <2>; + active-low; + label = "NB4-SER:white:tv"; + }; + + led@3 { + reg = <3>; + active-low; + label = "NB4-SER:white:tel"; + }; + + led@4 { + reg = <4>; + active-low; + label = "NB4-SER:white:adsl"; + }; +}; + +&pflash { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/board/sfr/nb4_ser/Kconfig b/board/sfr/nb4_ser/Kconfig new file mode 100644 index 0000000..78aefb5 --- /dev/null +++ b/board/sfr/nb4_ser/Kconfig @@ -0,0 +1,12 @@ +if BOARD_SFR_NB4_SER + +config SYS_BOARD + default "nb4_ser" + +config SYS_VENDOR + default "sfr" + +config SYS_CONFIG_NAME + default "sfr_nb4_ser" + +endif diff --git a/board/sfr/nb4_ser/MAINTAINERS b/board/sfr/nb4_ser/MAINTAINERS new file mode 100644 index 0000000..bf80267 --- /dev/null +++ b/board/sfr/nb4_ser/MAINTAINERS @@ -0,0 +1,6 @@ +SFR NEUFBOX 4 SERCOMM BOARD +M: Álvaro Fernández Rojas +S: Maintained +F: board/sfr/nb4_ser/ +F: include/configs/sfr_nb4_ser.h +F: configs/sfr_nb4-ser_ram_defconfig diff --git a/board/sfr/nb4_ser/Makefile b/board/sfr/nb4_ser/Makefile new file mode 100644 index 0000000..f3b1404 --- /dev/null +++ b/board/sfr/nb4_ser/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += nb4-ser.o diff --git a/board/sfr/nb4_ser/nb4-ser.c b/board/sfr/nb4_ser/nb4-ser.c new file mode 100644 index 0000000..d181ca6 --- /dev/null +++ b/board/sfr/nb4_ser/nb4-ser.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig new file mode 100644 index 0000000..8b885e3 --- /dev/null +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARCH_BMIPS=y +CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_GPIO=y +CONFIG_BCM6345_SERIAL=y +CONFIG_BMIPS_BOOT_RAM=y +CONFIG_BOARD_SFR_NB4_SER=y +CONFIG_CFI_FLASH=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTM=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_FLASH=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LED=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_XIMG is not set +CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_HUSH_PARSER=y +CONFIG_LED=y +CONFIG_LED_BCM6358=y +CONFIG_LED_GPIO=y +CONFIG_MIPS=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SOC_BMIPS_BCM6358=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_PROMPT="NB4-SER # " +CONFIG_SYS_TEXT_BASE=0x80010000 diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h new file mode 100644 index 0000000..ab64518 --- /dev/null +++ b/include/configs/sfr_nb4_ser.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 -- cgit v0.10.2 From 5357eb95c02394ace9d2a26c516a07922f1a34aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:13:01 +0200 Subject: dm: clk: add BCM6345 clock driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5ca958c..44da716 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,6 +20,14 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. +config CLK_BCM6345 + bool "Clock controller driver for BCM6345" + depends on CLK && ARCH_BMIPS + default y + help + This clock driver adds support for enabling and disabling peripheral + clocks on BCM6345 SoCs. HW has no rate changing capabilities. + config CLK_BOSTON def_bool y if TARGET_BOSTON depends on CLK diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 01a8cd6..2746a80 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ +obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_STM32F7) += clk_stm32f7.o diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c new file mode 100644 index 0000000..4c7a2df --- /dev/null +++ b/drivers/clk/clk_bcm6345.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/bcm63xx/clk.c: + * Copyright (C) 2008 Maxime Bizon + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MAX_CLKS 32 + +struct bcm6345_clk_priv { + void __iomem *regs; +}; + +static int bcm6345_clk_enable(struct clk *clk) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MAX_CLKS) + return -EINVAL; + + setbits_be32(priv->regs, BIT(clk->id)); + + return 0; +} + +static int bcm6345_clk_disable(struct clk *clk) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MAX_CLKS) + return -EINVAL; + + clrbits_be32(priv->regs, BIT(clk->id)); + + return 0; +} + +static struct clk_ops bcm6345_clk_ops = { + .disable = bcm6345_clk_disable, + .enable = bcm6345_clk_enable, +}; + +static const struct udevice_id bcm6345_clk_ids[] = { + { .compatible = "brcm,bcm6345-clk" }, + { /* sentinel */ } +}; + +static int bcm63xx_clk_probe(struct udevice *dev) +{ + struct bcm6345_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + return 0; +} + +U_BOOT_DRIVER(clk_bcm6345) = { + .name = "clk_bcm6345", + .id = UCLASS_CLK, + .of_match = bcm6345_clk_ids, + .ops = &bcm6345_clk_ops, + .probe = bcm63xx_clk_probe, + .priv_auto_alloc_size = sizeof(struct bcm6345_clk_priv), +}; -- cgit v0.10.2 From 70789bd2a5d885671f5256b5c2717fec30ac3fe7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:13:02 +0200 Subject: mips: bmips: add bcm6345-clk driver support for BCM6358 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index edd0002..369c240 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "skeleton.dtsi" @@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0xfffe0004 0x4>; + #clock-cells = <1>; + }; }; pflash: nor@1e000000 { diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h new file mode 100644 index 0000000..ff22321 --- /dev/null +++ b/include/dt-bindings/clock/bcm6358-clock.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6358_H +#define __DT_BINDINGS_CLOCK_BCM6358_H + +#define BCM6358_CLK_ENET 4 +#define BCM6358_CLK_ADSL 5 +#define BCM6358_CLK_PCM 8 +#define BCM6358_CLK_SPI 9 +#define BCM6358_CLK_USBS 10 +#define BCM6358_CLK_SAR 11 +#define BCM6358_CLK_EMUSB 17 +#define BCM6358_CLK_ENET0 18 +#define BCM6358_CLK_ENET1 19 +#define BCM6358_CLK_USBSU 20 +#define BCM6358_CLK_EPHY 21 + +#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ -- cgit v0.10.2 From 5b14e13c24f6a26fc30147404af8c570530f0a8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:13:03 +0200 Subject: mips: bmips: add bcm6345-clk driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index a5b43ae..6b5c5dd 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "skeleton.dtsi" @@ -43,6 +44,12 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; }; ubus { diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h new file mode 100644 index 0000000..5d0fc11 --- /dev/null +++ b/include/dt-bindings/clock/bcm6328-clock.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6328_H +#define __DT_BINDINGS_CLOCK_BCM6328_H + +#define BCM6328_CLK_PHYMIPS 0 +#define BCM6328_CLK_ADSL_QPROC 1 +#define BCM6328_CLK_ADSL_AFE 2 +#define BCM6328_CLK_ADSL 3 +#define BCM6328_CLK_MIPS 4 +#define BCM6328_CLK_SAR 5 +#define BCM6328_CLK_PCM 6 +#define BCM6328_CLK_USBD 7 +#define BCM6328_CLK_USBH 8 +#define BCM6328_CLK_HSSPI 9 +#define BCM6328_CLK_PCIE 10 +#define BCM6328_CLK_ROBOSW 11 + +#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ -- cgit v0.10.2 From 969ebdb9306e3aa731fb96be64f5f96e9457b234 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:13:04 +0200 Subject: mips: bmips: add bcm6345-clk driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 11c6729..4d02024 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "skeleton.dtsi" @@ -43,6 +44,18 @@ clock-frequency = <50000000>; u-boot,dm-pre-reloc; }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + + timer_clk: timer-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x100000ac 0x4>; + #clock-cells = <1>; + }; }; ubus { diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h new file mode 100644 index 0000000..23818da --- /dev/null +++ b/include/dt-bindings/clock/bcm63268-clock.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM63268_H +#define __DT_BINDINGS_CLOCK_BCM63268_H + +#define BCM63268_CLK_GLESS 0 +#define BCM63268_CLK_VDSL_QPROC 1 +#define BCM63268_CLK_VDSL_AFE 2 +#define BCM63268_CLK_VDSL 3 +#define BCM63268_CLK_MIPS 4 +#define BCM63268_CLK_WLAN_OCP 5 +#define BCM63268_CLK_DECT 6 +#define BCM63268_CLK_FAP0 7 +#define BCM63268_CLK_FAP1 8 +#define BCM63268_CLK_SAR 9 +#define BCM63268_CLK_ROBOSW 10 +#define BCM63268_CLK_PCM 11 +#define BCM63268_CLK_USBD 12 +#define BCM63268_CLK_USBH 13 +#define BCM63268_CLK_IPSEC 14 +#define BCM63268_CLK_SPI 15 +#define BCM63268_CLK_HSSPI 16 +#define BCM63268_CLK_PCIE 17 +#define BCM63268_CLK_PHYMIPS 18 +#define BCM63268_CLK_GMAC 19 +#define BCM63268_CLK_NAND 20 +#define BCM63268_CLK_TBUS 27 +#define BCM63268_CLK_ROBOSW250 31 + +#define BCM63268_TCLK_EPHY1 0 +#define BCM63268_TCLK_EPHY2 1 +#define BCM63268_TCLK_EPHY3 2 +#define BCM63268_TCLK_GPHY 3 +#define BCM63268_TCLK_DSL 4 +#define BCM63268_TCLK_WO_EPHY 5 +#define BCM63268_TCLK_WO_DSL 6 +#define BCM63268_TCLK_FAP1 11 +#define BCM63268_TCLK_FAP2 15 +#define BCM63268_TCLK_UTO_50 16 +#define BCM63268_TCLK_UTO_EXT 17 +#define BCM63268_TCLK_USB_REF 18 +#define BCM63268_TCLK_SW_RST 29 +#define BCM63268_TCLK_HW_RST 30 +#define BCM63268_TCLK_POR_RST 31 + +#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ -- cgit v0.10.2 From a6c1827722ea45e303a39810d11030d41ffea56f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:13:05 +0200 Subject: mips: bmips: enable bcm6345-clk driver for all BMIPS boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index f8656c4..55cb4bf 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_AR5387UN=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index a04b0e5..7f13d24 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y CONFIG_BOARD_COMTREND_VR3032U=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index ccfdf1d..71e1163 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 8b885e3..cd6c4a2 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6345_CLK=y CONFIG_BCM6345_GPIO=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y -- cgit v0.10.2 From 18393f70f6854e80d34b3b12d3a9eca84bae0a45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 3 May 2017 15:10:21 +0200 Subject: dm: reset: add BCM6345 reset driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a simplified version of linux/arch/mips/bcm63xx/reset.c Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 80f4646..e6af7da 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -42,6 +42,12 @@ config TEGRA186_RESET Enable support for manipulating Tegra's on-SoC reset signals via IPC requests to the BPMP (Boot and Power Management Processor). +config RESET_BCM6345 + bool "Reset controller driver for BCM6345" + depends on DM_RESET && ARCH_BMIPS + help + Support reset controller on BCM6345. + config RESET_UNIPHIER bool "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 630b4b4..d5e06c2 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o obj-$(CONFIG_STI_RESET) += sti-reset.o obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o +obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c new file mode 100644 index 0000000..774c2a7 --- /dev/null +++ b/drivers/reset/reset-bcm6345.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/bcm63xx/reset.c: + * Copyright (C) 2012 Jonas Gorski + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MAX_RESETS 32 + +struct bcm6345_reset_priv { + void __iomem *regs; +}; + +static int bcm6345_reset_assert(struct reset_ctl *rst) +{ + struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev); + + clrbits_be32(priv->regs, BIT(rst->id)); + mdelay(20); + + return 0; +} + +static int bcm6345_reset_deassert(struct reset_ctl *rst) +{ + struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev); + + setbits_be32(priv->regs, BIT(rst->id)); + mdelay(20); + + return 0; +} + +static int bcm6345_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int bcm6345_reset_request(struct reset_ctl *rst) +{ + if (rst->id >= MAX_RESETS) + return -EINVAL; + + return bcm6345_reset_assert(rst); +} + +struct reset_ops bcm6345_reset_reset_ops = { + .free = bcm6345_reset_free, + .request = bcm6345_reset_request, + .rst_assert = bcm6345_reset_assert, + .rst_deassert = bcm6345_reset_deassert, +}; + +static const struct udevice_id bcm6345_reset_ids[] = { + { .compatible = "brcm,bcm6345-reset" }, + { /* sentinel */ } +}; + +static int bcm6345_reset_probe(struct udevice *dev) +{ + struct bcm6345_reset_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + return 0; +} + +U_BOOT_DRIVER(bcm6345_reset) = { + .name = "bcm6345-reset", + .id = UCLASS_RESET, + .of_match = bcm6345_reset_ids, + .ops = &bcm6345_reset_reset_ops, + .probe = bcm6345_reset_probe, + .priv_auto_alloc_size = sizeof(struct bcm6345_reset_priv), +}; -- cgit v0.10.2 From efe8b9d0122e5ab25f7284a36a716cd6610e8ad4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 3 May 2017 15:10:22 +0200 Subject: mips: bmips: add bcm6345-rst driver support for BCM6358 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 resets. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 369c240..df75988 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -80,6 +81,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@fffe0034 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0034 0x4>; + #reset-cells = <1>; + }; + gpio1: gpio-controller@fffe0080 { compatible = "brcm,bcm6345-gpio"; reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h new file mode 100644 index 0000000..4b3cff3 --- /dev/null +++ b/include/dt-bindings/reset/bcm6358-reset.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6358_H +#define __DT_BINDINGS_RESET_BCM6358_H + +#define BCM6358_RST_SPI 0 +#define BCM6358_RST_ENET 2 +#define BCM6358_RST_MPI 3 +#define BCM6358_RST_EPHY 6 +#define BCM6358_RST_SAR 7 +#define BCM6358_RST_USBH 12 +#define BCM6358_RST_PCM 13 +#define BCM6358_RST_ADSL 14 + +#endif /* __DT_BINDINGS_RESET_BCM6358_H */ -- cgit v0.10.2 From 78118211fb61df2f6427dc0ea7a65c97c20b3d11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 3 May 2017 15:10:23 +0200 Subject: mips: bmips: add bcm6345-rst driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 6b5c5dd..9b76a23 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -58,6 +59,12 @@ #size-cells = <1>; u-boot,dm-pre-reloc; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + pll_cntl: syscon@10000068 { compatible = "syscon"; reg = <0x10000068 0x4>; diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h new file mode 100644 index 0000000..c144ad2 --- /dev/null +++ b/include/dt-bindings/reset/bcm6328-reset.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6328_H +#define __DT_BINDINGS_RESET_BCM6328_H + +#define BCM6328_RST_SPI 0 +#define BCM6328_RST_EPHY 1 +#define BCM6328_RST_SAR 2 +#define BCM6328_RST_ENETSW 3 +#define BCM6328_RST_USBS 4 +#define BCM6328_RST_USBH 5 +#define BCM6328_RST_PCM 6 +#define BCM6328_RST_PCIE_CORE 7 +#define BCM6328_RST_PCIE 8 +#define BCM6328_RST_PCIE_EXT 9 +#define BCM6328_RST_PCIE_HARD 10 + +#endif /* __DT_BINDINGS_RESET_BCM6328_H */ -- cgit v0.10.2 From 02bb1fa09ed4caec6d2aa6565fac62087016b306 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 3 May 2017 15:10:24 +0200 Subject: mips: bmips: add bcm6345-rst driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 4d02024..8ff13c1 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -76,6 +77,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + gpio1: gpio-controller@100000c0 { compatible = "brcm,bcm6345-gpio"; reg = <0x100000c0 0x4>, <0x100000c8 0x4>; diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h new file mode 100644 index 0000000..1373884 --- /dev/null +++ b/include/dt-bindings/reset/bcm63268-reset.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM63268_H +#define __DT_BINDINGS_RESET_BCM63268_H + +#define BCM63268_RST_SPI 0 +#define BCM63268_RST_IPSEC 1 +#define BCM63268_RST_EPHY 2 +#define BCM63268_RST_SAR 3 +#define BCM63268_RST_ENETSW 4 +#define BCM63268_RST_USBS 5 +#define BCM63268_RST_USBH 6 +#define BCM63268_RST_PCM 7 +#define BCM63268_RST_PCIE_CORE 8 +#define BCM63268_RST_PCIE 9 +#define BCM63268_RST_PCIE_EXT 10 +#define BCM63268_RST_WLAN_SHIM 11 +#define BCM63268_RST_DDR_PHY 12 +#define BCM63268_RST_FAP0 13 +#define BCM63268_RST_WLAN_UBUS 14 +#define BCM63268_RST_DECT 15 +#define BCM63268_RST_FAP1 16 +#define BCM63268_RST_PCIE_HARD 17 +#define BCM63268_RST_GPHY 18 + +#endif /* __DT_BINDINGS_RESET_BCM63268_H */ -- cgit v0.10.2 From 6327aa478332ed1970a0dbe33333f2ee7394ac06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Wed, 3 May 2017 15:10:25 +0200 Subject: mips: bmips: enable bcm6345-reset driver for all BMIPS boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 55cb4bf..d613740 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" CONFIG_DISPLAY_CPUINFO=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_LED=y @@ -41,6 +42,8 @@ CONFIG_MIPS=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM6328=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 7f13d24..fa2b2ae 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" CONFIG_DISPLAY_CPUINFO=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_LED=y @@ -41,6 +42,8 @@ CONFIG_MIPS=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM63268=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 71e1163..c2e6472 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" CONFIG_DISPLAY_CPUINFO=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_LED=y @@ -45,6 +46,8 @@ CONFIG_MTD=y CONFIG_MTD_DEVICE=y CONFIG_MTD_NOR_FLASH=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM6358=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index cd6c4a2..d7c8329 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" CONFIG_DISPLAY_CPUINFO=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y +CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_HUSH_PARSER=y CONFIG_LED=y @@ -46,6 +47,8 @@ CONFIG_MTD=y CONFIG_MTD_DEVICE=y CONFIG_MTD_NOR_FLASH=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_RESET=y +CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM6358=y # CONFIG_SPL_SERIAL_PRESENT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -- cgit v0.10.2 From 7810fb9547a2101a9570ec359db480be2f2939b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:28:36 +0200 Subject: dm: power: domain: add BCM6328 power domain driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows controlling MISC IDDQ register on BCM6328 SoCs. Signed-off-by: Álvaro Fernández Rojas diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 132e332..7cfa761 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -9,6 +9,13 @@ config POWER_DOMAIN domains). This may be used to save power. This API provides the means to control such power management hardware. +config BCM6328_POWER_DOMAIN + bool "Enable the BCM6328 power domain driver" + depends on POWER_DOMAIN && ARCH_BMIPS + help + Enable support for manipulating BCM6345 power domains via MMIO + mapped registers. + config SANDBOX_POWER_DOMAIN bool "Enable the sandbox power domain test driver" depends on POWER_DOMAIN && SANDBOX diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 2c3d926..c7d7644 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -3,6 +3,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_POWER_DOMAIN) += power-domain-uclass.o +obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o diff --git a/drivers/power/domain/bcm6328-power-domain.c b/drivers/power/domain/bcm6328-power-domain.c new file mode 100644 index 0000000..15638bf --- /dev/null +++ b/drivers/power/domain/bcm6328-power-domain.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define MAX_DOMAINS 32 + +struct bcm6328_power_domain { + void __iomem *regs; +}; + +static int bcm6328_power_domain_request(struct power_domain *power_domain) +{ + if (power_domain->id >= MAX_DOMAINS) + return -EINVAL; + + return 0; +} + +static int bcm6328_power_domain_free(struct power_domain *power_domain) +{ + return 0; +} + +static int bcm6328_power_domain_on(struct power_domain *power_domain) +{ + struct bcm6328_power_domain *priv = dev_get_priv(power_domain->dev); + + clrbits_be32(priv->regs, BIT(power_domain->id)); + + return 0; +} + +static int bcm6328_power_domain_off(struct power_domain *power_domain) +{ + struct bcm6328_power_domain *priv = dev_get_priv(power_domain->dev); + + setbits_be32(priv->regs, BIT(power_domain->id)); + + return 0; +} + +static int bcm6328_power_domain_probe(struct udevice *dev) +{ + struct bcm6328_power_domain *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + return 0; +} + +static const struct udevice_id bcm6328_power_domain_ids[] = { + { .compatible = "brcm,bcm6328-power-domain" }, + { /* sentinel */ } +}; + +struct power_domain_ops bcm6328_power_domain_ops = { + .free = bcm6328_power_domain_free, + .off = bcm6328_power_domain_off, + .on = bcm6328_power_domain_on, + .request = bcm6328_power_domain_request, +}; + +U_BOOT_DRIVER(bcm6328_power_domain) = { + .name = "bcm6328_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = bcm6328_power_domain_ids, + .ops = &bcm6328_power_domain_ops, + .priv_auto_alloc_size = sizeof(struct bcm6328_power_domain), + .probe = bcm6328_power_domain_probe, +}; -- cgit v0.10.2 From 9a5cb22fda01327384e8dabb775cfb2615dbbe10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:28:37 +0200 Subject: mips: bmips: add bcm6328-power-domain driver support for BCM6328 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 9b76a23..4adc83f 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include "skeleton.dtsi" @@ -111,6 +112,12 @@ status = "disabled"; }; + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x1000>; diff --git a/include/dt-bindings/power-domain/bcm6328-power-domain.h b/include/dt-bindings/power-domain/bcm6328-power-domain.h new file mode 100644 index 0000000..006806c --- /dev/null +++ b/include/dt-bindings/power-domain/bcm6328-power-domain.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6328_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6328_H + +#define BCM6328_PWR_ADSL2_MIPS 0 +#define BCM6328_PWR_ADSL2_PHY 1 +#define BCM6328_PWR_ADSL2_AFE 2 +#define BCM6328_PWR_SAR 3 +#define BCM6328_PWR_PCM 4 +#define BCM6328_PWR_USBD 5 +#define BCM6328_PWR_USBH 6 +#define BCM6328_PWR_PCIE 7 +#define BCM6328_PWR_ROBOSW 8 +#define BCM6328_PWR_EPHY 9 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6328_H */ -- cgit v0.10.2 From a1b5e5e7c164868cff1b5c53a8ed70640512b42e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:28:38 +0200 Subject: mips: bmips: add bcm6328-power-domain driver support for BCM63268 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver can control up to 32 power domains. Signed-off-by: Álvaro Fernández Rojas diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 8ff13c1..3d0f8e0 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include "skeleton.dtsi" @@ -118,6 +119,12 @@ status = "disabled"; }; + periph_pwr: power-controller@1000184c { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x1000184c 0x4>; + #power-domain-cells = <1>; + }; + leds: led-controller@10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>; diff --git a/include/dt-bindings/power-domain/bcm63268-power-domain.h b/include/dt-bindings/power-domain/bcm63268-power-domain.h new file mode 100644 index 0000000..d9eba44 --- /dev/null +++ b/include/dt-bindings/power-domain/bcm63268-power-domain.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM63268_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM63268_H + +#define BCM63268_PWR_SAR 0 +#define BCM63268_PWR_IPSEC 1 +#define BCM63268_PWR_MIPS 2 +#define BCM63268_PWR_DECT 3 +#define BCM63268_PWR_USBH 4 +#define BCM63268_PWR_USBD 5 +#define BCM63268_PWR_ROBOSW 6 +#define BCM63268_PWR_PCM 7 +#define BCM63268_PWR_PERIPH 8 +#define BCM63268_PWR_VDSL_PHY 9 +#define BCM63268_PWR_VDSL_MIPS 10 +#define BCM63268_PWR_FAP 11 +#define BCM63268_PWR_PCIE 12 +#define BCM63268_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM63268_H */ -- cgit v0.10.2 From a41481bfcba89d1d8dd8b51faa7775cd3ff1c15f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 7 May 2017 20:28:39 +0200 Subject: mips: bmips: enable bcm6328-power-domain driver for BCM6328 and BCM63268 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index d613740..5b05fd2 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y @@ -42,6 +43,7 @@ CONFIG_MIPS=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_POWER_DOMAIN=y CONFIG_RESET=y CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM6328=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index fa2b2ae..c056d73 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -1,5 +1,6 @@ CONFIG_ARCH_BMIPS=y CONFIG_BAUDRATE=115200 +CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_BCM6345_CLK=y CONFIG_BCM6345_SERIAL=y CONFIG_BMIPS_BOOT_RAM=y @@ -42,6 +43,7 @@ CONFIG_MIPS=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_POWER_DOMAIN=y CONFIG_RESET=y CONFIG_RESET_BCM6345=y CONFIG_SOC_BMIPS_BCM63268=y -- cgit v0.10.2