From 078078cfa91f72331421e6f7a46938a58a9b21a7 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 15 May 2012 14:32:40 -0700 Subject: spi: Tegra2: Seaboard: fix UART corruption during SPI transactions Simon Glass's proposal to fix this on Seaboard was NAK'd, so I removed his NS16550 references and added a small delay before SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes and saw no corruption (crc's matched) and no spurious comm chars. Signed-off-by: Tom Warren Acked-by: Simon Glass Tested-by: Jimmy Zhang diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h index e4503b1..82ac180 100644 --- a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h +++ b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h @@ -29,7 +29,7 @@ * time! If the board file provides this, the board config will declare it. * Let this be a lesson for others. */ -void pinmux_select_uart(NS16550_t regs); +void pinmux_select_uart(void); /* * Signal that we are about the use the SPI bus. @@ -38,7 +38,7 @@ void pinmux_select_spi(void); #else /* not CONFIG_SPI_UART_SWITCH */ -static inline void pinmux_select_uart(NS16550_t regs) {} +static inline void pinmux_select_uart(void) {} static inline void pinmux_select_spi(void) {} #endif diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c index 23aa0b9..1ba1afd 100644 --- a/board/nvidia/common/uart-spi-switch.c +++ b/board/nvidia/common/uart-spi-switch.c @@ -21,7 +21,6 @@ */ #include -#include #include #include #include @@ -40,7 +39,6 @@ enum spi_uart_switch { /* Information about the spi/uart switch */ struct spi_uart { int gpio; /* GPIO to control switch */ - NS16550_t regs; /* Address of UART affected */ u32 port; /* Port number of UART affected */ }; @@ -52,7 +50,6 @@ static void get_config(struct spi_uart *config) { #if defined CONFIG_SPI_CORRUPTS_UART config->gpio = CONFIG_UART_DISABLE_GPIO; - config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART; config->port = CONFIG_SPI_CORRUPTS_UART_NR; #else config->gpio = -1; @@ -101,34 +98,24 @@ static void spi_uart_switch(struct spi_uart *config, if (switch_pos == SWITCH_BOTH || new_pos == switch_pos) return; - /* if the UART was selected, allow it to drain */ - if (switch_pos == SWITCH_UART) - NS16550_drain(config->regs, config->port); + /* pre-delay, allow SPI/UART to settle, FIFO to empty, etc. */ + udelay(CONFIG_SPI_CORRUPTS_UART_DLY); /* We need to dynamically change the pinmux, shared w/UART RXD/CTS */ pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ? PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD); /* - * On Seaboard, MOSI/MISO are shared w/UART. - * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. - * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. - */ + * On Seaboard, MOSI/MISO are shared w/UART. + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. + */ gpio_direction_output(config->gpio, new_pos == SWITCH_SPI); switch_pos = new_pos; - - /* if the SPI was selected, clear any junk bytes in the UART */ - if (switch_pos == SWITCH_UART) { - /* TODO: What if it is part-way through clocking in junk? */ - udelay(100); - NS16550_clear(config->regs, config->port); - } } -void pinmux_select_uart(NS16550_t regs) +void pinmux_select_uart(void) { - /* Also prevents calling spi_uart_switch() before relocation */ - if (regs == local.regs) spi_uart_switch(&local, SWITCH_UART); } diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c index 56cb229..fe7b405 100644 --- a/drivers/spi/tegra2_spi.c +++ b/drivers/spi/tegra2_spi.c @@ -28,13 +28,18 @@ #include #include #include -#include #include #include #include #include #include +#if defined(CONFIG_SPI_CORRUPTS_UART) + #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY); +#else + #define corrupt_delay() +#endif + struct tegra_spi_slave { struct spi_slave slave; struct spi_tegra *regs; @@ -161,14 +166,20 @@ void spi_cs_activate(struct spi_slave *slave) /* CS is negated on Tegra, so drive a 1 to get a 0 */ setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); + + corrupt_delay(); /* Let UART settle */ } void spi_cs_deactivate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); + pinmux_select_uart(); + /* CS is negated on Tegra, so drive a 0 to get a 1 */ clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); + + corrupt_delay(); /* Let SPI settle */ } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, -- cgit v0.10.2 From 046c76a6c0af77952a1ec5ab576d12f93ed52641 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 15 May 2012 14:38:03 -0700 Subject: spi: Tegra2: Seaboard: enable SPI/UART corruption fix Signed-off-by: Tom Warren diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 46d4228..889bdff 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -52,6 +52,15 @@ /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ #define CONFIG_UART_DISABLE_GPIO GPIO_PI3 +/* + * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are + * needed to work around that design error. + */ +#define CONFIG_SPI_UART_SWITCH +#define CONFIG_SPI_CORRUPTS_UART NV_PA_APB_UARTD_BASE +#define CONFIG_SPI_CORRUPTS_UART_NR 3 +#define CONFIG_SPI_CORRUPTS_UART_DLY 2500 +#undef CONFIG_CMDLINE_EDITING /* avoid NUL in input buffer */ #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ -- cgit v0.10.2 From aa53c7f55fdf93d4377b4eecbfc235144902cc91 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 15 May 2012 11:58:11 +0000 Subject: tegra: paz00: fix typo in SD slot CD detect GPIO Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 3b48917..b07ce11 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -55,8 +55,8 @@ static void pin_mux_mmc(void) /* For power GPIO PV1 */ pinmux_tristate_disable(PINGRP_UAC); - /* For CD GPIO PI5 */ - pinmux_tristate_disable(PINGRP_ATC); + /* For CD GPIO PV5 */ + pinmux_tristate_disable(PINGRP_GPV); } /* this is a weak define that we are overriding */ @@ -74,7 +74,7 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init SD slot\n"); /* init dev 3, SD slot, with 4-bit bus */ - tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PI5); + tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); return 0; } -- cgit v0.10.2 From b9607e70614823893d1a47a377232d2a12e4464f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 14 May 2012 13:13:45 +0000 Subject: tegra: add alternate UART1 funcmux entry (In at least some configurations) Whistler uses UART1 on pingroups UAA, UAB. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index a50b1b9..629ad5d 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -101,6 +101,18 @@ int arch_cpu_init(void) } #endif +static int uart_configs[] = { +#ifdef CONFIG_TEGRA2_UARTA_UAA_UAB + FUNCMUX_UART1_UAA_UAB, +#else + FUNCMUX_UART1_IRRX_IRTX, +#endif + FUNCMUX_UART2_IRDA, + -1, + FUNCMUX_UART4_GMC, + -1, +}; + /** * Set up the specified uarts * @@ -120,7 +132,7 @@ static void setup_uarts(int uart_ids) if (uart_ids & (1 << i)) { enum periph_id id = id_for_uart[i]; - funcmux_select(id, FUNCMUX_DEFAULT); + funcmux_select(id, uart_configs[i]); clock_ll_start_uart(id); } } diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c index 0ef7753..e2d1273 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -31,11 +31,22 @@ int funcmux_select(enum periph_id id, int config) switch (id) { case PERIPH_ID_UART1: - if (config == FUNCMUX_UART1_IRRX_IRTX) { + switch (config) { + case FUNCMUX_UART1_IRRX_IRTX: pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); pinmux_tristate_disable(PINGRP_IRRX); pinmux_tristate_disable(PINGRP_IRTX); + break; + case FUNCMUX_UART1_UAA_UAB: + pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_UAA); + pinmux_tristate_disable(PINGRP_UAB); + bad_config = 0; + break; + } + if (!bad_config) { /* * Tegra appears to boot with function UARTA pre- * selected on mux group SDB. If two mux groups are diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h index ae73c72..b455122 100644 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -30,6 +30,7 @@ enum { /* UART configs */ FUNCMUX_UART1_IRRX_IRTX = 0, + FUNCMUX_UART1_UAA_UAB, FUNCMUX_UART2_IRDA = 0, FUNCMUX_UART4_GMC = 0, -- cgit v0.10.2 From d5ebc937c90b95f52bd85c15ce74edff4df2e0be Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 15 May 2012 06:45:28 +0000 Subject: tegra: Whistler board support Whistler is a highly configurable Tegra evaluation and development board. This change adds support for the following specific configuration: E1120 motherboard E1108 CPU board E1116 PMU board The motherboard configuration switches are set as follows: SW1=0 SW2=0 SW3=5 S1/S2/S3/S4 all on, except S3 7/8 are off. Other combinations of daugher boards may work to varying degrees, but will likely require some SW adjustment. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/MAINTAINERS b/MAINTAINERS index e55893b..0db7e84 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -914,6 +914,7 @@ Stephen Warren ventana Tegra2 (ARM7 & A9 Dual Core) paz00 Tegra2 (ARM7 & A9 Dual Core) + whistler Tegra2 (ARM7 & A9 Dual Core) Thomas Weber diff --git a/board/nvidia/dts/tegra2-whistler.dts b/board/nvidia/dts/tegra2-whistler.dts new file mode 100644 index 0000000..b22d407 --- /dev/null +++ b/board/nvidia/dts/tegra2-whistler.dts @@ -0,0 +1,67 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; + + aliases { + i2c0 = "/i2c@7000d000"; + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + }; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x20000000 >; + }; + + clocks { + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + + pmic@3c { + compatible = "maxim,max8907b"; + reg = <0x3c>; + + clk_32k: clock { + compatible = "fixed-clock"; + /* + * leave out for now due to CPP: + * #clock-cells = <0>; + */ + clock-frequency = <32768>; + }; + }; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile new file mode 100644 index 0000000..a910577 --- /dev/null +++ b/board/nvidia/whistler/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c new file mode 100644 index 0000000..1c2f33f --- /dev/null +++ b/board/nvidia/whistler/whistler.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_TEGRA2_MMC +#include +#endif + +/* + * Routine: gpio_config_uart + * Description: Does nothing on Whistler - no UART-related GPIOs. + */ +void gpio_config_uart(void) +{ +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); +} + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + uchar val; + int ret; + + debug("board_mmc_init called\n"); + + /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x29; + ret = i2c_write(0x3c, 0x46, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); + val = 0x00; + ret = i2c_write(0x3c, 0x45, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); + val = 0x1f; + ret = i2c_write(0x3c, 0x44, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ + tegra2_mmc_init(0, 8, -1, -1); + + /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ + tegra2_mmc_init(1, 8, -1, -1); + + return 0; +} + +/* this is a weak define that we are overriding */ +void pin_mux_usb(void) +{ + uchar val; + int ret; + + /* + * This is a hack. This should be represented in DT using the + * vbus-gpio property. However, U-Boot's DT support doesn't + * support any GPIO controller other than the Tegra's yet. + */ + + /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x03; + ret = i2c_write(0x20, 2, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 2 failed: %d\n", ret); + val = 0xfc; + ret = i2c_write(0x20, 6, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 6 failed: %d\n", ret); +} diff --git a/boards.cfg b/boards.cfg index a723f67..055dbbc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -231,6 +231,7 @@ trats arm armv7 trats samsung harmony arm armv7 harmony nvidia tegra2 seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 +whistler arm armv7 whistler nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB diff --git a/include/configs/whistler.h b/include/configs/whistler.h new file mode 100644 index 0000000..6b9ef98 --- /dev/null +++ b/include/configs/whistler.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra2-common.h" + +/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-whistler +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define TEGRA2_SYSMEM "mem=512M@0M" +#define V_PROMPT "Tegra2 (Whistler) # " +#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Whistler" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA +#define CONFIG_TEGRA2_UARTA_UAA_UAB +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER +#define CONFIG_SYS_BOARD_ODMDATA 0x2B080105 /* lp?, 512MB, UARTA */ + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* Environment not stored */ +#define CONFIG_ENV_IS_NOWHERE + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX + +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 07a84b7b1905f5b7464ad5746507306733eae964 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 06:20:59 +0000 Subject: tegra: remove some cruft from CONFIG_EXTRA_ENV_SETTINGS console isn't used by anything, and the kernel should be set appropriately by whatever script is booting the kernel, not imposed by the bootloader. mem might be useful, but the current value is pretty bogus, since it includes nvmem options that make no sense for an upstream kernel, and equally should not be required for any downstream kernel. Either way, this is also best left to the kernel boot script. smpflag isn't used by anything, and again was probably intended to be a kernel command-line option better set by the kernel boot script. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/harmony.h b/include/configs/harmony.h index ce0ae9f..3706a40 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -28,7 +28,6 @@ #include "tegra2-common.h" /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (Harmony) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony" diff --git a/include/configs/medcom.h b/include/configs/medcom.h index 2dc3507..725abc3 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -29,7 +29,6 @@ #include "tegra2-common.h" /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M" #define V_PROMPT "Tegra2 (Medcom) # " #define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom" #define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 diff --git a/include/configs/paz00.h b/include/configs/paz00.h index f53f20e..ae3a2de 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -21,7 +21,6 @@ #include "tegra2-common.h" /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=512M@0M" #define V_PROMPT "Tegra2 (Paz00) MOD # " #define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00" diff --git a/include/configs/plutux.h b/include/configs/plutux.h index f869191..475be6c 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -29,7 +29,6 @@ #include "tegra2-common.h" /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M" #define V_PROMPT "Tegra2 (Plutux) # " #define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux" #define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011 diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 889bdff..c346366 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -41,7 +41,6 @@ #define CONFIG_OF_SEPARATE /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (SeaBoard) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard" diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 52dc38e..d60b5a1 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -140,9 +140,6 @@ "stderr=serial\0" #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttyS0,115200n8\0" \ - "mem=" TEGRA2_SYSMEM "\0" \ - "smpflag=smp\0" \ TEGRA2_DEVICE_SETTINGS #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 3e55fe5..a7338f1 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -33,7 +33,6 @@ #define CONFIG_OF_SEPARATE /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (Ventana) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana" diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 6b9ef98..5efa60c 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -33,7 +33,6 @@ #define CONFIG_OF_SEPARATE /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=512M@0M" #define V_PROMPT "Tegra2 (Whistler) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Whistler" -- cgit v0.10.2 From bea2674ccde5a495710adef62ebd5a294752f59d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 06:21:00 +0000 Subject: tegra: flesh out bootcmd This implements a useful bootcmd for Tegra. The boot order is: * If USB enabled, USB storage * Internal MMC (SD card or eMMC) * If networking is enabled, BOOTP/TFTP When booting from USB or MMC, the boot script is assumed to be in partition 1 (although this may be overridden via the rootpart variable), both ext2 and FAT filesystems are supported, the boot script may exist in either / or /boot, and the boot script may be named boot.scr.uimg or boot.scr. When booting over the network, it is assumed that boot.scr.uimg exists on the TFTP server. There is less flexibility here since those setting up network booting are expected to need less hand-holding. In all cases, it is expected that the initial file loaded is a U-Boot image containing a script that will load the kernel, load any required initrd, load any required DTB, and finally bootm the kernel. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 3706a40..25d6ec7 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -60,4 +60,7 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/medcom.h b/include/configs/medcom.h index 725abc3..eecfa50 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -60,4 +60,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index ae3a2de..ced185e 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -47,4 +47,7 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 475be6c..1888276 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -60,4 +60,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index c346366..d02a11e 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -116,4 +116,7 @@ #define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ "stdout=serial\0" \ "stderr=serial\0" + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/tegra2-common-post.h b/include/configs/tegra2-common-post.h new file mode 100644 index 0000000..0484a52 --- /dev/null +++ b/include/configs/tegra2-common-post.h @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TEGRA2_COMMON_POST_H +#define __TEGRA2_COMMON_POST_H + +#ifdef CONFIG_BOOTCOMMAND + +#define BOOTCMDS_COMMON "" + +#else + +#ifdef CONFIG_CMD_EXT2 +#define BOOTCMD_FS_EXT2 "ext2 " +#else +#define BOOTCMD_FS_EXT2 "" +#endif + +#ifdef CONFIG_CMD_FAT +#define BOOTCMD_FS_FAT "fat" +#else +#define BOOTCMD_FS_FAT "" +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOTCMDS_MMC \ + "mmc_boot=" \ + "setenv devtype mmc; " \ + "if mmc dev ${devnum}; then " \ + "run script_boot; " \ + "fi\0" \ + "mmc0_boot=setenv devnum 0; run mmc_boot;\0" \ + "mmc1_boot=setenv devnum 1; run mmc_boot;\0" \ + "bootcmd_mmc=run mmc1_boot; run mmc0_boot\0" +#define BOOTCMD_MMC "run bootcmd_mmc; " +#else +#define BOOTCMDS_MMC "" +#define BOOTCMD_MMC "" +#endif + +#ifdef CONFIG_CMD_USB +#define BOOTCMDS_USB \ + "usb_boot=" \ + "setenv devtype usb; " \ + "if usb dev ${devnum}; then " \ + "run script_boot; " \ + "fi\0" \ + "usb0_boot=setenv devnum 0; run usb_boot;\0" \ + "bootcmd_usb=run usb0_boot\0" +#define BOOTCMD_USB "run bootcmd_usb; " +#define BOOTCMD_INIT_USB "usb start 0; " +#else +#define BOOTCMDS_USB "" +#define BOOTCMD_USB "" +#define BOOTCMD_INIT_USB "" +#endif + +#ifdef CONFIG_CMD_DHCP +#define BOOTCMDS_DHCP \ + "bootcmd_dhcp=" \ + "if dhcp ${scriptaddr} boot.scr.uimg; then "\ + "source ${scriptaddr}; " \ + "fi\0" +#define BOOTCMD_DHCP "run bootcmd_dhcp; " +#else +#define BOOTCMDS_DHCP "" +#define BOOTCMD_DHCP "" +#endif + +#define BOOTCMDS_COMMON \ + "scriptaddr=0x400000\0" \ + "rootpart=1\0" \ + "script_boot=" \ + "for fs in " BOOTCMD_FS_EXT2 BOOTCMD_FS_FAT "; do " \ + "for prefix in / /boot/; do " \ + "for script in boot.scr.uimg boot.scr; do " \ + "echo Scanning ${devtype} ${devnum}:${rootpart} ${fs} ${prefix}${script} ...; " \ + "if ${fs}load ${devtype} ${devnum}:${rootpart} ${scriptaddr} ${prefix}${script}; then " \ + "echo ${script} found! Executing ...;" \ + "source ${scriptaddr};" \ + "fi; " \ + "done; " \ + "done; " \ + "done;\0" \ + BOOTCMDS_MMC \ + BOOTCMDS_USB \ + BOOTCMDS_DHCP + +#define CONFIG_BOOTCOMMAND BOOTCMD_INIT_USB BOOTCMD_USB BOOTCMD_MMC BOOTCMD_DHCP + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + TEGRA2_DEVICE_SETTINGS \ + BOOTCMDS_COMMON + +#endif /* __TEGRA2_COMMON_POST_H */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index d60b5a1..a4146a5 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -139,9 +139,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ - TEGRA2_DEVICE_SETTINGS - #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index a7338f1..8e95db1 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -59,4 +59,7 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 5efa60c..2f2a512 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -86,4 +86,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ -- cgit v0.10.2 From dae2aeab7161aad105cfdb61b722c9b22c6ac6fb Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 06:36:11 +0000 Subject: tegra: whistler: reduce and comment network cfg options CONFIG_CMD_PING/NFS aren't required for Whistler to boot. Add some comments. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 2f2a512..6c0c77e 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -74,16 +74,14 @@ #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_USB_ETHER_ASIX + +/* USB networking support */ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_PING +/* General networking support */ +#define CONFIG_CMD_NET #define CONFIG_CMD_DHCP #include "tegra2-common-post.h" -- cgit v0.10.2 From defd5e497960b870d11bffbfd952ec3eaf2dd20e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 06:36:12 +0000 Subject: tegra: seaboard: add support for USB networking Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index d02a11e..643af81 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -108,6 +108,15 @@ #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + /* Enable keyboard */ #define CONFIG_TEGRA2_KEYBOARD #define CONFIG_KEYBOARD -- cgit v0.10.2 From e21649be56a0cbe17ea892fc6c1a633369df0d50 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 05:59:59 +0000 Subject: tegra: add UART1 on GPU funcmux entry TrimSlice uses UART1 on the GPU pingroup. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 629ad5d..6106ef9 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -102,8 +102,10 @@ int arch_cpu_init(void) #endif static int uart_configs[] = { -#ifdef CONFIG_TEGRA2_UARTA_UAA_UAB +#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB) FUNCMUX_UART1_UAA_UAB, +#elif defined(CONFIG_TEGRA2_UARTA_GPU) + FUNCMUX_UART1_GPU, #else FUNCMUX_UART1_IRRX_IRTX, #endif diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c index e2d1273..c279088 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -45,6 +45,11 @@ int funcmux_select(enum periph_id id, int config) pinmux_tristate_disable(PINGRP_UAB); bad_config = 0; break; + case FUNCMUX_UART1_GPU: + pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_GPU); + bad_config = 0; + break; } if (!bad_config) { /* diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h index b455122..dba2cf5 100644 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -31,6 +31,7 @@ enum { /* UART configs */ FUNCMUX_UART1_IRRX_IRTX = 0, FUNCMUX_UART1_UAA_UAB, + FUNCMUX_UART1_GPU, FUNCMUX_UART2_IRDA = 0, FUNCMUX_UART4_GMC = 0, -- cgit v0.10.2 From ffec1eb9c7a88db4be06dbf596fc8578e4586b62 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 16 May 2012 08:21:01 +0000 Subject: tegra: sync SDIO1 pingroup enum name with TRM Signed-off-by: Lucas Stach CC: Tom Warren Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h index 469d742..03fa7ca 100644 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ b/arch/arm/include/asm/arch-tegra2/pinmux.h @@ -67,7 +67,7 @@ enum pmux_pingrp { PINGRP_KBCF, PINGRP_GMA, PINGRP_GMC, - PINGRP_SDMMC1, + PINGRP_SDIO1, PINGRP_OWC, /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index b07ce11..0c09ce0 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -48,10 +48,10 @@ static void pin_mux_mmc(void) pinmux_tristate_disable(PINGRP_GMA); pinmux_tristate_disable(PINGRP_GME); - /* SDMMC1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ - pinmux_set_func(PINGRP_SDMMC1, PMUX_FUNC_SDIO1); + /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PINGRP_SDMMC1); + pinmux_tristate_disable(PINGRP_SDIO1); /* For power GPIO PV1 */ pinmux_tristate_disable(PINGRP_UAC); -- cgit v0.10.2 From a2cfe63eeb6a09c52a748849590a898f1032aeea Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 16 May 2012 08:21:02 +0000 Subject: tegra: add SDIO1 funcmux entry for UARTA This is based on top of: tegra: add alternate UART1 funcmux entry tegra: add UART1 on GPU funcmux entry v2: remove enum change Signed-off-by: Lucas Stach Acked-by: Stephen Warren CC: Stephen Warren CC: Tom Warren CC: Marek Vasut Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 6106ef9..923678d 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -106,6 +106,8 @@ static int uart_configs[] = { FUNCMUX_UART1_UAA_UAB, #elif defined(CONFIG_TEGRA2_UARTA_GPU) FUNCMUX_UART1_GPU, +#elif defined(CONFIG_TEGRA2_UARTA_SDIO1) + FUNCMUX_UART1_SDIO1, #else FUNCMUX_UART1_IRRX_IRTX, #endif diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c index c279088..1559869 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -50,6 +50,11 @@ int funcmux_select(enum periph_id id, int config) pinmux_tristate_disable(PINGRP_GPU); bad_config = 0; break; + case FUNCMUX_UART1_SDIO1: + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_SDIO1); + bad_config = 0; + break; } if (!bad_config) { /* diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h index dba2cf5..19184d1 100644 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -32,6 +32,7 @@ enum { FUNCMUX_UART1_IRRX_IRTX = 0, FUNCMUX_UART1_UAA_UAB, FUNCMUX_UART1_GPU, + FUNCMUX_UART1_SDIO1, FUNCMUX_UART2_IRDA = 0, FUNCMUX_UART4_GMC = 0, -- cgit v0.10.2 From d1e4607901883c84a2f727c9ae2dac3cfcfd2b91 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 13:54:06 +0000 Subject: tegra: add SDMMC1 on SDIO1 funcmux entry This will be used on TrimSlice. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c index 1559869..820ba4e9 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -127,6 +127,13 @@ int funcmux_select(enum periph_id id, int config) } break; + case PERIPH_ID_SDMMC1: + if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) { + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); + pinmux_tristate_disable(PINGRP_SDIO1); + } + break; + case PERIPH_ID_SDMMC2: if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) { pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2); diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h index 19184d1..b16c496 100644 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -44,6 +44,7 @@ enum { FUNCMUX_I2C3_DTF = 0, /* SDMMC configs */ + FUNCMUX_SDMMC1_SDIO1_4BIT = 0, FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, FUNCMUX_SDMMC3_SDB_4BIT = 0, FUNCMUX_SDMMC3_SDB_SLXA_8BIT, -- cgit v0.10.2 From 39e37118398158d98f0e9b926d69af289ae7e7b8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 May 2012 13:54:07 +0000 Subject: tegra: Compulab TrimSlice board support Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/MAINTAINERS b/MAINTAINERS index 0db7e84..6438e1c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -914,6 +914,7 @@ Stephen Warren ventana Tegra2 (ARM7 & A9 Dual Core) paz00 Tegra2 (ARM7 & A9 Dual Core) + trimslice Tegra2 (ARM7 & A9 Dual Core) whistler Tegra2 (ARM7 & A9 Dual Core) Thomas Weber diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra2-trimslice.dts new file mode 100644 index 0000000..c707eb8 --- /dev/null +++ b/board/compulab/dts/tegra2-trimslice.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile new file mode 100644 index 0000000..bf624f4 --- /dev/null +++ b/board/compulab/trimslice/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../nvidia/common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +COBJS += ../../nvidia/common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c new file mode 100644 index 0000000..7167c91 --- /dev/null +++ b/board/compulab/trimslice/trimslice.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_TEGRA2_MMC +#include +#endif + +/* + * Routine: gpio_config_uart + * Description: Does nothing on TrimSlice - no UART-related GPIOs. + */ +void gpio_config_uart(void) +{ +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + + /* For CD GPIO PP1 */ + pinmux_tristate_disable(PINGRP_DAP3); +} + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ + tegra2_mmc_init(0, 4, -1, GPIO_PP1); + + /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ + tegra2_mmc_init(3, 4, -1, -1); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 055dbbc..92050708 100644 --- a/boards.cfg +++ b/boards.cfg @@ -260,6 +260,7 @@ jornada arm sa1100 plutux arm armv7 plutux avionic-design tegra2 medcom arm armv7 medcom avionic-design tegra2 paz00 arm armv7 paz00 compal tegra2 +trimslice arm armv7 trimslice compulab tegra2 atngw100 avr32 at32ap - atmel at32ap700x atstk1002 avr32 at32ap atstk1000 atmel at32ap700x atstk1003 avr32 at32ap atstk1000 atmel at32ap700x diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h new file mode 100644 index 0000000..dafca5e --- /dev/null +++ b/include/configs/trimslice.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra2-common.h" + +/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-trimslice +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra2 (TrimSlice) # " +#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Trimslice" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA +#define CONFIG_TEGRA2_UARTA_GPU +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE +#define CONFIG_SYS_BOARD_ODMDATA 0x300c0011 /* lp?, 1GB, UARTA */ + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* Environment not stored */ +#define CONFIG_ENV_IS_NOWHERE + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra2-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From f3d93309c1ab0fe22e3229f99dbcfa7c857eb067 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 May 2012 10:04:27 +0000 Subject: tegra: harmony: add device tree support ... to enable USB host support, which enables Ethernet support. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/board/nvidia/dts/tegra2-harmony.dts b/board/nvidia/dts/tegra2-harmony.dts new file mode 100644 index 0000000..4f60a05 --- /dev/null +++ b/board/nvidia/dts/tegra2-harmony.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 25d6ec7..88189be 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2012 * NVIDIA Corporation * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,11 @@ #include #include "tegra2-common.h" +/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-harmony +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define V_PROMPT "Tegra2 (Harmony) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony" @@ -61,6 +66,21 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra2-common-post.h" #endif /* __CONFIG_H */ -- cgit v0.10.2 From 00a55add04222539846dd884217bcf40c504da92 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 May 2012 10:04:37 +0000 Subject: tegra: paz00: add device tree support ... to enable USB host support, which enables Ethernet support. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/board/compal/dts/tegra2-paz00.dts b/board/compal/dts/tegra2-paz00.dts new file mode 100644 index 0000000..9e3e169 --- /dev/null +++ b/board/compal/dts/tegra2-paz00.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/include/configs/paz00.h b/include/configs/paz00.h index ced185e..f8bd7dc 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010,2011, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -20,6 +20,11 @@ #include #include "tegra2-common.h" +/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-paz00 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define V_PROMPT "Tegra2 (Paz00) MOD # " #define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00" @@ -48,6 +53,21 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra2-common-post.h" #endif /* __CONFIG_H */ -- cgit v0.10.2 From 27c4a3318f716cce0a23248317534bda7792230b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 19 Apr 2012 08:04:39 +0000 Subject: tegra: Correct PLL access in ap20.c and clock.c Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 698bfd0..24e582d 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void) void init_pllx(void) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_simple *pll = + &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE]; u32 reg; /* If PLLX is already enabled, just return */ diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index ccad351..602589c 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - assert(clock_id_isvalid(clkid)); + assert(clock_id_is_pll(clkid)); return &clkrst->crc_pll[clkid]; } @@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, assert(clkid != CLOCK_ID_USB); /* Safety check, adds to code size but is small */ - if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB) + if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) return -1; data = readl(&pll->pll_base); *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 1d3ae38..ff83bbf 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -186,8 +186,9 @@ enum periph_id { /* Mask value for a clock (within PERIPH_REG(id)) */ #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) -/* return 1 if a PLL ID is in range */ -#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 -- cgit v0.10.2 From f3717ac5848ec389919596d5e518b528fb8bebdd Mon Sep 17 00:00:00 2001 From: "amartin@nvidia.com" Date: Mon, 14 May 2012 13:14:39 +0000 Subject: tegra: override compiler flags for low level init code Override -march setting for tegra to -march=armv4t for files that are necessary for low level init on tegra. The recent change to use -march=armv7-a for armv7 caused a regression on tegra because tegra starts boot on a arm7tdmi processor before transferring control to the cortex-a9. While still executing on the arm7tdmi there are calls to getenv_ulong() and memset() that cause an illegal instruction exception if compiled for armv7. Signed-off-by: Allen Martin Tested-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index fe9ef5b..4dd8cb8 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -24,10 +24,13 @@ # MA 02111-1307 USA # -# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this -# file with compatible flags +# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these +# files with compatible flags ifdef CONFIG_TEGRA2 CFLAGS_arch/arm/lib/board.o += -march=armv4t +CFLAGS_arch/arm/lib/memset.o += -march=armv4t +CFLAGS_lib/string.o += -march=armv4t +CFLAGS_common/cmd_nvedit.o += -march=armv4t endif USE_PRIVATE_LIBGCC = yes -- cgit v0.10.2 From 59f8ac65f823fa02c73606860480b0e16febc68d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 May 2012 07:29:29 +0000 Subject: tegra: remove CONFIG_USB_ETHER_SMSC95XX from boards without it The SMSC95xx series may exist either directly on a main board, or as a USB to Ethernet dongle. However, dongles containing these chips are very rare. Hence, remove this config option, except on Harmony where such a chip is actually present on the board. The asix option remains, since it's a popular chip, and I actively use a dongle containing this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren Acked-by: Igor Grinberg diff --git a/include/configs/paz00.h b/include/configs/paz00.h index f8bd7dc..3edd102 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -61,7 +61,6 @@ /* USB networking support */ #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX /* General networking support */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 643af81..f46740e 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -110,7 +110,6 @@ /* USB networking support */ #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX /* General networking support */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index dafca5e..21b9ef2 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -77,7 +77,6 @@ /* USB networking support */ #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX /* General networking support */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 6c0c77e..51f806a 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -77,7 +77,6 @@ /* USB networking support */ #define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX /* General networking support */ -- cgit v0.10.2 From b1b9e4ce3af6d10c8442bff48b69cad151ddff82 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 23 May 2012 07:46:15 +0000 Subject: tegra: ventana: add own device tree, enable USB Add a device tree for Ventana; the Seaboard file no longer represents the HW present on Ventana. Enable USB on Ventana. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/board/nvidia/dts/tegra2-ventana.dts b/board/nvidia/dts/tegra2-ventana.dts new file mode 100644 index 0000000..900e871 --- /dev/null +++ b/board/nvidia/dts/tegra2-ventana.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 8e95db1..2c7355b 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -28,7 +28,7 @@ #include "tegra2-common.h" /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-ventana #define CONFIG_OF_CONTROL #define CONFIG_OF_SEPARATE @@ -60,6 +60,20 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include "tegra2-common-post.h" #endif /* __CONFIG_H */ -- cgit v0.10.2 From 4036b6301efab9f5196e986a7e1d3925cf816c31 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:33 +0000 Subject: env_mmc: align buffers using ALLOC_CACHE_ALIGN_BUFFER This allows MMC drivers to perform cache flusing on the bufffers without issue. Signed-off-by: Stephen Warren Cc: Andy Fleming Signed-off-by: Tom Warren diff --git a/common/env_mmc.c b/common/env_mmc.c index 0c58ae1..be2f2be 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -95,7 +95,7 @@ static inline int write_env(struct mmc *mmc, unsigned long size, int saveenv(void) { - env_t env_new; + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); ssize_t len; char *res; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); @@ -104,16 +104,16 @@ int saveenv(void) if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset)) return 1; - res = (char *)&env_new.data; + res = (char *)&env_new->data; len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE); printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV); - if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)&env_new)) { + if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) { puts("failed\n"); return 1; } @@ -140,7 +140,7 @@ static inline int read_env(struct mmc *mmc, unsigned long size, void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) - char buf[CONFIG_ENV_SIZE]; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); u32 offset; -- cgit v0.10.2 From 1edaf094dc1a89c24017da4fd30723bd1c64ac46 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:34 +0000 Subject: sf: winbond: Add support for the Winbond W25Q80BL This chip is present on the Compulab TrimSlice. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index a6a6653..c20faa2 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -68,6 +68,14 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .name = "W25X64", }, { + .id = 0x4014, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "W25Q80BL", + }, + { .id = 0x4015, .l2_page_size = 8, .pages_per_sector = 16, -- cgit v0.10.2 From 294cd67c8d4a7049dc8d972a52527f605dbdaff7 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:35 +0000 Subject: tegra: ventana: store environment in eMMC Store the environment in eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage: U-Boot is stored well below this location, and the kernel only uses the general area of the eMMC once booted, not the boot sectors. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 2c7355b..665076d 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -57,8 +57,10 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USB Host support */ #define CONFIG_USB_EHCI -- cgit v0.10.2 From 616887016d4e82f15fa5acc5d111c16bf2d29843 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:36 +0000 Subject: tegra: whistler: store environment in eMMC Store the environment in eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage: U-Boot is stored well below this location, and the kernel only uses the general area of the eMMC once booted, not the boot sectors. Note: This assumes the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If they didn't, the boot sector layout may be different. However, use of that particular card is standard practice as far as I know. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 51f806a..ec96cff 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -66,8 +66,15 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* + * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes + * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If + * they didn't, the boot sector layout may be different. However, use of that + * particular card is standard practice as far as I know. + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USB Host support */ #define CONFIG_USB_EHCI -- cgit v0.10.2 From edffa63d3d6e76991998789f9fcbaa483731ca65 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 22 May 2012 07:33:47 +0000 Subject: spi: tegra2: rename tegra2_spi.* to tegra_spi.* In anticipation of Tegra3 support, start removing/renaming Tegra2-specific files. No functional changes (yet). Also updated copyright to 2012. Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h deleted file mode 100644 index ceec428..0000000 --- a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * NVIDIA Tegra2 SPI-FLASH controller - * - * Copyright 2010-2011 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA2_SPI_H_ -#define _TEGRA2_SPI_H_ - -#include - -struct spi_tegra { - u32 command; /* SPI_COMMAND_0 register */ - u32 status; /* SPI_STATUS_0 register */ - u32 rx_cmp; /* SPI_RX_CMP_0 register */ - u32 dma_ctl; /* SPI_DMA_CTL_0 register */ - u32 tx_fifo; /* SPI_TX_FIFO_0 register */ - u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ - u32 rx_fifo; /* SPI_RX_FIFO_0 register */ -}; - -#define SPI_CMD_GO (1 << 30) -#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 -#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) -#define SPI_CMD_CK_SDA (1 << 21) -#define SPI_CMD_ACTIVE_SDA_SHIFT 18 -#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) -#define SPI_CMD_CS_POL (1 << 16) -#define SPI_CMD_TXEN (1 << 15) -#define SPI_CMD_RXEN (1 << 14) -#define SPI_CMD_CS_VAL (1 << 13) -#define SPI_CMD_CS_SOFT (1 << 12) -#define SPI_CMD_CS_DELAY (1 << 9) -#define SPI_CMD_CS3_EN (1 << 8) -#define SPI_CMD_CS2_EN (1 << 7) -#define SPI_CMD_CS1_EN (1 << 6) -#define SPI_CMD_CS0_EN (1 << 5) -#define SPI_CMD_BIT_LENGTH (1 << 4) -#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F - -#define SPI_STAT_BSY (1 << 31) -#define SPI_STAT_RDY (1 << 30) -#define SPI_STAT_RXF_FLUSH (1 << 29) -#define SPI_STAT_TXF_FLUSH (1 << 28) -#define SPI_STAT_RXF_UNR (1 << 27) -#define SPI_STAT_TXF_OVF (1 << 26) -#define SPI_STAT_RXF_EMPTY (1 << 25) -#define SPI_STAT_RXF_FULL (1 << 24) -#define SPI_STAT_TXF_EMPTY (1 << 23) -#define SPI_STAT_TXF_FULL (1 << 22) -#define SPI_STAT_SEL_TXRX_N (1 << 16) -#define SPI_STAT_CUR_BLKCNT (1 << 15) - -#define SPI_TIMEOUT 1000 -#define TEGRA2_SPI_MAX_FREQ 52000000 - - -#endif /* _TEGRA2_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra_spi.h b/arch/arm/include/asm/arch-tegra2/tegra_spi.h new file mode 100644 index 0000000..892d90c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra_spi.h @@ -0,0 +1,75 @@ +/* + * NVIDIA Tegra2 SPI-FLASH controller + * + * Copyright 2010-2012 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_SPI_H_ +#define _TEGRA_SPI_H_ + +#include + +struct spi_tegra { + u32 command; /* SPI_COMMAND_0 register */ + u32 status; /* SPI_STATUS_0 register */ + u32 rx_cmp; /* SPI_RX_CMP_0 register */ + u32 dma_ctl; /* SPI_DMA_CTL_0 register */ + u32 tx_fifo; /* SPI_TX_FIFO_0 register */ + u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ + u32 rx_fifo; /* SPI_RX_FIFO_0 register */ +}; + +#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 +#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) +#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_ACTIVE_SDA_SHIFT 18 +#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) +#define SPI_CMD_CS_POL (1 << 16) +#define SPI_CMD_TXEN (1 << 15) +#define SPI_CMD_RXEN (1 << 14) +#define SPI_CMD_CS_VAL (1 << 13) +#define SPI_CMD_CS_SOFT (1 << 12) +#define SPI_CMD_CS_DELAY (1 << 9) +#define SPI_CMD_CS3_EN (1 << 8) +#define SPI_CMD_CS2_EN (1 << 7) +#define SPI_CMD_CS1_EN (1 << 6) +#define SPI_CMD_CS0_EN (1 << 5) +#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F + +#define SPI_STAT_BSY (1 << 31) +#define SPI_STAT_RDY (1 << 30) +#define SPI_STAT_RXF_FLUSH (1 << 29) +#define SPI_STAT_TXF_FLUSH (1 << 28) +#define SPI_STAT_RXF_UNR (1 << 27) +#define SPI_STAT_TXF_OVF (1 << 26) +#define SPI_STAT_RXF_EMPTY (1 << 25) +#define SPI_STAT_RXF_FULL (1 << 24) +#define SPI_STAT_TXF_EMPTY (1 << 23) +#define SPI_STAT_TXF_FULL (1 << 22) +#define SPI_STAT_SEL_TXRX_N (1 << 16) +#define SPI_STAT_CUR_BLKCNT (1 << 15) + +#define SPI_TIMEOUT 1000 +#define TEGRA2_SPI_MAX_FREQ 52000000 + +#endif /* _TEGRA_SPI_H_ */ diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c index 1ba1afd..307937a 100644 --- a/board/nvidia/common/uart-spi-switch.c +++ b/board/nvidia/common/uart-spi-switch.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include /* position of the UART/SPI select switch */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c967d87..c20f1f2 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -43,7 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o -COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o +COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c deleted file mode 100644 index fe7b405..0000000 --- a/drivers/spi/tegra2_spi.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (c) 2010-2011 NVIDIA Corporation - * With help from the mpc8xxx SPI driver - * With more help from omap3_spi SPI driver - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI_CORRUPTS_UART) - #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY); -#else - #define corrupt_delay() -#endif - -struct tegra_spi_slave { - struct spi_slave slave; - struct spi_tegra *regs; - unsigned int freq; - unsigned int mode; -}; - -static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) -{ - return container_of(slave, struct tegra_spi_slave, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */ - if (bus != 0 || cs != 0) - return 0; - else - return 1; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct tegra_spi_slave *spi; - - if (!spi_cs_is_valid(bus, cs)) { - printf("SPI error: unsupported bus %d / chip select %d\n", - bus, cs); - return NULL; - } - - if (max_hz > TEGRA2_SPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %d Hz. Max frequency" - " is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ); - return NULL; - } - - spi = malloc(sizeof(struct tegra_spi_slave)); - if (!spi) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } - spi->slave.bus = bus; - spi->slave.cs = cs; - spi->freq = max_hz; - spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE; - spi->mode = mode; - - return &spi->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct tegra_spi_slave *spi = to_tegra_spi(slave); - - free(spi); -} - -void spi_init(void) -{ - /* do nothing */ -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_tegra *regs = spi->regs; - u32 reg; - - /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq); - - /* Clear stale status here */ - reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ - SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; - writel(reg, ®s->status); - debug("spi_init: STATUS = %08x\n", readl(®s->status)); - - /* - * Use sw-controlled CS, so we can clock in data after ReadID, etc. - */ - reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; - if (spi->mode & 2) - reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; - clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | - SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); - debug("spi_init: COMMAND = %08x\n", readl(®s->command)); - - /* - * SPI pins on Tegra2 are muxed - change pinmux later due to UART - * issue. - */ - pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); - pinmux_tristate_disable(PINGRP_LSPI); - -#ifndef CONFIG_SPI_UART_SWITCH - /* - * NOTE: - * Only set PinMux bits 3:2 to SPI here on boards that don't have the - * SPI UART switch or subsequent UART data won't go out! See - * spi_uart_switch(). - */ - /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */ -#endif - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* - * We can't release UART_DISABLE and set pinmux to UART4 here since - * some code (e,g, spi_flash_probe) uses printf() while the SPI - * bus is held. That is arguably bad, but it has the advantage of - * already being in the source tree. - */ -} - -void spi_cs_activate(struct spi_slave *slave) -{ - struct tegra_spi_slave *spi = to_tegra_spi(slave); - - pinmux_select_spi(); - - /* CS is negated on Tegra, so drive a 1 to get a 0 */ - setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); - - corrupt_delay(); /* Let UART settle */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct tegra_spi_slave *spi = to_tegra_spi(slave); - - pinmux_select_uart(); - - /* CS is negated on Tegra, so drive a 0 to get a 1 */ - clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); - - corrupt_delay(); /* Let SPI settle */ -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags) -{ - struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_tegra *regs = spi->regs; - u32 reg, tmpdout, tmpdin = 0; - const u8 *dout = data_out; - u8 *din = data_in; - int num_bytes; - int ret; - - debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", - slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); - if (bitlen % 8) - return -1; - num_bytes = bitlen / 8; - - ret = 0; - - reg = readl(®s->status); - writel(reg, ®s->status); /* Clear all SPI events via R/W */ - debug("spi_xfer entry: STATUS = %08x\n", reg); - - reg = readl(®s->command); - reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; - writel(reg, ®s->command); - debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); - - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); - - /* handle data in 32-bit chunks */ - while (num_bytes > 0) { - int bytes; - int is_read = 0; - int tm, i; - - tmpdout = 0; - bytes = (num_bytes > 4) ? 4 : num_bytes; - - if (dout != NULL) { - for (i = 0; i < bytes; ++i) - tmpdout = (tmpdout << 8) | dout[i]; - } - - num_bytes -= bytes; - if (dout) - dout += bytes; - - clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, - bytes * 8 - 1); - writel(tmpdout, ®s->tx_fifo); - setbits_le32(®s->command, SPI_CMD_GO); - - /* - * Wait for SPI transmit FIFO to empty, or to time out. - * The RX FIFO status will be read and cleared last - */ - for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { - u32 status; - - status = readl(®s->status); - - /* We can exit when we've had both RX and TX activity */ - if (is_read && (status & SPI_STAT_TXF_EMPTY)) - break; - - if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != - SPI_STAT_RDY) - tm++; - - else if (!(status & SPI_STAT_RXF_EMPTY)) { - tmpdin = readl(®s->rx_fifo); - is_read = 1; - - /* swap bytes read in */ - if (din != NULL) { - for (i = bytes - 1; i >= 0; --i) { - din[i] = tmpdin & 0xff; - tmpdin >>= 8; - } - din += bytes; - } - } - } - - if (tm >= SPI_TIMEOUT) - ret = tm; - - /* clear ACK RDY, etc. bits */ - writel(readl(®s->status), ®s->status); - } - - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); - - debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", - tmpdin, readl(®s->status)); - - if (ret) { - printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); - return -1; - } - - return 0; -} diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c new file mode 100644 index 0000000..4a3e799 --- /dev/null +++ b/drivers/spi/tegra_spi.c @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2010-2012 NVIDIA Corporation + * With help from the mpc8xxx SPI driver + * With more help from omap3_spi SPI driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPI_CORRUPTS_UART) + #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY); +#else + #define corrupt_delay() +#endif + +struct tegra_spi_slave { + struct spi_slave slave; + struct spi_tegra *regs; + unsigned int freq; + unsigned int mode; +}; + +static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) +{ + return container_of(slave, struct tegra_spi_slave, slave); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */ + if (bus != 0 || cs != 0) + return 0; + else + return 1; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct tegra_spi_slave *spi; + + if (!spi_cs_is_valid(bus, cs)) { + printf("SPI error: unsupported bus %d / chip select %d\n", + bus, cs); + return NULL; + } + + if (max_hz > TEGRA2_SPI_MAX_FREQ) { + printf("SPI error: unsupported frequency %d Hz. Max frequency" + " is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ); + return NULL; + } + + spi = malloc(sizeof(struct tegra_spi_slave)); + if (!spi) { + printf("SPI error: malloc of SPI structure failed\n"); + return NULL; + } + spi->slave.bus = bus; + spi->slave.cs = cs; + spi->freq = max_hz; + spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE; + spi->mode = mode; + + return &spi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + free(spi); +} + +void spi_init(void) +{ + /* do nothing */ +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_tegra *regs = spi->regs; + u32 reg; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq); + + /* Clear stale status here */ + reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ + SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; + writel(reg, ®s->status); + debug("spi_init: STATUS = %08x\n", readl(®s->status)); + + /* + * Use sw-controlled CS, so we can clock in data after ReadID, etc. + */ + reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; + if (spi->mode & 2) + reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; + clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | + SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); + debug("spi_init: COMMAND = %08x\n", readl(®s->command)); + + /* + * SPI pins on Tegra2 are muxed - change pinmux later due to UART + * issue. + */ + pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); + pinmux_tristate_disable(PINGRP_LSPI); + +#ifndef CONFIG_SPI_UART_SWITCH + /* + * NOTE: + * Only set PinMux bits 3:2 to SPI here on boards that don't have the + * SPI UART switch or subsequent UART data won't go out! See + * spi_uart_switch(). + */ + /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */ +#endif + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* + * We can't release UART_DISABLE and set pinmux to UART4 here since + * some code (e,g, spi_flash_probe) uses printf() while the SPI + * bus is held. That is arguably bad, but it has the advantage of + * already being in the source tree. + */ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + pinmux_select_spi(); + + /* CS is negated on Tegra, so drive a 1 to get a 0 */ + setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); + + corrupt_delay(); /* Let UART settle */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + pinmux_select_uart(); + + /* CS is negated on Tegra, so drive a 0 to get a 1 */ + clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); + + corrupt_delay(); /* Let SPI settle */ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_tegra *regs = spi->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + reg = readl(®s->status); + writel(reg, ®s->status); /* Clear all SPI events via R/W */ + debug("spi_xfer entry: STATUS = %08x\n", reg); + + reg = readl(®s->command); + reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; + writel(reg, ®s->command); + debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int is_read = 0; + int tm, i; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + for (i = 0; i < bytes; ++i) + tmpdout = (tmpdout << 8) | dout[i]; + } + + num_bytes -= bytes; + if (dout) + dout += bytes; + + clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, + bytes * 8 - 1); + writel(tmpdout, ®s->tx_fifo); + setbits_le32(®s->command, SPI_CMD_GO); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { + u32 status; + + status = readl(®s->status); + + /* We can exit when we've had both RX and TX activity */ + if (is_read && (status & SPI_STAT_TXF_EMPTY)) + break; + + if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != + SPI_STAT_RDY) + tm++; + + else if (!(status & SPI_STAT_RXF_EMPTY)) { + tmpdin = readl(®s->rx_fifo); + is_read = 1; + + /* swap bytes read in */ + if (din != NULL) { + for (i = bytes - 1; i >= 0; --i) { + din[i] = tmpdin & 0xff; + tmpdin >>= 8; + } + din += bytes; + } + } + } + + if (tm >= SPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(®s->status), ®s->status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", + tmpdin, readl(®s->status)); + + if (ret) { + printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); + return -1; + } + + return 0; +} diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index f46740e..db11d8a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -67,7 +67,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* SPI */ -#define CONFIG_TEGRA2_SPI +#define CONFIG_TEGRA_SPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -- cgit v0.10.2 From 3f82d89d3de76acf86279815a7752f7c04d043a2 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 22 May 2012 11:44:48 +0000 Subject: mmc: tegra2: rename tegra2_mmc.* to tegra_mmc.* In anticipation of Tegra3 support, continue removing/renaming Tegra2-specific files. No functional changes (yet). Updated copyrights to 2012. Signed-off-by: Tom Warren diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 8f8e7bf..f27ad37 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -29,7 +29,7 @@ #include #include #include -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include #endif @@ -41,7 +41,7 @@ void gpio_config_uart(void) { } -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 94efb1e..36039c4 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -29,7 +29,7 @@ #include #include #include -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include #endif @@ -54,7 +54,7 @@ void gpio_config_uart(void) } #endif -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 1c2f33f..3ec24df 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -30,7 +30,7 @@ #include #include #include -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include #endif diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a8e681c..c567737 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -42,7 +42,7 @@ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o COBJS-$(CONFIG_SDHCI) += sdhci.o COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o -COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o +COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c deleted file mode 100644 index fb8a57d..0000000 --- a/drivers/mmc/tegra2_mmc.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang - * Jaehoon Chung - * Portions Copyright 2011 NVIDIA Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include "tegra2_mmc.h" - -/* support 4 mmc hosts */ -struct mmc mmc_dev[4]; -struct mmc_host mmc_host[4]; - - -/** - * Get the host address and peripheral ID for a device. Devices are numbered - * from 0 to 3. - * - * @param host Structure to fill in (base, reg, mmc_id) - * @param dev_index Device index (0-3) - */ -static void tegra2_get_setup(struct mmc_host *host, int dev_index) -{ - debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index); - - switch (dev_index) { - case 1: - host->base = TEGRA2_SDMMC3_BASE; - host->mmc_id = PERIPH_ID_SDMMC3; - break; - case 2: - host->base = TEGRA2_SDMMC2_BASE; - host->mmc_id = PERIPH_ID_SDMMC2; - break; - case 3: - host->base = TEGRA2_SDMMC1_BASE; - host->mmc_id = PERIPH_ID_SDMMC1; - break; - case 0: - default: - host->base = TEGRA2_SDMMC4_BASE; - host->mmc_id = PERIPH_ID_SDMMC4; - break; - } - - host->reg = (struct tegra2_mmc *)host->base; -} - -static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) -{ - unsigned char ctrl; - - debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n", - (u32)data->dest, data->blocks, data->blocksize); - - writel((u32)data->dest, &host->reg->sysad); - /* - * DMASEL[4:3] - * 00 = Selects SDMA - * 01 = Reserved - * 10 = Selects 32-bit Address ADMA2 - * 11 = Selects 64-bit Address ADMA2 - */ - ctrl = readb(&host->reg->hostctl); - ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; - ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; - writeb(ctrl, &host->reg->hostctl); - - /* We do not handle DMA boundaries, so set it to max (512 KiB) */ - writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); - writew(data->blocks, &host->reg->blkcnt); -} - -static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) -{ - unsigned short mode; - debug(" mmc_set_transfer_mode called\n"); - /* - * TRNMOD - * MUL1SIN0[5] : Multi/Single Block Select - * RD1WT0[4] : Data Transfer Direction Select - * 1 = read - * 0 = write - * ENACMD12[2] : Auto CMD12 Enable - * ENBLKCNT[1] : Block Count Enable - * ENDMA[0] : DMA Enable - */ - mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | - TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); - - if (data->blocks > 1) - mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; - - if (data->flags & MMC_DATA_READ) - mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; - - if (data->flags & MMC_DATA_WRITE) { - if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1)) - printf("Warning: unaligned write to %p may fail\n", - data->src); - flush_dcache_range((ulong)data->src, (ulong)data->src + - data->blocks * data->blocksize); - } - - writew(mode, &host->reg->trnmod); -} - -static int mmc_wait_inhibit(struct mmc_host *host, - struct mmc_cmd *cmd, - struct mmc_data *data, - unsigned int timeout) -{ - /* - * PRNSTS - * CMDINHDAT[1] : Command Inhibit (DAT) - * CMDINHCMD[0] : Command Inhibit (CMD) - */ - unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; - - /* - * We shouldn't wait for data inhibit for stop commands, even - * though they might use busy signaling - */ - if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) - mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; - - while (readl(&host->reg->prnsts) & mask) { - if (timeout == 0) { - printf("%s: timeout error\n", __func__); - return -1; - } - timeout--; - udelay(1000); - } - - return 0; -} - -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct mmc_host *host = (struct mmc_host *)mmc->priv; - int flags, i; - int result; - unsigned int mask = 0; - unsigned int retry = 0x100000; - debug(" mmc_send_cmd called\n"); - - result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); - - if (result < 0) - return result; - - if (data) - mmc_prepare_data(host, data); - - debug("cmd->arg: %08x\n", cmd->cmdarg); - writel(cmd->cmdarg, &host->reg->argument); - - if (data) - mmc_set_transfer_mode(host, data); - - if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) - return -1; - - /* - * CMDREG - * CMDIDX[13:8] : Command index - * DATAPRNT[5] : Data Present Select - * ENCMDIDX[4] : Command Index Check Enable - * ENCMDCRC[3] : Command CRC Check Enable - * RSPTYP[1:0] - * 00 = No Response - * 01 = Length 136 - * 10 = Length 48 - * 11 = Length 48 Check busy after response - */ - if (!(cmd->resp_type & MMC_RSP_PRESENT)) - flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; - else if (cmd->resp_type & MMC_RSP_136) - flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; - else if (cmd->resp_type & MMC_RSP_BUSY) - flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; - else - flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; - - if (cmd->resp_type & MMC_RSP_CRC) - flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; - if (cmd->resp_type & MMC_RSP_OPCODE) - flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; - if (data) - flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; - - debug("cmd: %d\n", cmd->cmdidx); - - writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); - - for (i = 0; i < retry; i++) { - mask = readl(&host->reg->norintsts); - /* Command Complete */ - if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { - if (!data) - writel(mask, &host->reg->norintsts); - break; - } - } - - if (i == retry) { - printf("%s: waiting for status update\n", __func__); - writel(mask, &host->reg->norintsts); - return TIMEOUT; - } - - if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { - /* Timeout Error */ - debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); - writel(mask, &host->reg->norintsts); - return TIMEOUT; - } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { - /* Error Interrupt */ - debug("error: %08x cmd %d\n", mask, cmd->cmdidx); - writel(mask, &host->reg->norintsts); - return -1; - } - - if (cmd->resp_type & MMC_RSP_PRESENT) { - if (cmd->resp_type & MMC_RSP_136) { - /* CRC is stripped so we need to do some shifting. */ - for (i = 0; i < 4; i++) { - unsigned int offset = - (unsigned int)(&host->reg->rspreg3 - i); - cmd->response[i] = readl(offset) << 8; - - if (i != 3) { - cmd->response[i] |= - readb(offset - 1); - } - debug("cmd->resp[%d]: %08x\n", - i, cmd->response[i]); - } - } else if (cmd->resp_type & MMC_RSP_BUSY) { - for (i = 0; i < retry; i++) { - /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ - if (readl(&host->reg->prnsts) - & (1 << 20)) /* DAT[0] */ - break; - } - - if (i == retry) { - printf("%s: card is still busy\n", __func__); - writel(mask, &host->reg->norintsts); - return TIMEOUT; - } - - cmd->response[0] = readl(&host->reg->rspreg0); - debug("cmd->resp[0]: %08x\n", cmd->response[0]); - } else { - cmd->response[0] = readl(&host->reg->rspreg0); - debug("cmd->resp[0]: %08x\n", cmd->response[0]); - } - } - - if (data) { - unsigned long start = get_timer(0); - - while (1) { - mask = readl(&host->reg->norintsts); - - if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { - /* Error Interrupt */ - writel(mask, &host->reg->norintsts); - printf("%s: error during transfer: 0x%08x\n", - __func__, mask); - return -1; - } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { - /* - * DMA Interrupt, restart the transfer where - * it was interrupted. - */ - unsigned int address = readl(&host->reg->sysad); - - debug("DMA end\n"); - writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, - &host->reg->norintsts); - writel(address, &host->reg->sysad); - } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { - /* Transfer Complete */ - debug("r/w is done\n"); - break; - } else if (get_timer(start) > 2000UL) { - writel(mask, &host->reg->norintsts); - printf("%s: MMC Timeout\n" - " Interrupt status 0x%08x\n" - " Interrupt status enable 0x%08x\n" - " Interrupt signal enable 0x%08x\n" - " Present status 0x%08x\n", - __func__, mask, - readl(&host->reg->norintstsen), - readl(&host->reg->norintsigen), - readl(&host->reg->prnsts)); - return -1; - } - } - writel(mask, &host->reg->norintsts); - if (data->flags & MMC_DATA_READ) { - if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1)) - printf("Warning: unaligned read from %p " - "may fail\n", data->dest); - invalidate_dcache_range((ulong)data->dest, - (ulong)data->dest + - data->blocks * data->blocksize); - } - } - - udelay(1000); - return 0; -} - -static void mmc_change_clock(struct mmc_host *host, uint clock) -{ - int div; - unsigned short clk; - unsigned long timeout; - - debug(" mmc_change_clock called\n"); - - /* - * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz, - * PLLP_OUT0 - */ - if (clock == 0) - goto out; - clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, - &div); - debug("div = %d\n", div); - - writew(0, &host->reg->clkcon); - - /* - * CLKCON - * SELFREQ[15:8] : base clock divided by value - * ENSDCLK[2] : SD Clock Enable - * STBLINTCLK[1] : Internal Clock Stable - * ENINTCLK[0] : Internal Clock Enable - */ - div >>= 1; - clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | - TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); - writew(clk, &host->reg->clkcon); - - /* Wait max 10 ms */ - timeout = 10; - while (!(readw(&host->reg->clkcon) & - TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { - if (timeout == 0) { - printf("%s: timeout error\n", __func__); - return; - } - timeout--; - udelay(1000); - } - - clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; - writew(clk, &host->reg->clkcon); - - debug("mmc_change_clock: clkcon = %08X\n", clk); - -out: - host->clock = clock; -} - -static void mmc_set_ios(struct mmc *mmc) -{ - struct mmc_host *host = mmc->priv; - unsigned char ctrl; - debug(" mmc_set_ios called\n"); - - debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); - - /* Change clock first */ - mmc_change_clock(host, mmc->clock); - - ctrl = readb(&host->reg->hostctl); - - /* - * WIDE8[5] - * 0 = Depend on WIDE4 - * 1 = 8-bit mode - * WIDE4[1] - * 1 = 4-bit mode - * 0 = 1-bit mode - */ - if (mmc->bus_width == 8) - ctrl |= (1 << 5); - else if (mmc->bus_width == 4) - ctrl |= (1 << 1); - else - ctrl &= ~(1 << 1); - - writeb(ctrl, &host->reg->hostctl); - debug("mmc_set_ios: hostctl = %08X\n", ctrl); -} - -static void mmc_reset(struct mmc_host *host) -{ - unsigned int timeout; - debug(" mmc_reset called\n"); - - /* - * RSTALL[0] : Software reset for all - * 1 = reset - * 0 = work - */ - writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); - - host->clock = 0; - - /* Wait max 100 ms */ - timeout = 100; - - /* hw clears the bit when it's done */ - while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { - if (timeout == 0) { - printf("%s: timeout error\n", __func__); - return; - } - timeout--; - udelay(1000); - } -} - -static int mmc_core_init(struct mmc *mmc) -{ - struct mmc_host *host = (struct mmc_host *)mmc->priv; - unsigned int mask; - debug(" mmc_core_init called\n"); - - mmc_reset(host); - - host->version = readw(&host->reg->hcver); - debug("host version = %x\n", host->version); - - /* mask all */ - writel(0xffffffff, &host->reg->norintstsen); - writel(0xffffffff, &host->reg->norintsigen); - - writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ - /* - * NORMAL Interrupt Status Enable Register init - * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable - * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable - * [3] ENSTADMAINT : DMA boundary interrupt - * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable - * [0] ENSTACMDCMPLT : Command Complete Status Enable - */ - mask = readl(&host->reg->norintstsen); - mask &= ~(0xffff); - mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | - TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | - TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | - TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | - TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); - writel(mask, &host->reg->norintstsen); - - /* - * NORMAL Interrupt Signal Enable Register init - * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable - */ - mask = readl(&host->reg->norintsigen); - mask &= ~(0xffff); - mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; - writel(mask, &host->reg->norintsigen); - - return 0; -} - -int tegra2_mmc_getcd(struct mmc *mmc) -{ - struct mmc_host *host = (struct mmc_host *)mmc->priv; - - debug("tegra2_mmc_getcd called\n"); - - if (host->cd_gpio >= 0) - return !gpio_get_value(host->cd_gpio); - - return 1; -} - -int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) -{ - struct mmc_host *host; - char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ - struct mmc *mmc; - - debug(" tegra2_mmc_init: index %d, bus width %d " - "pwr_gpio %d cd_gpio %d\n", - dev_index, bus_width, pwr_gpio, cd_gpio); - - host = &mmc_host[dev_index]; - - host->clock = 0; - host->pwr_gpio = pwr_gpio; - host->cd_gpio = cd_gpio; - tegra2_get_setup(host, dev_index); - - clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); - - if (host->pwr_gpio >= 0) { - sprintf(gpusage, "SD/MMC%d PWR", dev_index); - gpio_request(host->pwr_gpio, gpusage); - gpio_direction_output(host->pwr_gpio, 1); - } - - if (host->cd_gpio >= 0) { - sprintf(gpusage, "SD/MMC%d CD", dev_index); - gpio_request(host->cd_gpio, gpusage); - gpio_direction_input(host->cd_gpio); - } - - mmc = &mmc_dev[dev_index]; - - sprintf(mmc->name, "Tegra2 SD/MMC"); - mmc->priv = host; - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_core_init; - mmc->getcd = tegra2_mmc_getcd; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - if (bus_width == 8) - mmc->host_caps = MMC_MODE_8BIT; - else - mmc->host_caps = MMC_MODE_4BIT; - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; - - /* - * min freq is for card identification, and is the highest - * low-speed SDIO card frequency (actually 400KHz) - * max freq is highest HS eMMC clock as per the SD/MMC spec - * (actually 52MHz) - * Both of these are the closest equivalents w/216MHz source - * clock and Tegra2 SDMMC divisors. - */ - mmc->f_min = 375000; - mmc->f_max = 48000000; - - mmc_register(mmc); - - return 0; -} diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h deleted file mode 100644 index 67c00db..0000000 --- a/drivers/mmc/tegra2_mmc.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang - * Portions Copyright (C) 2011 NVIDIA Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __TEGRA2_MMC_H_ -#define __TEGRA2_MMC_H_ - -#define TEGRA2_SDMMC1_BASE 0xC8000000 -#define TEGRA2_SDMMC2_BASE 0xC8000200 -#define TEGRA2_SDMMC3_BASE 0xC8000400 -#define TEGRA2_SDMMC4_BASE 0xC8000600 - -#ifndef __ASSEMBLY__ -struct tegra2_mmc { - unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ - unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ - unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ - unsigned int argument; /* _ARGUMENT_0 */ - unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ - unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ - unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ - unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ - unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ - unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ - unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ - unsigned int prnsts; /* _PRESENT_STATE_0 */ - unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ - unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ - unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ - unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ - unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ - unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ - unsigned char swrst; /* _SW_RESET_ 31:24 */ - unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ - unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ - unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ - unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ - unsigned char res1[2]; /* _RESERVED 31:16 */ - unsigned int capareg; /* _CAPABILITIES_0 */ - unsigned char res2[4]; /* RESERVED, offset 44h-47h */ - unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ - unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ - unsigned short setacmd12err; /* offset 50h */ - unsigned short setinterr; /* offset 52h */ - unsigned char admaerr; /* offset 54h */ - unsigned char res4[3]; /* RESERVED, offset 55h-57h */ - unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ - unsigned short slotintstatus; /* offset FCh */ - unsigned short hcver; /* HOST Version */ - unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ -}; - -#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) - -#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) -#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) -#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) - -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) - -#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) -#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) -#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) - -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) - -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) -#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) - -#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 -#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) - -#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) - -#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) -#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) - -#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) - -#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) - -struct mmc_host { - struct tegra2_mmc *reg; - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ - unsigned int base; /* Base address, SDMMC1/2/3/4 */ - enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ - int pwr_gpio; /* Power GPIO */ - int cd_gpio; /* Change Detect GPIO */ -}; - -#endif /* __ASSEMBLY__ */ -#endif /* __TEGRA2_MMC_H_ */ diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c new file mode 100644 index 0000000..29bf583 --- /dev/null +++ b/drivers/mmc/tegra_mmc.c @@ -0,0 +1,570 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang + * Jaehoon Chung + * Portions Copyright 2011-2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "tegra_mmc.h" + +/* support 4 mmc hosts */ +struct mmc mmc_dev[4]; +struct mmc_host mmc_host[4]; + + +/** + * Get the host address and peripheral ID for a device. Devices are numbered + * from 0 to 3. + * + * @param host Structure to fill in (base, reg, mmc_id) + * @param dev_index Device index (0-3) + */ +static void tegra2_get_setup(struct mmc_host *host, int dev_index) +{ + debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index); + + switch (dev_index) { + case 1: + host->base = TEGRA2_SDMMC3_BASE; + host->mmc_id = PERIPH_ID_SDMMC3; + break; + case 2: + host->base = TEGRA2_SDMMC2_BASE; + host->mmc_id = PERIPH_ID_SDMMC2; + break; + case 3: + host->base = TEGRA2_SDMMC1_BASE; + host->mmc_id = PERIPH_ID_SDMMC1; + break; + case 0: + default: + host->base = TEGRA2_SDMMC4_BASE; + host->mmc_id = PERIPH_ID_SDMMC4; + break; + } + + host->reg = (struct tegra2_mmc *)host->base; +} + +static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) +{ + unsigned char ctrl; + + debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n", + (u32)data->dest, data->blocks, data->blocksize); + + writel((u32)data->dest, &host->reg->sysad); + /* + * DMASEL[4:3] + * 00 = Selects SDMA + * 01 = Reserved + * 10 = Selects 32-bit Address ADMA2 + * 11 = Selects 64-bit Address ADMA2 + */ + ctrl = readb(&host->reg->hostctl); + ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; + ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; + writeb(ctrl, &host->reg->hostctl); + + /* We do not handle DMA boundaries, so set it to max (512 KiB) */ + writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); + writew(data->blocks, &host->reg->blkcnt); +} + +static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) +{ + unsigned short mode; + debug(" mmc_set_transfer_mode called\n"); + /* + * TRNMOD + * MUL1SIN0[5] : Multi/Single Block Select + * RD1WT0[4] : Data Transfer Direction Select + * 1 = read + * 0 = write + * ENACMD12[2] : Auto CMD12 Enable + * ENBLKCNT[1] : Block Count Enable + * ENDMA[0] : DMA Enable + */ + mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | + TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); + + if (data->blocks > 1) + mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; + + if (data->flags & MMC_DATA_READ) + mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; + + if (data->flags & MMC_DATA_WRITE) { + if ((uintptr_t)data->src & (ARCH_DMA_MINALIGN - 1)) + printf("Warning: unaligned write to %p may fail\n", + data->src); + flush_dcache_range((ulong)data->src, (ulong)data->src + + data->blocks * data->blocksize); + } + + writew(mode, &host->reg->trnmod); +} + +static int mmc_wait_inhibit(struct mmc_host *host, + struct mmc_cmd *cmd, + struct mmc_data *data, + unsigned int timeout) +{ + /* + * PRNSTS + * CMDINHDAT[1] : Command Inhibit (DAT) + * CMDINHCMD[0] : Command Inhibit (CMD) + */ + unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; + + /* + * We shouldn't wait for data inhibit for stop commands, even + * though they might use busy signaling + */ + if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) + mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; + + while (readl(&host->reg->prnsts) & mask) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return -1; + } + timeout--; + udelay(1000); + } + + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + int flags, i; + int result; + unsigned int mask = 0; + unsigned int retry = 0x100000; + debug(" mmc_send_cmd called\n"); + + result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); + + if (result < 0) + return result; + + if (data) + mmc_prepare_data(host, data); + + debug("cmd->arg: %08x\n", cmd->cmdarg); + writel(cmd->cmdarg, &host->reg->argument); + + if (data) + mmc_set_transfer_mode(host, data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + /* + * CMDREG + * CMDIDX[13:8] : Command index + * DATAPRNT[5] : Data Present Select + * ENCMDIDX[4] : Command Index Check Enable + * ENCMDCRC[3] : Command CRC Check Enable + * RSPTYP[1:0] + * 00 = No Response + * 01 = Length 136 + * 10 = Length 48 + * 11 = Length 48 Check busy after response + */ + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; + else if (cmd->resp_type & MMC_RSP_136) + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; + else if (cmd->resp_type & MMC_RSP_BUSY) + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; + else + flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; + if (cmd->resp_type & MMC_RSP_OPCODE) + flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; + if (data) + flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; + + debug("cmd: %d\n", cmd->cmdidx); + + writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); + + for (i = 0; i < retry; i++) { + mask = readl(&host->reg->norintsts); + /* Command Complete */ + if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { + if (!data) + writel(mask, &host->reg->norintsts); + break; + } + } + + if (i == retry) { + printf("%s: waiting for status update\n", __func__); + writel(mask, &host->reg->norintsts); + return TIMEOUT; + } + + if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { + /* Timeout Error */ + debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); + writel(mask, &host->reg->norintsts); + return TIMEOUT; + } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { + /* Error Interrupt */ + debug("error: %08x cmd %d\n", mask, cmd->cmdidx); + writel(mask, &host->reg->norintsts); + return -1; + } + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + unsigned int offset = + (unsigned int)(&host->reg->rspreg3 - i); + cmd->response[i] = readl(offset) << 8; + + if (i != 3) { + cmd->response[i] |= + readb(offset - 1); + } + debug("cmd->resp[%d]: %08x\n", + i, cmd->response[i]); + } + } else if (cmd->resp_type & MMC_RSP_BUSY) { + for (i = 0; i < retry; i++) { + /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ + if (readl(&host->reg->prnsts) + & (1 << 20)) /* DAT[0] */ + break; + } + + if (i == retry) { + printf("%s: card is still busy\n", __func__); + writel(mask, &host->reg->norintsts); + return TIMEOUT; + } + + cmd->response[0] = readl(&host->reg->rspreg0); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); + } else { + cmd->response[0] = readl(&host->reg->rspreg0); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); + } + } + + if (data) { + unsigned long start = get_timer(0); + + while (1) { + mask = readl(&host->reg->norintsts); + + if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { + /* Error Interrupt */ + writel(mask, &host->reg->norintsts); + printf("%s: error during transfer: 0x%08x\n", + __func__, mask); + return -1; + } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { + /* + * DMA Interrupt, restart the transfer where + * it was interrupted. + */ + unsigned int address = readl(&host->reg->sysad); + + debug("DMA end\n"); + writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, + &host->reg->norintsts); + writel(address, &host->reg->sysad); + } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { + /* Transfer Complete */ + debug("r/w is done\n"); + break; + } else if (get_timer(start) > 2000UL) { + writel(mask, &host->reg->norintsts); + printf("%s: MMC Timeout\n" + " Interrupt status 0x%08x\n" + " Interrupt status enable 0x%08x\n" + " Interrupt signal enable 0x%08x\n" + " Present status 0x%08x\n", + __func__, mask, + readl(&host->reg->norintstsen), + readl(&host->reg->norintsigen), + readl(&host->reg->prnsts)); + return -1; + } + } + writel(mask, &host->reg->norintsts); + if (data->flags & MMC_DATA_READ) { + if ((uintptr_t)data->dest & (ARCH_DMA_MINALIGN - 1)) + printf("Warning: unaligned read from %p " + "may fail\n", data->dest); + invalidate_dcache_range((ulong)data->dest, + (ulong)data->dest + + data->blocks * data->blocksize); + } + } + + udelay(1000); + return 0; +} + +static void mmc_change_clock(struct mmc_host *host, uint clock) +{ + int div; + unsigned short clk; + unsigned long timeout; + + debug(" mmc_change_clock called\n"); + + /* + * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz, + * PLLP_OUT0 + */ + if (clock == 0) + goto out; + clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, + &div); + debug("div = %d\n", div); + + writew(0, &host->reg->clkcon); + + /* + * CLKCON + * SELFREQ[15:8] : base clock divided by value + * ENSDCLK[2] : SD Clock Enable + * STBLINTCLK[1] : Internal Clock Stable + * ENINTCLK[0] : Internal Clock Enable + */ + div >>= 1; + clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | + TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); + writew(clk, &host->reg->clkcon); + + /* Wait max 10 ms */ + timeout = 10; + while (!(readw(&host->reg->clkcon) & + TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return; + } + timeout--; + udelay(1000); + } + + clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk, &host->reg->clkcon); + + debug("mmc_change_clock: clkcon = %08X\n", clk); + +out: + host->clock = clock; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct mmc_host *host = mmc->priv; + unsigned char ctrl; + debug(" mmc_set_ios called\n"); + + debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); + + /* Change clock first */ + mmc_change_clock(host, mmc->clock); + + ctrl = readb(&host->reg->hostctl); + + /* + * WIDE8[5] + * 0 = Depend on WIDE4 + * 1 = 8-bit mode + * WIDE4[1] + * 1 = 4-bit mode + * 0 = 1-bit mode + */ + if (mmc->bus_width == 8) + ctrl |= (1 << 5); + else if (mmc->bus_width == 4) + ctrl |= (1 << 1); + else + ctrl &= ~(1 << 1); + + writeb(ctrl, &host->reg->hostctl); + debug("mmc_set_ios: hostctl = %08X\n", ctrl); +} + +static void mmc_reset(struct mmc_host *host) +{ + unsigned int timeout; + debug(" mmc_reset called\n"); + + /* + * RSTALL[0] : Software reset for all + * 1 = reset + * 0 = work + */ + writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); + + host->clock = 0; + + /* Wait max 100 ms */ + timeout = 100; + + /* hw clears the bit when it's done */ + while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return; + } + timeout--; + udelay(1000); + } +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + unsigned int mask; + debug(" mmc_core_init called\n"); + + mmc_reset(host); + + host->version = readw(&host->reg->hcver); + debug("host version = %x\n", host->version); + + /* mask all */ + writel(0xffffffff, &host->reg->norintstsen); + writel(0xffffffff, &host->reg->norintsigen); + + writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ + /* + * NORMAL Interrupt Status Enable Register init + * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable + * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable + * [3] ENSTADMAINT : DMA boundary interrupt + * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable + * [0] ENSTACMDCMPLT : Command Complete Status Enable + */ + mask = readl(&host->reg->norintstsen); + mask &= ~(0xffff); + mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | + TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | + TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | + TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | + TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); + writel(mask, &host->reg->norintstsen); + + /* + * NORMAL Interrupt Signal Enable Register init + * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable + */ + mask = readl(&host->reg->norintsigen); + mask &= ~(0xffff); + mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; + writel(mask, &host->reg->norintsigen); + + return 0; +} + +int tegra2_mmc_getcd(struct mmc *mmc) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + + debug("tegra2_mmc_getcd called\n"); + + if (host->cd_gpio >= 0) + return !gpio_get_value(host->cd_gpio); + + return 1; +} + +int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) +{ + struct mmc_host *host; + char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ + struct mmc *mmc; + + debug(" tegra2_mmc_init: index %d, bus width %d " + "pwr_gpio %d cd_gpio %d\n", + dev_index, bus_width, pwr_gpio, cd_gpio); + + host = &mmc_host[dev_index]; + + host->clock = 0; + host->pwr_gpio = pwr_gpio; + host->cd_gpio = cd_gpio; + tegra2_get_setup(host, dev_index); + + clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); + + if (host->pwr_gpio >= 0) { + sprintf(gpusage, "SD/MMC%d PWR", dev_index); + gpio_request(host->pwr_gpio, gpusage); + gpio_direction_output(host->pwr_gpio, 1); + } + + if (host->cd_gpio >= 0) { + sprintf(gpusage, "SD/MMC%d CD", dev_index); + gpio_request(host->cd_gpio, gpusage); + gpio_direction_input(host->cd_gpio); + } + + mmc = &mmc_dev[dev_index]; + + sprintf(mmc->name, "Tegra2 SD/MMC"); + mmc->priv = host; + mmc->send_cmd = mmc_send_cmd; + mmc->set_ios = mmc_set_ios; + mmc->init = mmc_core_init; + mmc->getcd = tegra2_mmc_getcd; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + if (bus_width == 8) + mmc->host_caps = MMC_MODE_8BIT; + else + mmc->host_caps = MMC_MODE_4BIT; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; + + /* + * min freq is for card identification, and is the highest + * low-speed SDIO card frequency (actually 400KHz) + * max freq is highest HS eMMC clock as per the SD/MMC spec + * (actually 52MHz) + * Both of these are the closest equivalents w/216MHz source + * clock and Tegra2 SDMMC divisors. + */ + mmc->f_min = 375000; + mmc->f_max = 48000000; + + mmc_register(mmc); + + return 0; +} diff --git a/drivers/mmc/tegra_mmc.h b/drivers/mmc/tegra_mmc.h new file mode 100644 index 0000000..f9cdcaa --- /dev/null +++ b/drivers/mmc/tegra_mmc.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang + * Portions Copyright (C) 2011-2012 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __TEGRA_MMC_H_ +#define __TEGRA_MMC_H_ + +#define TEGRA2_SDMMC1_BASE 0xC8000000 +#define TEGRA2_SDMMC2_BASE 0xC8000200 +#define TEGRA2_SDMMC3_BASE 0xC8000400 +#define TEGRA2_SDMMC4_BASE 0xC8000600 + +#ifndef __ASSEMBLY__ +struct tegra2_mmc { + unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ + unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ + unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ + unsigned int argument; /* _ARGUMENT_0 */ + unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ + unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ + unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ + unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ + unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ + unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ + unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ + unsigned int prnsts; /* _PRESENT_STATE_0 */ + unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ + unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ + unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ + unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ + unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ + unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ + unsigned char swrst; /* _SW_RESET_ 31:24 */ + unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ + unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ + unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ + unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ + unsigned char res1[2]; /* _RESERVED 31:16 */ + unsigned int capareg; /* _CAPABILITIES_0 */ + unsigned char res2[4]; /* RESERVED, offset 44h-47h */ + unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ + unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ + unsigned short setacmd12err; /* offset 50h */ + unsigned short setinterr; /* offset 52h */ + unsigned char admaerr; /* offset 54h */ + unsigned char res4[3]; /* RESERVED, offset 55h-57h */ + unsigned long admaaddr; /* offset 58h-5Fh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned short slotintstatus; /* offset FCh */ + unsigned short hcver; /* HOST Version */ + unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ +}; + +#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) +#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) + +#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) +#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) +#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) +#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) + +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) +#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) + +#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) +#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) +#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) + +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) +#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) + +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) +#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) +#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) + +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 +#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) + +#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) +#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) + +#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) +#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) + +#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) +#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) +#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) +#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) + +#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) + +struct mmc_host { + struct tegra2_mmc *reg; + unsigned int version; /* SDHCI spec. version */ + unsigned int clock; /* Current clock (MHz) */ + unsigned int base; /* Base address, SDMMC1/2/3/4 */ + enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ + int pwr_gpio; /* Power GPIO */ + int cd_gpio; /* Change Detect GPIO */ +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __TEGRA_MMC_H_ */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 88189be..d13ead9 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -55,7 +55,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/medcom.h b/include/configs/medcom.h index eecfa50..d3d1055 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -45,7 +45,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 3edd102..d6f7fe3 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -42,7 +42,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 1888276..e73be0b 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -45,7 +45,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index db11d8a..cae6e23 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -86,7 +86,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 21b9ef2..7e6adc7 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -58,7 +58,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 665076d..77a0a14 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -49,7 +49,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/whistler.h b/include/configs/whistler.h index ec96cff..9dafe5c 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -58,7 +58,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION -- cgit v0.10.2 From 52a8b82074d1c3a3dcde8e3d90e6a04f7eb3a1f8 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 22 May 2012 12:19:25 +0000 Subject: gpio: tegra2: rename tegra2_gpio.* to tegra_gpio.* In anticipation of Tegra3 support, continue removing/renaming Tegra2-specific files. No functional changes (yet). Updated copyrights to 2012. Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h index 41e66fe..40ddb02 100644 --- a/arch/arm/include/asm/arch-tegra2/gpio.h +++ b/arch/arm/include/asm/arch-tegra2/gpio.h @@ -2,6 +2,7 @@ * Copyright (c) 2011, Google Inc. All rights reserved. * See file CREDITS for list of people who contributed to this * project. + * Portions Copyright 2011-2012 NVIDIA Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,8 +20,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA2_GPIO_H_ -#define _TEGRA2_GPIO_H_ +#ifndef _TEGRA_GPIO_H_ +#define _TEGRA_GPIO_H_ /* * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, @@ -286,4 +287,4 @@ enum gpio_pin { void gpio_info(void); #define gpio_status() gpio_info() -#endif /* TEGRA2_GPIO_H_ */ +#endif /* TEGRA_GPIO_H_ */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb3b09a..5ae68d5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -35,7 +35,7 @@ COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_PCA9698) += pca9698.o COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS-$(CONFIG_SANDBOX_GPIO) += sandbox.o -COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o +COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o diff --git a/drivers/gpio/tegra2_gpio.c b/drivers/gpio/tegra2_gpio.c deleted file mode 100644 index 70ca46f..0000000 --- a/drivers/gpio/tegra2_gpio.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * NVIDIA Tegra2 GPIO handling. - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. - * Tom Warren (twarren@nvidia.com) - */ - -#include -#include -#include -#include -#include - -enum { - TEGRA2_CMD_INFO, - TEGRA2_CMD_PORT, - TEGRA2_CMD_OUTPUT, - TEGRA2_CMD_INPUT, -}; - -static struct gpio_names { - char name[GPIO_NAME_SIZE]; -} gpio_names[MAX_NUM_GPIOS]; - -static char *get_name(int i) -{ - return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; -} - -/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ -static int get_config(unsigned gpio) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - u32 u; - int type; - - u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - type = (u >> GPIO_BIT(gpio)) & 1; - - debug("get_config: port = %d, bit = %d is %s\n", - GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - - return type; -} - -/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ -static void set_config(unsigned gpio, int type) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - u32 u; - - debug("set_config: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - - u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - if (type) /* GPIO */ - u |= 1 << GPIO_BIT(gpio); - else - u &= ~(1 << GPIO_BIT(gpio)); - writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); -} - -/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ -static int get_direction(unsigned gpio) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - u32 u; - int dir; - - u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); - dir = (u >> GPIO_BIT(gpio)) & 1; - - debug("get_direction: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); - - return dir; -} - -/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ -static void set_direction(unsigned gpio, int output) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - u32 u; - - debug("set_direction: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); - - u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); - if (output) - u |= 1 << GPIO_BIT(gpio); - else - u &= ~(1 << GPIO_BIT(gpio)); - writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); -} - -/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ -static void set_level(unsigned gpio, int high) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - u32 u; - - debug("set_level: port = %d, bit %d == %d\n", - GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); - - u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); - if (high) - u |= 1 << GPIO_BIT(gpio); - else - u &= ~(1 << GPIO_BIT(gpio)); - writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); -} - -/* - * Generic_GPIO primitives. - */ - -int gpio_request(unsigned gpio, const char *label) -{ - if (gpio >= MAX_NUM_GPIOS) - return -1; - - if (label != NULL) { - strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE); - gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0'; - } - - /* Configure as a GPIO */ - set_config(gpio, 1); - - return 0; -} - -int gpio_free(unsigned gpio) -{ - if (gpio >= MAX_NUM_GPIOS) - return -1; - - gpio_names[gpio].name[0] = '\0'; - /* Do not configure as input or change pin mux here */ - return 0; -} - -/* read GPIO OUT value of pin 'gpio' */ -static int gpio_get_output_value(unsigned gpio) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - int val; - - debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - - val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); - - return (val >> GPIO_BIT(gpio)) & 1; -} - -/* set GPIO pin 'gpio' as an input */ -int gpio_direction_input(unsigned gpio) -{ - debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - - /* Configure GPIO direction as input. */ - set_direction(gpio, 0); - - return 0; -} - -/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gpio, int value) -{ - debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), - value ? "HIGH" : "LOW"); - - /* Configure GPIO output value. */ - set_level(gpio, value); - - /* Configure GPIO direction as output. */ - set_direction(gpio, 1); - - return 0; -} - -/* read GPIO IN value of pin 'gpio' */ -int gpio_get_value(unsigned gpio) -{ - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; - int val; - - debug("gpio_get_value: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - - val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); - - return (val >> GPIO_BIT(gpio)) & 1; -} - -/* write GPIO OUT value to pin 'gpio' */ -int gpio_set_value(unsigned gpio, int value) -{ - debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); - - /* Configure GPIO output value. */ - set_level(gpio, value); - - return 0; -} - -/* - * Display Tegra GPIO information - */ -void gpio_info(void) -{ - unsigned c; - int type; - - for (c = 0; c < MAX_NUM_GPIOS; c++) { - type = get_config(c); /* GPIO, not SFPIO */ - if (type) { - printf("GPIO_%d:\t%s is an %s, ", c, - get_name(c), - get_direction(c) ? "OUTPUT" : "INPUT"); - if (get_direction(c)) - printf("value = %d", gpio_get_output_value(c)); - else - printf("value = %d", gpio_get_value(c)); - printf("\n"); - } else - continue; - } -} diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c new file mode 100644 index 0000000..60ec6e3 --- /dev/null +++ b/drivers/gpio/tegra_gpio.c @@ -0,0 +1,262 @@ +/* + * NVIDIA Tegra2 GPIO handling. + * (C) Copyright 2010-2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. + * Tom Warren (twarren@nvidia.com) + */ + +#include +#include +#include +#include +#include + +enum { + TEGRA2_CMD_INFO, + TEGRA2_CMD_PORT, + TEGRA2_CMD_OUTPUT, + TEGRA2_CMD_INPUT, +}; + +static struct gpio_names { + char name[GPIO_NAME_SIZE]; +} gpio_names[MAX_NUM_GPIOS]; + +static char *get_name(int i) +{ + return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; +} + +/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ +static int get_config(unsigned gpio) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + u32 u; + int type; + + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); + type = (u >> GPIO_BIT(gpio)) & 1; + + debug("get_config: port = %d, bit = %d is %s\n", + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); + + return type; +} + +/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ +static void set_config(unsigned gpio, int type) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + u32 u; + + debug("set_config: port = %d, bit = %d, %s\n", + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); + + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); + if (type) /* GPIO */ + u |= 1 << GPIO_BIT(gpio); + else + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); +} + +/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ +static int get_direction(unsigned gpio) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + u32 u; + int dir; + + u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); + dir = (u >> GPIO_BIT(gpio)) & 1; + + debug("get_direction: port = %d, bit = %d, %s\n", + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); + + return dir; +} + +/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ +static void set_direction(unsigned gpio, int output) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + u32 u; + + debug("set_direction: port = %d, bit = %d, %s\n", + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); + + u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); + if (output) + u |= 1 << GPIO_BIT(gpio); + else + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); +} + +/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ +static void set_level(unsigned gpio, int high) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + u32 u; + + debug("set_level: port = %d, bit %d == %d\n", + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); + + u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); + if (high) + u |= 1 << GPIO_BIT(gpio); + else + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); +} + +/* + * Generic_GPIO primitives. + */ + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio >= MAX_NUM_GPIOS) + return -1; + + if (label != NULL) { + strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE); + gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0'; + } + + /* Configure as a GPIO */ + set_config(gpio, 1); + + return 0; +} + +int gpio_free(unsigned gpio) +{ + if (gpio >= MAX_NUM_GPIOS) + return -1; + + gpio_names[gpio].name[0] = '\0'; + /* Do not configure as input or change pin mux here */ + return 0; +} + +/* read GPIO OUT value of pin 'gpio' */ +static int gpio_get_output_value(unsigned gpio) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + int val; + + debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + + val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); + + return (val >> GPIO_BIT(gpio)) & 1; +} + +/* set GPIO pin 'gpio' as an input */ +int gpio_direction_input(unsigned gpio) +{ + debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + + /* Configure GPIO direction as input. */ + set_direction(gpio, 0); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int gpio_direction_output(unsigned gpio, int value) +{ + debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), + value ? "HIGH" : "LOW"); + + /* Configure GPIO output value. */ + set_level(gpio, value); + + /* Configure GPIO direction as output. */ + set_direction(gpio, 1); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +int gpio_get_value(unsigned gpio) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + int val; + + debug("gpio_get_value: pin = %d (port %d:bit %d)\n", + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + + val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); + + return (val >> GPIO_BIT(gpio)) & 1; +} + +/* write GPIO OUT value to pin 'gpio' */ +int gpio_set_value(unsigned gpio, int value) +{ + debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); + + /* Configure GPIO output value. */ + set_level(gpio, value); + + return 0; +} + +/* + * Display Tegra GPIO information + */ +void gpio_info(void) +{ + unsigned c; + int type; + + for (c = 0; c < MAX_NUM_GPIOS; c++) { + type = get_config(c); /* GPIO, not SFPIO */ + if (type) { + printf("GPIO_%d:\t%s is an %s, ", c, + get_name(c), + get_direction(c) ? "OUTPUT" : "INPUT"); + if (get_direction(c)) + printf("value = %d", gpio_get_output_value(c)); + else + printf("value = %d", gpio_get_value(c)); + printf("\n"); + } else + continue; + } +} diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index a4146a5..94e1aa6 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2012 * NVIDIA Corporation * * See file CREDITS for list of people who contributed to this @@ -190,6 +190,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_TEGRA2_GPIO +#define CONFIG_TEGRA_GPIO #define CONFIG_CMD_GPIO #endif /* __TEGRA2_COMMON_H */ -- cgit v0.10.2 From a5c168c6d6699e050c9333c03a4d53d62eb7949b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:37 +0000 Subject: tegra: trimslice: store environment in SPI flash The chosen flash offset matches Compulab's downstream U-Boot. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 7e6adc7..915b07a 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -47,6 +47,14 @@ #define CONFIG_BOARD_EARLY_INIT_F +/* SPI */ +#define CONFIG_TEGRA_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF + /* I2C */ #define CONFIG_TEGRA_I2C #define CONFIG_SYS_I2C_INIT_BOARD @@ -66,8 +74,12 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* Environment in SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ 48000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (512 * 1024) /* USB Host support */ #define CONFIG_USB_EHCI -- cgit v0.10.2 From e87c2bda9c45bcfcc8239f6052d6fa9aec7351d6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:38 +0000 Subject: tegra: paz00: store environment in eMMC Store the environment in eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage: U-Boot is stored well below this location, and the kernel only uses the general area of the eMMC once booted, not the boot sectors. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/paz00.h b/include/configs/paz00.h index d6f7fe3..29c368a 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -50,8 +50,10 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USB Host support */ #define CONFIG_USB_EHCI -- cgit v0.10.2 From f9f2f12e2cace3685ea0dbb6b6d78789fb75f043 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 24 May 2012 11:38:39 +0000 Subject: tegra: seaboard: disable SPI, move environment to eMMC The SPI hardware on Seaboard is too broken to use; it is muxed with the console UART and requires evil interactions between the SPI and UART drivers to work even partially. The current code in U-Boot is not sufficient to make this work correctly; auto boot is aborted due to corruption in the UART RX channel interrupting it. Instead, move the environment to eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage, irrespective of whether the board boots from SPI, NAND, or eMMC: if U-Boot is stored in eMMC, it will be stored well below this location. The kernel only uses the general area of the eMMC once booted, not the boot sectors. Boards that are derivatives of Seaboard don't have the muxing issue, and should/could have a separate U-Boot configuration file that does enable SPI if desired. Alternatively, the environment could be stored in NAND flash, but we currently have no driver for that controller. Signed-off-by: Stephen Warren Cc: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index cae6e23..537ab0e 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -51,30 +51,12 @@ /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ #define CONFIG_UART_DISABLE_GPIO GPIO_PI3 -/* - * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are - * needed to work around that design error. - */ -#define CONFIG_SPI_UART_SWITCH -#define CONFIG_SPI_CORRUPTS_UART NV_PA_APB_UARTD_BASE -#define CONFIG_SPI_CORRUPTS_UART_NR 3 -#define CONFIG_SPI_CORRUPTS_UART_DLY 2500 -#undef CONFIG_CMDLINE_EDITING /* avoid NUL in input buffer */ #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F -/* SPI */ -#define CONFIG_TEGRA_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - /* I2C */ #define CONFIG_TEGRA_I2C #define CONFIG_SYS_I2C_INIT_BOARD @@ -94,13 +76,10 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment in SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MAX_HZ 48000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 - -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USB Host support */ #define CONFIG_USB_EHCI -- cgit v0.10.2 From 76e350b7a3c568c8d27cf72f98036ec3ddb64f31 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 30 May 2012 14:06:09 -0700 Subject: arm: Tegra: Use ODMDATA from BCT in IRAM Walk the BIT and BCT to find the ODMDATA word in the CustomerData field and put it into Scratch20 reg for use by kernel, etc. Built all Tegra builds OK; Booted on Seaboard and saw ODMDATA in PMC scratch20 was the same as the value in my burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities will have to specify the odmdata (nvflash --odmdata n) on the command line or via a cfg file, or built in to their BCT. Signed-off-by: Tom Warren Acked-by: Stephen Warren diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 24e582d..1aad387 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -314,9 +314,28 @@ void enable_scu(void) writel(reg, &scu->scu_ctrl); } +static u32 get_odmdata(void) +{ + /* + * ODMDATA is stored in the BCT in IRAM by the BootROM. + * The BCT start and size are stored in the BIT in IRAM. + * Read the data @ bct_start + (bct_size - 12). This works + * on T20 and T30 BCTs, which are locked down. If this changes + * in new chips (T114, etc.), we can revisit this algorithm. + */ + + u32 bct_start, odmdata; + + bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR); + odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); + + return odmdata; +} + void init_pmc_scratch(void) { struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + u32 odmdata; int i; /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ @@ -324,7 +343,8 @@ void init_pmc_scratch(void) writel(0, &pmc->pmc_scratch1+i); /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ - writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); + odmdata = get_odmdata(); + writel(odmdata, &pmc->pmc_scratch20); #ifdef CONFIG_TEGRA2_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index d4ada10..3c8d8a8 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -60,6 +60,10 @@ struct timerus { /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define AP20_WB_RUN_ADDRESS 0x40020000 +#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ +#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ + /* These are the available SKUs (product types) for Tegra */ enum { SKU_ID_T20 = 0x8, diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d13ead9..df5265a 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -48,7 +48,6 @@ #endif #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY -#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/medcom.h b/include/configs/medcom.h index d3d1055..bdea7c9 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -31,7 +31,6 @@ /* High-level configuration options */ #define V_PROMPT "Tegra2 (Medcom) # " #define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom" -#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 29c368a..0dd1e83 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 -#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/plutux.h b/include/configs/plutux.h index e73be0b..6397eb1 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -31,7 +31,6 @@ /* High-level configuration options */ #define V_PROMPT "Tegra2 (Plutux) # " #define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux" -#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011 /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 537ab0e..f661583 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -53,7 +53,6 @@ #define CONFIG_UART_DISABLE_GPIO GPIO_PI3 #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD -#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 915b07a..91de348 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -43,7 +43,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE -#define CONFIG_SYS_BOARD_ODMDATA 0x300c0011 /* lp?, 1GB, UARTA */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 77a0a14..5e4d538 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_MACH_TYPE MACH_TYPE_VENTANA -#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 9dafe5c..f2952d5 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -43,7 +43,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER -#define CONFIG_SYS_BOARD_ODMDATA 0x2B080105 /* lp?, 512MB, UARTA */ #define CONFIG_BOARD_EARLY_INIT_F -- cgit v0.10.2 From 1e7e716e80f7a8f599390dd5aa4ae7dce465a1da Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 30 May 2012 06:45:50 +0000 Subject: tegra: trimslice: fix a couple typos Fix the .dts file USB unit addresses not to duplicate each-other. Fix the board name string to indicate the vendor is Compulab not NVIDIA. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren Acked-by: Igor Grinberg diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra2-trimslice.dts index c707eb8..db79e77 100644 --- a/board/compulab/dts/tegra2-trimslice.dts +++ b/board/compulab/dts/tegra2-trimslice.dts @@ -47,7 +47,7 @@ status = "disabled"; }; - usb@c5004000 { + usb@c5000000 { status = "disabled"; }; diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 91de348..34be8a9 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -34,7 +34,7 @@ /* High-level configuration options */ #define V_PROMPT "Tegra2 (TrimSlice) # " -#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Trimslice" +#define CONFIG_TEGRA2_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -- cgit v0.10.2 From d1df0fd37388fe0dc77a75f5aece04f70cc3f7e6 Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Mon, 14 May 2012 10:28:54 +0000 Subject: omap4/5: Use CPUDIR for .lds script Signed-off-by: Thomas Weber diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 8448142..e7a3de5 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -281,7 +281,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_ENABLE_PADS_ALL diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 60c7a29..8378387 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -261,7 +261,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* * 64 bytes before this address should be set aside for u-boot.img's -- cgit v0.10.2 From 2ab281037555de1710aa597531562fe071470198 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 14 May 2012 12:38:18 +0000 Subject: am33xx: Do not call init_timer twice We do not need to call init_timer both in SPL and U-Boot itself, just SPL needs to initialize the timer. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 6b7a494..71309a7 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -40,6 +40,22 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #define UART_SMART_IDLE_EN (0x1 << 0x3) #endif +#ifdef CONFIG_SPL_BUILD +/* Initialize timer */ +static void init_timer(void) +{ + /* Reset the Timer */ + writel(0x2, (&timer_base->tscir)); + + /* Wait until the reset is done */ + while (readl(&timer_base->tiocp_cfg) & 1) + ; + + /* Start the Timer */ + writel(0x1, (&timer_base->tclr)); +} +#endif + /* * early system init of muxing and clocks. */ @@ -88,20 +104,6 @@ void s_init(void) enable_mmc0_pin_mux(); } -/* Initialize timer */ -void init_timer(void) -{ - /* Reset the Timer */ - writel(0x2, (&timer_base->tscir)); - - /* Wait until the reset is done */ - while (readl(&timer_base->tiocp_cfg) & 1) - ; - - /* Start the Timer */ - writel(0x1, (&timer_base->tclr)); -} - #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index cd002e6..8760cc0 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -213,8 +213,6 @@ struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ }; - -void init_timer(void); #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c index 13dc603..5e2d53a 100644 --- a/board/ti/am335x/evm.c +++ b/board/ti/am335x/evm.c @@ -29,17 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; /* * Basic board specific setup */ -int init_basic_setup(void) -{ - /* Initialize the Timer */ - init_timer(); - - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; - - return 0; -} - int board_init(void) { enable_uart0_pin_mux(); @@ -49,7 +38,7 @@ int board_init(void) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - init_basic_setup(); + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; return 0; } -- cgit v0.10.2 From 14b9f16c401206097c361ae4198c6b2ece805964 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 14 May 2012 20:24:14 +0000 Subject: arm,davinci: update for enbw_cmc board - change gpio pin settings: - gpio pin 6[13] (PLC reset) default value low - gpio pin 6[0] (TPM reset) default value low - 4 new GPIO pins pin i/o name - 3[9] input Board Type - 2[7] input HW-ID0 - 2[6] input HW-ID1 - 2[3] input HW-ID2 - read board type and hw id from gpio pins on the enbw_cmc board, and use board type for setting up different gpio pin settings. - do not pass "davinci_mmc.use_dma=0" to linux, as MMC now works with DMA. - update logbuf support: store post word in RTC scratch register - add support for configuring KSZ8864RMN switch through a config file on u-boot startup. For more infos see: doc/README.switch_config Signed-off-by: Heiko Schocher Cc: Wolfgang Denk Cc: Tom Rini Cc: Christian Riesch Cc: Sandeep Paulraj diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 6c0d931..0874e9c 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -35,6 +35,8 @@ #include #include #include +#include +#include #include #include #include @@ -86,16 +88,22 @@ static const struct pinmux_config enbw_pins[] = { { pinmux(5), 1, 0 }, { pinmux(5), 1, 3 }, { pinmux(5), 1, 7 }, - { pinmux(6), 1, 0 }, - { pinmux(6), 1, 1 }, + { pinmux(5), 1, 5 }, + { pinmux(5), 1, 4 }, + { pinmux(5), 1, 3 }, + { pinmux(5), 1, 2 }, + { pinmux(5), 1, 1 }, + { pinmux(5), 1, 0 }, + { pinmux(6), 8, 0 }, + { pinmux(6), 8, 1 }, { pinmux(6), 8, 2 }, { pinmux(6), 8, 3 }, - { pinmux(6), 1, 4 }, + { pinmux(6), 8, 4 }, { pinmux(6), 8, 5 }, { pinmux(6), 1, 7 }, { pinmux(7), 8, 2 }, { pinmux(7), 1, 3 }, - { pinmux(7), 1, 6 }, + { pinmux(7), 8, 6 }, { pinmux(7), 1, 7 }, { pinmux(13), 8, 2 }, { pinmux(13), 8, 3 }, @@ -163,24 +171,37 @@ struct gpio_config { unsigned char value; }; -static const struct gpio_config enbw_gpio_config[] = { +static const struct gpio_config enbw_gpio_config_hut[] = { + { "RS485 enable", 8, 11, 1, 0 }, + { "RS485 iso", 8, 10, 1, 1 }, + { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, + { "W2HUT RS485 iso", 8, 8, 1, 1 }, +}; + +static const struct gpio_config enbw_gpio_config_w[] = { { "RS485 enable", 8, 11, 1, 0 }, { "RS485 iso", 8, 10, 1, 0 }, { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, { "W2HUT RS485 iso", 8, 8, 1, 0 }, +}; + +static const struct gpio_config enbw_gpio_config[] = { { "LAN reset", 7, 15, 1, 1 }, { "ena 11V PLC", 7, 14, 1, 0 }, { "ena 1.5V PLC", 7, 13, 1, 0 }, { "disable VBUS", 7, 12, 1, 1 }, - { "PLC reset", 6, 13, 1, 1 }, + { "PLC reset", 6, 13, 1, 0 }, { "LCM RS", 6, 12, 1, 0 }, { "LCM R/W", 6, 11, 1, 0 }, { "PLC pairing", 6, 10, 1, 1 }, { "PLC MDIO CLK", 6, 9, 1, 0 }, { "HK218", 6, 8, 1, 0 }, { "HK218 Rx", 6, 1, 1, 1 }, - { "TPM reset", 6, 0, 1, 1 }, - { "LCM E", 2, 2, 1, 1 }, + { "TPM reset", 6, 0, 1, 0 }, + { "Board-Type", 3, 9, 0, 0 }, + { "HW-ID0", 2, 7, 0, 0 }, + { "HW-ID1", 2, 6, 0, 0 }, + { "HW-ID2", 2, 3, 0, 0 }, { "PV-IF RxD ena", 0, 15, 1, 1 }, { "LED1", 1, 15, 1, 1 }, { "LED2", 0, 1, 1, 1 }, @@ -229,34 +250,57 @@ static void enbw_cmc_switch(int port, int on) } } -int board_init(void) +static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz) { int i, ret; -#ifndef CONFIG_USE_IRQ - irq_init(); -#endif - /* address of boot parameters, not used as booting with DTT */ - gd->bd->bi_boot_params = 0; + for (i = 0; i < sz; i++) { + int gpio = conf[i].bank * 16 + + conf[i].gpio; - for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { - int gpio = enbw_gpio_config[i].bank * 16 + - enbw_gpio_config[i].gpio; - - ret = gpio_request(gpio, enbw_gpio_config[i].name); + ret = gpio_request(gpio, conf[i].name); if (ret) { printf("%s: Could not get %s gpio\n", __func__, - enbw_gpio_config[i].name); - return -1; + conf[i].name); + return ret; } - if (enbw_gpio_config[i].out) + if (conf[i].out) gpio_direction_output(gpio, - enbw_gpio_config[i].value); + conf[i].value); else gpio_direction_input(gpio); } + return 0; +} + +int board_init(void) +{ + int board_type, hw_id; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + /* address of boot parameters, not used as booting with DTT */ + gd->bd->bi_boot_params = 0; + + enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config)); + + /* detect HW version */ + board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE); + hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) + + (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) + + (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2); + printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"), + hw_id); + if (board_type) + enbw_cmc_init_gpio(enbw_gpio_config_w, + ARRAY_SIZE(enbw_gpio_config_w)); + else + enbw_cmc_init_gpio(enbw_gpio_config_hut, + ARRAY_SIZE(enbw_gpio_config_hut)); + /* setup the SUSPSRC for ARM to control emulation suspend */ clrbits_le32(&davinci_syscfg_regs->suspsrc, (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | @@ -267,14 +311,231 @@ int board_init(void) } #ifdef CONFIG_DRIVER_TI_EMAC + +#define KSZ_CMD_READ 0x03 +#define KSZ_CMD_WRITE 0x02 +#define KSZ_ID 0x95 + +static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + int cmd_len; + u8 cmd[2]; + + cmd[0] = KSZ_CMD_READ; + cmd[1] = reg; + cmd_len = 2; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + flags |= SPI_XFER_END; + *val = 0; + cmd_len = 1; + ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags); + if (ret) { + debug("Failed to read (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + + return 0; +} + +static int enbw_cmc_switch_read_ident(struct spi_slave *spi) +{ + int ret; + u8 val; + + ret = enbw_cmc_switch_read(spi, 0, &val); + if (ret) { + debug("Failed to read\n"); + return -EINVAL; + } + + if (val != KSZ_ID) + return -EINVAL; + + return 0; +} + +static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg, + unsigned long val) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + int cmd_len; + u8 cmd[3]; + + cmd[0] = KSZ_CMD_WRITE; + cmd[1] = reg; + cmd[2] = val; + cmd_len = 3; + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + + udelay(1000); + ret = enbw_cmc_switch_read(spi, reg, &cmd[0]); + if (ret) { + debug("Failed to read\n"); + return -EINVAL; + } + if (val != cmd[0]) + debug("warning: reg: %lx va: %x soll: %lx\n", + reg, cmd[0], val); + + return 0; +} + +static int enbw_cmc_eof(unsigned char *ptr) +{ + if (*ptr == 0xff) + return 1; + + return 0; +} + +static char *enbw_cmc_getnewline(char *ptr) +{ + while (*ptr != 0x0a) { + ptr++; + if (enbw_cmc_eof((unsigned char *)ptr)) + return NULL; + } + + ptr++; + return ptr; +} + +static char *enbw_cmc_getvalue(char *ptr, int *value) +{ + int end = 0; + + *value = -EINVAL; + + if (!isxdigit(*ptr)) + end = 1; + + while (end) { + if ((*ptr == '#') || (*ptr == ';')) { + ptr = enbw_cmc_getnewline(ptr); + return ptr; + } + if (ptr != NULL) { + if (isxdigit(*ptr)) { + end = 0; + } else if (*ptr == 0x0a) { + ptr++; + return ptr; + } else { + ptr++; + if (enbw_cmc_eof((unsigned char *)ptr)) + return NULL; + } + } else { + return NULL; + } + } + *value = (int)simple_strtoul((const char *)ptr, &ptr, 16); + ptr++; + return ptr; +} + +static int enbw_cmc_config_switch(unsigned long addr) +{ + struct spi_slave *spi; + char *ptr = (char *)addr; + int value, reg; + int ret; + int bus, cs, max_hz, spi_mode; + + debug("configure switch with file on addr: 0x%lx\n", addr); + + bus = 0; + cs = 0; + max_hz = 1000000; + spi_mode = 0; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printf("Failed to set up slave\n"); + return -EINVAL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + ret = enbw_cmc_switch_read_ident(spi); + if (ret) + goto err_claim_bus; + + ptr = (char *)addr; + while (ptr != NULL) { + ptr = enbw_cmc_getvalue(ptr, ®); + if (ptr != NULL) { + ptr = enbw_cmc_getvalue(ptr, &value); + if ((ptr != NULL) && (value >= 0)) + if (enbw_cmc_switch_write(spi, reg, value)) + goto err_read; + } + } + return 0; + +err_read: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return -EINVAL; +} + +static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long addr; + + if (argc < 2) + return cmd_usage(cmdtp); + + addr = simple_strtoul(argv[1], NULL, 16); + enbw_cmc_config_switch(addr); + + return 0; +} + +U_BOOT_CMD(switch, 3, 1, do_switch, + "switch addr", + "[addr]" +); + /* * Initializes on-board ethernet controllers. */ int board_eth_init(bd_t *bis) { -#ifdef CONFIG_DRIVER_TI_EMAC + const char *s; + size_t len; + davinci_emac_mii_mode_sel(0); -#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* send a config file to the switch */ + s = hwconfig_subarg("switch", "config", &len); + if (len) { + unsigned long addr = simple_strtoul(s, NULL, 16); + + enbw_cmc_config_switch(addr); + } if (!davinci_emac_initialize()) { printf("Error: Ethernet init failed!\n"); @@ -546,6 +807,29 @@ ulong bootcount_load(void) } #endif +ulong post_word_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; + + return in_be32(®->scratch2); +} + +void post_word_store(ulong value) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + writel(RTC_KICK0R_WE, ®->kick0r); + writel(RTC_KICK1R_WE, ®->kick1r); + out_be32(®->scratch2, value); +} + void board_gpio_init(void) { struct davinci_gpio *gpio = davinci_gpio_bank01; @@ -558,6 +842,19 @@ void board_gpio_init(void) clrbits_le32(&gpio->out_data, 0x8000407e); /* set LED 1 - 5 to state on */ setbits_le32(&gpio->out_data, 0x8000001e); + + /* + * set some gpio pins to low, this is needed early, + * so we have no gpio Interface here + * gpios: + * 8[8] Mode PV select low + * 8[9] Debug Rx Enable low + * 8[10] Mode Select PV low + * 8[11] Counter Interface RS485 Rx-Enable low + */ + gpio = davinci_gpio_bank8; + clrbits_le32(&gpio->dir, 0x00000f00); + clrbits_le32(&gpio->out_data, 0x0f00); } int board_late_init(void) diff --git a/doc/README.switch_config b/doc/README.switch_config new file mode 100644 index 0000000..f890373 --- /dev/null +++ b/doc/README.switch_config @@ -0,0 +1,25 @@ +On the enbw_cmc board is a KSZ8864RMN switch which needs +configured through spi before working. This is done on +startup from u-boot through a config file stored at an +address specified in the "hwconfig" environment variable, +subcommand "config". + +For example on the enbw_cmc board: + +hwconfig=switch:lan=on,pwl=off,config=0x60160000 + +The file has the following structure: + +- a comment starts with a '#' or a ';' and ends with a newline +- The switch needs for its config a reg/value pair, so we + have two columns in the file: + reg : contains the register address + value: contains a 8 bit register value + This 2 columns are seperated through space or tab. + +example (minimal configuration on the enbw_cmc board): + +;reg value comment +;----------------------------------------- +0x01 0x00 +0x01 0x01 ; Start Switch with this configuration diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index c1a0f6a..3fc07e6 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -102,6 +102,14 @@ #define CONFIG_SYS_DTT_HYSTERESIS 3 /* + * SPI Configuration + */ +#define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CONFIG_CMD_SPI + +/* * Flash & Environment */ #ifdef CONFIG_USE_NAND @@ -225,9 +233,9 @@ "key_magic_2=2\0" \ "key_magic_3=3\0" \ "magic_keys=0123\0" \ - "hwconfig=switch:lan=on,pwl=off\0" \ + "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "logversion=2\0" \ @@ -336,6 +344,11 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MMC +/* GPIO */ +#define CONFIG_ENBW_CMC_BOARD_TYPE 57 +#define CONFIG_ENBW_CMC_HW_ID_BIT0 39 +#define CONFIG_ENBW_CMC_HW_ID_BIT1 38 +#define CONFIG_ENBW_CMC_HW_ID_BIT2 35 /* FDT support */ #define CONFIG_OF_LIBFDT @@ -438,7 +451,8 @@ #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #define CONFIG_POST (CONFIG_SYS_POST_MEMORY) -#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0 +#define CONFIG_POST_EXTERNAL_WORD_FUNCS +#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE #define CONFIG_LOGBUFFER #define CONFIG_SYS_CONSOLE_IS_IN_ENV -- cgit v0.10.2 From e06e914d872f3bd5098d2f1120ecee1447a3f566 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Thu, 17 May 2012 00:12:06 +0000 Subject: ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections. The DMM sections can be overlapping with each other, with sections 3 to 0 having the highest to lowest priority in that order. There could also be a section that is used trap the unmapped Tiler entries and this trap section could be overlapping with the actual sdram area. So take care of the above scenarios while calculating the size of the actual ram. Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index cf71ab4..6600323 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -162,11 +162,16 @@ void watchdog_init(void) */ u32 omap_sdram_size(void) { - u32 section, i, total_size = 0, size, addr; + u32 section, i, valid; + u64 sdram_start = 0, sdram_end = 0, addr, + size, total_size = 0, trap_size = 0; for (i = 0; i < 4; i++) { section = __raw_readl(DMM_BASE + i*4); + valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> + (EMIF_SDRC_ADDRSPC_SHIFT); addr = section & EMIF_SYS_ADDR_MASK; + /* See if the address is valid */ if ((addr >= DRAM_ADDR_SPACE_START) && (addr < DRAM_ADDR_SPACE_END)) { @@ -174,9 +179,20 @@ u32 omap_sdram_size(void) EMIF_SYS_SIZE_SHIFT); size = 1 << size; size *= SZ_16M; - total_size += size; + + if (valid != DMM_SDRC_ADDR_SPC_INVALID) { + if (!sdram_start || (addr < sdram_start)) + sdram_start = addr; + if (!sdram_end || ((addr + size) > sdram_end)) + sdram_end = addr + size; + } else { + trap_size = size; + } + } + } + total_size = (sdram_end - sdram_start) - (trap_size); return total_size; } -- cgit v0.10.2 From 77efdeb7588aeae585fcde7e59cc8693df592fd7 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Thu, 17 May 2012 00:12:07 +0000 Subject: ARM: OMAP5: dmm: Create a tiler trap section. The unmapped entries in tiler space are set with values 0xFF. So creating a DMM section of size 16MB at 0xFF000000 with ADDRSPACE set to 0x2. This way all the unmapped entry accesses to tiler will be trapped by the EMIF and a error response is sent to the L3 interconnect. L3 errors are inturn reported to MPU. Note that here the tiler trap section is overlapping with the actual ddr physical space and we lose 16MB out of the total 2GB. Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index b2b5753..368b78b 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -88,9 +88,9 @@ const struct emif_regs emif_regs_266_mhz_2cs = { const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0, - .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80740300 + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100 }; const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { -- cgit v0.10.2 From 41321fd4d64492689bfad20c98b8970171aee7ce Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Thu, 17 May 2012 00:12:08 +0000 Subject: ARM: OMAP5: Align memory used for testing to the power of 2 get_ram_size checks the given memory range for valid ram, but expects the size of memory to be aligned to the power of 2. In case of OMAP5 evm board the memory available is 2GB - 16MB(used for TRAP section) = 2032MB. So always ensure that the size of memory used for testing is aligned to the power of 2. Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index db509c9..389feda 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1161,6 +1161,9 @@ void sdram_init(void) /* Do some testing after the init */ if (!in_sdram) { size_prog = omap_sdram_size(); + size_prog = log_2_n_round_down(size_prog); + size_prog = (1 << size_prog); + size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ -- cgit v0.10.2 From e843d0f7ee1b67500d5cbbb20320df17ecbdf32c Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Thu, 17 May 2012 00:12:09 +0000 Subject: ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro. OMAP5 evm board has 2GB of memory. So correct the macro to take in to account of the full dram size. Signed-off-by: R Sricharan diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e3f55d2..2961c6b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -40,7 +40,7 @@ #define OMAP54XX_L4_PER_BASE 0x48000000 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END -- cgit v0.10.2 From d5b069ecb4199f1672fd98041bd0037bd33d2f0f Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Fri, 18 May 2012 13:21:59 +0000 Subject: DaVinci: fix ddr2 vtp i/o calibration Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 5b39484..0e45426 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -523,9 +523,8 @@ VTPLock: ldr r6, DDRVTPR ldr r7, [r6] - and r7, r7, $0x1f - and r8, r7, $0x3e0 - orr r8, r7, r8 + mov r8, r7, LSL #32-10 + mov r8, r8, LSR #32-10 /* grab low 10 bits */ ldr r7, VTP_RECAL orr r8, r7, r8 ldr r7, VTP_EN @@ -644,7 +643,7 @@ VTP_LOCK_COUNT: VTP_MASK: .word 0xffffdfff VTP_RECAL: - .word 0x40000 + .word 0x08000 VTP_EN: .word 0x02000 CFGTEST: -- cgit v0.10.2 From 168a5acb81a8d92a7effcb2727aaa89367b97e05 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 06:46:29 +0000 Subject: Revert "I2C: OMAP: detect more devices when probing an i2c bus" This reverts commit 0e57968a215d1b9d271f3fa5bebeddeaea0c8075. The short version of the original commit is that some i2c devices cannot be probed via read as they NAK the first cycle, so try and probe via a write that we abort before it writes to the device. This however is not allowed by the TRM for any of these parts. The section on I2C_CON (table 17-35 I2C_CON for am/dm37x for example) says you must not change the register while STT has been set. On these parts, the unpredictable behavior that the chip exhibits is not problematic. On OMAP4 however it results in the chip being in a bad state: Panda # i2c probe Valid chip addresses: 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Panda # i2c md 50 0 timed out in wait_for_pin: I2C_STAT=0 I2C read: I/O error Error reading the chip. We must revert the original behavior to bring probe back into line with the TRM. Cc: Nick Thompson Cc: Heiko Schocher Signed-off-by: Tom Rini Acked-by: Heiko Schocher diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a7ffd95..3a50417 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -255,23 +255,43 @@ int i2c_probe(uchar chip) /* wait until bus not busy */ wait_for_bb(); - /* try to write one byte */ + /* try to read one byte */ writew(1, &i2c_base->cnt); /* set slave address */ writew(chip, &i2c_base->sa); /* stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); - - status = wait_for_pin(); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); - /* check for ACK (!NAK) */ - if (!(status & I2C_STAT_NACK)) - res = 0; - - /* abort transfer (force idle state) */ - writew(0, &i2c_base->con); + while (1) { + status = wait_for_pin(); + if (status == 0 || status & I2C_STAT_AL) { + res = 1; + goto probe_exit; + } + if (status & I2C_STAT_NACK) { + res = 1; + writew(0xff, &i2c_base->stat); + writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); + wait_for_bb (); + break; + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + if (status & I2C_STAT_RRDY) { + res = 0; +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_OMAP44XX) + readb(&i2c_base->data); +#else + readw(&i2c_base->data); +#endif + writew(I2C_STAT_RRDY, &i2c_base->stat); + } + } +probe_exit: flush_fifo(); /* don't allow any more data in... we don't want it. */ writew(0, &i2c_base->cnt); -- cgit v0.10.2 From fe4f97b98faccc142fe6e1668ba7ff945fcf3994 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 06:46:30 +0000 Subject: am335x: Correct i2c sysc offset Signed-off-by: Tom Rini Acked-by: Heiko Schocher diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 366e2bb..dcb294c 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -34,9 +34,9 @@ struct i2c { unsigned short revnb_lo; /* 0x00 */ unsigned short res1; unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; + unsigned short res2[5]; + unsigned short sysc; /* 0x10 */ + unsigned short res3[9]; unsigned short irqstatus_raw; /* 0x24 */ unsigned short res4; unsigned short stat; /* 0x28 */ -- cgit v0.10.2 From d88bc0425b333ba5baa185b4f8797be444a03f44 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 06:46:31 +0000 Subject: am33xx: Fill in more cm_wkuppll / cm_perpll Signed-off-by: Tom Rini Acked-by: Heiko Schocher diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 8760cc0..5a6534e 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -62,7 +62,7 @@ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ unsigned int wkctrlclkctrl; /* offset 0x04 */ - unsigned int resv1[1]; + unsigned int wkgpio0clkctrl; /* offset 0x08 */ unsigned int wkl4wkclkctrl; /* offset 0x0c */ unsigned int resv2[4]; unsigned int idlestdpllmpu; /* offset 0x20 */ @@ -111,34 +111,54 @@ struct cm_perpll { unsigned int l3clkstctrl; /* offset 0x0c */ unsigned int resv1; unsigned int cpgmac0clkctrl; /* offset 0x14 */ - unsigned int resv2[4]; + unsigned int lcdclkctrl; /* offset 0x18 */ + unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int resv2; + unsigned int tptc0clkctrl; /* offset 0x24 */ unsigned int emifclkctrl; /* offset 0x28 */ unsigned int ocmcramclkctrl; /* offset 0x2c */ unsigned int gpmcclkctrl; /* offset 0x30 */ - unsigned int resv3[2]; + unsigned int mcasp0clkctrl; /* offset 0x34 */ + unsigned int uart5clkctrl; /* offset 0x38 */ unsigned int mmc0clkctrl; /* offset 0x3C */ unsigned int elmclkctrl; /* offset 0x40 */ unsigned int i2c2clkctrl; /* offset 0x44 */ unsigned int i2c1clkctrl; /* offset 0x48 */ unsigned int spi0clkctrl; /* offset 0x4C */ unsigned int spi1clkctrl; /* offset 0x50 */ - unsigned int resv4[3]; + unsigned int resv3[3]; unsigned int l4lsclkctrl; /* offset 0x60 */ unsigned int l4fwclkctrl; /* offset 0x64 */ - unsigned int resv5[6]; + unsigned int mcasp1clkctrl; /* offset 0x68 */ + unsigned int uart1clkctrl; /* offset 0x6C */ + unsigned int uart2clkctrl; /* offset 0x70 */ + unsigned int uart3clkctrl; /* offset 0x74 */ + unsigned int uart4clkctrl; /* offset 0x78 */ + unsigned int timer7clkctrl; /* offset 0x7C */ unsigned int timer2clkctrl; /* offset 0x80 */ - unsigned int resv6[11]; + unsigned int timer3clkctrl; /* offset 0x84 */ + unsigned int timer4clkctrl; /* offset 0x88 */ + unsigned int resv4[8]; + unsigned int gpio1clkctrl; /* offset 0xAC */ unsigned int gpio2clkctrl; /* offset 0xB0 */ - unsigned int resv7[7]; + unsigned int gpio3clkctrl; /* offset 0xB4 */ + unsigned int resv5; + unsigned int tpccclkctrl; /* offset 0xBC */ + unsigned int dcan0clkctrl; /* offset 0xC0 */ + unsigned int dcan1clkctrl; /* offset 0xC4 */ + unsigned int resv6[2]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv8[2]; + unsigned int resv7[2]; unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv9[14]; + unsigned int resv8[4]; + unsigned int mmc1clkctrl; /* offset 0xF4 */ + unsigned int mmc2clkctrl; /* offset 0xF8 */ + unsigned int resv9[8]; unsigned int l4hsclkstctrl; /* offset 0x11C */ unsigned int l4hsclkctrl; /* offset 0x120 */ unsigned int resv10[8]; - unsigned int cpswclkctrl; /* offset 0x144 */ + unsigned int cpswclkstctrl; /* offset 0x144 */ }; /* Encapsulating Display pll registers */ -- cgit v0.10.2 From 65c206b68896e3486c4d05c0a0b570513ba0291f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 06:46:32 +0000 Subject: am33xx: Fix i2c sampling rate typo Signed-off-by: Tom Rini Acked-by: Heiko Schocher diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index dcb294c..32b2258 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -76,6 +76,6 @@ struct i2c { }; #define I2C_IP_CLK 48000000 -#define I2C_INTERNAL_SAMLPING_CLK 12000000 +#define I2C_INTERNAL_SAMPLING_CLK 12000000 #endif /* _I2C_H_ */ -- cgit v0.10.2 From 402d17fc4c406fe49a7b2d94aee640f389a68738 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 06:46:33 +0000 Subject: omap24xx_i2c: Add AM33XX support The same places that check for CONFIG_OMAP44XX need to check for CONFIG_AM33XX as we share the same i2c block. Cc: Heiko Schocher Signed-off-by: Tom Rini Acked-by: Heiko Schocher diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 3a50417..81193b0 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -202,7 +202,7 @@ static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) } if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) *value = readb(&i2c_base->data); #else *value = readw(&i2c_base->data); @@ -232,7 +232,7 @@ static void flush_fifo(void) stat = readw(&i2c_base->stat); if (stat == I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) readb(&i2c_base->data); #else readw(&i2c_base->data); @@ -282,7 +282,7 @@ int i2c_probe(uchar chip) if (status & I2C_STAT_RRDY) { res = 0; #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) readb(&i2c_base->data); #else readw(&i2c_base->data); -- cgit v0.10.2 From 1dd07fe8e9ba4e0ae449faf871bb81ebd36c62a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 11:20:44 +0000 Subject: OMAP3 Beagle: Set BOOTDELAY to 3 We change the bootdelay to give users a little bit longer to break in if needed. Signed-off-by: Tom Rini diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 268215c..c10ac82 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -213,7 +213,7 @@ /* partition */ /* Environment information */ -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ -- cgit v0.10.2 From 2e4b8b5cd282515d496f5a5b30f5a9c037b70fce Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 11:20:45 +0000 Subject: omap3evm: Set BOOTDELAY to 3 We reduce the bootdelay from 10s to 3s to give users a short but usable window to interrupt the boot process if needed. Signed-off-by: Tom Rini diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 1fcb7af..fb3bf34 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -134,7 +134,7 @@ * Default environment * ----------------------------------------------------------------------------- */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ -- cgit v0.10.2 From 776bebb75875dee80401ce098d06d7728c1e4a89 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 11:20:46 +0000 Subject: omap3_beagle: Add CONFIG_CMD_ASKENV Signed-off-by: Tom Rini diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c10ac82..657780e 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -146,6 +146,8 @@ /* commands to include */ #include +#define CONFIG_CMD_ASKENV + #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ -- cgit v0.10.2 From 1ee6d31ff4a0cff3176f722ead734f31e58d0c26 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 21 May 2012 11:20:47 +0000 Subject: omap3evm: Add CONFIG_CMD_ASKENV Signed-off-by: Tom Rini diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index fb3bf34..632a13f 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -42,6 +42,8 @@ */ #include +#define CONFIG_CMD_ASKENV + #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 -- cgit v0.10.2 From 851bebd68cfc0cd3f638b3afbd3325a3b32df341 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:21 +0000 Subject: OMAP5: Adding correct Control id code for OMAP5430 Control id code for omap5430 ES1.0 is hard coded with a wrong value. This patch corrects the value Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 2961c6b..3d4d08c 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -56,7 +56,7 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204) /* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B94202F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) -- cgit v0.10.2 From 0a0bf7b217660589b846bd5d6fcebc1deef20971 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:22 +0000 Subject: OMAP5: ADD chip detection for OMAP5432 SOC This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d01cc81..e2f76a1 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -154,7 +154,15 @@ void init_omap_revision(void) switch (rev) { case MIDR_CORTEX_A15_R0P0: - *omap_si_rev = OMAP5430_ES1_0; + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + default: + *omap_si_rev = OMAP5432_ES1_0; + break; + } break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 3d4d08c..94b6f3a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -56,7 +56,8 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204) /* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 459b6b1..4e95eee 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -136,4 +136,5 @@ static inline u32 omap_revision(void) /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 +#define OMAP5432_ES1_0 0x54320100 #endif /* _OMAP_COMMON_H_ */ -- cgit v0.10.2 From eb4e18e89eec8d63f064cb5ec597ba9387fe4987 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:23 +0000 Subject: OMAP5: Configure the io settings for omap5432 uevm board This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index e2f76a1..df0b760 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -52,6 +52,81 @@ static struct gpio_bank gpio_bank_54xx[6] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; #ifdef CONFIG_SPL_BUILD +/* LPDDR2 specific IO settings */ +static void io_settings_lpddr2(void) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_1)); + writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, + &(ioregs_base->control_ddrio_2)); +} + +/* DDR3 specific IO settings */ +static void io_settings_ddr3(void) +{ + u32 io_settings = 0; + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddr3ch1_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch1_1)); + + writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddr3ch2_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch2_1)); + + writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_2)); + + /* omap5432 does not use lpddr2 */ + writel(0x0, &(ioregs_base->control_lpddr2ch1_0)); + writel(0x0, &(ioregs_base->control_lpddr2ch1_1)); + + writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); + + /* Disable DLL select */ + io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config)) + & 0xFFEFFFFF); + writel(io_settings, + &(ioregs_base->control_port_emif1_sdram_config)); + + io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config)) + & 0xFFEFFFFF); + writel(io_settings, + &(ioregs_base->control_port_emif2_sdram_config)); +} + /* * Some tuning of IOs for optimal power and performance */ @@ -115,25 +190,10 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); - /* LPDDR2 io settings */ - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_1)); - writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - &(ioregs_base->control_ddrio_0)); - writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - &(ioregs_base->control_ddrio_1)); - writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - &(ioregs_base->control_ddrio_2)); + if (omap_revision() <= OMAP5430_ES1_0) + io_settings_lpddr2(); + else + io_settings_ddr3(); /* Efuse settings */ writel(EFUSE_1, &(ioregs_base->control_efuse_1)); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 94b6f3a..7f05cb5 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -179,7 +179,14 @@ struct omap_sys_ctrl_regs { u32 control_srcomp_east_side; /*0x4A002E7C*/ u32 control_srcomp_west_side; /*0x4A002E80*/ u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3680198]; + u32 pad4[3679394]; + u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ + u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ + u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ + u32 pad5[10]; + u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ + u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ + u32 pad6[789]; u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ u32 control_padconf_mode; /* 0x4AE0CDA8 */ @@ -234,6 +241,12 @@ struct omap_sys_ctrl_regs { #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100 -- cgit v0.10.2 From 43037d76316db1a53be16a4c1ed97203257fa4ee Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:24 +0000 Subject: OMAP5: ADD precalculated timings for ddr3 Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b538960..239ad2b 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -92,6 +92,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { /* Dummy registers for OMAP44xx */ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 368b78b..817f933 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -86,6 +86,29 @@ const struct emif_regs emif_regs_266_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 }; +const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020420A, + .emif_ddr_phy_ctlr_1 = 0x0024420A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000077 }; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x01004010, + 0x00001004, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x0, + 0x0, + 0x0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { - *regs = &emif_regs_532_mhz_2cs; + if (omap_revision() == OMAP5432_ES1_0) + *regs = &emif_regs_ddr3_532_mhz_1cs; + else + *regs = &emif_regs_532_mhz_2cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad2..5d2649e 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -650,6 +650,7 @@ struct dmm_lisa_map_regs { }; extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define CS0 0 #define CS1 1 @@ -1073,6 +1074,10 @@ struct emif_regs { u32 emif_ddr_ext_phy_ctrl_3; u32 emif_ddr_ext_phy_ctrl_4; u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 emif_rd_wr_exec_thresh; }; /* assert macros */ -- cgit v0.10.2 From 784ab7c545d25288a82216d18e2b0ca3beae470b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:25 +0000 Subject: OMAP5: EMIF: Add support for DDR3 device In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 389feda..846511d 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -190,7 +190,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if (omap_revision() == OMAP5430_ES1_0) { + if (omap_revision() >= OMAP5430_ES1_0) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -202,6 +202,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } +static void ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* keep sdram in self-refresh */ + writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + __udelay(130); + + /* + * Set invert_clkout (if activated)--DDR_PHYCTRL_1 + * Invert clock adds an additional half cycle delay on the command + * interface. The additional half cycle, is usually meant to enable + * leveling in the situation that DQS is later than CK on the board.It + * also helps provide some additional margin for leveling. + */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + __udelay(130); + + writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ + config_data_eye_leveling_samples(base); + + /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Launch Incremental leveling */ + writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); +} + +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + /* + * Set SDRAM_CONFIG and PHY control registers to locked frequency + * and RL =7. As the default values of the Mode Registers are not + * defined, contents of mode Registers must be fully initialized. + * H/W takes care of this initialization + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } + + /* enable leveling */ + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + + ddr3_leveling(base, regs); +} + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) @@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!in_sdram) - lpddr2_init(base, regs); + if (!in_sdram) { + if (omap_revision() != OMAP5432_ES1_0) + lpddr2_init(base, regs); + else + ddr3_init(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 187e938..2c34e48 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -118,6 +118,11 @@ void do_io_settings(void) } #endif +/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + void init_omap_revision(void) { /* diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index df0b760..d0c3ff7 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -203,6 +204,20 @@ void do_io_settings(void) } #endif +void config_data_eye_leveling_samples(u32 emif_base) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ + if (emif_base == EMIF1_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + else if (emif_base == EMIF2_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); +} + void init_omap_revision(void) { /* diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5d2649e..c2ad877 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -471,6 +471,49 @@ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) +/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 + /* DMM */ #define DMM_BASE 0x4E000040 @@ -1104,5 +1147,5 @@ extern u32 *const T_den; extern u32 *const emif_sizes; #endif - +void config_data_eye_leveling_samples(u32 emif_base); #endif -- cgit v0.10.2 From 753bae8c5dd4ba92a39b06ea9a551be962053f93 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:26 +0000 Subject: OMAP5: DPLL core lock for OMAP5432 No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 10d286a..b1fd277 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -299,8 +299,12 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, - "core"); + if (omap_revision() != OMAP5432_ES1_0) + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + DPLL_NO_LOCK, "core"); + else + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + DPLL_LOCK, "core"); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 846511d..23cf619 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1232,6 +1232,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; + u32 omap_rev = omap_revision(); debug(">>sdram_init()\n"); @@ -1241,9 +1242,12 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!in_sdram) - bypass_dpll(&prcm->cm_clkmode_dpll_core); - + if (!in_sdram) { + if (omap_rev != OMAP5432_ES1_0) + bypass_dpll(&prcm->cm_clkmode_dpll_core); + else + writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); + } do_sdram_init(EMIF1_BASE); do_sdram_init(EMIF2_BASE); @@ -1255,7 +1259,8 @@ void sdram_init(void) } /* for the shadow registers to take effect */ - freq_update_core(); + if (omap_rev != OMAP5432_ES1_0) + freq_update_core(); /* Do some testing after the init */ if (!in_sdram) { diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 617729c..be20fc0 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -525,6 +525,11 @@ struct omap4_scrm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index f32cf3e..409e0e3 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -490,6 +490,11 @@ struct omap5_prcm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -- cgit v0.10.2 From 7fd5b9bfe4a66a0eec232ab36ddafdd823e263c2 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 22 May 2012 00:03:27 +0000 Subject: OMAP5: Change voltages for omap5432 Change voltages for OMAP5432 Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index 1a59f26..65dc5c7 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void) */ void scale_vcores(void) { - u32 volt; + u32 volt_core, volt_mpu, volt_mm; omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); /* Palmas settings */ - volt = VDD_CORE; - do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); - - volt = VDD_MPU; - do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - - volt = VDD_MM; - do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - + if (omap_revision() != OMAP5432_ES1_0) { + volt_core = VDD_CORE; + volt_mpu = VDD_MPU; + volt_mm = VDD_MM; + } else { + volt_core = VDD_CORE_5432; + volt_mpu = VDD_MPU_5432; + volt_mm = VDD_MM_5432; + } + + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); + + if (omap_revision() == OMAP5432_ES1_0) { + /* Configure LDO SRAM "magic" bits */ + writel(2, &prcm->prm_sldo_core_setup); + writel(2, &prcm->prm_sldo_mpu_setup); + writel(2, &prcm->prm_sldo_mm_setup); + } } u32 get_offset_code(u32 volt_offset) diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 409e0e3..5f1a7aa 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -480,6 +480,13 @@ struct omap5_prcm_regs { u32 pad217[4]; u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ + u32 pad218[2]; + u32 prm_sldo_core_setup; /* 4ae07bc4 */ + u32 prm_sldo_core_ctrl; /* 4ae07bc8 */ + u32 prm_sldo_mpu_setup; /* 4ae07bcc */ + u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */ + u32 prm_sldo_mm_setup; /* 4ae07bd4 */ + u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */ }; /* DPLL register offsets */ @@ -646,6 +653,9 @@ struct omap5_prcm_regs { #define VDD_MPU 1000 #define VDD_MM 1000 #define VDD_CORE 1040 +#define VDD_MPU_5432 1150 +#define VDD_MM_5432 1150 +#define VDD_CORE_5432 1150 /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 -- cgit v0.10.2 From e423a8f76d8dac55d067fd4c0eea8f18fb8929dc Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Thu, 24 May 2012 00:30:25 +0000 Subject: ARM: OMAP4: Correct the lpddr2 io settings register value. To meet certain timing requirements on the lpddr2 cmd and data phy interfaces ,lpddr iopads have to be configured as differential buffers and a Vref has to be internally generated and provided to these buffers. Correcting the above settings here. Signed-off-by: R Sricharan diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 47c5883..03bd923 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -112,7 +112,7 @@ #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C #define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 -- cgit v0.10.2 From 390cdcda1b1d07eb054120e9bdfc4374b6ef8f6e Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Thu, 24 May 2012 04:01:21 +0000 Subject: cm-t35: reduce the environment size Reduce the environment size (128KB => 16KB) to improve the environment operations time (e.g. reading, ecc calculation). Also, remove the unused CONFIG_SYS_ENV_SECT_SIZE. Signed-off-by: Igor Grinberg diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 782d28c..b97e887 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -77,7 +77,7 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ /* Sector */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) @@ -315,7 +315,6 @@ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -- cgit v0.10.2 From 6f3b300c0a324725e468f496f89372388ff5ee66 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Thu, 24 May 2012 04:01:22 +0000 Subject: cm-t35: fix incorrect BOARD_REV_SIZE value Non-legacy layouts have an extended revision field, but only the first 2 bytes are the PCB revision. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c index dfa171d..6053811 100644 --- a/board/cm_t35/eeprom.c +++ b/board/cm_t35/eeprom.c @@ -27,8 +27,7 @@ #define BOARD_SERIAL_OFFSET_LEGACY 8 #define BOARD_REV_OFFSET 0 #define BOARD_REV_OFFSET_LEGACY 6 -#define BOARD_REV_SIZE 4 -#define BOARD_REV_SIZE_LEGACY 2 +#define BOARD_REV_SIZE 2 #define MAC_ADDR_OFFSET 4 #define MAC_ADDR_OFFSET_LEGACY 0 @@ -107,17 +106,14 @@ u32 get_board_rev(void) { u32 rev = 0; uint offset = BOARD_REV_OFFSET_LEGACY; - int len = BOARD_REV_SIZE_LEGACY; if (eeprom_setup_layout()) return 0; - if (eeprom_layout != LAYOUT_LEGACY) { + if (eeprom_layout != LAYOUT_LEGACY) offset = BOARD_REV_OFFSET; - len = BOARD_REV_SIZE; - } - if (cm_t3x_eeprom_read(offset, (uchar *)&rev, len)) + if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) return 0; return rev; -- cgit v0.10.2 From 2ef6302f8728d52ee4fb3b169be5dc6becae566f Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Thu, 24 May 2012 04:01:23 +0000 Subject: cm-t35: fix legacy board revision representation Legacy eeprom layout represents the revision number syntactically (i.e. revision 1.00 is written as 0x100). This is inconsistent with the representation in newer layouts, where it is defined semantically (i.e. 0x64). This patch fixes the issue by replacing the syntactic representation with the semantic one. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c index 6053811..4986b23 100644 --- a/board/cm_t35/eeprom.c +++ b/board/cm_t35/eeprom.c @@ -105,6 +105,7 @@ int cm_t3x_eeprom_read_mac_addr(uchar *buf) u32 get_board_rev(void) { u32 rev = 0; + char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; if (eeprom_setup_layout()) @@ -116,5 +117,14 @@ u32 get_board_rev(void) if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) return 0; + /* + * Convert legacy syntactic representation to semantic + * representation. i.e. for rev 1.00: 0x100 --> 0x64 + */ + if (eeprom_layout == LAYOUT_LEGACY) { + sprintf(str, "%x", rev); + rev = simple_strtoul(str, NULL, 10); + } + return rev; }; -- cgit v0.10.2 From 8c318eb3a0db27ea7f0ae3e7be42f5b4b375cf3b Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Thu, 24 May 2012 04:01:24 +0000 Subject: cm-t35: print PCB revision information Buffer the PCB revision to avoid multiple eeprom accesses for the same data and print it as a part of board information. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg Signed-off-by: Tom Rini diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 89e6b08..700c184 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -99,6 +99,39 @@ int board_init(void) return 0; } +static u32 cm_t3x_rev; + +/* + * Routine: get_board_rev + * Description: read system revision + */ +u32 get_board_rev(void) +{ + if (!cm_t3x_rev) + cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); + + return cm_t3x_rev; +}; + +/* + * Routine: misc_init_r + * Description: display die ID + */ +int misc_init_r(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); + dieid_num_r(); + + return 0; +} + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c index 4986b23..b0af103 100644 --- a/board/cm_t35/eeprom.c +++ b/board/cm_t35/eeprom.c @@ -99,10 +99,10 @@ int cm_t3x_eeprom_read_mac_addr(uchar *buf) } /* - * Routine: get_board_rev - * Description: read system revision + * Routine: cm_t3x_eeprom_get_board_rev + * Description: read system revision from eeprom */ -u32 get_board_rev(void) +u32 cm_t3x_eeprom_get_board_rev(void) { u32 rev = 0; char str[5]; /* Legacy representation can contain at most 4 digits */ diff --git a/board/cm_t35/eeprom.h b/board/cm_t35/eeprom.h index ec772c6..38824d1 100644 --- a/board/cm_t35/eeprom.h +++ b/board/cm_t35/eeprom.h @@ -23,11 +23,16 @@ #ifdef CONFIG_DRIVER_OMAP34XX_I2C int cm_t3x_eeprom_read_mac_addr(uchar *buf); +u32 cm_t3x_eeprom_get_board_rev(void); #else static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) { return 1; } +static inline u32 cm_t3x_eeprom_get_board_rev(void) +{ + return 0; +} #endif #endif -- cgit v0.10.2 From 7775831dd39ba3cadefd3158ee84aa619873b759 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 26 Apr 2012 15:48:32 +0900 Subject: Exynos: fix cpuinfo and cpu detecting Since Exynos architecture have new SoCs, need to fix cpuinfo correctly. Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park Tested-by: Jaehoon Chung Cc: Chander Kashyap diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index 527f32d..1642733 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -48,8 +48,9 @@ int print_cpuinfo(void) { char buf[32]; - printf("CPU:\tS5P%X@%sMHz\n", - s5p_cpu_id, strmhz(buf, get_arm_clk())); + printf("CPU:\t%s%X@%sMHz\n", + s5p_get_cpu_name(), s5p_cpu_id, + strmhz(buf, get_arm_clk())); return 0; } diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..b1e22f2 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -24,6 +24,7 @@ #define DEVICE_NOT_AVAILABLE 0 +#define EXYNOS_CPU_NAME "Exynos" #define EXYNOS4_ADDR_BASE 0x10000000 /* EXYNOS4 */ @@ -93,29 +94,42 @@ static inline int s5p_get_cpu_rev(void) static inline void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS4_PRO_ID); - s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); - - /* - * 0xC200: EXYNOS4210 EVT0 - * 0xC210: EXYNOS4210 EVT1 - */ - if (s5p_cpu_id == 0xC200) { - s5p_cpu_id |= 0x10; + unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; + + switch (pro_id) { + case 0x200: + /* Exynos4210 EVT0 */ + s5p_cpu_id = 0x4210; s5p_cpu_rev = 0; - } else if (s5p_cpu_id == 0xC210) { - s5p_cpu_rev = 1; + break; + case 0x210: + /* Exynos4210 EVT1 */ + s5p_cpu_id = 0x4210; + break; + case 0x412: + /* Exynos4412 */ + s5p_cpu_id = 0x4412; + break; + case 0x520: + /* Exynos5250 */ + s5p_cpu_id = 0x5250; + break; } } +static inline char *s5p_get_cpu_name(void) +{ + return EXYNOS_CPU_NAME; +} + #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ - return s5p_cpu_id == id ? 1 : 0; \ + return (s5p_cpu_id >> 12) == id; \ } -IS_SAMSUNG_TYPE(exynos4, 0xc210) -IS_SAMSUNG_TYPE(exynos5, 0xc520) +IS_SAMSUNG_TYPE(exynos4, 0x4) +IS_SAMSUNG_TYPE(exynos5, 0x5) #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index 510ead4..2362b99 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -23,6 +23,7 @@ #ifndef _S5PC1XX_CPU_H #define _S5PC1XX_CPU_H +#define S5P_CPU_NAME "S5P" #define S5PC1XX_ADDR_BASE 0xE0000000 /* S5PC100 */ @@ -71,6 +72,11 @@ static inline void s5p_set_cpu_id(void) s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); } +static inline char *s5p_get_cpu_name(void) +{ + return S5P_CPU_NAME; +} + #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ -- cgit v0.10.2 From c20545691a3861ece0319cf5ad257714f1b502fd Mon Sep 17 00:00:00 2001 From: Donghwa Lee Date: Wed, 25 Apr 2012 13:29:39 +0000 Subject: TRATS: initialize panel_info data structure in board file panel_info data structure is gloable variable, so, I have initialized it in board file. If it is initialized in init_panel_info() like existing, it can't be used in drv_lcd_init() in common/lcd.c because init_panel_info() is called after drv_lcd_init(). Signed-off-by: Donghwa Lee Signed-off-by: Kyungmin Park Acked-by: Anatolij Gustschin Signed-off-by: Minkyu Kang diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a0eec75..08ca63d 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -461,42 +461,44 @@ static int mipi_power(void) return 0; } +vidinfo_t panel_info = { + .vl_freq = 60, + .vl_col = 720, + .vl_row = 1280, + .vl_width = 720, + .vl_height = 1280, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_LOW, + .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ + + /* s6e8ax0 Panel infomation */ + .vl_hspw = 5, + .vl_hbpd = 10, + .vl_hfpd = 10, + + .vl_vspw = 2, + .vl_vbpd = 1, + .vl_vfpd = 13, + .vl_cmd_allow_len = 0xf, + + .win_id = 3, + .cfg_gpio = NULL, + .backlight_on = NULL, + .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ + .reset_lcd = lcd_reset, + .dual_lcd_enabled = 0, + + .init_delay = 0, + .power_on_delay = 0, + .reset_delay = 0, + .interface_mode = FIMD_RGB_INTERFACE, + .mipi_enabled = 1, +}; + void init_panel_info(vidinfo_t *vid) { - vid->vl_freq = 60; - vid->vl_col = 720; - vid->vl_row = 1280; - vid->vl_width = 720; - vid->vl_height = 1280; - vid->vl_clkp = CONFIG_SYS_HIGH; - vid->vl_hsp = CONFIG_SYS_LOW; - vid->vl_vsp = CONFIG_SYS_LOW; - vid->vl_dp = CONFIG_SYS_LOW; - - vid->vl_bpix = 5; - vid->dual_lcd_enabled = 0; - - /* s6e8ax0 Panel */ - vid->vl_hspw = 5; - vid->vl_hbpd = 10; - vid->vl_hfpd = 10; - - vid->vl_vspw = 2; - vid->vl_vbpd = 1; - vid->vl_vfpd = 13; - vid->vl_cmd_allow_len = 0xf; - - vid->win_id = 3; - vid->cfg_gpio = NULL; - vid->backlight_on = NULL; - vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */ - vid->reset_lcd = lcd_reset; - - vid->init_delay = 0; - vid->power_on_delay = 0; - vid->reset_delay = 0; - vid->interface_mode = FIMD_RGB_INTERFACE; - vid->mipi_enabled = 1; vid->logo_on = 1, vid->resolution = HD_RESOLUTION, vid->rgb_mode = MODE_RGB_P, diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 92be4ea..49fdfec 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -44,9 +44,6 @@ short console_row; static unsigned int panel_width, panel_height; -/* LCD Panel data */ -vidinfo_t panel_info; - static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) { unsigned long palette_size; -- cgit v0.10.2 From a0f5b5a3a28e5ba82515e58bf6a2209f6b7cb684 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Wed, 25 Apr 2012 23:30:18 +0000 Subject: misc:pmic:trats: Correct procedure of enabling/disabling USB regulators In the MAX8997, LDO regulators needs to preserve previously set voltage values. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 08ca63d..a8b2b11 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -220,6 +220,7 @@ int board_mmc_init(bd_t *bis) static int s5pc210_phy_control(int on) { int ret = 0; + u32 val = 0; struct pmic *p = get_pmic(); if (pmic_probe(p)) @@ -228,11 +229,17 @@ static int s5pc210_phy_control(int on) if (on) { ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_ON); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); } else { - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_OFF); } -- cgit v0.10.2 From c5e3710a185d821c3c68ae92f932a7a9956522bd Mon Sep 17 00:00:00 2001 From: Rajeshwari Shinde Date: Wed, 6 Jun 2012 19:54:29 +0000 Subject: EXYNOS5: PINMUX: Added default pinumx settings This patch performs the pinmux configuration in a common file. As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is supported. Signed-off-by: Abhilash Kesavan Signed-off-by: Che-Liang Chiou Signed-off-by: Rajeshwari Shinde Acked-by: Chander Kashyap Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index 90ec2bd..9119961 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o power.o soc.o system.o +COBJS += clock.o power.o soc.o system.o pinmux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c new file mode 100644 index 0000000..d2b7d2c --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2012 Samsung Electronics. + * Abhilash Kesavan + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static void exynos5_uart_config(int peripheral) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + +static int exynos5_mmc_config(int peripheral, int flags) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank, *bank_ext; + int i; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio1->c0; + bank_ext = &gpio1->c1; + break; + case PERIPH_ID_SDMMC1: + bank = &gpio1->c1; + bank_ext = NULL; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio1->c2; + bank_ext = &gpio1->c3; + break; + case PERIPH_ID_SDMMC3: + bank = &gpio1->c3; + bank_ext = NULL; + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + return 0; +} + +static void exynos5_sromc_config(int flags) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + int i; + + /* + * SROM:CS1 and EBI + * + * GPY0[0] SROM_CSn[0] + * GPY0[1] SROM_CSn[1](2) + * GPY0[2] SROM_CSn[2] + * GPY0[3] SROM_CSn[3] + * GPY0[4] EBI_OEn(2) + * GPY0[5] EBI_EEn(2) + * + * GPY1[0] EBI_BEn[0](2) + * GPY1[1] EBI_BEn[1](2) + * GPY1[2] SROM_WAIT(2) + * GPY1[3] EBI_DATA_RDn(2) + */ + s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + + for (i = 0; i < 4; i++) + s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + + /* + * EBI: 8 Addrss Lines + * + * GPY3[0] EBI_ADDR[0](2) + * GPY3[1] EBI_ADDR[1](2) + * GPY3[2] EBI_ADDR[2](2) + * GPY3[3] EBI_ADDR[3](2) + * GPY3[4] EBI_ADDR[4](2) + * GPY3[5] EBI_ADDR[5](2) + * GPY3[6] EBI_ADDR[6](2) + * GPY3[7] EBI_ADDR[7](2) + * + * EBI: 16 Data Lines + * + * GPY5[0] EBI_DATA[0](2) + * GPY5[1] EBI_DATA[1](2) + * GPY5[2] EBI_DATA[2](2) + * GPY5[3] EBI_DATA[3](2) + * GPY5[4] EBI_DATA[4](2) + * GPY5[5] EBI_DATA[5](2) + * GPY5[6] EBI_DATA[6](2) + * GPY5[7] EBI_DATA[7](2) + * + * GPY6[0] EBI_DATA[8](2) + * GPY6[1] EBI_DATA[9](2) + * GPY6[2] EBI_DATA[10](2) + * GPY6[3] EBI_DATA[11](2) + * GPY6[4] EBI_DATA[12](2) + * GPY6[5] EBI_DATA[13](2) + * GPY6[6] EBI_DATA[14](2) + * GPY6[7] EBI_DATA[15](2) + */ + for (i = 0; i < 8; i++) { + s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + } +} + +static int exynos5_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5_mmc_config(peripheral, flags); + case PERIPH_ID_SROMC: + exynos5_sromc_config(flags); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + +int exynos_pinmux_config(int peripheral, int flags) +{ + if (cpu_is_exynos5()) + return exynos5_pinmux_config(peripheral, flags); + else { + debug("pinmux functionality not supported\n"); + return -1; + } +} diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h new file mode 100644 index 0000000..5db25aa --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals requiring clock/pinmux configuration. List will + * grow with support for more devices getting added. + * + */ +enum periph_id { + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_SROMC, + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h new file mode 100644 index 0000000..10ea736 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +#endif -- cgit v0.10.2 From c6baaa670580e1b3137518896d199ddc75503459 Mon Sep 17 00:00:00 2001 From: Rajeshwari Shinde Date: Wed, 6 Jun 2012 19:54:30 +0000 Subject: EXYNOS: SMDK5250: Enable the pinmux setup Use the pinmux configuration function for SMDK5250. Signed-off-by: Abhilash Kesavan Signed-off-by: Rajeshwari Shinde Acked-by: Chander Kashyap Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 32786e2..3b078da 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -26,81 +26,16 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; -struct exynos5_gpio_part1 *gpio1; #ifdef CONFIG_SMC911X -static void smc9115_pre_init(void) +static int smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - int i; - - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); - - for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); - } + int err; /* Ethernet needs data bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK) @@ -112,14 +47,20 @@ static void smc9115_pre_init(void) | SROMC_BC_PMC(0x01); /* Select and configure the SROMC bank */ + err = exynos_pinmux_config(PERIPH_ID_SROMC, + CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT); + if (err) { + debug("SROMC not configured\n"); + return err; + } + s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + return 0; } #endif int board_init(void) { - gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } @@ -168,7 +109,8 @@ void dram_init_banksize(void) int board_eth_init(bd_t *bis) { #ifdef CONFIG_SMC911X - smc9115_pre_init(); + if (smc9115_pre_init()) + return -1; return smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif return 0; @@ -186,31 +128,12 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPC2[0] SD_2_CLK(2) - * GPC2[1] SD_2_CMD(2) - * GPC2[2] SD_2_CDn - * GPC2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPC2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X); + int err; - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; } err = s5p_mmc_init(2, 4); @@ -218,63 +141,40 @@ int board_mmc_init(bd_t *bis) } #endif -static void board_uart_init(void) +static int board_uart_init(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - int i; + int err; - /* - * UART0 GPIOs : GPA0CON[3:0] 0x2222 - * Must set CFG17 switches to select UART0 to use. - */ - for (i = 0; i <= 3; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); + if (err) { + debug("UART0 not configured\n"); + return err; } - /* - * UART1 GPIOs : GPA0CON[5:4] 0x22 - * Must set CFG17 switches to select UART1 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); + if (err) { + debug("UART1 not configured\n"); + return err; } - /* - * UART2 GPIOs : GPA1CON[1:0] 0x22 - * Must set CFG17 switches to select UART2 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 0; i <= 1; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); + if (err) { + debug("UART2 not configured\n"); + return err; } - /* - * UART3 GPIOs : GPA1CON[5:4] 0x22 - * Must set CFG16 switches to select UART3 to use. - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + if (err) { + debug("UART3 not configured\n"); + return err; } - /* - * There's no mux for UART4--it's internal only - */ + return 0; } #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - board_uart_init(); - return 0; + return board_uart_init(); } #endif -- cgit v0.10.2 From 0d952e5d2eef9320338a87007959ce0d80a264e3 Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Wed, 11 Apr 2012 01:18:02 +0000 Subject: i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctly If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct Signed-off-by: Jason Liu CC: Stefano Babic Acked-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h index afaa068..9979651 100644 --- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h @@ -48,8 +48,8 @@ #define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_SLOW (0 << 0) -#define NO_MUX_I 0x3FF -#define NO_PAD_I 0x7FF +#define NO_MUX_I 0 +#define NO_PAD_I 0 enum { MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), -- cgit v0.10.2 From eae08eb2b53ffb87f3342e45ab422d8625659fcd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 05:54:39 +0000 Subject: mx53loco: Fix revision of Dialog boards Original code was assuming that the fuse revision version for all mx53loco boards based on Dialog PMIC was the same, which is not the case. Force the revision of all Dialog-based boards to 0. This fixes a kernel crash when PMIC is accessed in the 2.6.35 kernel for Dialog rev E boards. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d8e027c..cbdcfad 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -75,6 +75,9 @@ u32 get_board_rev(void) int rev = readl(&fuse->gp[6]); + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) + rev = 0; + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } @@ -495,11 +498,6 @@ int print_cpuinfo(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - setup_iomux_i2c(); - if (!power_init()) - clock_1GHz(); - print_cpuinfo(); - setenv("stdout", "serial"); return 0; @@ -511,6 +509,10 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; mxc_set_sata_internal_clock(); + setup_iomux_i2c(); + if (!power_init()) + clock_1GHz(); + print_cpuinfo(); lcd_enable(); diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8b4e008..b63d37d 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_REVISION_TAG -- cgit v0.10.2 From 3f5f200bbe9aee283b88a2647763b1f97abb96ac Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 11 May 2012 14:39:11 +0000 Subject: mx53: Fix mask for SATA reference clock SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c. Fix the mask for these bits. Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fc2406b..64862b3 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -843,7 +843,7 @@ void mxc_set_sata_internal_clock(void) set_usb_phy1_clk(); - writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base); + writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base); } #endif -- cgit v0.10.2 From 2fb563f2f52d3e4c59c8f0c0309ea6a65c558878 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:39:54 +0000 Subject: mx53loco: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Cc: Jason Liu Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile index a6ea939..8bc69a9 100644 --- a/board/freescale/mx53loco/Makefile +++ b/board/freescale/mx53loco/Makefile @@ -24,12 +24,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53loco.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From b4896cd618aaaa63e05c33266997c5b720484305 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:39:55 +0000 Subject: mx53evk: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Cc: Jason Liu Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile index b7f92b3..dcc83e2 100644 --- a/board/freescale/mx53evk/Makefile +++ b/board/freescale/mx53evk/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53evk.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From 5094fbf79b51c66273f4500c8241e845845455f4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:39:56 +0000 Subject: mx53ard: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile index eac4b2a..335af11 100644 --- a/board/freescale/mx53ard/Makefile +++ b/board/freescale/mx53ard/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53ard.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From d0004a687cbba2943cbd26f702b9b4ecf69eaf96 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:39:57 +0000 Subject: mx53smd: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile index ed8e473..8a404c8 100644 --- a/board/freescale/mx53smd/Makefile +++ b/board/freescale/mx53smd/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53smd.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From cf0a8ec227342cce14c477658edead508f8b3209 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:39:58 +0000 Subject: mx51evk: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile index 470588e..224eaa3 100644 --- a/board/freescale/mx51evk/Makefile +++ b/board/freescale/mx51evk/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx51evk.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From 38e984dec66e3542a00381e714586d58733e3d7e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:39:59 +0000 Subject: efikamx: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Cc: Marek Vasut Signed-off-by: Fabio Estevam diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile index fdd188e..bd2174f 100644 --- a/board/efikamx/Makefile +++ b/board/efikamx/Makefile @@ -33,12 +33,11 @@ ifdef CONFIG_CMD_USB COBJS += efikamx-usb.o endif -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From 8c19e8f46536b4edfaaa3e774c4c31f952814c62 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:40:00 +0000 Subject: vision2: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Signed-off-by: Fabio Estevam diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile index 393ad68..1e018b0 100644 --- a/board/ttcontrol/vision2/Makefile +++ b/board/ttcontrol/vision2/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := vision2.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From bd4219b6199a5be2b3087e2cc85c5b3c30df19de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:40:01 +0000 Subject: ima3-mx53: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Signed-off-by: Fabio Estevam diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile index f3b13bc..ab18944 100644 --- a/board/esg/ima3-mx53/Makefile +++ b/board/esg/ima3-mx53/Makefile @@ -25,7 +25,7 @@ LIB = $(obj)lib$(BOARD).o COBJS := ima3-mx53.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) -- cgit v0.10.2 From ef0ed6a48d14448ec3d3fd9d0ed33b783cf1f41a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:40:02 +0000 Subject: mx6qarm2: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Cc: Jason Liu Signed-off-by: Fabio Estevam Acked-by: Jason Liu diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile index 79bc315..6ce4495 100644 --- a/board/freescale/mx6qarm2/Makefile +++ b/board/freescale/mx6qarm2/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx6qarm2.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From 001533eb0ec0197f0888daae41b8bcbe79a371cf Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 29 May 2012 07:40:03 +0000 Subject: mx6qsabrelite: Remove unused SOBJS There is no .S file in this directory, so just remove SOBJS. Cc: Jason Liu Signed-off-by: Fabio Estevam Acked-by: Jason Liu diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile index 53c26e7..cf344e4 100644 --- a/board/freescale/mx6qsabrelite/Makefile +++ b/board/freescale/mx6qsabrelite/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx6qsabrelite.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### -- cgit v0.10.2 From 8b8d81047df5ac005adf4f5ed7db637d6bfb196c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 11 May 2012 05:37:59 +0000 Subject: MX28: Fix a typo in mx28_reg_8 macro The macro mistakenly referred to 32bit struct instead of 8bit one. Signed-off-by: Otavio Salvador Cc: Fabio Estevam Cc: Marek Vasut Acked-by: Marek Vasut diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index 94b512d..d2e1953 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -70,7 +70,7 @@ struct mx28_register_32 { #define mx28_reg_8(name) \ union { \ struct { __mx28_reg_8(name) }; \ - struct mx28_register_32 name##_reg; \ + struct mx28_register_8 name##_reg; \ }; #define mx28_reg_32(name) \ -- cgit v0.10.2 From 212033fc9a6bb10e97712e309fc53c9316acdaa8 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 12 May 2012 13:40:15 +0000 Subject: m28evk: fix board config include guardian macro name Signed-off-by: Otavio Salvador Acked-by: Marek Vasut diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 3abaadc..6cefaa4 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -17,8 +17,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __M28_H__ -#define __M28_H__ +#ifndef __M28EVK_CONFIG_H__ +#define __M28EVK_CONFIG_H__ #include @@ -325,4 +325,4 @@ "fi ; " \ "fi\0" -#endif /* __M28_H__ */ +#endif /* __M28EVK_CONFIG_H__ */ -- cgit v0.10.2 From 3b4efee97c50b5fb85890498034ced32668e0809 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 12 May 2012 13:40:13 +0000 Subject: mx28evk: ensure command definition is in alphabetic order Signed-off-by: Otavio Salvador Acked-by: Fabio Estevam diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 51b172d..8d44380 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -54,11 +54,11 @@ #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO #define CONFIG_CMD_MII #define CONFIG_CMD_MMC -- cgit v0.10.2 From 606de8b6a606823366fb7b59555446cb18fd28ec Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 12 May 2012 13:40:16 +0000 Subject: mx28evk: fix board config include guardian macro name Signed-off-by: Otavio Salvador Acked-by: Fabio Estevam diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 8d44380..640dcb4 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -16,8 +16,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __MX28EVK_CONFIG_H__ +#define __MX28EVK_CONFIG_H__ #include @@ -250,4 +250,4 @@ "run netargs; " \ "dhcp ${uimage}; bootm\0" \ -#endif /* __CONFIG_H */ +#endif /* __MX28EVK_CONFIG_H__ */ -- cgit v0.10.2 From a2277e84036fb22aac44e83a391431539086f110 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Tue, 15 May 2012 10:59:30 +0000 Subject: m28evk: drop duplicated definition of CONFIG_OF_LIBFDT Signed-off-by: Otavio Salvador Cc: Marek Vasut Cc: Stefano Babic Cc: Wolfgang Denk Acked-by: Marek Vasut diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 6cefaa4..156af27 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -43,8 +43,6 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT -#define CONFIG_OF_LIBFDT - /* * SPL */ -- cgit v0.10.2 From be8d6b614f0868fe3b92dff4e00bd9f3458d9e8c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 12 May 2012 13:40:11 +0000 Subject: m28evk: use same notation to alloc the 128kB stack Signed-off-by: Otavio Salvador Acked-by: Wolfgang Denk diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 156af27..a0e90ca 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -86,7 +86,7 @@ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -- cgit v0.10.2 From b29da17494269c7e7f62eccc8ab78651a6c7b3d9 Mon Sep 17 00:00:00 2001 From: Vikram Narayanan Date: Tue, 12 Jun 2012 04:50:33 +0000 Subject: mx6: Avoid writing to read-only bits in imximage.cfg If in case this is valid according to the latest datasheet, ignore this patch. Acked-by: Marek Vasut diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F -- cgit v0.10.2 From 3e5a0f35f1785a65d2269f21a3aaec335140a08c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 7 Jun 2012 08:05:41 +0000 Subject: mx53ard: Remove unused CONFIG_MII_GASKET CONFIG_MII_GASKET is not defined anywhere, so remove it. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index f4512ff..8da381f 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -68,7 +68,6 @@ /* Eth Configs */ #define CONFIG_HAS_ETH1 #define CONFIG_MII -#define CONFIG_MII_GASKET #define CONFIG_DISCOVER_PHY #define CONFIG_CMD_PING -- cgit v0.10.2 From 29ee7f5487b8081d264e91daaa2ae98577cca7aa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Jun 2012 21:53:25 +0000 Subject: imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Signed-off-by: Fabio Estevam diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1728358..acbd670 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -56,7 +56,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX31_PORT2 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -- cgit v0.10.2 From bd6f402b2af061bda27a68e7b7aa8cfc03a2f585 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Jun 2012 21:53:26 +0000 Subject: mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 016864a..ebbd371 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -59,7 +59,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX35_PORT1 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO -- cgit v0.10.2 From b6a5fbf4bfc139d48b91e1e7b3ccbabb37727e80 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Jun 2012 21:53:27 +0000 Subject: mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 8da381f..ffc799c 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -52,7 +52,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX53_PORT2 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* MMC Configs */ #define CONFIG_FSL_ESDHC -- cgit v0.10.2 From 6ce85ad5c76a7d6a9c50c39842d9c5705f98e229 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Jun 2012 21:53:28 +0000 Subject: mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Cc: Jason Liu Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index a5f32e3..8f2c03f 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -55,7 +55,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX53_PORT2 1 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* PMIC Configs */ #define CONFIG_PMIC -- cgit v0.10.2 From fd8223eaa94539b60d6a26e6bdf8f60146431951 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Jun 2012 21:53:29 +0000 Subject: mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Cc: Jason Liu Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index b63d37d..e71148d 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -91,7 +91,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX53_PORT1 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* PMIC Controller */ #define CONFIG_PMIC -- cgit v0.10.2 From 7d778916053aa579155c71e68debb0bde612b139 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Jun 2012 21:53:30 +0000 Subject: mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 0d7086d..1df20fa 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -52,7 +52,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX53_PORT2 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* MMC Configs */ #define CONFIG_FSL_ESDHC -- cgit v0.10.2 From eeacb73b8e0823b400eda5022e56e9f5a59b37a0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 12 May 2012 08:16:46 +0000 Subject: mx28evk: Fix PSWITCH key position Fix the position for PSWITCH key. The good benefit of doing this is that boot time is greatly reduced: from 5 seconds to less then 1 second. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/doc/README.mx28evk b/doc/README.mx28evk index c6c3d37..571dfda 100644 --- a/doc/README.mx28evk +++ b/doc/README.mx28evk @@ -17,7 +17,7 @@ Jumper configuration To boot MX28EVK from an SD card, set the boot mode DIP switches as: * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) - * JTAG PSWITCH RESET: To the left (reset enabled) + * JTAG PSWITCH RESET: To the right (reset disabled) * Battery Source: Down * Wall 5V: Up * VDD 5V: To the left (off) -- cgit v0.10.2 From e3ddc646031551627c4eeae4598f8862251a3f94 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 29 May 2012 19:43:13 +0000 Subject: i.MX28: Add function to adjust memory parameters This function can be overridden at run-time and allows implementors of new boards based on the i.MX28 chip to fine-tune the memory params. It is possible to write into the dram_vals array because when the SPL runs, it is located SRAM. Therefore the location is writable. There is no possibility of these data to be read-only. Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Detlev Zundel Cc: Stefano Babic Cc: Fabio Estevam diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 9fa5d29..e17a4d7 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -82,10 +82,18 @@ uint32_t dram_vals[] = { 0x00000000, 0x00010001 }; +void __mx28_adjust_memory_params(uint32_t *dram_vals) +{ +} +void mx28_adjust_memory_params(uint32_t *dram_vals) + __attribute__((weak, alias("__mx28_adjust_memory_params"))); + void init_m28_200mhz_ddr2(void) { int i; + mx28_adjust_memory_params(dram_vals); + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); } -- cgit v0.10.2 From f69b0653acf5482a94fa1ec9542165914e30e50c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Jun 2012 07:24:56 +0000 Subject: mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register commit acc4959fc1 (Revert "i.MX28: Enable additional DRAM address bits") broke mx28evk boot. Fix it by properly adjusting the HW_DRAM_CTL29 register value. Suggested-by: Marek Vasut Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 6587c45..00cc0cc 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -161,6 +161,20 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), }; +#define HW_DRAM_CTL29 (0x74 >> 2) +#define CS_MAP 0xf +#define COLUMN_SIZE 0x2 +#define ADDR_PINS 0x1 +#define APREBIT 0xa + +#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ + ADDR_PINS << 8 | APREBIT) + +void mx28_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; +} + void board_init_ll(void) { mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); -- cgit v0.10.2 From 5c23712dbdeeaef84ee28a18dc23abd479a95ede Mon Sep 17 00:00:00 2001 From: Michael Langer Date: Thu, 14 Jun 2012 03:44:33 +0000 Subject: i.MX6 USDHC: Use the ESDHC clock The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces support for the i.MX6Q MMC host controller USDHC. MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()). Signed-off-by: Michael Langer CC: Stefano Babic CC: Jason Liu Acked-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/armv7/imx-common/speed.c index 2187e8e..80989c4 100644 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ b/arch/arm/cpu/armv7/imx-common/speed.c @@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_USDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#else gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); #endif +#endif return 0; } -- cgit v0.10.2 From 2feb73666174518e50364f76966af8b291cb6fa7 Mon Sep 17 00:00:00 2001 From: "esw@bus-elektronik.de" Date: Mon, 19 Mar 2012 04:25:59 +0000 Subject: Fix: broken boot message at serial line on AT91SAM9263-EK board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jens Scharsig (BuS Elektronik) Signed-off-by: Andreas Bießmann diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 41ec752..60ff1c0 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -254,6 +254,7 @@ int board_early_init_f(void) (1 << ATMEL_ID_PIOCDE), &pmc->pcer); + at91_seriald_hw_init(); return 0; } @@ -267,7 +268,6 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); #endif -- cgit v0.10.2 From 5e7d0917b644e1768ddfdeb1fa5822dc7c974fa4 Mon Sep 17 00:00:00 2001 From: "esw@bus-elektronik.de" Date: Mon, 19 Mar 2012 05:18:17 +0000 Subject: Fix: AT91SAM9263 nor flash usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix: board doesn't boot from norflash Fix: environment can't write to flash (end address/start address not on sector boundary) Signed-off-by: Jens Scharsig (BuS Elektronik) Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 61a622a..f2163f1 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -33,7 +33,11 @@ */ #include +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH #define CONFIG_SYS_TEXT_BASE 0x21F00000 +#else +#define CONFIG_SYS_TEXT_BASE 0x0000000 +#endif /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ @@ -147,11 +151,11 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) /* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x10000 #define xstr(s) str(s) #define str(s) #s -- cgit v0.10.2 From cc30b7803d3a3237fbcef860b9320e9b4bfbffaf Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 27 Jun 2012 21:58:20 +0000 Subject: Atmel : usb : add EHCI driver for Atmel SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some Atmel SoC support USB EHCI, add the EHCI driver to support it. To enable the USB EHCI, add the following configuration options into board relative configuration file and remove USB OHCI options. #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 Signed-off-by: Bo Shen Acked-by: Marek Vasut Signed-off-by: Andreas Bießmann diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 59c3e57..4547f37 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -36,6 +36,7 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o # echi COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o +COBJS-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o ifdef CONFIG_MPC512X COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o else diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c new file mode 100644 index 0000000..532db22 --- /dev/null +++ b/drivers/usb/host/ehci-atmel.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2012 + * Atmel Semiconductor + * Written-by: Bo Shen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ehci.h" +#include "ehci-core.h" + +/* Enable UTMI PLL time out 500us + * 10 times as datasheet specified + */ +#define EN_UPLL_TIMEOUT 500UL + +int ehci_hcd_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + /* Enable UTMI PLL */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + while (readl(&pmc->sr) & AT91_PMC_LOCKU != AT91_PMC_LOCKU) { + WATCHDOG_RESET(); + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { + printf("ERROR: failed to enable UPLL\n"); + return -1; + } + } + + /* Enable USB Host clock */ + writel(1 << ATMEL_ID_UHPHS, &pmc->pcer); + + hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI; + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return 0; +} + +int ehci_hcd_stop(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + /* Disable USB Host Clock */ + writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr); + + start_time = get_timer(0); + /* Disable UTMI PLL */ + writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr); + while (readl(&pmc->sr) & AT91_PMC_LOCKU == AT91_PMC_LOCKU) { + WATCHDOG_RESET(); + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { + printf("ERROR: failed to stop UPLL\n"); + return -1; + } + } + + return 0; +} -- cgit v0.10.2 From e1edd06594f41a53cbc3344db78b3093ccb84bf3 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 27 Jun 2012 21:24:10 +0000 Subject: AT91: at91sam9m10g45ek : Enable EHCI instead OHCI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable EHCI support instead OHCI Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index f8b3095..1d5fc8f 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -59,17 +59,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR8 @@ -147,13 +136,10 @@ #define CONFIG_RESET_PHY_R /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -- cgit v0.10.2 From 81f40345d1d5c5ba04620873e3ca0bc60b6b2fe0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Thu, 28 Jun 2012 02:50:37 +0000 Subject: ehci-atmel: fix compiler warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 7a101e946cba55e32d3d1265e30456c810046da3 introduced following warning: ---8<--- ehci-atmel.c: In function 'ehci_hcd_init': ehci-atmel.c:49:2: warning: suggest parentheses around comparison in operand of '&' [-Wparentheses] ehci-atmel.c: In function 'ehci_hcd_stop': ehci-atmel.c:79:2: warning: suggest parentheses around comparison in operand of '&' [-Wparentheses] --->8--- This patch fixes it. Signed-off-by: Andreas Bießmann cc: Bo Shen cc: Marek Vasut diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 532db22..15b9b60 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -46,7 +46,7 @@ int ehci_hcd_init(void) start_time = get_timer(0); /* Enable UTMI PLL */ writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); - while (readl(&pmc->sr) & AT91_PMC_LOCKU != AT91_PMC_LOCKU) { + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) { WATCHDOG_RESET(); tmp_time = get_timer(0); if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { @@ -76,7 +76,7 @@ int ehci_hcd_stop(void) start_time = get_timer(0); /* Disable UTMI PLL */ writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr); - while (readl(&pmc->sr) & AT91_PMC_LOCKU == AT91_PMC_LOCKU) { + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) { WATCHDOG_RESET(); tmp_time = get_timer(0); if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { -- cgit v0.10.2 From 2b3b1c668be539d897d2a9352bc8dca54467f425 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Sun, 20 May 2012 15:50:00 +0000 Subject: ATMEL/PIO: Enable new feature of PIO on Atmel device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable new PIO feature supported by Atmel SoC. Using CPU_HAS_PIO3 micro to enable PIO new feature. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf..0483c98 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -66,14 +66,50 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; /* */ +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ + u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ + u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ + u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr; /* 0xE0 Lock Status */ + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE8 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[63]; +#else u32 reserved6[85]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +130,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a026..ac3b322 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -86,7 +86,14 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].asr); +#endif writel(mask, &pio->port[port].pdr); } return 0; @@ -104,12 +111,63 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].bsr); +#endif writel(mask, &pio->port[port].pdr); } return 0; } +#if defined(CPU_HAS_PIO3) +/* + * mux the pin to the "C" internal peripheral role. + */ +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * mux the pin to the "D" internal peripheral role. + */ +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} +#endif + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. @@ -162,13 +220,76 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; - if (is_on) + if (is_on) { +#if defined(CPU_HAS_PIO3) + writel(mask, &pio->port[port].ifscdr); +#endif writel(mask, &pio->port[port].ifer); - else + } else { writel(mask, &pio->port[port].ifdr); + } + } + return 0; +} + +#if defined(CPU_HAS_PIO3) +/* + * enable/disable the debounce filter. + */ +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + if (is_on) { + writel(mask, &pio->port[port].ifscer); + writel(div & PIO_SCDR_DIV, &pio->port[port].scdr); + writel(mask, &pio->port[port].ifer); + } else { + writel(mask, &pio->port[port].ifdr); + } + } + return 0; +} + +/* + * enable/disable the pull-down. + * If pull-up already enabled while calling the function, we disable it. + */ +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].pudr); + if (is_on) + writel(mask, &pio->port[port].ppder); + else + writel(mask, &pio->port[port].ppddr); + } + return 0; +} + +/* + * disable Schmitt trigger + */ +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(readl(&pio->port[port].schmitt) | mask, + &pio->port[port].schmitt); } return 0; } +#endif /* * enable/disable the multi-driver. This is only valid for output and -- cgit v0.10.2 From e139cb31d32a4f39241bfd83bf622a97d08f6c9d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 2 Jul 2012 04:26:58 +0000 Subject: AT91SAM9*: Change kernel address in dataflash to match u-boot's size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On at91sam platforms, u-boot grew larger than the allocated size in dataflash, the layout was: bootstrap 0x00000000 ubootenv 0x00004200 uboot 0x00008400 kernel 0x00042000 fs 0x00252000 u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 = 0x39C00 bytes anymore. Now, the layout is: bootstrap 0x00000000 ubootenv 0x00004200 uboot 0x00008400 kernel 0x00084000 fs 0x00294000 Signed-off-by: Alexandre Belloni Signed-off-by: Andreas Bießmann diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c index 2629c67..9ec054f 100644 --- a/board/atmel/at91sam9260ek/partition.c +++ b/board/atmel/at91sam9260ek/partition.c @@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c index c739b11..51cac77 100644 --- a/board/atmel/at91sam9261ek/partition.c +++ b/board/atmel/at91sam9261ek/partition.c @@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c index 7e1d46f..d48fab7 100644 --- a/board/atmel/at91sam9263ek/partition.c +++ b/board/atmel/at91sam9263ek/partition.c @@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c index 7e1d46f..d48fab7 100644 --- a/board/atmel/at91sam9rlek/partition.c +++ b/board/atmel/at91sam9rlek/partition.c @@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 07b1968..ef25fa5 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -187,7 +187,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -201,7 +201,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -230,6 +230,7 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE /* * Size of malloc() pool diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 6fd0b83..014437b 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -189,7 +189,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -203,7 +203,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -232,6 +232,7 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE /* * Size of malloc() pool diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f2163f1..4309f71 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -318,7 +318,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) "\ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 45f8baf..c5952e9 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -155,7 +155,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) "\ @@ -182,6 +182,7 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE /* * Size of malloc() pool -- cgit v0.10.2 From e29c6d040183cad9aab413f2c22599a09b717197 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:13 +0000 Subject: arm/km: add board type to boards.cfg Some other kirkwood boards from keymile will follow. They will have some small differences, but we want to use the km_kirkwood.h for all to distinguish them. This patch a preparation for this. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/boards.cfg b/boards.cfg index 92050708..7e1241d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -138,8 +138,8 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index ed36124..f639edc 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -42,10 +42,10 @@ /* * Version number information */ -#ifdef CONFIG_KM_DISABLE_PCI +#if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #undef CONFIG_KIRKWOOD_PCIE_INIT -#else +#elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" #endif -- cgit v0.10.2 From f5b5a1c80ede478c44de605e41c41daae5bfcda3 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:14 +0000 Subject: arm/km: add piggy mac adress offset for mgcoge3un On mgcoge3un the piggy mac adress is at offset 3. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h index 797b0df..156821c 100644 --- a/include/configs/mgcoge3un.h +++ b/include/configs/mgcoge3un.h @@ -77,6 +77,7 @@ MVGBE_SET_MII_SPEED_TO_100) #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 /* * PCIe port not used on mgcoge3un -- cgit v0.10.2 From af85f0858808cb1598dd4353def58cf8eec3a83e Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:16 +0000 Subject: arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE This config option sounds like the it is responsible for the update of the environment, but it is the u-boot update handling. Therefore we adapt it to a more apropriate naming. Signed-off-by: Holger Brunck Signed-off-by: Prafulla Wadaskar Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 011f838..20b0c36 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -81,7 +81,7 @@ "boot=bootm ${load_addr_r} - -\0" \ "cramfsloadfdt=true\0" \ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ - CONFIG_KM_DEF_ENV_UPDATE \ + CONFIG_KM_UPDATE_UBOOT \ "" #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -239,7 +239,7 @@ int get_scl(void); "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" #endif /* MTDPARTS_DEFAULT */ -#define CONFIG_KM_DEF_ENV_UPDATE \ +#define CONFIG_KM_UPDATE_UBOOT \ "update=" \ "spi on;sf probe 0;sf erase 0 50000;" \ "sf write ${load_addr_r} 0 ${filesize};" \ -- cgit v0.10.2 From b732632389f09bed3418e270c50cfdaec08cc0b6 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:16 +0000 Subject: arm/km: use ARRAY_SIZE macro Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 9e9940c..c6c9a71 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -410,7 +410,7 @@ const ulong patterns[] = { 0x00000000, 0xFF00FF00, 0x0F0F0F0F, 0xF0F0F0F0}; -const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns); +const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns); const ulong OFFS_PATTERN = 3; const ulong REPEAT_PATTERN = 1000; -- cgit v0.10.2 From e947cbc94e9f7e972e10c59eb87ed145d897f04d Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:17 +0000 Subject: arm/km: fix wrong comment in SDRAM config for mgcoge3un Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg index 2faaf2b..6df2ad7 100644 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -149,7 +149,7 @@ DATA 0xFFD01424 0x0000F17F # DDR Controller Control High DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low # bit3-0 : 0000, required # bit7-4 : 0010, M_ODT assertion 2 cycles after read -# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read +# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read # bit15-12: 0100, internal ODT assertion 4 cycles after read # bit19-16: 1000, internal ODT de-assertion 8 cycles after read # bit31-20: 0 , required -- cgit v0.10.2 From 4b09701b30fbfcb1097ab12a3065d178dd4f2b86 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:18 +0000 Subject: arm/km: change maintainer for mgcoge3un Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp Acked-By: Heiko Schocher cc: Prafulla Wadaskar cc: Gerlando Falauto diff --git a/MAINTAINERS b/MAINTAINERS index 6438e1c..8a524ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -740,6 +740,7 @@ Sergey Lapin Valentin Longchamp km_kirkwood ARM926EJS (Kirkwood SoC) + mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC) Nishanth Menon @@ -850,7 +851,6 @@ Heiko Schocher enbw_cmc ARM926EJS (AM1808 SoC) magnesium i.MX27 - mgcoge3un ARM926EJS (Kirkwood SoC) Michael Schwingen -- cgit v0.10.2 From be67190e48b0f5f57f05104ee1e01d285cc96844 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 25 May 2012 01:57:19 +0000 Subject: arm/km: remove CONFIG_RESET_PHY_R This is already defined in the generic kirkwood header. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 20b0c36..6423a07 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -164,7 +164,6 @@ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */ /* * UBI related stuff -- cgit v0.10.2 From 002ec08d6d4e6bc32ac8f5d35ea4fbbc1f9138ab Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 25 May 2012 01:57:20 +0000 Subject: arm/km: enable mii cmd This is useful to debug the switch initialization Signed-off-by: Valentin Longchamp Signed-off-by: Holger Brunck cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 6423a07..43a0efb 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -159,6 +159,7 @@ */ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_CMD_MII /* to debug mdio phy config */ #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -- cgit v0.10.2 From a0fb94f9ed865ff8073b4d493918cb78411de2b1 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 25 May 2012 01:57:21 +0000 Subject: km_arm: use filesize for erase in update command We used to have an arbitrary value, which can be a problem if we have a u-boot image that is bigger than this value. This patch is dependant on the whole km/arm series and will be included in the v3 of the series if there is one. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 43a0efb..4a0b80e 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -241,7 +241,7 @@ int get_scl(void); #define CONFIG_KM_UPDATE_UBOOT \ "update=" \ - "spi on;sf probe 0;sf erase 0 50000;" \ + "spi on;sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};" \ "spi off\0" -- cgit v0.10.2 From 8f5d7a03986ac357f95c1131074e2abaa9e3fd22 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 1 Jun 2012 01:30:59 +0000 Subject: kirkwood: add save functionality kirkwood_mpp_conf function If a second non NULL argument is given to the kirkwood_mpp_conf function, it will be used to store the current configuration of the MPP registers. mpp_save must be a preallocated table of the same size as mpp_list and it must be zero terminated as well. A later call to kirkwood_mpp_conf function with this saved list as first (mpp_conf) argment will set the configuration back. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 3da6c98..03eb2de 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -31,7 +31,7 @@ static u32 kirkwood_variant(void) #define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) #define MPP_NR_REGS (1 + MPP_MAX/8) -void kirkwood_mpp_conf(u32 *mpp_list) +void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save) { u32 mpp_ctrl[MPP_NR_REGS]; unsigned int variant_mask; @@ -52,6 +52,7 @@ void kirkwood_mpp_conf(u32 *mpp_list) while (*mpp_list) { unsigned int num = MPP_NUM(*mpp_list); unsigned int sel = MPP_SEL(*mpp_list); + unsigned int sel_save; int shift; if (num > MPP_MAX) { @@ -66,6 +67,13 @@ void kirkwood_mpp_conf(u32 *mpp_list) } shift = (num & 7) << 2; + + if (mpp_save) { + sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf; + *mpp_save = num | (sel_save << 8) | variant_mask; + mpp_save++; + } + mpp_ctrl[num / 8] &= ~(0xf << shift); mpp_ctrl[num / 8] |= sel << shift; diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index b3c090e..8e50ee7 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -312,6 +312,6 @@ #define MPP_MAX 49 -void kirkwood_mpp_conf(unsigned int *mpp_list); +void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save); #endif -- cgit v0.10.2 From 846836386fbd24362559fbdf9e2f89c6786887d5 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 1 Jun 2012 01:31:00 +0000 Subject: kirkwood: fix calls to kirkwood_mpp_conf With the new second save argument introduced by the previous patch, all the calls to the function had to be fixed. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index d0b4adf..0f5e5a5 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -75,7 +75,7 @@ int board_early_init_f(void) 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index fbf020f..704005f 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -73,7 +73,7 @@ int board_early_init_f(void) MPP33_GPIO, /* Fan speed (bit 2) */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 31b73c9..d6497aa 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -99,7 +99,7 @@ int board_early_init_f(void) MPP49_GPIO, /* Wifi AP LED */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 057c558..f5c1c3c 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -96,7 +96,7 @@ int board_early_init_f(void) MPP49_GPIO, /* B_GLED */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index 4c41f3b..43852f6 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -98,7 +98,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 2a10e69..d48f05a 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -102,7 +102,7 @@ int board_early_init_f(void) 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 9c768bf..1fd7677 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -97,7 +97,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 71e6793..688d308 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -96,7 +96,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 38473e5..fc88520 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -100,7 +100,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index ff3421d..bac9ce5 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -71,7 +71,7 @@ int board_early_init_f(void) MPP49_GPIO, /* LED orange */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 990d79f..11260fe 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -97,7 +97,7 @@ int board_early_init_f(void) MPP49_GPIO, /* thermal sensor */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1); diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index c6c9a71..ed12b5c 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -244,7 +244,7 @@ int board_early_init_f(void) { u32 tmp; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); /* * The FLASH_GPIO_PIN switches between using a @@ -299,7 +299,7 @@ int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) kwmpp_config[2] = MPP2_NF_IO4; kwmpp_config[3] = MPP3_NF_IO5; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); tmp = readl(KW_GPIO0_BASE); writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); } else if ((strcmp(argv[1], "on") == 0)) { @@ -310,7 +310,7 @@ int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) kwmpp_config[2] = MPP2_SPI_SCK; kwmpp_config[3] = MPP3_SPI_MISO; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); tmp = readl(KW_GPIO0_BASE); writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); } else { diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 65f2c2e..1164d6b 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -66,7 +66,7 @@ int board_early_init_f(void) MPP29_GPIO, /* USB Copy button */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } -- cgit v0.10.2 From ca880679dda63f8d58393526c7e3257f772ccabe Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 1 Jun 2012 01:31:01 +0000 Subject: kw_spi: backup and reset the MPP of the chosen CS pin This was not done before, and in the case of a shared pin (for MPP0 between NF_IO[2] and CSn) this could lead to problems. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index db8ba8b..01e1d11 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -34,16 +34,14 @@ static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE; +u32 cs_spi_mpp_back[2]; + struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct spi_slave *slave; u32 data; - u32 kwspi_mpp_config[] = { - MPP0_GPIO, - MPP7_SPI_SCn, - 0 - }; + u32 kwspi_mpp_config[] = { 0, 0 }; if (!spi_cs_is_valid(bus, cs)) return NULL; @@ -70,19 +68,18 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, /* program mpp registers to select SPI_CSn */ if (cs) { - kwspi_mpp_config[0] = MPP0_GPIO; - kwspi_mpp_config[1] = MPP7_SPI_SCn; + kwspi_mpp_config[0] = MPP7_SPI_SCn; } else { kwspi_mpp_config[0] = MPP0_SPI_SCn; - kwspi_mpp_config[1] = MPP7_GPO; } - kirkwood_mpp_conf(kwspi_mpp_config); + kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back); return slave; } void spi_free_slave(struct spi_slave *slave) { + kirkwood_mpp_conf(cs_spi_mpp_back, NULL); free(slave); } -- cgit v0.10.2 From ac486e3ba16c37514d135c359f61ed6e32a2921d Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 1 Jun 2012 01:31:02 +0000 Subject: kw_spi: support spi_claim/release_bus functions These two function nows ensure that the MPP is configured correctly for the SPI controller before any SPI access, and restore the initial configuration when the access is over. Since the used pins for the SPI controller can differ (2 possibilities for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h index 1d5043f..c79bed7 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-kirkwood/spi.h @@ -37,6 +37,17 @@ struct kwspi_registers { u32 irq_mask; /* 0x10614 */ }; +/* They are used to define CONFIG_SYS_KW_SPI_MPP + * each of the below #defines selects which mpp is + * configured for each SPI signal in spi_claim_bus + * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) + * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) + * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) + */ +#define MOSI_MPP6 (1 << 0) +#define SCK_MPP10 (1 << 1) +#define MISO_MPP11 (1 << 2) + #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 01e1d11..db4bb0a 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -83,13 +83,49 @@ void spi_free_slave(struct spi_slave *slave) free(slave); } +#if defined(CONFIG_SYS_KW_SPI_MPP) +u32 spi_mpp_backup[4]; +#endif + int spi_claim_bus(struct spi_slave *slave) { +#if defined(CONFIG_SYS_KW_SPI_MPP) + u32 config; + u32 spi_mpp_config[4]; + + config = CONFIG_SYS_KW_SPI_MPP; + + if (config & MOSI_MPP6) + spi_mpp_config[0] = MPP6_SPI_MOSI; + else + spi_mpp_config[0] = MPP1_SPI_MOSI; + + if (config & SCK_MPP10) + spi_mpp_config[1] = MPP10_SPI_SCK; + else + spi_mpp_config[1] = MPP2_SPI_SCK; + + if (config & MISO_MPP11) + spi_mpp_config[2] = MPP11_SPI_MISO; + else + spi_mpp_config[2] = MPP3_SPI_MISO; + + spi_mpp_config[3] = 0; + spi_mpp_backup[3] = 0; + + /* set new spi mpp and save current mpp config */ + kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); + +#endif + return 0; } void spi_release_bus(struct spi_slave *slave) { +#if defined(CONFIG_SYS_KW_SPI_MPP) + kirkwood_mpp_conf(spi_mpp_backup, NULL); +#endif } #ifndef CONFIG_SPI_CS_IS_VALID -- cgit v0.10.2 From 24934fea0c6248ac33ccf398dd1a86e0b9904eeb Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 1 Jun 2012 01:31:03 +0000 Subject: kw_spi: add weak functions board_spi_claim/release_bus This allows a final, board specific, step in the claim/relase_bus function for the SPI controller, which may be needed for some hardware designs. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index db4bb0a..f4523a3 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -87,6 +87,11 @@ void spi_free_slave(struct spi_slave *slave) u32 spi_mpp_backup[4]; #endif +__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + int spi_claim_bus(struct spi_slave *slave) { #if defined(CONFIG_SYS_KW_SPI_MPP) @@ -118,7 +123,11 @@ int spi_claim_bus(struct spi_slave *slave) #endif - return 0; + return board_spi_claim_bus(slave); +} + +__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave) +{ } void spi_release_bus(struct spi_slave *slave) @@ -126,6 +135,8 @@ void spi_release_bus(struct spi_slave *slave) #if defined(CONFIG_SYS_KW_SPI_MPP) kirkwood_mpp_conf(spi_mpp_backup, NULL); #endif + + board_spi_release_bus(slave); } #ifndef CONFIG_SPI_CS_IS_VALID -- cgit v0.10.2 From d131ad68c6566749df10154d2a6fa93df5865495 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 27 May 2012 11:44:51 +0000 Subject: kwboot: boot kirkwood SoCs over a serial link The kwboot program boots boards based on Marvell's Kirkwood platform via Xmodem over their integrated UART. Signed-off-by: Daniel Stodden Acked-by: Luka Perkov Tested-By: Holger Brunck Tested-By: David Purdy Tested-by: Simon Guinot diff --git a/doc/kwboot.1 b/doc/kwboot.1 new file mode 100644 index 0000000..ed08398 --- /dev/null +++ b/doc/kwboot.1 @@ -0,0 +1,84 @@ +.TH KWBOOT 1 "2012-05-19" + +.SH NAME +kwboot \- Boot Marvell Kirkwood SoCs over a serial link. +.SH SYNOPSIS +.B kwboot +.RB [ "-b \fIimage\fP" ] +.RB [ "-p" ] +.RB [ "-t" ] +.RB [ "-B \fIbaudrate\fP" ] +.RB \fITTY\fP +.SH "DESCRIPTION" + +The \fBmkimage\fP program boots boards based on Marvell's Kirkwood +platform over their integrated UART. Boot image files will typically +contain a second stage boot loader, such as U-Boot. The image file +must conform to Marvell's BootROM firmware image format +(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP. + +Following power-up or a system reset, system BootROM code polls the +UART for a brief period of time, sensing a handshake message which +initiates an image upload. This program sends this boot message until +it receives a positive acknowledgement. The image is transfered using +Xmodem. + +Additionally, this program implements a minimal terminal mode, which +can be used either standalone, or entered immediately following boot +image transfer completion. This is often useful to catch early boot +messages, or to manually interrupt a default boot procedure performed +by the second-stage loader. + +.SH "OPTIONS" + +.TP +.BI "\-b \fIimage\fP" +Handshake; then upload file \fIimage\fP over \fITTY\fP. + +Note that for the encapsulated boot code to be executed, \fIimage\fP +must be of type "UART boot" (0x69). Boot images of different types, +such as backup images of vendor firmware downloaded from flash memory +(type 0x8B), will not work (or not as expected). See \fB-p\fP for a +workaround. + +This mode writes handshake status and upload progress indication to +stdout. + +.TP +.BI "\-p" +In combination with \fB-b\fP, patches the header in \fIimage\fP prior +to upload, to "UART boot" type. + +This option attempts on-the-fly conversion of some none-UART image +types, such as images which were originally formatted to be stored in +flash memory. + +Conversion is performed in memory. The contents of \fIimage\fP will +not be altered. + +.TP +.BI "\-t" +Run a terminal program, connecting standard input and output to +.RB \fITTY\fP. + +If used in combination with \fB-b\fP, terminal mode is entered +immediately following a successful image upload. + +If standard I/O streams connect to a console, this mode will terminate +after receiving 'ctrl-\\' followed by 'c' from console input. + +.TP +.BI "\-B \fIbaudrate\fP" +Adjust the baud rate on \fITTY\fP. Default rate is 115200. + +.SH "SEE ALSO" +.PP +\fBmkimage\fP(1) + +.SH "AUTHORS" + +Daniel Stodden +.br +Luka Perkov +.br +David Purdy diff --git a/tools/Makefile b/tools/Makefile index 8993fdd..8097d95 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -72,6 +72,7 @@ BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) +BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX) # Source files which exist outside the tools directory EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o @@ -101,6 +102,7 @@ OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o NOPED_OBJ_FILES-y += ublimage.o +OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o # Don't build by default #ifeq ($(ARCH),ppc) @@ -234,6 +236,10 @@ $(obj)ncb$(SFX): $(obj)ncb.o $(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ +$(obj)kwboot$(SFX): $(obj)kwboot.o + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ + $(HOSTSTRIP) $@ + # Some of the tool objects need to be accessed from outside the tools directory $(obj)%.o: $(SRCTREE)/common/%.c $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< diff --git a/tools/kwboot.c b/tools/kwboot.c new file mode 100644 index 0000000..e773f01 --- /dev/null +++ b/tools/kwboot.c @@ -0,0 +1,742 @@ +/* + * Boot a Marvell Kirkwood SoC, with Xmodem over UART0. + * + * (c) 2012 Daniel Stodden + * + * References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281 + * Integrated Controller: Functional Specifications" December 2, + * 2008. Chapter 24.2 "BootROM Firmware". + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kwbimage.h" + +#ifdef __GNUC__ +#define PACKED __attribute((packed)) +#else +#define PACKED +#endif + +/* + * Marvell BootROM UART Sensing + */ + +static unsigned char kwboot_msg_boot[] = { + 0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 +}; + +#define KWBOOT_MSG_REQ_DELAY 10 /* ms */ +#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */ + +/* + * Xmodem Transfers + */ + +#define SOH 1 /* sender start of block header */ +#define EOT 4 /* sender end of block transfer */ +#define ACK 6 /* target block ack */ +#define NAK 21 /* target block negative ack */ +#define CAN 24 /* target/sender transfer cancellation */ + +struct kwboot_block { + uint8_t soh; + uint8_t pnum; + uint8_t _pnum; + uint8_t data[128]; + uint8_t csum; +} PACKED; + +#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */ + +static int kwboot_verbose; + +static void +kwboot_printv(const char *fmt, ...) +{ + va_list ap; + + if (kwboot_verbose) { + va_start(ap, fmt); + vprintf(fmt, ap); + va_end(ap); + fflush(stdout); + } +} + +static void +__spinner(void) +{ + const char seq[] = { '-', '\\', '|', '/' }; + const int div = 8; + static int state, bs; + + if (state % div == 0) { + fputc(bs, stdout); + fputc(seq[state / div % sizeof(seq)], stdout); + fflush(stdout); + } + + bs = '\b'; + state++; +} + +static void +kwboot_spinner(void) +{ + if (kwboot_verbose) + __spinner(); +} + +static void +__progress(int pct, char c) +{ + const int width = 70; + static const char *nl = ""; + static int pos; + + if (pos % width == 0) + printf("%s%3d %% [", nl, pct); + + fputc(c, stdout); + + nl = "]\n"; + pos++; + + if (pct == 100) { + while (pos++ < width) + fputc(' ', stdout); + fputs(nl, stdout); + } + + fflush(stdout); + +} + +static void +kwboot_progress(int _pct, char c) +{ + static int pct; + + if (_pct != -1) + pct = _pct; + + if (kwboot_verbose) + __progress(pct, c); +} + +static int +kwboot_tty_recv(int fd, void *buf, size_t len, int timeo) +{ + int rc, nfds; + fd_set rfds; + struct timeval tv; + ssize_t n; + + rc = -1; + + FD_ZERO(&rfds); + FD_SET(fd, &rfds); + + tv.tv_sec = 0; + tv.tv_usec = timeo * 1000; + if (tv.tv_usec > 1000000) { + tv.tv_sec += tv.tv_usec / 1000000; + tv.tv_usec %= 1000000; + } + + do { + nfds = select(fd + 1, &rfds, NULL, NULL, &tv); + if (nfds < 0) + goto out; + if (!nfds) { + errno = ETIMEDOUT; + goto out; + } + + n = read(fd, buf, len); + if (n < 0) + goto out; + + buf = (char *)buf + n; + len -= n; + } while (len > 0); + + rc = 0; +out: + return rc; +} + +static int +kwboot_tty_send(int fd, const void *buf, size_t len) +{ + int rc; + ssize_t n; + + rc = -1; + + do { + n = write(fd, buf, len); + if (n < 0) + goto out; + + buf = (char *)buf + n; + len -= n; + } while (len > 0); + + rc = tcdrain(fd); +out: + return rc; +} + +static int +kwboot_tty_send_char(int fd, unsigned char c) +{ + return kwboot_tty_send(fd, &c, 1); +} + +static speed_t +kwboot_tty_speed(int baudrate) +{ + switch (baudrate) { + case 115200: + return B115200; + case 57600: + return B57600; + case 38400: + return B38400; + case 19200: + return B19200; + case 9600: + return B9600; + } + + return -1; +} + +static int +kwboot_open_tty(const char *path, speed_t speed) +{ + int rc, fd; + struct termios tio; + + rc = -1; + + fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY); + if (fd < 0) + goto out; + + memset(&tio, 0, sizeof(tio)); + + tio.c_iflag = 0; + tio.c_cflag = CREAD|CLOCAL|CS8; + + tio.c_cc[VMIN] = 1; + tio.c_cc[VTIME] = 10; + + cfsetospeed(&tio, speed); + cfsetispeed(&tio, speed); + + rc = tcsetattr(fd, TCSANOW, &tio); + if (rc) + goto out; + + rc = fd; +out: + if (rc < 0) { + if (fd >= 0) + close(fd); + } + + return rc; +} + +static int +kwboot_bootmsg(int tty, void *msg) +{ + int rc; + char c; + + kwboot_printv("Sending boot message. Please reboot the target..."); + + do { + rc = tcflush(tty, TCIOFLUSH); + if (rc) + break; + + rc = kwboot_tty_send(tty, msg, 8); + if (rc) { + usleep(KWBOOT_MSG_REQ_DELAY * 1000); + continue; + } + + rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO); + + kwboot_spinner(); + + } while (rc || c != NAK); + + kwboot_printv("\n"); + + return rc; +} + +static int +kwboot_xm_makeblock(struct kwboot_block *block, const void *data, + size_t size, int pnum) +{ + const size_t blksz = sizeof(block->data); + size_t n; + int i; + + block->pnum = pnum; + block->_pnum = ~block->pnum; + + n = size < blksz ? size : blksz; + memcpy(&block->data[0], data, n); + memset(&block->data[n], 0, blksz - n); + + block->csum = 0; + for (i = 0; i < n; i++) + block->csum += block->data[i]; + + return n; +} + +static int +kwboot_xm_sendblock(int fd, struct kwboot_block *block) +{ + int rc, retries; + char c; + + retries = 16; + do { + rc = kwboot_tty_send(fd, block, sizeof(*block)); + if (rc) + break; + + rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO); + if (rc) + break; + + if (c != ACK) + kwboot_progress(-1, '+'); + + } while (c == NAK && retries-- > 0); + + rc = -1; + + switch (c) { + case ACK: + rc = 0; + break; + case NAK: + errno = EBADMSG; + break; + case CAN: + errno = ECANCELED; + break; + default: + errno = EPROTO; + break; + } + + return rc; +} + +static int +kwboot_xmodem(int tty, const void *_data, size_t size) +{ + const uint8_t *data = _data; + int rc, pnum, N, err; + + pnum = 1; + N = 0; + + kwboot_printv("Sending boot image...\n"); + + do { + struct kwboot_block block; + int n; + + n = kwboot_xm_makeblock(&block, + data + N, size - N, + pnum++); + if (n < 0) + goto can; + + if (!n) + break; + + rc = kwboot_xm_sendblock(tty, &block); + if (rc) + goto out; + + N += n; + kwboot_progress(N * 100 / size, '.'); + } while (1); + + rc = kwboot_tty_send_char(tty, EOT); + +out: + return rc; + +can: + err = errno; + kwboot_tty_send_char(tty, CAN); + errno = err; + goto out; +} + +static int +kwboot_term_pipe(int in, int out, char *quit, int *s) +{ + ssize_t nin, nout; + char _buf[128], *buf = _buf; + + nin = read(in, buf, sizeof(buf)); + if (nin < 0) + return -1; + + if (quit) { + int i; + + for (i = 0; i < nin; i++) { + if (*buf == quit[*s]) { + (*s)++; + if (!quit[*s]) + return 0; + buf++; + nin--; + } else + while (*s > 0) { + nout = write(out, quit, *s); + if (nout <= 0) + return -1; + (*s) -= nout; + } + } + } + + while (nin > 0) { + nout = write(out, buf, nin); + if (nout <= 0) + return -1; + nin -= nout; + } + + return 0; +} + +static int +kwboot_terminal(int tty) +{ + int rc, in, s; + char *quit = "\34c"; + struct termios otio, tio; + + rc = -1; + + in = STDIN_FILENO; + if (isatty(in)) { + rc = tcgetattr(in, &otio); + if (!rc) { + tio = otio; + cfmakeraw(&tio); + rc = tcsetattr(in, TCSANOW, &tio); + } + if (rc) { + perror("tcsetattr"); + goto out; + } + + kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n", + quit[0]|0100, quit[1]); + } else + in = -1; + + rc = 0; + s = 0; + + do { + fd_set rfds; + int nfds = 0; + + FD_SET(tty, &rfds); + nfds = nfds < tty ? tty : nfds; + + if (in >= 0) { + FD_SET(in, &rfds); + nfds = nfds < in ? in : nfds; + } + + nfds = select(nfds + 1, &rfds, NULL, NULL, NULL); + if (nfds < 0) + break; + + if (FD_ISSET(tty, &rfds)) { + rc = kwboot_term_pipe(tty, STDOUT_FILENO, NULL, NULL); + if (rc) + break; + } + + if (FD_ISSET(in, &rfds)) { + rc = kwboot_term_pipe(in, tty, quit, &s); + if (rc) + break; + } + } while (quit[s] != 0); + + tcsetattr(in, TCSANOW, &otio); +out: + return rc; +} + +static void * +kwboot_mmap_image(const char *path, size_t *size, int prot) +{ + int rc, fd, flags; + struct stat st; + void *img; + + rc = -1; + fd = -1; + img = NULL; + + fd = open(path, O_RDONLY); + if (fd < 0) + goto out; + + rc = fstat(fd, &st); + if (rc) + goto out; + + flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED; + + img = mmap(NULL, st.st_size, prot, flags, fd, 0); + if (img == MAP_FAILED) { + img = NULL; + goto out; + } + + rc = 0; + *size = st.st_size; +out: + if (rc && img) { + munmap(img, st.st_size); + img = NULL; + } + if (fd >= 0) + close(fd); + + return img; +} + +static uint8_t +kwboot_img_csum8(void *_data, size_t size) +{ + uint8_t *data = _data, csum; + + for (csum = 0; size-- > 0; data++) + csum += *data; + + return csum; +} + +static int +kwboot_img_patch_hdr(void *img, size_t size) +{ + int rc; + bhr_t *hdr; + uint8_t csum; + const size_t hdrsz = sizeof(*hdr); + + rc = -1; + hdr = img; + + if (size < hdrsz) { + errno = EINVAL; + goto out; + } + + csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum; + if (csum != hdr->checkSum) { + errno = EINVAL; + goto out; + } + + if (hdr->blockid == IBR_HDR_UART_ID) { + rc = 0; + goto out; + } + + hdr->blockid = IBR_HDR_UART_ID; + + hdr->nandeccmode = IBR_HDR_ECC_DISABLED; + hdr->nandpagesize = 0; + + hdr->srcaddr = hdr->ext + ? sizeof(struct kwb_header) + : sizeof(*hdr); + + hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum; + + rc = 0; +out: + return rc; +} + +static void +kwboot_usage(FILE *stream, char *progname) +{ + fprintf(stream, + "Usage: %s -b [ -p ] [ -t ] " + "[-B ] \n", progname); + fprintf(stream, "\n"); + fprintf(stream, " -b : boot \n"); + fprintf(stream, " -p: patch to type 0x69 (uart boot)\n"); + fprintf(stream, "\n"); + fprintf(stream, " -t: mini terminal\n"); + fprintf(stream, "\n"); + fprintf(stream, " -B : set baud rate\n"); + fprintf(stream, "\n"); +} + +int +main(int argc, char **argv) +{ + const char *ttypath, *imgpath; + int rv, rc, tty, term, prot, patch; + void *bootmsg; + void *img; + size_t size; + speed_t speed; + + rv = 1; + tty = -1; + bootmsg = NULL; + imgpath = NULL; + img = NULL; + term = 0; + patch = 0; + size = 0; + speed = B115200; + + kwboot_verbose = isatty(STDOUT_FILENO); + + do { + int c = getopt(argc, argv, "hb:ptB:"); + if (c < 0) + break; + + switch (c) { + case 'b': + bootmsg = kwboot_msg_boot; + imgpath = optarg; + break; + + case 'p': + patch = 1; + break; + + case 't': + term = 1; + break; + + case 'B': + speed = kwboot_tty_speed(atoi(optarg)); + if (speed == -1) + goto usage; + break; + + case 'h': + rv = 0; + default: + goto usage; + } + } while (1); + + if (!bootmsg && !term) + goto usage; + + if (patch && !imgpath) + goto usage; + + if (argc - optind < 1) + goto usage; + + ttypath = argv[optind++]; + + tty = kwboot_open_tty(ttypath, speed); + if (tty < 0) { + perror(ttypath); + goto out; + } + + if (imgpath) { + prot = PROT_READ | (patch ? PROT_WRITE : 0); + + img = kwboot_mmap_image(imgpath, &size, prot); + if (!img) { + perror(imgpath); + goto out; + } + } + + if (patch) { + rc = kwboot_img_patch_hdr(img, size); + if (rc) { + fprintf(stderr, "%s: Invalid image.\n", imgpath); + goto out; + } + } + + if (bootmsg) { + rc = kwboot_bootmsg(tty, bootmsg); + if (rc) { + perror("bootmsg"); + goto out; + } + } + + if (img) { + rc = kwboot_xmodem(tty, img, size); + if (rc) { + perror("xmodem"); + goto out; + } + } + + if (term) { + rc = kwboot_terminal(tty); + if (rc && !(errno == EINTR)) { + perror("terminal"); + goto out; + } + } + + rv = 0; +out: + if (tty >= 0) + close(tty); + + if (img) + munmap(img, size); + + return rv; + +usage: + kwboot_usage(rv ? stderr : stdout, basename(argv[0])); + goto out; +} -- cgit v0.10.2 From 9acf1ca50d8b031511d146f6ffd73201fedce28c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 5 Jun 2012 11:33:14 +0000 Subject: lib: add rand() function It's a PRNG using the simple and fast xorshift method. Signed-off-by: Michael Walle Cc: Wolfgang Denk diff --git a/include/common.h b/include/common.h index 7cf15c5..e16c53e 100644 --- a/include/common.h +++ b/include/common.h @@ -760,6 +760,14 @@ char * strmhz(char *buf, unsigned long hz); /* lib/crc32.c */ #include +/* lib/rand.c */ +#ifdef CONFIG_RANDOM_MACADDR +#define RAND_MAX -1U +void srand(unsigned int seed); +unsigned int rand(void); +unsigned int rand_r(unsigned int *seedp); +#endif + /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ int console_init_r(void); /* After relocation; uses the console stuff */ diff --git a/lib/Makefile b/lib/Makefile index 1e8478f..0ca45fc 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -66,6 +66,7 @@ COBJS-y += string.o COBJS-y += time.o COBJS-$(CONFIG_BOOTP_PXE) += uuid.o COBJS-y += vsprintf.o +COBJS-$(CONFIG_RANDOM_MACADDR) += rand.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/lib/rand.c b/lib/rand.c new file mode 100644 index 0000000..c9764f5 --- /dev/null +++ b/lib/rand.c @@ -0,0 +1,48 @@ +/* + * Simple xorshift PRNG + * see http://www.jstatsoft.org/v08/i14/paper + * + * Copyright (c) 2012 Michael Walle + * Michael Walle + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +static unsigned int y = 1U; + +unsigned int rand_r(unsigned int *seedp) +{ + *seedp ^= (*seedp << 13); + *seedp ^= (*seedp >> 17); + *seedp ^= (*seedp << 5); + + return *seedp; +} + +unsigned int rand(void) +{ + return rand_r(&y); +} + +void srand(unsigned int seed) +{ + y = seed; +} -- cgit v0.10.2 From 99e139d5902e488eb779cd4f00c978f3803c39be Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 5 Jun 2012 11:33:15 +0000 Subject: net: use common rand()/srand() functions Replace rand() with the functions from lib/. The link-local network code stores its own seed, derived from the MAC address. Thus making it independent from calls to srand() in other modules. Signed-off-by: Michael Walle Acked-by: Joe Hershberger diff --git a/include/common.h b/include/common.h index e16c53e..d1dd65a 100644 --- a/include/common.h +++ b/include/common.h @@ -761,7 +761,9 @@ char * strmhz(char *buf, unsigned long hz); #include /* lib/rand.c */ -#ifdef CONFIG_RANDOM_MACADDR +#if defined(CONFIG_RANDOM_MACADDR) || \ + defined(CONFIG_BOOTP_RANDOM_DELAY) || \ + defined(CONFIG_CMD_LINK_LOCAL) #define RAND_MAX -1U void srand(unsigned int seed); unsigned int rand(void); diff --git a/lib/Makefile b/lib/Makefile index 0ca45fc..556601c 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -67,8 +67,10 @@ COBJS-y += time.o COBJS-$(CONFIG_BOOTP_PXE) += uuid.o COBJS-y += vsprintf.o COBJS-$(CONFIG_RANDOM_MACADDR) += rand.o +COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o +COBJS-$(CONFIG_CMD_LINK_LOCAL) += rand.o -COBJS := $(COBJS-y) +COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/net/Makefile b/net/Makefile index 5264687..e7764ce 100644 --- a/net/Makefile +++ b/net/Makefile @@ -34,8 +34,6 @@ COBJS-$(CONFIG_CMD_DNS) += dns.o COBJS-$(CONFIG_CMD_NET) += eth.o COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o COBJS-$(CONFIG_CMD_NET) += net.o -COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += net_rand.o -COBJS-$(CONFIG_CMD_LINK_LOCAL) += net_rand.o COBJS-$(CONFIG_CMD_NFS) += nfs.o COBJS-$(CONFIG_CMD_PING) += ping.o COBJS-$(CONFIG_CMD_RARP) += rarp.o diff --git a/net/link_local.c b/net/link_local.c index 3362863..582d011 100644 --- a/net/link_local.c +++ b/net/link_local.c @@ -56,6 +56,7 @@ static unsigned conflicts; static unsigned nprobes; static unsigned nclaims; static int ready; +static unsigned int seed; static void link_local_timeout(void); @@ -68,7 +69,7 @@ static IPaddr_t pick(void) unsigned tmp; do { - tmp = rand() & IN_CLASSB_HOST; + tmp = rand_r(&seed) & IN_CLASSB_HOST; } while (tmp > (IN_CLASSB_HOST - 0x0200)); return (IPaddr_t) htonl((LINKLOCAL_ADDR + 0x0100) + tmp); } @@ -78,7 +79,7 @@ static IPaddr_t pick(void) */ static inline unsigned random_delay_ms(unsigned secs) { - return rand() % (secs * 1000); + return rand_r(&seed) % (secs * 1000); } static void configure_wait(void) @@ -109,7 +110,7 @@ void link_local_start(void) } NetOurSubnetMask = IN_CLASSB_NET; - srand_mac(); + seed = seed_mac(); if (ip == 0) ip = pick(); diff --git a/net/net_rand.c b/net/net_rand.c deleted file mode 100644 index 5387aba..0000000 --- a/net/net_rand.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Based on LiMon - BOOTP. - * - * Copyright 1994, 1995, 2000 Neil Russell. - * (See License) - * Copyright 2000 Roland Borde - * Copyright 2000 Paolo Scaffardi - * Copyright 2000-2004 Wolfgang Denk, wd@denx.de - */ - -#include -#include -#include "net_rand.h" - -static ulong seed1, seed2; - -void srand_mac(void) -{ - ulong tst1, tst2, m_mask; - ulong m_value = 0; - int reg; - unsigned char bi_enetaddr[6]; - - /* get our mac */ - eth_getenv_enetaddr("ethaddr", bi_enetaddr); - - debug("BootpRequest => Our Mac: "); - for (reg = 0; reg < 6; reg++) - debug("%x%c", bi_enetaddr[reg], reg == 5 ? '\n' : ':'); - - /* Mac-Manipulation 2 get seed1 */ - tst1 = 0; - tst2 = 0; - for (reg = 2; reg < 6; reg++) { - tst1 = tst1 << 8; - tst1 = tst1 | bi_enetaddr[reg]; - } - for (reg = 0; reg < 2; reg++) { - tst2 = tst2 | bi_enetaddr[reg]; - tst2 = tst2 << 8; - } - - seed1 = tst1^tst2; - - /* Mirror seed1*/ - m_mask = 0x1; - for (reg = 1; reg <= 32; reg++) { - m_value |= (m_mask & seed1); - seed1 = seed1 >> 1; - m_value = m_value << 1; - } - seed1 = m_value; - seed2 = 0xb78d0945; -} - -unsigned long rand(void) -{ - ulong sum; - - /* Random Number Generator */ - sum = seed1 + seed2; - if (sum < seed1 || sum < seed2) - sum++; - seed2 = seed1; - seed1 = sum; - - return sum; -} diff --git a/net/net_rand.h b/net/net_rand.h index c98db64..ba9d064 100644 --- a/net/net_rand.h +++ b/net/net_rand.h @@ -9,18 +9,35 @@ #ifndef __NET_RAND_H__ #define __NET_RAND_H__ -#define RAND_MAX 0xffffffff +#include /* - * Seed the random number generator using the eth0 MAC address + * Return a seed for the PRNG derived from the eth0 MAC address. */ -void srand_mac(void); +static inline unsigned int seed_mac(void) +{ + unsigned char enetaddr[6]; + unsigned int seed; + + /* get our mac */ + eth_getenv_enetaddr("ethaddr", enetaddr); + + seed = enetaddr[5]; + seed ^= enetaddr[4] << 8; + seed ^= enetaddr[3] << 16; + seed ^= enetaddr[2] << 24; + seed ^= enetaddr[1]; + seed ^= enetaddr[0] << 8; + + return seed; +} /* - * Get a random number (after seeding with MAC address) - * - * @return random number + * Seed the random number generator using the eth0 MAC address. */ -unsigned long rand(void); +static inline void srand_mac(void) +{ + srand(seed_mac()); +} #endif /* __NET_RAND_H__ */ -- cgit v0.10.2 From 03c1b04f86ddd6a296e2d80d73f5e4670e55da1d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 5 Jun 2012 11:33:16 +0000 Subject: net: add helper to generate random mac address Add new function eth_random_enetaddr() to generate a locally administered ethernet address. Signed-off-by: Michael Walle Acked-by: Joe Hershberger diff --git a/include/net.h b/include/net.h index a092f29..6d2d6cd 100644 --- a/include/net.h +++ b/include/net.h @@ -122,6 +122,23 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); extern int eth_getenv_enetaddr_by_index(const char *base_name, int index, uchar *enetaddr); +#ifdef CONFIG_RANDOM_MACADDR +/* + * The u-boot policy does not allow hardcoded ethernet addresses. Under the + * following circumstances a random generated address is allowed: + * - in emergency cases, where you need a working network connection to set + * the ethernet address. + * Eg. you want a rescue boot and don't have a serial port to access the + * CLI to set environment variables. + * + * In these cases, we generate a random locally administered ethernet address. + * + * Args: + * enetaddr - returns 6 byte hardware address + */ +extern void eth_random_enetaddr(uchar *enetaddr); +#endif + extern int usb_eth_initialize(bd_t *bi); extern int eth_init(bd_t *bis); /* Initialize the device */ extern int eth_send(void *packet, int length); /* Send a packet */ diff --git a/net/eth.c b/net/eth.c index d9a6430..d526264 100644 --- a/net/eth.c +++ b/net/eth.c @@ -70,6 +70,28 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } +#ifdef CONFIG_RANDOM_MACADDR +void eth_random_enetaddr(uchar *enetaddr) +{ + uint32_t rval; + + srand(get_timer(0)); + + rval = rand(); + enetaddr[0] = rval & 0xff; + enetaddr[1] = (rval >> 8) & 0xff; + enetaddr[2] = (rval >> 16) & 0xff; + + rval = rand(); + enetaddr[3] = rval & 0xff; + enetaddr[4] = (rval >> 8) & 0xff; + enetaddr[5] = (rval >> 16) & 0xff; + + /* make sure it's local and unicast */ + enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01; +} +#endif + /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on -- cgit v0.10.2 From f214a20e7e4c072da3d5d857e8fa79a41a6446ab Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 5 Jun 2012 11:33:17 +0000 Subject: Kirkwood: add lschlv2 and lsxhl board support This patch adds support for both the Linkstation Live (LS-CHLv2) and Linkstation Pro (LS-XHL) by Buffalo. Signed-off-by: Michael Walle Cc: Prafulla Wadaskar diff --git a/MAINTAINERS b/MAINTAINERS index 8a524ba..ce9fc9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -904,6 +904,11 @@ Prafulla Wadaskar rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Michael Walle + + lschlv2 ARM926EJS (Kirkwood SoC) + lsxhl ARM926EJS (Kirkwood SoC) + Tom Warren harmony Tegra2 (ARM7 & A9 Dual Core) diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile new file mode 100644 index 0000000..36f2560 --- /dev/null +++ b/board/buffalo/lsxl/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := lsxl.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg new file mode 100644 index 0000000..2b9b3cd --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lschl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B1B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543000 +# bit3-0: 0 required +# bit4: 0, addr/cmd in same cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x3302444F +# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 4, 5 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 0, 16 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 3, 4 cycle tRRD +# bit31-28: 3, 4 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000823 +# bit6-0: 0x23, 35 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x00000009 +# bit1-0: 1, Cs0width=x16 +# bit3-2: 2, Cs0size=512Mbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000042 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) +# bit5-3: 0 required +# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x03FFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x03, Size (i.e. 64MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x003C0000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3 +# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1 +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg new file mode 100644 index 0000000..8a94b6c --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B9B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543010 +# bit3-0: 0 required +# bit4: 1, T2 mode, addr/cmd are driven for two cycles +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x22125441 +# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 5, 6 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 1, 18 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 2, 3 cycle tRRD +# bit31-28: 2, 3 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000832 +# bit6-0: 0x32, 50 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x0000000C +# bit1-0: 0, Cs0width=x8 +# bit3-2: 3, Cs0size=1Gbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000006 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) +# bit5-3: 0 required +# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x0FFFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x0f, Size (i.e. 256MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x00010000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 +# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c new file mode 100644 index 0000000..fe15511 --- /dev/null +++ b/board/buffalo/lsxl/lsxl.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle + * + * Based on sheevaplug/sheevaplug.c by + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lsxl.h" + +/* + * Rescue mode + * + * Selected by holding the push button for 3 seconds, while powering on + * the device. + * + * These linkstations don't have a (populated) serial port. There is no + * way to access an (unmodified) board other than using the netconsole. If + * you want to recover from a bad environment setting or an empty environment, + * you can do this only with a working network connection. Therefore, a random + * ethernet address is generated if none is set and a DHCP request is sent. + * After a successful DHCP response is received, the network settings are + * configured and the ncip parameter is set to the serverip. Eg. for a working + * resuce mode, you should set 'next-server' to the host where the netconsole + * client is started. + * Additionally, the bootsource is set to 'rescue'. + */ + +#ifndef CONFIG_ENV_OVERWRITE +# error "You need to set CONFIG_ENV_OVERWRITE" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH); + + /* + * Multi-Purpose Pins Functionality configuration + * These strappings are taken from the original vendor uboot port. + */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_UART0_RXD, + MPP5_UART0_TXD, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_GPIO, + MPP9_GPIO, + MPP10_GPO, /* HDD power */ + MPP11_GPIO, /* USB Vbus enable */ + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_GPO, /* fan speed high */ + MPP19_GPO, /* fan speed low */ + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* function LED */ + MPP37_GPIO, /* alarm LED */ + MPP38_GPIO, /* info LED */ + MPP39_GPIO, /* power LED */ + MPP40_GPIO, /* fan alarm */ + MPP41_GPIO, /* funtion button */ + MPP42_GPIO, /* power switch */ + MPP43_GPIO, /* power auto switch */ + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, /* function red LED */ + MPP49_GPIO, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +#define LED_OFF 0 +#define LED_ALARM_ON 1 +#define LED_ALARM_BLINKING 2 +#define LED_POWER_ON 3 +#define LED_POWER_BLINKING 4 +#define LED_INFO_ON 5 +#define LED_INFO_BLINKING 6 + +static void __set_led(int blink_alarm, int blink_info, int blink_power, + int value_alarm, int value_info, int value_power) +{ + kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm); + kw_gpio_set_blink(GPIO_INFO_LED, blink_info); + kw_gpio_set_blink(GPIO_POWER_LED, blink_power); + kw_gpio_set_value(GPIO_ALARM_LED, value_alarm); + kw_gpio_set_value(GPIO_INFO_LED, value_info); + kw_gpio_set_value(GPIO_POWER_LED, value_power); +} + +static void set_led(int state) +{ + switch (state) { + case LED_OFF: + __set_led(0, 0, 0, 0, 0, 0); + break; + case LED_ALARM_ON: + __set_led(0, 0, 0, 0, 1, 1); + break; + case LED_ALARM_BLINKING: + __set_led(1, 0, 0, 1, 1, 1); + break; + case LED_INFO_ON: + __set_led(0, 0, 0, 1, 0, 1); + break; + case LED_INFO_BLINKING: + __set_led(0, 1, 0, 1, 1, 1); + break; + case LED_POWER_ON: + __set_led(0, 0, 0, 1, 1, 0); + break; + case LED_POWER_BLINKING: + __set_led(0, 0, 1, 1, 1, 1); + break; + } +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + set_led(LED_POWER_BLINKING); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +void check_enetaddr(void) +{ + uchar enetaddr[6]; + + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + /* signal unset/invalid ethaddr to user */ + set_led(LED_INFO_BLINKING); + } +} + +static void erase_environment(void) +{ + struct spi_flash *flash; + + printf("Erasing environment..\n"); + flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) { + printf("Erasing flash failed\n"); + return; + } + + spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + spi_flash_free(flash); + do_reset(NULL, 0, 0, NULL); +} + +static void rescue_mode(void) +{ + uchar enetaddr[6]; + + printf("Entering rescue mode..\n"); +#ifdef CONFIG_RANDOM_MACADDR + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + eth_random_enetaddr(enetaddr); + if (eth_setenv_enetaddr("ethaddr", enetaddr)) { + printf("Failed to set ethernet address\n"); + set_led(LED_ALARM_BLINKING); + return; + } + } +#endif + setenv("bootsource", "rescue"); +} + +static void check_push_button(void) +{ + int i = 0; + + while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) { + udelay(100000); + i++; + + if (i == 10) + set_led(LED_INFO_ON); + + if (i >= 100) { + set_led(LED_INFO_BLINKING); + break; + } + } + + if (i >= 100) + erase_environment(); + else if (i >= 10) + rescue_mode(); +} + +int misc_init_r(void) +{ + check_enetaddr(); + check_push_button(); + + return 0; +} +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{ + if (progress > 0) + return; + + /* this is not an error, eg. bootp with autoload=no will trigger this */ + if (progress == -BOOTSTAGE_ID_NET_LOADED) + return; + + set_led(LED_ALARM_BLINKING); +} +#endif diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h new file mode 100644 index 0000000..2a2642e --- /dev/null +++ b/board/buffalo/lsxl/lsxl.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __LSXL_H +#define __LSXL_H + +#define GPIO_HDD_POWER 10 +#define GPIO_USB_VBUS 11 +#define GPIO_FAN_HIGH 18 +#define GPIO_FAN_LOW 19 +#define GPIO_FUNC_LED 36 +#define GPIO_ALARM_LED 37 +#define GPIO_INFO_LED 38 +#define GPIO_POWER_LED 39 +#define GPIO_FAN_LOCK 40 +#define GPIO_FUNC_BUTTON 41 +#define GPIO_POWER_SWITCH 42 +#define GPIO_POWER_AUTO_SWITCH 43 +#define GPIO_FUNC_RED_LED 48 + +#define _BIT(x) (1<<(x)) + +#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \ + | _BIT(GPIO_USB_VBUS) \ + | _BIT(GPIO_FAN_HIGH) \ + | _BIT(GPIO_FAN_LOW))) + +#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32))) + +#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \ + | _BIT(GPIO_USB_VBUS)) + +#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32)) + +#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \ + | _BIT(GPIO_FAN_LOW)) + +#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_BUTTON - 32) \ + | _BIT(GPIO_POWER_SWITCH - 32) \ + | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32)) + +#endif /* __LSXL_H */ diff --git a/boards.cfg b/boards.cfg index 7e1241d..d33ff27 100644 --- a/boards.cfg +++ b/boards.cfg @@ -138,6 +138,8 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood +lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 +lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX mgcoge3un arm arm926ejs km_arm keymile kirkwood diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h new file mode 100644 index 0000000..0db559c --- /dev/null +++ b/include/configs/lsxl.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_LSXL_H +#define _CONFIG_LSXL_H + +/* + * Version number information + */ +#if defined(CONFIG_LSCHLV2) +#define CONFIG_IDENT_STRING " LS-CHLv2" +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg +#define CONFIG_MACH_TYPE 3006 +#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ +#elif defined(CONFIG_LSXHL) +#define CONFIG_IDENT_STRING " LS-XHL" +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg +#define CONFIG_MACH_TYPE 2663 +/* CONFIG_SYS_TCLK is 200000000 by default */ +#else +#error "unknown board" +#endif + +/* + * General configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_RANDOM_MACADDR +#define CONFIG_KIRKWOOD_GPIO +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * Enable u-boot API for standalone programs. + */ +#define CONFIG_API + +/* + * Commands configuration + */ +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_PING +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_USB + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* ST M25P40 */ +#undef CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_STMICRO +#undef CONFIG_ENV_SPI_MAX_HZ +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#undef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 25000000 + + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 8 +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x10000 /* 64k */ +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_LOADADDR 0x00800000 +#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}" +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootsource=hdd\0" \ + "hdpart=0:1\0" \ + "bootcmd_net=bootp 0x00100000 uImage " \ + "&& tftpboot 0x00800000 uInitrd " \ + "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_hdd=ide reset " \ + "&& ext2load ide ${hdpart} 0x00100000 /uImage " \ + "&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \ + "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_usb=usb start " \ + "&& fatload usb 0:1 0x00100000 /uImage " \ + "&& fatload usb 0:1 0x00800000 /uInitrd " \ + "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ + "eraseenv=sf probe 0 " \ + "&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \ + " +" MK_STR(CONFIG_ENV_SIZE) "\0" \ + "config_nc_dhcp=setenv autoload_old ${autoload}; " \ + "setenv autoload no " \ + "&& bootp " \ + "&& setenv ncip ${serverip} " \ + "&& setenv autoload ${autoload_old}; " \ + "setenv autoload_old\0" \ + "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ + "setenv ncip; setenv gatewayip; setenv ethact; " \ + "setenv bootfile; setenv dnsip; " \ + "setenv bootsource hdd; run ser\0" \ + "restore_env=run standard_env; saveenv; reset\0" \ + "ser=setenv stdin serial; setenv stdout serial; " \ + "setenv stderr serial\0" \ + "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */ +#define CONFIG_PHY_BASE_ADR 7 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +#ifdef CONFIG_CMD_IDE +#undef CONFIG_IDE_LED +#undef CONFIG_SYS_IDE_MAXBUS +#define CONFIG_SYS_IDE_MAXBUS 1 +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif + +#endif /* _CONFIG_LSXL_H */ -- cgit v0.10.2 From c4c4b0e66188e7a21256ba67255f8bc874994039 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 5 Jun 2012 13:15:58 +0000 Subject: lacie_kw: fix SDRAM banks number for net2big_v2 Signed-off-by: Simon Guinot diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index cd8d59f..0796ccf 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -66,11 +66,7 @@ /* * SDRAM configuration */ -#if defined(CONFIG_NET2BIG_V2) -#define CONFIG_NR_DRAM_BANKS 2 -#else #define CONFIG_NR_DRAM_BANKS 1 -#endif #ifdef CONFIG_INETSPACE_V2 /* Different SDRAM configuration and size for Internet Space v2 */ -- cgit v0.10.2 From d92151b9259bc009a4dd8ed1683770520f3b10ac Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 5 Jun 2012 13:15:59 +0000 Subject: lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2 Signed-off-by: Simon Guinot diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 0796ccf..c35c2db 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -70,7 +70,7 @@ #ifdef CONFIG_INETSPACE_V2 /* Different SDRAM configuration and size for Internet Space v2 */ -#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg) +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg #endif /* -- cgit v0.10.2 From c59c085731571d8e04344f815fd3a25bb0f69ae1 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 5 Jun 2012 13:16:00 +0000 Subject: ARM: don't probe PHY address for LaCie boards The command miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr) always returns 8 for the PHY address. It is the reset value for the PHY Address Register. Obviously, this default value could be incorrect. Moreover, as the PHY address is well known, there is no need to auto-detect it. Now, the PHY address must given as a parameter to the PHY initialization function. Additionally this patch also fixes some aesthetic issues. Signed-off-by: Simon Guinot diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index dc5350d..78d0edc 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -20,34 +20,25 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5) -void mv_phy_88e1116_init(const char *name) +void mv_phy_88e1116_init(const char *name, u16 phyaddr) { u16 reg; - u16 devadr; if (miiphy_set_current_dev(name)) return; - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; - } - /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); - printf("88E1116 Initialized on %s\n", name); + if (miiphy_reset(name, phyaddr) == 0) + printf("88E1116 Initialized on %s\n", name); } #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h index 82a9522..2edd5ab 100644 --- a/board/LaCie/common/common.h +++ b/board/LaCie/common/common.h @@ -11,7 +11,7 @@ #define _LACIE_COMMON_H #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -void mv_phy_88e1116_init(const char *name); +void mv_phy_88e1116_init(const char *name, u16 phyaddr); #endif #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) int lacie_read_mac_address(uchar *mac); diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 1b33875..4a9b308 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -96,6 +96,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 0f5e5a5..0e06c29 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -109,7 +109,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 704005f..68e8a77 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -107,7 +107,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif -- cgit v0.10.2 From dacc8c6f79aa4016e431278d31431a19d43c6b37 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 13 Jun 2012 03:03:52 +0000 Subject: arm/kirkwood: protect the ENV_SPI #defines So that they can be redefined by some boards specific values. Signed-off-by: Valentin Longchamp Signed-off-by: Holger Brunck cc: Prafulla Wadaskar diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 91164eb..a9499b7 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -82,9 +82,15 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI 1 #define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif #endif /* -- cgit v0.10.2 From 0c25defccdc0461bf6695d7e0fe3091c9da8778e Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 13 Jun 2012 03:01:03 +0000 Subject: arm/km: use spi claim bus to switch between SPI and NAND We overwrite these weak functions from the kirkwood spi code to use our own method to be able to switch between the SPI NOR and the NAND flash. This is needed e.g. to update the u-boot. The former command do_spi_toggle can therefore be removed. And the usage of this command is removed from the u-boot update command in the u-boot environment. Signed-off-by: Valentin Longchamp Signed-off-by: Prafulla Wadaskar cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed12b5c..cb3402b 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -284,48 +285,17 @@ int board_init(void) return 0; } -#if defined(CONFIG_CMD_SF) -int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int board_spi_claim_bus(struct spi_slave *slave) { - u32 tmp; - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "off") == 0)) { - printf("SPI FLASH disabled, NAND enabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_NF_IO2; - kwmpp_config[1] = MPP1_NF_IO3; - kwmpp_config[2] = MPP2_NF_IO4; - kwmpp_config[3] = MPP3_NF_IO5; - - kirkwood_mpp_conf(kwmpp_config, NULL); - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - } else if ((strcmp(argv[1], "on") == 0)) { - printf("SPI FLASH enabled, NAND disabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_SPI_SCn; - kwmpp_config[1] = MPP1_SPI_MOSI; - kwmpp_config[2] = MPP2_SPI_SCK; - kwmpp_config[3] = MPP3_SPI_MISO; - - kirkwood_mpp_conf(kwmpp_config, NULL); - tmp = readl(KW_GPIO0_BASE); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); - } else { - return cmd_usage(cmdtp); - } + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); return 0; } -U_BOOT_CMD( - spitoggle, 2, 0, do_spi_toggle, - "En-/disable SPI FLASH access", - " - Enable (on) or disable (off) SPI FLASH access\n" - ); -#endif +void board_spi_release_bus(struct spi_slave *slave) +{ + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); +} int dram_init(void) { diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 4a0b80e..b14093f 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -227,7 +227,11 @@ int get_scl(void); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +/* SPI bus claim MPP configuration */ +#define CONFIG_SYS_KW_SPI_MPP 0x0 + #define FLASH_GPIO_PIN 0x00010000 +#define KM_FLASH_GPIO_PIN 16 #ifndef MTDIDS_DEFAULT # define MTDIDS_DEFAULT "nand0=orion_nand" @@ -241,9 +245,8 @@ int get_scl(void); #define CONFIG_KM_UPDATE_UBOOT \ "update=" \ - "spi on;sf probe 0;sf erase 0 +${filesize};" \ - "sf write ${load_addr_r} 0 ${filesize};" \ - "spi off\0" + "sf probe 0;sf erase 0 +${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};\0" /* * Default environment variables -- cgit v0.10.2 From 0ec005fe00b9057fd16531f44146c9e363bb7861 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 3 Jul 2012 03:02:20 +0000 Subject: Kirkwood: Add support for Ka-Ro TK71 Signed-off-by: Marek Vasut Cc: Prafulla Wadaskar Cc: Wolfgang Denk diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile new file mode 100644 index 0000000..934e391 --- /dev/null +++ b/board/karo/tk71/Makefile @@ -0,0 +1,45 @@ +# +# Copyright (C) 2012 Marek Vasut +# on behalf of DENX Software Engineering GmbH +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tk71.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg new file mode 100644 index 0000000..0166826 --- /dev/null +++ b/board/karo/tk71/kwbimage.cfg @@ -0,0 +1,174 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# adopted to TK71 by +# Nils Faerber +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000034 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c new file mode 100644 index 0000000..96410d7 --- /dev/null +++ b/board/karo/tk71/tk71.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2012 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TK71_OE_LOW (~0) +#define TK71_OE_HIGH (~0) +#define TK71_OE_VAL_LOW (0) +#define TK71_OE_VAL_HIGH (0) + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET + +#define MV88E1116_MAC_CTRL2_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +static void mv_phy_88e1118_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1118 Initialized on %s\n", name); +} + +/* Configure and enable Switch and PHY */ +void reset_phy(void) +{ + /* configure and initialize PHY */ + mv_phy_88e1118_init("egiga0"); + +} +#endif diff --git a/boards.cfg b/boards.cfg index d33ff27..a423555 100644 --- a/boards.cfg +++ b/boards.cfg @@ -158,6 +158,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood dockstar arm arm926ejs - Seagate kirkwood +tk71 arm arm926ejs tk71 karo kirkwood devkit3250 arm arm926ejs devkit3250 timll lpc32xx jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg diff --git a/include/configs/tk71.h b/include/configs/tk71.h new file mode 100644 index 0000000..f929f20 --- /dev/null +++ b/include/configs/tk71.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2012 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __CONFIG_TK71_H__ +#define __CONFIG_TK71_H__ + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKa-Ro TK71" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define MACH_TYPE_TK71 2399 +#define CONFIG_MACH_TYPE MACH_TYPE_TK71 + +/* + * Commands configuration + */ +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * NAND flash + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "nand0,3" +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} +#define CONFIG_PHY_BASE_ADR 0x08 +#endif + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_KIRKWOOD +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;" +#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \ + "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \ + "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \ + "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \ + "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0" +#define MTDIDS_DEFAULT "nand0=orion_nand" +#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS + +#define PHYS_SDRAM_1 0x00000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ + +#endif /* __CONFIG_TK71_H__ */ -- cgit v0.10.2 From f8b9d1d30ece82abccefac3c860c06f8b7da8fbb Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Mon, 25 Jun 2012 02:40:57 +0000 Subject: arm: bugfix: Move vector table before jumping relocated code Interrupts and exceptions doesn't work in relocated code. It badly use IRQ_STACK_START_IN in rom area as interrupt stack. It is because the vecotr table is not moved to ram area. This patch moves vector table before jumping relocated code. Signed-off-by: Tetsuyuki Kobayashi Tested-by: Tom Rini diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 261835b..22a3ced 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -277,6 +277,18 @@ jump_2_ram: mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif +/* + * Move vector table + */ +#if !defined(CONFIG_TEGRA2) +#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + add r0, r0, r9 + mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif +#endif /* !Tegra2 */ + ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 -- cgit v0.10.2 From 702395073fa746f0dcfe6f16f781b4d84645fc40 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 29 May 2012 19:26:41 +0000 Subject: ARM: OMAP3+: Detect reset type Certain modules are not affected by means of a warm reset and need not be configured again. Adding an API to detect the reset reason warm/cold. This will be used to skip the module configurations that are retained across a warm reset. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c index 234e90a..587bb47 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.c +++ b/arch/arm/cpu/armv7/omap-common/reset.c @@ -34,3 +34,8 @@ void __weak reset_cpu(unsigned long ignored) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); } + +u32 __weak warm_reset(void) +{ + return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); +} diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 5a6534e..a027e31 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -53,8 +53,10 @@ /* Reset control */ #ifdef CONFIG_AM33XX #define PRM_RSTCTRL 0x44E00F00 +#define PRM_RSTST 0x44E00F08 #endif #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST_WARM_RESET_MASK 0x232 #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 457f99d..5683e16 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -479,6 +479,8 @@ struct prm { #define PRM_RSTCTRL 0x48307250 #define PRM_RSTCTRL_RESET 0x04 +#define PRM_RSTST 0x48307258 +#define PRM_RSTST_WARM_RESET_MASK 0x7D2 #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 2a89e56..9e52b12 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,4 +74,5 @@ void power_init_r(void); void dieid_num_r(void); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_gp_romcode_call(u32 service_id, u32 parameter); +u32 warm_reset(void); #endif diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index feddb7d..a8c4c60 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -178,5 +178,7 @@ struct watchdog { #define PRM_RSTCTRL PRM_DEVICE_BASE #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x07EA #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index c6e3ad2..4f0a29d 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,6 +57,7 @@ void init_omap_revision(void); void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 8ef17c9..5e62013 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -182,5 +182,7 @@ struct watchdog { #define PRM_RSTCTRL PRM_DEVICE_BASE #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x7FEA #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 8396a22..b3bbdb7 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -57,6 +57,7 @@ void init_omap_revision(void); void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); /* * This is used to verify if the configuration header -- cgit v0.10.2 From 784229cc25feee0bb3f2bba6c1318f4d73c293e0 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 29 May 2012 19:26:42 +0000 Subject: OMAP4+: Handle sdram init after warm reset EMIF and DDR device state are preserved in warmreset. Redoing the full initialisation would cause unexpected behaviour. Do only partial initialisation to account for frequency change. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Signed-off-by: Senthilvadivu Guruswamy diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 23cf619..edc63fa 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -990,7 +990,7 @@ struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, return NULL; /* Do the minimum init for mode register accesses */ - if (!running_from_sdram()) { + if (!(running_from_sdram() || warm_reset())) { phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); writel(phy, &emif->emif_ddr_phy_ctrl_1); } @@ -1070,7 +1070,7 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!in_sdram) { + if (!(in_sdram || warm_reset())) { if (omap_revision() != OMAP5432_ES1_0) lpddr2_init(base, regs); else @@ -1242,7 +1242,7 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!in_sdram) { + if (!(in_sdram || warm_reset())) { if (omap_rev != OMAP5432_ES1_0) bypass_dpll(&prcm->cm_clkmode_dpll_core); else @@ -1252,8 +1252,10 @@ void sdram_init(void) do_sdram_init(EMIF1_BASE); do_sdram_init(EMIF2_BASE); - if (!in_sdram) { + if (!in_sdram) dmm_init(DMM_BASE); + + if (!(in_sdram || warm_reset())) { emif_post_init_config(EMIF1_BASE); emif_post_init_config(EMIF2_BASE); } -- cgit v0.10.2 From 38f25b125e446ab4a64a54e9aa2c10023d8eccc3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 29 May 2012 19:26:43 +0000 Subject: OMAP4+: Force DDR in self-refresh after warm reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Errata ID:i727 Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0] REG_REFRESH_RATE parameter taking into account frequency of the device. When a warm reset is applied on the system, the OMAP processor restarts with another OPP and so frequency is not the same. Due to this frequency change, the refresh rate will be too low and could result in an unexpected behavior on the memory side. Workaround: The workaround is to force self-refresh when coming back from the warm reset with the following sequence: • Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 • Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0 • Do a dummy read (loads automatically new value of sr_tim) This will reduce the risk of memory content corruption, but memory content can't be guaranteed after a warm reset. This errata is impacted on OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3 OMAP4460: 1.0, 1.1 OMAP4470: 1.0 OMAP5430: 1.0 Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Signed-off-by: Senthilvadivu Guruswamy diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index edc63fa..64427e6 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -32,6 +32,27 @@ #include #include +void set_lpmode_selfrefresh(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 reg; + + reg = readl(&emif->emif_pwr_mgmt_ctrl); + reg &= ~EMIF_REG_LP_MODE_MASK; + reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; + reg &= ~EMIF_REG_SR_TIM_MASK; + writel(reg, &emif->emif_pwr_mgmt_ctrl); + + /* dummy read for the new SR_TIM to be loaded */ + readl(&emif->emif_pwr_mgmt_ctrl); +} + +void force_emif_self_refresh() +{ + set_lpmode_selfrefresh(EMIF1_BASE); + set_lpmode_selfrefresh(EMIF2_BASE); +} + inline u32 emif_num(u32 base) { if (base == EMIF1_BASE) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 6600323..459ebb5 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -111,6 +111,10 @@ static void init_boot_params(void) void s_init(void) { init_omap_revision(); +#ifdef CONFIG_SPL_BUILD + if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) + force_emif_self_refresh(); +#endif watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 4f0a29d..d633573 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -58,6 +58,7 @@ void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); +void force_emif_self_refresh(void); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index b3bbdb7..74feb90 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -58,6 +58,7 @@ void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); +void force_emif_self_refresh(void); /* * This is used to verify if the configuration header -- cgit v0.10.2 From 55c1284942b18cf83a297d33c8746aadcbf5f096 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 30 May 2012 07:38:07 +0000 Subject: omap: emif: deal with rams that return duplicate mr data on all byte lanes Some rams (Micron for example) return duplicate mr data on all byte lanes. Users of the get_mr function currently don't deal with this duplicated data gracefully. This patch detects the duplicated data and returns only the expected 8 bit mr data. Signed-off-by: Steve Sakoman diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 64427e6..61ade4c 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -77,7 +77,12 @@ static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) mr = readl(&emif->emif_lpddr2_mode_reg_data); debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), cs, mr_addr, mr); - return mr; + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; } static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) -- cgit v0.10.2 From ad0878a7492928696a93245c1f9190d51eebe549 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 30 May 2012 07:38:08 +0000 Subject: omap: emif: fix bug in manufacturer code test Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so Micron memory will not be detected! Signed-off-by: Steve Sakoman diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 61ade4c..7c2352c 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -947,7 +947,7 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs, } mr = get_mr(base, cs, LPDDR2_MR5); - if (mr >= 0xFF) { + if (mr > 0xFF) { /* Mode register value bigger than 8 bit */ return 0; } -- cgit v0.10.2 From f2b37a6533cfc45af53cdd1f5c721a6f64c0d7da Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 30 May 2012 07:46:00 +0000 Subject: omap: am33xx: accomodate input clocks other than 24 Mhz The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index abc5b6b..d748dd2 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -19,16 +19,16 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ -#define OSC 24 +#define OSC (V_OSCK/1000000) /* MAIN PLL Fdll = 550 MHZ, */ #define MPUPLL_M 550 -#define MPUPLL_N 23 +#define MPUPLL_N (OSC-1) #define MPUPLL_M2 1 /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 -#define COREPLL_N 23 +#define COREPLL_N (OSC-1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ @@ -40,13 +40,13 @@ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below */ #define PERPLL_M 960 -#define PERPLL_N 23 +#define PERPLL_N (OSC-1) #define PERPLL_M2 5 /* DDR Freq is 266 MHZ for now */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M 266 -#define DDRPLL_N 23 +#define DDRPLL_N (OSC-1) #define DDRPLL_M2 1 extern void pll_init(void); -- cgit v0.10.2 From b78375a806ed04eb22b963255cfdef8df702de47 Mon Sep 17 00:00:00 2001 From: "Rajashekhara, Sudhakar" Date: Thu, 7 Jun 2012 00:27:44 +0000 Subject: da850/omap-l138: Enable auto negotiation in RMII mode On DA850/OMAP-L138 it was observed that in RMII mode, auto negotiation was not performed. This patch enables auto negotiation in RMII mode. Without this patch, EMAC initialization takes more time and sometimes tftp fails in RMII mode. Signed-off-by: Rajashekhara, Sudhakar Signed-off-by: Lad, Prabhakar Signed-off-by: Hadli, Manjunath diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index e471d2c..b2516d1 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -895,5 +895,13 @@ int davinci_emac_initialize(void) miiphy_register(phy[i].name, davinci_mii_phy_read, davinci_mii_phy_write); } + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + for (i = 0; i < num_phy; i++) { + if (phy[i].is_phy_connected(i)) + phy[i].auto_negotiate(i); + } +#endif return(1); } -- cgit v0.10.2 From cc009defa4211aa58b3387b59d568cf8ea863ef4 Mon Sep 17 00:00:00 2001 From: Sebastien Jan Date: Wed, 13 Jun 2012 05:16:40 +0000 Subject: omap4: Use a smaller M,N couple for IVA DPLL This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c568951..1d92e66 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ -- cgit v0.10.2 From 254763822e966b6c630d78dc17018b97a50d8f6e Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Jun 2012 03:40:23 +0000 Subject: ARM: OMAP4+: Move external phy initialisations to arch specific place. The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 7c2352c..30dcf1b 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -31,6 +31,7 @@ #include #include #include +#include void set_lpmode_selfrefresh(u32 base) { @@ -140,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs) static void lpddr2_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - u32 i = 0; /* Not NVM */ clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); @@ -160,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) writel(regs->sdram_config_init, &emif->emif_sdram_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); - - if (omap_revision() >= OMAP5430_ES1_0) { - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - - /* - * external phy 6-24 registers do not change with - * ddr frequency - */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - } - } + do_ext_phy_settings(base, regs); do_lpddr2_init(base, CS0); if (regs->sdram_config & EMIF_REG_EBANK_MASK) @@ -194,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) /* Enable refresh now */ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + } + +__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ } void emif_update_timings(u32 base, const struct emif_regs *regs) diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index 239ad2b..b9128fa 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -91,7 +91,6 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { }; /* Dummy registers for OMAP44xx */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 817f933..6ebdf5f 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -204,6 +204,37 @@ void emif_get_device_details(u32 emif_nr, #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } +} + #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .max_freq = 532000000, diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index c2ad877..674c3de 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1141,6 +1141,8 @@ void emif_get_device_timings(u32 emif_nr, const struct lpddr2_device_timings **cs1_device_timings); #endif +void do_ext_phy_settings(u32 base, const struct emif_regs *regs); + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; extern u32 *const T_den; -- cgit v0.10.2 From dbf8fb6ad1fc8b1708e0460bf3b5b7b2035badea Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Jun 2012 19:53:30 +0000 Subject: ARM: OMAP4/5: Move gpmc clocks to essential group. GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 1d92e66..484a96a 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -354,6 +354,7 @@ void enable_basic_clocks(void) }; u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_memif_emif_1_clkctrl, &prcm->cm_memif_emif_2_clkctrl, &prcm->cm_l4cfg_l4_cfg_clkctrl, @@ -452,7 +453,6 @@ void enable_non_essential_clocks(void) }; u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index 65dc5c7..d553d12 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -317,6 +317,7 @@ void enable_basic_clocks(void) }; u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_memif_emif_1_clkctrl, &prcm->cm_memif_emif_2_clkctrl, &prcm->cm_l4cfg_l4_cfg_clkctrl, @@ -427,7 +428,6 @@ void enable_non_essential_clocks(void) &prcm->cm_ivahd_ivahd_clkctrl, &prcm->cm_ivahd_sl2_clkctrl, &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, -- cgit v0.10.2 From 5e9cd44ca08a03fdf1b8271f265981bc0a038c8d Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Jun 2012 19:53:31 +0000 Subject: ARM: OMAP4/5: Move USB clocks to essential group. USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 484a96a..5bd0a88 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -364,9 +364,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gpio4_clkctrl, &prcm->cm_l4per_gpio5_clkctrl, &prcm->cm_l4per_gpio6_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_clksel_usb_60mhz, - &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -377,7 +374,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gptimer2_clkctrl, &prcm->cm_wkup_wdtimer2_clkctrl, &prcm->cm_l4per_uart3_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -414,6 +410,9 @@ void enable_basic_uboot_clocks(void) u32 *const clk_modules_hw_auto_essential[] = { &prcm->cm_l3init_hsusbotg_clkctrl, &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_clksel_usb_60mhz, + &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -423,6 +422,7 @@ void enable_basic_uboot_clocks(void) &prcm->cm_l4per_i2c2_clkctrl, &prcm->cm_l4per_i2c3_clkctrl, &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -457,7 +457,6 @@ void enable_non_essential_clocks(void) &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -497,7 +496,6 @@ void enable_non_essential_clocks(void) &prcm->cm_cam_fdif_clkctrl, &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index d553d12..eecfbad 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -394,6 +394,9 @@ void enable_basic_uboot_clocks(void) &prcm->cm_l4per_i2c2_clkctrl, &prcm->cm_l4per_i2c3_clkctrl, &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_l3init_hsusbtll_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, + &prcm->cm_l3init_fsusb_clkctrl, 0 }; @@ -432,7 +435,6 @@ void enable_non_essential_clocks(void) &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, &prcm->cm_l4per_hdq1w_clkctrl, 0 }; @@ -471,8 +473,6 @@ void enable_non_essential_clocks(void) &prcm->cm_cam_fdif_clkctrl, &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, - &prcm->cm_l3init_fsusb_clkctrl, 0 }; -- cgit v0.10.2 From 1a89a217f5c5ab3645c80c1247e8911a8b5ad491 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Jun 2012 19:53:32 +0000 Subject: ARM: OMAP4/5: Move USB pads to essential list. USB module pads are getting enabled under non-essential group. These will be required for fastboot, tftp support. So move this to essential list to have them working when non-essential pads are no more muxed. Signed-off-by: R Sricharan diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h index 296eb68..a82795d 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_evm/mux_data.h @@ -47,6 +47,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ + {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ + {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ + {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ + {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ }; @@ -114,10 +123,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ - {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ - {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ - {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ @@ -254,11 +259,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ - {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ - {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ - {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ - {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 6140b99..0760dad 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -53,8 +53,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ -{UART3_TX_IRTX, (M0)} /* uart3_tx */ - +{UART3_TX_IRTX, (M0)}, /* uart3_tx */ +{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ +{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ +{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ +{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ +{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ +{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ +{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ +{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ +{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ +{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ }; const struct pad_conf_entry wkup_padconf_array_essential[] = { @@ -135,14 +145,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ - {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ - {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ - {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ @@ -210,9 +212,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ -- cgit v0.10.2 From f3f98bb0b8cc520e08ea2bdfc3f9cbe4e4ac29f5 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Jun 2012 19:53:33 +0000 Subject: ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls. Currently on OMAP4/5 platforms, many kernel drivers are dependent upon the bootloaders for mux, dpll and clock configurations. This should not be the case and bootloaders should set only the minimum required for the uboot functionality and kernel boot. Note that this is going to break the kernel drivers. But this is the only way to get things fixed in the kernel. Signed-off-by: R Sricharan diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index e7a3de5..2192c2b 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -120,9 +120,6 @@ /* Flash */ #define CONFIG_SYS_NO_FLASH 1 -/* clocks */ -#define CONFIG_SYS_CLOCKS_ENABLE_ALL - /* commands to include */ #include @@ -283,8 +280,6 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SYS_ENABLE_PADS_ALL - #define CONFIG_SYS_THUMB_BUILD #endif /* __CONFIG_OMAP4_COMMON_H */ diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 8378387..c5874bb 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -50,8 +50,6 @@ /* Clock Defines */ #define V_OSCK 19200000 /* Clock output from T2 */ #define V_SCLK V_OSCK -#define CONFIG_SYS_CLOCKS_ENABLE_ALL 1 /* Enable all clocks */ -#define CONFIG_SYS_ENABLE_PADS_ALL 1 /* Enable all PADS for now */ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R -- cgit v0.10.2 From 816e3921480d216c415a7c27ac4e0bf62004db1d Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 2 Jul 2012 02:27:59 +0000 Subject: cm-t35: fix incorrect NAND_ECC layout selection The current configuration selects an incorrect NAND ECC layout, which causes u-boot to write HW ECC data incorrectly. This patch selects the right layout. Signed-off-by: Nikita Kiryanov diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index b97e887..ee4bce5 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -174,7 +174,7 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_ECC_LP_x8_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -- cgit v0.10.2 From fa042186b932e9b9ee9a2fd8a04a3acf7c70d224 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 28 Jun 2012 23:36:21 +0000 Subject: arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0 save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). Signed-off-by: Tetsuyuki Kobayashi Acked-by: Tom Rini diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index c6fa8ef..9eb484a 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -36,9 +36,15 @@ #include #include #include +#include -void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) +void __naked save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) { + /* + * Stack pointer is not yet initialized + * Don't save anything to stack even if compiled with -O0 + */ + asm("bx lr"); } void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) -- cgit v0.10.2 From 8170aefc84b04af1e5bd217b04aef81a047f8d28 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Jul 2012 05:37:46 +0000 Subject: arm/km: add kmnusa board support This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have. Some other details: - IVM EEPROM is at adress: pca9547:70:9 - PCI is enabled - PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/MAINTAINERS b/MAINTAINERS index ce9fc9d..864a827 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -740,6 +740,7 @@ Sergey Lapin Valentin Longchamp km_kirkwood ARM926EJS (Kirkwood SoC) + kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index cb3402b..e77c5ad 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -134,10 +134,11 @@ int startup_allowed(void) } #endif -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \ + defined(CONFIG_KM_PIGGY4_88E6352)) /* - * These two boards have always ethernet present. Its connected to the mv - * switch. + * All boards with PIGGY4 connected via a simple switch have ethernet always + * present. */ int ethernet_present(void) { diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg new file mode 100644 index 0000000..bcce907 --- /dev/null +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15] + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay + +DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) + +DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index a423555..64b5dbc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -142,6 +142,7 @@ lschlv2 arm arm926ejs lsxl buffalo lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index b14093f..60e2450 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif + #include "asm/arch/config.h" #define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ @@ -211,6 +218,15 @@ int get_scl(void); /* * Environment variables configurations */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */ +#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ +#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ +#else #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 #define CONFIG_ENV_EEPROM_IS_ON_I2C @@ -218,11 +234,11 @@ int get_scl(void); #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) #define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO @@ -248,17 +264,27 @@ int get_scl(void); "sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};\0" -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " xstr(CONFIG_ENV_OFFSET) " " \ + xstr(CONFIG_ENV_TOTAL_SIZE)"\0" +#else +#define CONFIG_KM_NEW_ENV \ "newenv=setenv addr 0x100000 && " \ "i2c dev 1; mw.b ${addr} 0 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" +#endif + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_NEW_ENV \ "arch=arm\0" \ "EEprom_ivm=" KM_IVM_BUS "\0" \ "" diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index f639edc..34dd0a6 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -6,8 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de + * (C) Copyright 2011-2012 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com * * See file CREDITS for list of people who contributed to this * project. @@ -36,23 +37,67 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ #if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #undef CONFIG_KIRKWOOD_PCIE_INIT +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile NUSA" +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG +#define CONFIG_KM_PIGGY4_88E6352 + +#else +#error ("Board unsupported") #endif +/* include common defines/options for all arm based Keymile boards */ +#include "km/km_arm.h" + #define CONFIG_HOSTNAME km_kirkwood -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#endif + +#if defined(CONFIG_KM_PIGGY4_88E6352) +/* + * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via + * an Marvell 88E6352 simple switch. + * In this case we have to change the default settings for the etherent mac. + * There is NO ethernet phy. The ARM and Switch are conencted directly over + * RGMII in MAC-MAC mode + * In this case 1GBit full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_1000 |\ + MVGBE_SET_MII_SPEED_TO_100) + +#endif /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ #define KM_XLX_PROGRAM_B_PIN 39 -- cgit v0.10.2 From d9354530fe3a891718e3a9b88a756545c3891475 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Jul 2012 05:05:02 +0000 Subject: arm/km: add kmcoge5un board support For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/MAINTAINERS b/MAINTAINERS index 864a827..e42a327 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -742,6 +742,7 @@ Valentin Longchamp km_kirkwood ARM926EJS (Kirkwood SoC) kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) + kmcoge5un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC) Nishanth Menon diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index e77c5ad..73ddb61 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -457,7 +457,11 @@ int get_scl(void) int post_hotkeys_pressed(void) { +#if defined(CONFIG_KM_COGE5UN) + return kw_gpio_get_value(KM_POST_EN_L); +#else return !kw_gpio_get_value(KM_POST_EN_L); +#endif } ulong post_word_load(void) diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg new file mode 100644 index 0000000..3e1237b --- /dev/null +++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com +# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ?, Reserved +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ?,Reserved + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM +# bit 30-28: 3, required +# bit 31: 0, no additional STARTBURST delay + +DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles +# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles +# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles +# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles +# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles +# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles + +DATA 0xFFD0140C 0x0000003E # DDR Timing (High) +# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit 1-0: 0, Cs0width=x8 (2 devices) +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strenght reduced +# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for > 266Mhz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24:0x1F, Size (i.e. 512MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 1, ODT1 never active +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 64b5dbc..808f85b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -144,6 +144,7 @@ km_kirkwood arm arm926ejs km_arm keymile km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood +kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 34dd0a6..d839a02 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -39,15 +39,18 @@ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_HOSTNAME km_kirkwood #undef CONFIG_KIRKWOOD_PCIE_INIT #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_HOSTNAME km_kirkwood_pci #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ #define CONFIG_IDENT_STRING "\nKeymile NUSA" +#define CONFIG_HOSTNAME kmnusa #undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg @@ -55,6 +58,17 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352 +#elif defined(CONFIG_KM_COGE5UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE5UN" +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_HOSTNAME kmcoge5un +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6352 #else #error ("Board unsupported") #endif @@ -62,8 +76,6 @@ /* include common defines/options for all arm based Keymile boards */ #include "km/km_arm.h" -#define CONFIG_HOSTNAME km_kirkwood - #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ #endif -- cgit v0.10.2 From f945439af9198be07a32f8799e96df60ae1b0adb Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Jul 2012 05:05:03 +0000 Subject: arm/km: convert mgcoge3un target to km_kirkwood Use the generic header km_kirkwood.h and get rid of the board specific header. changes for v2: rebased because of changes in other patches Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 73ddb61..831cbd9 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -114,7 +114,7 @@ u32 kwmpp_config[] = { 0 }; -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ @@ -134,8 +134,7 @@ int startup_allowed(void) } #endif -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \ - defined(CONFIG_KM_PIGGY4_88E6352)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) /* * All boards with PIGGY4 connected via a simple switch have ethernet always * present. @@ -203,7 +202,7 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); if (wait_for_ne != NULL) { @@ -318,7 +317,7 @@ void dram_init_banksize(void) } } -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2)) #define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index 808f85b..003c2af 100644 --- a/boards.cfg +++ b/boards.cfg @@ -143,7 +143,7 @@ lsxhl arm arm926ejs lsxl buffalo km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA -mgcoge3un arm arm926ejs km_arm keymile kirkwood +mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index d839a02..f5b9d27 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -58,6 +58,20 @@ #define CONFIG_KM_FPGA_CONFIG #define CONFIG_KM_PIGGY4_88E6352 +/* KM_MGCOGE3UN */ +#elif defined(CONFIG_KM_MGCOGE3UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE3UN" +#define CONFIG_HOSTNAME mgcoge3un +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6061 + +/* KMCOGE5UN */ #elif defined(CONFIG_KM_COGE5UN) #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ @@ -111,7 +125,39 @@ #endif +#ifdef CONFIG_KM_PIGGY4_88E6061 +/* + * Some keymile boards like mgcoge3un have their PIGGY4 connected via + * an Marvell 88E6061 simple switch. + * In this case we have to change the default settings for the + * ethernet phy connected to the kirkwood. + * In this case 100MB full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) +#endif + /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ #define KM_XLX_PROGRAM_B_PIN 39 +#ifdef CONFIG_KM_DISABLE_PCI +#undef CONFIG_KIRKWOOD_PCIE_INIT +#endif #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h deleted file mode 100644 index 156821c..0000000 --- a/include/configs/mgcoge3un.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Prafulla Wadaskar - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_MGCOGE3UN_H -#define _CONFIG_MGCOGE3UN_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN" -#define CONFIG_HOSTNAME mgcoge3un -#define CONFIG_MGCOGE3UN - -#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ -#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ - -/* we use a new RAM type on mgcoge3un board */ -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg - -/* - * mgcoge3un has a fixed link to the marvell switch - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" -#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 - -/* - * PCIe port not used on mgcoge3un - */ -#undef CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_MGCOGE3UN_H */ -- cgit v0.10.2 From 6ef6486180678ab86d511676ec68cf78bf267582 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Jul 2012 05:05:04 +0000 Subject: arm/km: remove portl2.h and use km_kirkwood instead The additional headerfile is unneeded here, we can use the generic km_kirkwood.h instead. And we can use the better config option KM_PIGGY4_88E6061 for the specific features for boards with this design in km_arm.c. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 831cbd9..daab27b 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -317,7 +317,7 @@ void dram_init_banksize(void) } } -#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)) #define PHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index 003c2af..db7902f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -145,7 +145,7 @@ km_kirkwood_pci arm arm926ejs km_arm keymile kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN -portl2 arm arm926ejs km_arm keymile kirkwood +portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index f5b9d27..44a3e7a 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -83,6 +83,14 @@ #define CONFIG_HOSTNAME kmcoge5un #define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_PIGGY4_88E6352 + +/* KM_PORTL2 */ +#elif defined(CONFIG_KM_PORTL2) +#define CONFIG_IDENT_STRING "\nKeymile Port-L2" +#define CONFIG_HOSTNAME portl2 +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_PIGGY4_88E6061 + #else #error ("Board unsupported") #endif diff --git a/include/configs/portl2.h b/include/configs/portl2.h deleted file mode 100644 index e436cfe..0000000 --- a/include/configs/portl2.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Prafulla Wadaskar - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. - * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_PORTL2_H -#define _CONFIG_PORTL2_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile Port-L2" -#define CONFIG_HOSTNAME portl2 -#define CONFIG_PORTL2 - -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ -/* - * Note: This is only valid for HW > P1A if you got an outdated P1A - * use KM_ENV_BUS "pca9544a:70:a" - */ -#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ - -/* - * portl2 has a fixed link to the XMPP backplane - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -/* - * portl2 does use the PCIe Port0 - */ -#define CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_PORTL2_H */ -- cgit v0.10.2 From b37f772433ab44d1730423eccf11f287ce61ec5f Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Thu, 5 Jul 2012 05:05:05 +0000 Subject: arm/km: enable BOCO2 FPGA download support This adds a first support of the FPGA download for a PCIe FPGA based on the BOCO2 CPLD. This takes place in 3 steps, all done accessing the SPICTRL reg of the BOCO2: 1) start the FPGA config with an access to the FPGA_PROG bit 2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1 for the end of the FPGA configuration (with a timeout) 3) reset the FPGA 4) finally remove the access to its config EEPROM from the FPGA so that the CPU can update the FPGA configuration when the kernel is running The boards with a PCIe FPGA but without BOCO2 still are supported. The config option name is CONFIG_KM_FPGA_CONFIG Signed-off-by: Valentin Longchamp Signed-off-by: Holger Brunck cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index f457aa3..aab706e 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -131,6 +131,11 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void); +int trigger_fpga_config(void); +int wait_for_fpga_config(void); +int fpga_reset(void); +int toggle_eeprom_spi_bus(void); + int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index aa51255..13d485a 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o ../common/common.o ../common/ivm.o +ifdef CONFIG_KM_FPGA_CONFIG +COBJS += fpga_config.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c new file mode 100644 index 0000000..4356b9a --- /dev/null +++ b/board/keymile/km_arm/fpga_config.c @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include + +/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ +#define KM_XLX_PROGRAM_B_PIN 39 + +#define BOCO_ADDR 0x10 + +#define ID_REG 0x00 +#define BOCO2_ID 0x5b + +static int check_boco2(void) +{ + int ret; + u8 id; + + ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); + if (ret) { + printf("%s: error reading the BOCO id !!\n", __func__); + return ret; + } + + return (id == BOCO2_ID); +} + +static int boco_clear_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval &= ~flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +static int boco_set_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval |= flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +#define SPI_REG 0x06 +#define CFG_EEPROM 0x02 +#define FPGA_PROG 0x04 +#define FPGA_DONE 0x20 + +int trigger_fpga_config(void) +{ + int ret = 0; + + if (check_boco2()) { + /* we have a BOCO2, this has to be triggered here */ + + /* make sure the FPGA_can access the EEPROM */ + ret = boco_clear_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + /* trigger the config start */ + ret = boco_clear_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + /* up signal for pulse end */ + ret = boco_set_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + } else { + /* we do it the old way, with the gpio pin */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + /* small delay for the pulse */ + udelay(10); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + } + + return 0; +} + +int wait_for_fpga_config(void) +{ + int ret = 0; + u8 spictrl; + u32 timeout = 20000; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe FPGA config:"); + do { + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); + if (ret) { + printf("%s: error reading the BOCO spictrl !!\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + return -EFAULT; + } + udelay(10); + } while (!(spictrl & FPGA_DONE)); + + printf(" done\n"); + + return 0; +} + +#define PRST1 0x4 +#define BRIDGE_RST 0x4 + +int fpga_reset(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_clear_bits(PRST1, BRIDGE_RST); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + ret = boco_set_bits(PRST1, BRIDGE_RST); + if (ret) + return ret; + + return 0; +} + +/* the FPGA was configured, we configure the BOCO2 so that the EEPROM + * is available from the Bobcat SPI bus */ +int toggle_eeprom_spi_bus(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_set_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + return 0; +} + diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index daab27b..c8da823 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -268,12 +268,6 @@ int board_early_init_f(void) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif -#if defined(CONFIG_KM_RECONFIG_XLX) - /* trigger the reconfiguration of the xilinx fpga */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); -#endif return 0; } @@ -282,6 +276,21 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; +#if defined(CONFIG_KM_FPGA_CONFIG) + trigger_fpga_config(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_KM_FPGA_CONFIG) + wait_for_fpga_config(); + fpga_reset(); + toggle_eeprom_spi_bus(); +#endif + return 0; } diff --git a/boards.cfg b/boards.cfg index db7902f..26c0a99 100644 --- a/boards.cfg +++ b/boards.cfg @@ -141,7 +141,7 @@ dns325 arm arm926ejs - d-link lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 60e2450..1a5f04b 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -313,4 +313,7 @@ int get_scl(void); #define CONFIG_POST_EXTERNAL_WORD_FUNCS #define CONFIG_CMD_DIAG +/* we do the whole PCIe FPGA config stuff here */ +#define BOARD_LATE_INIT + #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 44a3e7a..0a61b7d 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -162,10 +162,12 @@ MVGBE_SET_MII_SPEED_TO_100) #endif -/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39 - #ifdef CONFIG_KM_DISABLE_PCI #undef CONFIG_KIRKWOOD_PCIE_INIT #endif + +#ifndef CONFIG_KM_FPGA_CONFIG +#undef BOARD_LATE_INIT +#endif + #endif /* _CONFIG_KM_KIRKWOOD */ -- cgit v0.10.2 From 48ced62cfb1722c97b6e598036b4e204980c4c47 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Jul 2012 05:05:06 +0000 Subject: arm/km: cleanup km_kirkwood boards Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Gerlando Falauto cc: Prafulla Wadaskar diff --git a/boards.cfg b/boards.cfg index 26c0a99..a864ac5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,8 +140,8 @@ pogo_e02 arm arm926ejs - clouden dns325 arm arm926ejs - d-link kirkwood lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 0a61b7d..a95c665 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -37,15 +37,20 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H +/* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" #define CONFIG_HOSTNAME km_kirkwood -#undef CONFIG_KIRKWOOD_PCIE_INIT +#define CONFIG_KM_DISABLE_PCIE #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ + +/* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" #define CONFIG_HOSTNAME km_kirkwood_pci #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_FPGA_CONFIG + /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ -- cgit v0.10.2 From c1b8514a7a94b6b7e4e2bd779ecda16c86248299 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Thu, 5 Jul 2012 05:05:07 +0000 Subject: arm/km: redefine piggy 4 reg names to avoid conflicts Some very similar #defines for reg addresses are used in a later patch (managed_switch support for km_arm). Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index c8da823..ed2454f 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -328,13 +328,13 @@ void dram_init_banksize(void) #if (defined(CONFIG_KM_PIGGY4_88E6061)) -#define PHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL 0x1c +#define PHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) +#define PHY_CLSA (0x1<<1) /* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -346,15 +346,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ -- cgit v0.10.2 From bcac5b1b2c4f5f44a512dee7b0ac9ed64fd0bed0 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Thu, 5 Jul 2012 05:05:08 +0000 Subject: arm/km: skip FPGA config when already configured In order to be able to perform board resets without interrupting the traffic, the configuration of an already properly configured FPGA is skipped. This is because some PCIe FPGAs embed some other function that must continue to work over reset. It is then the responsibility of the application to trigger a reconfiguration when needed. This is done by lowering the FPGA_INIT_B pin for delaying the configuration to u-boot @ next reboot, and then lower the FPGA_PROGRAM_B signal. Signed-off-by: Valentin Longchamp diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 4356b9a..8ac6393 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -96,12 +96,43 @@ static int boco_set_bits(u8 reg, u8 flags) #define SPI_REG 0x06 #define CFG_EEPROM 0x02 #define FPGA_PROG 0x04 +#define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20 +static int fpga_done() +{ + int ret = 0; + u8 regval; + + /* this is only supported with the boco2 design */ + if (!check_boco2()) + return 0; + + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, SPI_REG); + return 0; + } + + return regval & FPGA_DONE ? 1 : 0; +} + +int skip; + int trigger_fpga_config(void) { int ret = 0; + /* if the FPGA is already configured, we do not want to + * reconfigure it */ + skip = 0; + if (fpga_done()) { + printf("PCIe FPGA config: skipped\n"); + skip = 1; + return 0; + } + if (check_boco2()) { /* we have a BOCO2, this has to be triggered here */ @@ -111,7 +142,7 @@ int trigger_fpga_config(void) return ret; /* trigger the config start */ - ret = boco_clear_bits(SPI_REG, FPGA_PROG); + ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B); if (ret) return ret; @@ -123,6 +154,11 @@ int trigger_fpga_config(void) if (ret) return ret; + /* finally, raise INIT_B to remove the config delay */ + ret = boco_set_bits(SPI_REG, FPGA_INIT_B); + if (ret) + return ret; + } else { /* we do it the old way, with the gpio pin */ kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); @@ -141,6 +177,9 @@ int wait_for_fpga_config(void) u8 spictrl; u32 timeout = 20000; + if (skip) + return 0; + if (!check_boco2()) { /* we do not have BOCO2, this is not really used */ return 0; -- cgit v0.10.2 From dbdee4ca591a3bf19446d8ab89285835e210b378 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Thu, 5 Jul 2012 05:05:09 +0000 Subject: arm/km: support the 2 PCIe fpga resets The PCIe FPGAs now have to support 2 resets: one for the non traffic affecting part (PCIe) and one for the traffic affecting part. When the FPGA is not reconfigured, we only reset the PCIe part. Signed-off-by: Valentin Longchamp diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c index 8ac6393..fcc5fe6 100644 --- a/board/keymile/km_arm/fpga_config.c +++ b/board/keymile/km_arm/fpga_config.c @@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags) #define FPGA_INIT_B 0x10 #define FPGA_DONE 0x20 -static int fpga_done() +static int fpga_done(void) { int ret = 0; u8 regval; @@ -206,25 +206,30 @@ int wait_for_fpga_config(void) } #define PRST1 0x4 -#define BRIDGE_RST 0x4 +#define PCIE_RST 0x10 +#define TRAFFIC_RST 0x04 int fpga_reset(void) { int ret = 0; + u8 resets; if (!check_boco2()) { /* we do not have BOCO2, this is not really used */ return 0; } - ret = boco_clear_bits(PRST1, BRIDGE_RST); + /* if we have skipped, we only want to reset the PCIe part */ + resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; + + ret = boco_clear_bits(PRST1, resets); if (ret) return ret; /* small delay for the pulse */ udelay(10); - ret = boco_set_bits(PRST1, BRIDGE_RST); + ret = boco_set_bits(PRST1, resets); if (ret) return ret; -- cgit v0.10.2 From b8cf7cc8860d30b85b08377183688bf9564896bf Mon Sep 17 00:00:00 2001 From: Thomas Herzmann Date: Thu, 5 Jul 2012 05:05:10 +0000 Subject: arm/km: add implementation for read_dip_switch Add a function to read the dip_switch on kmcoge5un. If the switch is set the actual_bank is set to 0 and this SW is booted. Signed-off-by: Thomas Herzmann Signed-off-by: Holger Brunck diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ed2454f..ea5d0db 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -285,12 +285,24 @@ int board_init(void) int board_late_init(void) { +#if defined(CONFIG_KMCOGE5UN) +/* I/O pin to erase flash RGPP09 = MPP43 */ +#define KM_FLASH_ERASE_ENABLE 43 + u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); + + /* if pin 1 do full erase */ + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); + } +#endif + #if defined(CONFIG_KM_FPGA_CONFIG) wait_for_fpga_config(); fpga_reset(); toggle_eeprom_spi_bus(); #endif - return 0; } diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index a95c665..fba181f 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -171,8 +171,5 @@ #undef CONFIG_KIRKWOOD_PCIE_INIT #endif -#ifndef CONFIG_KM_FPGA_CONFIG -#undef BOARD_LATE_INIT -#endif #endif /* _CONFIG_KM_KIRKWOOD */ -- cgit v0.10.2 From c471d84808843dce6174eaab624779aa15ff71bf Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Jul 2012 05:05:11 +0000 Subject: arm/km: remove calls to kw_gpio_* in board_early_init_f These functions tried to access two static tables before relocation (board_early_init_f is executed before relocation). But these static tables lie in the bss section which is not valid before relocation. These accesses then overwrote some parts of u-boot binary before it was relocated. For the kmnusa build, this results in a corrupted important env variable (bootcmd) but it may be that some other parts of the u-boot binary are corrupted. This patch solves this problem by moving all the kw_gpio_* calls to board_init, which should be early enough in the boot sequence. The only calls that could not be moved is the one for the SOFT (bitbang) I2C, and they have been replaced by a direct access to the GPIO dataout Control register to set the two GPIOs as output. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index ea5d0db..2b2ca39 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -243,38 +243,51 @@ int misc_init_r(void) int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp; + /* set the 2 bitbang i2c pins as output gpios */ + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); +#endif + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} +int board_init(void) +{ /* - * The FLASH_GPIO_PIN switches between using a + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; + + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + /* + * The KM_FLASH_GPIO_PIN switches between using a * NAND or a SPI FLASH. Set this pin on start * to NAND mode. */ - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); #if defined(CONFIG_SOFT_I2C) - /* init the GPIO for I2C Bitbang driver */ + /* + * Reinit the GPIO for I2C Bitbang driver so that the now + * available gpio framework is consistent. The calls to + * direction output in are not necessary, they are already done in + * board_early_init_f + */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); - kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); - kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif + #if defined(CONFIG_SYS_EEPROM_WREN) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; #if defined(CONFIG_KM_FPGA_CONFIG) trigger_fpga_config(); diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 1a5f04b..3aa5ca1 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -192,6 +192,7 @@ int get_sda(void); int get_scl(void); #define KM_KIRKWOOD_SDA_PIN 8 #define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 #define KM_KIRKWOOD_ENV_WP 38 #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) -- cgit v0.10.2 From 7f0730a02e412015b0fc4e78dc41aef14e8a3d8c Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Tue, 22 May 2012 00:15:54 +0000 Subject: mtd/NAND: Add FSMC driver support Flexible static memory controller is a peripheral provided by ST, which controls the access to NAND chips along with many other memory device chips eg NOR, SRAM. This patch adds the driver support for FSMC controller interfacing with NAND memory. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese Acked-by: Scott Wood diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 1d1b628..29dc20e 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c new file mode 100644 index 0000000..7a61d88 --- /dev/null +++ b/drivers/mtd/nand/fsmc_nand.c @@ -0,0 +1,486 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. + * + * (C) Copyright 2012 + * Amit Virdi, ST Microelectronics, amit.virdi@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static u32 fsmc_version; +static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *) + CONFIG_SYS_FSMC_BASE; + +/* + * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of + * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can + * correct 1 bit in 512 bytes + */ + +static struct nand_ecclayout fsmc_ecc4_lp_layout = { + .eccbytes = 104, + .eccpos = { 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, + 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, + 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, + 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, + 82, 83, 84, 85, 86, 87, 88, + 89, 90, 91, 92, 93, 94, + 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, + 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126 + }, + .oobfree = { + {.offset = 15, .length = 3}, + {.offset = 31, .length = 3}, + {.offset = 47, .length = 3}, + {.offset = 63, .length = 3}, + {.offset = 79, .length = 3}, + {.offset = 95, .length = 3}, + {.offset = 111, .length = 3}, + {.offset = 127, .length = 1} + } +}; + +/* + * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes + * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 + * bytes are free for use. + */ +static struct nand_ecclayout fsmc_ecc4_224_layout = { + .eccbytes = 104, + .eccpos = { 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, + 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, + 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, + 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, + 82, 83, 84, 85, 86, 87, 88, + 89, 90, 91, 92, 93, 94, + 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, + 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126 + }, + .oobfree = { + {.offset = 15, .length = 3}, + {.offset = 31, .length = 3}, + {.offset = 47, .length = 3}, + {.offset = 63, .length = 3}, + {.offset = 79, .length = 3}, + {.offset = 95, .length = 3}, + {.offset = 111, .length = 3}, + {.offset = 127, .length = 97} + } +}; + +/* + * ECC placement definitions in oobfree type format + * There are 13 bytes of ecc for every 512 byte block and it has to be read + * consecutively and immediately after the 512 byte data block for hardware to + * generate the error bit offsets in 512 byte data + * Managing the ecc bytes in the following way makes it easier for software to + * read ecc bytes consecutive to data bytes. This way is similar to + * oobfree structure maintained already in u-boot nand driver + */ +static struct fsmc_eccplace fsmc_eccpl_lp = { + .eccplace = { + {.offset = 2, .length = 13}, + {.offset = 18, .length = 13}, + {.offset = 34, .length = 13}, + {.offset = 50, .length = 13}, + {.offset = 66, .length = 13}, + {.offset = 82, .length = 13}, + {.offset = 98, .length = 13}, + {.offset = 114, .length = 13} + } +}; + +static struct nand_ecclayout fsmc_ecc4_sp_layout = { + .eccbytes = 13, + .eccpos = { 0, 1, 2, 3, 6, 7, 8, + 9, 10, 11, 12, 13, 14 + }, + .oobfree = { + {.offset = 15, .length = 1}, + } +}; + +static struct fsmc_eccplace fsmc_eccpl_sp = { + .eccplace = { + {.offset = 0, .length = 4}, + {.offset = 6, .length = 9} + } +}; + +static struct nand_ecclayout fsmc_ecc1_layout = { + .eccbytes = 24, + .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, + 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, + .oobfree = { + {.offset = 8, .length = 8}, + {.offset = 24, .length = 8}, + {.offset = 40, .length = 8}, + {.offset = 56, .length = 8}, + {.offset = 72, .length = 8}, + {.offset = 88, .length = 8}, + {.offset = 104, .length = 8}, + {.offset = 120, .length = 8} + } +}; + +/* Count the number of 0's in buff upto a max of max_bits */ +static int count_written_bits(uint8_t *buff, int size, int max_bits) +{ + int k, written_bits = 0; + + for (k = 0; k < size; k++) { + written_bits += hweight8(~buff[k]); + if (written_bits > max_bits) + break; + } + + return written_bits; +} + +static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ALE; + + if (ctrl & NAND_NCE) { + writel(readl(&fsmc_regs_p->pc) | + FSMC_ENABLE, &fsmc_regs_p->pc); + } else { + writel(readl(&fsmc_regs_p->pc) & + ~FSMC_ENABLE, &fsmc_regs_p->pc); + } + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + /* The calculated ecc is actually the correction index in data */ + u32 err_idx[8]; + u32 num_err, i; + u32 ecc1, ecc2, ecc3, ecc4; + + num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF; + + if (likely(num_err == 0)) + return 0; + + if (unlikely(num_err > 8)) { + /* + * This is a temporary erase check. A newly erased page read + * would result in an ecc error because the oob data is also + * erased to FF and the calculated ecc for an FF data is not + * FF..FF. + * This is a workaround to skip performing correction in case + * data is FF..FF + * + * Logic: + * For every page, each bit written as 0 is counted until these + * number of bits are greater than 8 (the maximum correction + * capability of FSMC for each 512 + 13 bytes) + */ + + int bits_ecc = count_written_bits(read_ecc, 13, 8); + int bits_data = count_written_bits(dat, 512, 8); + + if ((bits_ecc + bits_data) <= 8) { + if (bits_data) + memset(dat, 0xff, 512); + return bits_data + bits_ecc; + } + + return -EBADMSG; + } + + ecc1 = readl(&fsmc_regs_p->ecc1); + ecc2 = readl(&fsmc_regs_p->ecc2); + ecc3 = readl(&fsmc_regs_p->ecc3); + ecc4 = readl(&fsmc_regs_p->sts); + + err_idx[0] = (ecc1 >> 0) & 0x1FFF; + err_idx[1] = (ecc1 >> 13) & 0x1FFF; + err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); + err_idx[3] = (ecc2 >> 7) & 0x1FFF; + err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); + err_idx[5] = (ecc3 >> 1) & 0x1FFF; + err_idx[6] = (ecc3 >> 14) & 0x1FFF; + err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); + + i = 0; + while (i < num_err) { + err_idx[i] ^= 3; + + if (err_idx[i] < 512 * 8) + __change_bit(err_idx[i], dat); + + i++; + } + + return num_err; +} + +static int fsmc_read_hwecc(struct mtd_info *mtd, + const u_char *data, u_char *ecc) +{ + u_int ecc_tmp; + int timeout = CONFIG_SYS_HZ; + ulong start; + + switch (fsmc_version) { + case FSMC_VER8: + start = get_timer(0); + while (get_timer(start) < timeout) { + /* + * Busy waiting for ecc computation + * to finish for 512 bytes + */ + if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY) + break; + } + + ecc_tmp = readl(&fsmc_regs_p->ecc1); + ecc[0] = (u_char) (ecc_tmp >> 0); + ecc[1] = (u_char) (ecc_tmp >> 8); + ecc[2] = (u_char) (ecc_tmp >> 16); + ecc[3] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->ecc2); + ecc[4] = (u_char) (ecc_tmp >> 0); + ecc[5] = (u_char) (ecc_tmp >> 8); + ecc[6] = (u_char) (ecc_tmp >> 16); + ecc[7] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->ecc3); + ecc[8] = (u_char) (ecc_tmp >> 0); + ecc[9] = (u_char) (ecc_tmp >> 8); + ecc[10] = (u_char) (ecc_tmp >> 16); + ecc[11] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->sts); + ecc[12] = (u_char) (ecc_tmp >> 16); + break; + + default: + ecc_tmp = readl(&fsmc_regs_p->ecc1); + ecc[0] = (u_char) (ecc_tmp >> 0); + ecc[1] = (u_char) (ecc_tmp >> 8); + ecc[2] = (u_char) (ecc_tmp >> 16); + break; + } + + return 0; +} + +void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256, + &fsmc_regs_p->pc); + writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN, + &fsmc_regs_p->pc); + writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN, + &fsmc_regs_p->pc); +} + +/* + * fsmc_read_page_hwecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + * This routine is needed for fsmc verison 8 as reading from NAND chip has to be + * performed in a strict sequence as follows: + * data(512 byte) -> ecc(13 byte) + * After this read, fsmc hardware generates and reports error data bits(upto a + * max of 8 bits) + */ +static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + struct fsmc_eccplace *fsmc_eccpl; + int i, j, s, stat, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *ecc_code = chip->buffers->ecccode; + int off, len, group = 0; + uint8_t oob[13] __attribute__ ((aligned (2))); + + /* Differentiate between small and large page ecc place definitions */ + if (mtd->writesize == 512) + fsmc_eccpl = &fsmc_eccpl_sp; + else + fsmc_eccpl = &fsmc_eccpl_lp; + + for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { + + chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + + for (j = 0; j < eccbytes;) { + off = fsmc_eccpl->eccplace[group].offset; + len = fsmc_eccpl->eccplace[group].length; + group++; + + /* + * length is intentionally kept a higher multiple of 2 + * to read at least 13 bytes even in case of 16 bit NAND + * devices + */ + if (chip->options & NAND_BUSWIDTH_16) + len = roundup(len, 2); + chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); + chip->read_buf(mtd, oob + j, len); + j += len; + } + + memcpy(&ecc_code[i], oob, 13); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], + &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + + return 0; +} + +int fsmc_nand_init(struct nand_chip *nand) +{ + static int chip_nr; + struct mtd_info *mtd; + int i; + u32 peripid2 = readl(&fsmc_regs_p->peripid2); + + fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) & + FSMC_REVISION_MSK; + + writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl); + +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->pc); +#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) + writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->pc); +#else +#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT +#endif + writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1, + &fsmc_regs_p->pc); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->comm); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->attrib); + + nand->options = 0; +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + nand->options |= NAND_BUSWIDTH_16; +#endif + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 512; + nand->ecc.calculate = fsmc_read_hwecc; + nand->ecc.hwctl = fsmc_enable_hwecc; + nand->cmd_ctrl = fsmc_nand_hwcontrol; + nand->IO_ADDR_R = nand->IO_ADDR_W = + (void __iomem *)CONFIG_SYS_NAND_BASE; + nand->badblockbits = 7; + + mtd = &nand_info[chip_nr++]; + mtd->priv = nand; + + switch (fsmc_version) { + case FSMC_VER8: + nand->ecc.bytes = 13; + nand->ecc.correct = fsmc_bch8_correct_data; + nand->ecc.read_page = fsmc_read_page_hwecc; + if (mtd->writesize == 512) + nand->ecc.layout = &fsmc_ecc4_sp_layout; + else { + if (mtd->oobsize == 224) + nand->ecc.layout = &fsmc_ecc4_224_layout; + else + nand->ecc.layout = &fsmc_ecc4_lp_layout; + } + + break; + default: + nand->ecc.bytes = 3; + nand->ecc.layout = &fsmc_ecc1_layout; + nand->ecc.correct = nand_correct_data; + break; + } + + /* Detect NAND chips */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) + return -ENXIO; + + if (nand_scan_tail(mtd)) + return -ENXIO; + + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + if (nand_register(i)) + return -ENXIO; + + return 0; +} diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h new file mode 100644 index 0000000..3a61cea --- /dev/null +++ b/include/linux/mtd/fsmc_nand.h @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSMC_NAND_H__ +#define __FSMC_NAND_H__ + +#include + +struct fsmc_regs { + u32 ctrl; /* 0x00 */ + u8 reserved_1[0x40 - 0x04]; + u32 pc; /* 0x40 */ + u32 sts; /* 0x44 */ + u32 comm; /* 0x48 */ + u32 attrib; /* 0x4c */ + u32 ioata; /* 0x50 */ + u32 ecc1; /* 0x54 */ + u32 ecc2; /* 0x58 */ + u32 ecc3; /* 0x5c */ + u8 reserved_2[0xfe0 - 0x60]; + u32 peripid0; /* 0xfe0 */ + u32 peripid1; /* 0xfe4 */ + u32 peripid2; /* 0xfe8 */ + u32 peripid3; /* 0xfec */ + u32 pcellid0; /* 0xff0 */ + u32 pcellid1; /* 0xff4 */ + u32 pcellid2; /* 0xff8 */ + u32 pcellid3; /* 0xffc */ +}; + +/* ctrl register definitions */ +#define FSMC_WP (1 << 7) + +/* pc register definitions */ +#define FSMC_RESET (1 << 0) +#define FSMC_WAITON (1 << 1) +#define FSMC_ENABLE (1 << 2) +#define FSMC_DEVTYPE_NAND (1 << 3) +#define FSMC_DEVWID_8 (0 << 4) +#define FSMC_DEVWID_16 (1 << 4) +#define FSMC_ECCEN (1 << 6) +#define FSMC_ECCPLEN_512 (0 << 7) +#define FSMC_ECCPLEN_256 (1 << 7) +#define FSMC_TCLR_1 (1 << 9) +#define FSMC_TAR_1 (1 << 13) + +/* sts register definitions */ +#define FSMC_CODE_RDY (1 << 15) + +/* comm register definitions */ +#define FSMC_TSET_0 (0 << 0) +#define FSMC_TWAIT_6 (6 << 8) +#define FSMC_THOLD_4 (4 << 16) +#define FSMC_THIZ_1 (1 << 24) + +/* peripid2 register definitions */ +#define FSMC_REVISION_MSK (0xf) +#define FSMC_REVISION_SHFT (0x4) + +#define FSMC_VER8 0x8 + +/* + * There are 13 bytes of ecc for every 512 byte block and it has to be read + * consecutively and immediately after the 512 byte data block for hardware to + * generate the error bit offsets + * Managing the ecc bytes in the following way is easier. This way is similar to + * oobfree structure maintained already in u-boot nand driver + */ +#define FSMC_MAX_ECCPLACE_ENTRIES 32 + +struct fsmc_nand_eccplace { + u32 offset; + u32 length; +}; + +struct fsmc_eccplace { + struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES]; +}; + +extern int fsmc_nand_init(struct nand_chip *nand); +#endif -- cgit v0.10.2 From 1fa943b99d06fee8b6552f4215923e4681d4a5a4 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Tue, 22 May 2012 00:15:55 +0000 Subject: SPEAr: Configure FSMC driver for NAND interface Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese Acked-by: Scott Wood diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 818f36c..a6517b2 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -37,15 +37,15 @@ #if defined(CONFIG_SPEAR600) #define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) +#define CONFIG_SYS_FSMC_BASE (0xD1800000) #elif defined(CONFIG_SPEAR300) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) +#define CONFIG_SYS_FSMC_BASE (0x94000000) #elif defined(CONFIG_SPEAR310) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) +#define CONFIG_SYS_FSMC_BASE (0x44000000) #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE @@ -57,7 +57,7 @@ #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) +#define CONFIG_SYS_FSMC_BASE (0x4C000000) #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000) diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 60ee544..72a3631 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -24,10 +24,12 @@ #include #include #include +#include #include #include #include -#include + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -41,18 +43,20 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } - - return -1; +#endif + return; } diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 03dfe16..14e666d 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -25,10 +25,12 @@ #include #include #include +#include #include #include #include -#include + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -42,18 +44,20 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } - - return -1; +#endif + return; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 2ba2dbb..994eb2b 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -25,10 +25,12 @@ #include #include #include +#include #include #include #include -#include + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -42,18 +44,21 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif - return -1; + return; } diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index eef9a37..ab0f760 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -24,10 +24,12 @@ #include #include #include +#include #include #include #include -#include + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -41,13 +43,15 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) - return spear_nand_init(nand); - - return -1; + fsmc_nand_init(nand); +#endif + return; } diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index ab1b332..8d0f036 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -88,9 +88,10 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* NAND FLASH Configuration */ +#define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_NAND_SPEAR 1 +#define CONFIG_NAND_FSMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 37bdebb..2a86c21 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -117,6 +117,10 @@ #endif +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT + #if defined(CONFIG_SPEAR300) #define CONFIG_SYS_NAND_BASE (0x80000000) diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h index 2ad5beb..c5bcc30 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx.h @@ -38,6 +38,9 @@ #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1 } +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE (0xD2000000) #endif /* __CONFIG_H */ -- cgit v0.10.2 From 0def98e7be905e4e02eb22cb312bb4e3b327d2fa Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Tue, 22 May 2012 00:15:56 +0000 Subject: mtd/NAND: Remove obsolete SPEAr specific NAND drivers Since, SPEAr platform uses generic FSMC driver now, so spear specific files drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese Acked-by: Scott Wood diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7..0000000 --- a/arch/arm/include/asm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c deleted file mode 100644 index 097d0c6..0000000 --- a/drivers/mtd/nand/spr_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -static struct fsmc_regs *const fsmc_regs_p = - (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE; - -static struct nand_ecclayout spear_nand_ecclayout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->genmemctrl_pc) | - FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } else { - writel(readl(&fsmc_regs_p->genmemctrl_pc) & - ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int spear_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char ecc[3]) -{ - u_int ecc_tmp; - - /* read the h/w ECC */ - ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc); - - ecc[0] = (u_char) (ecc_tmp & 0xFF); - ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8); - ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16); - - return 0; -} - -void spear_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); -} - -int spear_nand_init(struct nand_chip *nand) -{ - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->genmemctrl_pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_attrib); - - nand->options = 0; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &spear_nand_ecclayout; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.calculate = spear_read_hwecc; - nand->ecc.hwctl = spear_enable_hwecc; - nand->ecc.correct = nand_correct_data; - nand->cmd_ctrl = spear_nand_hwcontrol; - return 0; -} -- cgit v0.10.2 From f3fcf92d595b297b47a1b58b8ec39f93f40ef912 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:00:19 +0530 Subject: st_smi: Add support for SPEAr SMI driver SMI is the serial memory interface controller provided by ST. Earlier, a driver exists in the u-boot source code for the SMI IP. However, it was specific to spear platforms. This commit converts the same driver to a more generic driver. As a result, the driver files are renamed to st_smi.c and st_smi.h and moved into drivers/mtd folder for reusability by other platforms using smi controller peripheral. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h deleted file mode 100644 index 06df745..0000000 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef SPR_SMI_H -#define SPR_SMI_H - -/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ -/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ - -#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE - -#define SMIBANK0_BASE (FLASH_START_ADDRESS) -#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) -#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) -#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) - -#define BANK0 0 -#define BANK1 1 -#define BANK2 2 -#define BANK3 3 - -struct smi_regs { - u32 smi_cr1; - u32 smi_cr2; - u32 smi_sr; - u32 smi_tr; - u32 smi_rr; -}; - -/* CONTROL REG 1 */ -#define BANK_EN 0x0000000F /* enables all banks */ -#define DSEL_TIME 0x00000060 /* Deselect time */ -#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ -#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ -#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ -#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ -#define SW_MODE 0x10000000 /* enables SW Mode */ -#define WB_MODE 0x20000000 /* Write Burst Mode */ -#define FAST_MODE 0x00008000 /* Fast Mode */ -#define HOLD1 0x00010000 - -/* CONTROL REG 2 */ -#define RD_STATUS_REG 0x00000400 /* reads status reg */ -#define WE 0x00000800 /* Write Enable */ -#define BANK0_SEL 0x00000000 /* Select Banck0 */ -#define BANK1_SEL 0x00001000 /* Select Banck1 */ -#define BANK2_SEL 0x00002000 /* Select Banck2 */ -#define BANK3_SEL 0x00003000 /* Select Banck3 */ -#define BANKSEL_SHIFT 12 -#define SEND 0x00000080 /* Send data */ -#define TX_LEN_1 0x00000001 /* data length = 1 byte */ -#define TX_LEN_2 0x00000002 /* data length = 2 byte */ -#define TX_LEN_3 0x00000003 /* data length = 3 byte */ -#define TX_LEN_4 0x00000004 /* data length = 4 byte */ -#define RX_LEN_1 0x00000010 /* data length = 1 byte */ -#define RX_LEN_2 0x00000020 /* data length = 2 byte */ -#define RX_LEN_3 0x00000030 /* data length = 3 byte */ -#define RX_LEN_4 0x00000040 /* data length = 4 byte */ -#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ -#define WCIE 0x00000200 /* WCF Interrupt Enable */ - -/* STATUS_REG */ -#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ -#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ -#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ -#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ -#define RSR 0x00000005 /* Read Status regiser */ -#define TFF 0x00000100 /* Transfer Finished FLag */ -#define WCF 0x00000200 /* Transfer Finished FLag */ -#define ERF1 0x00000400 /* Error Flag 1 */ -#define ERF2 0x00000800 /* Error Flag 2 */ -#define WM0 0x00001000 /* WM Bank 0 */ -#define WM1 0x00002000 /* WM Bank 1 */ -#define WM2 0x00004000 /* WM Bank 2 */ -#define WM3 0x00008000 /* WM Bank 3 */ -#define WM_SHIFT 12 - -/* TR REG */ -#define READ_ID 0x0000009F /* Read Identification */ -#define BULK_ERASE 0x000000C7 /* BULK erase */ -#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ -#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ - -struct flash_dev { - u32 density; - ulong size; - ushort sector_count; -}; - -#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ - -#endif diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 5a5ecdf..543c845 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -35,7 +35,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FTSMC020) += ftsmc020.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_ST_SMI) += st_smi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c deleted file mode 100644 index 6d4257a..0000000 --- a/drivers/mtd/spr_smi.c +++ /dev/null @@ -1,518 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include -#include -#include - -#if !defined(CONFIG_SYS_NO_FLASH) - -static struct smi_regs *const smicntl = - (struct smi_regs * const)CONFIG_SYS_SMI_BASE; -static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = - CONFIG_SYS_FLASH_ADDR_BASE; -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define ST_M25Pxx_ID 0x00002020 - -static struct flash_dev flash_ids[] = { - {0x10, 0x10000, 2}, /* 64K Byte */ - {0x11, 0x20000, 4}, /* 128K Byte */ - {0x12, 0x40000, 4}, /* 256K Byte */ - {0x13, 0x80000, 8}, /* 512K Byte */ - {0x14, 0x100000, 16}, /* 1M Byte */ - {0x15, 0x200000, 32}, /* 2M Byte */ - {0x16, 0x400000, 64}, /* 4M Byte */ - {0x17, 0x800000, 128}, /* 8M Byte */ - {0x18, 0x1000000, 64}, /* 16M Byte */ - {0x00,} -}; - -/* - * smi_wait_xfer_finish - Wait until TFF is set in status register - * @timeout: timeout in milliseconds - * - * Wait until TFF is set in status register - */ -static void smi_wait_xfer_finish(int timeout) -{ - while (timeout--) { - if (readl(&smicntl->smi_sr) & TFF) - break; - udelay(1000); - } -} - -/* - * smi_read_id - Read flash id - * @info: flash_info structure pointer - * @banknum: bank number - * - * Read the flash id present at bank #banknum - */ -static unsigned int smi_read_id(flash_info_t *info, int banknum) -{ - unsigned int value; - - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - writel(READ_ID, &smicntl->smi_tr); - writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, - &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); - - value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); - - writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - return value; -} - -/* - * flash_get_size - Detect the SMI flash by reading the ID. - * @base: Base address of the flash area bank #banknum - * @banknum: Bank number - * - * Detect the SMI flash by reading the ID. Initializes the flash_info structure - * with size, sector count etc. - */ -static ulong flash_get_size(ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - struct flash_dev *dev; - unsigned int value; - unsigned int density; - int i; - - value = smi_read_id(info, banknum); - density = (value >> 16) & 0xff; - - for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; - i++, dev = &flash_ids[i]) { - if (dev->density == density) { - info->size = dev->size; - info->sector_count = dev->sector_count; - break; - } - } - - if (dev->density == 0x0) - return 0; - - info->flash_id = value & 0xffff; - info->start[0] = base; - - return info->size; -} - -/* - * smi_read_sr - Read status register of SMI - * @bank: bank number - * - * This routine will get the status register of the flash chip present at the - * given bank - */ -static unsigned int smi_read_sr(int bank) -{ - u32 ctrlreg1; - - /* store the CTRL REG1 state */ - ctrlreg1 = readl(&smicntl->smi_cr1); - - /* Program SMI in HW Mode */ - writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), - &smicntl->smi_cr1); - - /* Performing a RSR instruction in HW mode */ - writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); - - smi_wait_xfer_finish(XFER_FINISH_TOUT); - - /* Restore the CTRL REG1 state */ - writel(ctrlreg1, &smicntl->smi_cr1); - - return readl(&smicntl->smi_sr); -} - -/* - * smi_wait_till_ready - Wait till last operation is over. - * @bank: bank number shifted. - * @timeout: timeout in milliseconds. - * - * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) - * The routine checks for #timeout loops, each at interval of 1 milli-second. - * If successful the routine returns 0. - */ -static int smi_wait_till_ready(int bank, int timeout) -{ - int count; - unsigned int sr; - - /* One chip guarantees max 5 msec wait here after page writes, - but potentially three seconds (!) after page erase. */ - for (count = 0; count < timeout; count++) { - - sr = smi_read_sr(bank); - if (sr < 0) - break; - else if (!(sr & WIP_BIT)) - return 0; - - /* Try again after 1m-sec */ - udelay(1000); - } - printf("SMI controller is still in wait, timeout=%d\n", timeout); - return -EIO; -} - -/* - * smi_write_enable - Enable the flash to do write operation - * @bank: bank number - * - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int smi_write_enable(int bank) -{ - u32 ctrlreg1; - int timeout = WMODE_TOUT; - - /* Store the CTRL REG1 state */ - ctrlreg1 = readl(&smicntl->smi_cr1); - - /* Program SMI in H/W Mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - /* Give the Flash, Write Enable command */ - writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); - - smi_wait_xfer_finish(XFER_FINISH_TOUT); - - /* Restore the CTRL REG1 state */ - writel(ctrlreg1, &smicntl->smi_cr1); - - while (timeout--) { - if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) - break; - udelay(1000); - } - - if (timeout) - return 0; - - return -1; -} - -/* - * smi_init - SMI initialization routine - * - * SMI initialization routine. Sets SMI control register1. - */ -static void smi_init(void) -{ - /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ - writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, - &smicntl->smi_cr1); -} - -/* - * smi_sector_erase - Erase flash sector - * @info: flash_info structure pointer - * @sector: sector number - * - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int smi_sector_erase(flash_info_t *info, unsigned int sector) -{ - int bank; - unsigned int sect_add; - unsigned int instruction; - - switch (info->start[0]) { - case SMIBANK0_BASE: - bank = BANK0; - break; - case SMIBANK1_BASE: - bank = BANK1; - break; - case SMIBANK2_BASE: - bank = BANK2; - break; - case SMIBANK3_BASE: - bank = BANK3; - break; - default: - return -1; - } - - sect_add = sector * (info->size / info->sector_count); - instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; - - writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); - - if (info->flash_id == ST_M25Pxx_ID) { - /* Wait until finished previous write command. */ - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; - - /* Send write enable, before erase commands. */ - if (smi_write_enable(bank)) - return -EIO; - - /* Put SMI in SW mode */ - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - - /* Send Sector Erase command in SW Mode */ - writel(instruction, &smicntl->smi_tr); - writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, - &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); - - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; - - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, - &smicntl->smi_cr1); - - return 0; - } else { - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, - &smicntl->smi_cr1); - return -EINVAL; - } -} - -/* - * smi_write - Write to SMI flash - * @src_addr: source buffer - * @dst_addr: destination buffer - * @length: length to write in words - * @bank: bank base address - * - * Write to SMI flash - */ -static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, - unsigned int length, ulong bank_addr) -{ - int banknum; - - switch (bank_addr) { - case SMIBANK0_BASE: - banknum = BANK0; - break; - case SMIBANK1_BASE: - banknum = BANK1; - break; - case SMIBANK2_BASE: - banknum = BANK2; - break; - case SMIBANK3_BASE: - banknum = BANK3; - break; - default: - return -1; - } - - if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - /* Set SMI in Hardware Mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - if (smi_write_enable(banknum)) - return -EIO; - - /* Perform the write command */ - while (length--) { - if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { - if (smi_wait_till_ready(banknum, - CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - if (smi_write_enable(banknum)) - return -EIO; - } - - *dst_addr++ = *src_addr++; - - if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) - return -EIO; - } - - if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); - - return 0; -} - -/* - * write_buff - Write to SMI flash - * @info: flash info structure - * @src: source buffer - * @dest_addr: destination buffer - * @length: length to write in words - * - * Write to SMI flash - */ -int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) -{ - return smi_write((unsigned int *)src, (unsigned int *)dest_addr, - (length + 3) / 4, info->start[0]); -} - -/* - * flash_init - SMI flash initialization - * - * SMI flash initialization - */ -unsigned long flash_init(void) -{ - unsigned long size = 0; - int i, j; - - smi_init(); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(bank_base[i], i); - } - - for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { - for (i = 1; i < flash_info[j].sector_count; i++) - flash_info[j].start[i] = - flash_info[j].start[i - 1] + - flash_info->size / flash_info->sector_count; - - } - - return size; -} - -/* - * flash_print_info - Print SMI flash information - * - * Print SMI flash information - */ -void flash_print_info(flash_info_t *info) -{ - int i; - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int size; - int erased; - u32 *flash; - - /* - * Check if whole sector is erased - */ - size = (info->size) / (info->sector_count); - flash = (u32 *) info->start[i]; - size = size / sizeof(int); - - while ((size--) && (*flash++ == ~0)) - ; - - size++; - if (size) - erased = 0; - else - erased = 1; - - if ((i % 5) == 0) - printf("\n"); - - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO) " : " "); -#endif - } - putc('\n'); - return; -} - -/* - * flash_erase - Erase SMI flash - * - * Erase SMI flash - */ -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot = 0; - flash_sect_t sect; - - if (info->flash_id != ST_M25Pxx_ID) { - puts("Can't erase unknown flash type - aborted\n"); - return 1; - } - - if ((s_first < 0) || (s_first > s_last)) { - puts("- no sectors to erase\n"); - return 1; - } - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - putc('\n'); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { - if (smi_sector_erase(info, sect)) - rcode = 1; - else - putc('.'); - } - } - puts(" done\n"); - return rcode; -} -#endif diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c new file mode 100644 index 0000000..db08ab9 --- /dev/null +++ b/drivers/mtd/st_smi.c @@ -0,0 +1,519 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include + +#if !defined(CONFIG_SYS_NO_FLASH) + +static struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; +static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = + CONFIG_SYS_FLASH_ADDR_BASE; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +#define ST_M25Pxx_ID 0x00002020 + +static struct flash_dev flash_ids[] = { + {0x10, 0x10000, 2}, /* 64K Byte */ + {0x11, 0x20000, 4}, /* 128K Byte */ + {0x12, 0x40000, 4}, /* 256K Byte */ + {0x13, 0x80000, 8}, /* 512K Byte */ + {0x14, 0x100000, 16}, /* 1M Byte */ + {0x15, 0x200000, 32}, /* 2M Byte */ + {0x16, 0x400000, 64}, /* 4M Byte */ + {0x17, 0x800000, 128}, /* 8M Byte */ + {0x18, 0x1000000, 64}, /* 16M Byte */ + {0x00,} +}; + +/* + * smi_wait_xfer_finish - Wait until TFF is set in status register + * @timeout: timeout in milliseconds + * + * Wait until TFF is set in status register + */ +static void smi_wait_xfer_finish(int timeout) +{ + while (timeout--) { + if (readl(&smicntl->smi_sr) & TFF) + break; + udelay(1000); + } +} + +/* + * smi_read_id - Read flash id + * @info: flash_info structure pointer + * @banknum: bank number + * + * Read the flash id present at bank #banknum + */ +static unsigned int smi_read_id(flash_info_t *info, int banknum) +{ + unsigned int value; + + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + writel(READ_ID, &smicntl->smi_tr); + writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, + &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); + + writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + return value; +} + +/* + * flash_get_size - Detect the SMI flash by reading the ID. + * @base: Base address of the flash area bank #banknum + * @banknum: Bank number + * + * Detect the SMI flash by reading the ID. Initializes the flash_info structure + * with size, sector count etc. + */ +static ulong flash_get_size(ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + struct flash_dev *dev; + unsigned int value; + unsigned int density; + int i; + + value = smi_read_id(info, banknum); + density = (value >> 16) & 0xff; + + for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; + i++, dev = &flash_ids[i]) { + if (dev->density == density) { + info->size = dev->size; + info->sector_count = dev->sector_count; + break; + } + } + + if (dev->density == 0x0) + return 0; + + info->flash_id = value & 0xffff; + info->start[0] = base; + + return info->size; +} + +/* + * smi_read_sr - Read status register of SMI + * @bank: bank number + * + * This routine will get the status register of the flash chip present at the + * given bank + */ +static unsigned int smi_read_sr(int bank) +{ + u32 ctrlreg1; + + /* store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in HW Mode */ + writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), + &smicntl->smi_cr1); + + /* Performing a RSR instruction in HW mode */ + writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + return readl(&smicntl->smi_sr); +} + +/* + * smi_wait_till_ready - Wait till last operation is over. + * @bank: bank number shifted. + * @timeout: timeout in milliseconds. + * + * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) + * The routine checks for #timeout loops, each at interval of 1 milli-second. + * If successful the routine returns 0. + */ +static int smi_wait_till_ready(int bank, int timeout) +{ + int count; + unsigned int sr; + + /* One chip guarantees max 5 msec wait here after page writes, + but potentially three seconds (!) after page erase. */ + for (count = 0; count < timeout; count++) { + + sr = smi_read_sr(bank); + if (sr < 0) + break; + else if (!(sr & WIP_BIT)) + return 0; + + /* Try again after 1m-sec */ + udelay(1000); + } + printf("SMI controller is still in wait, timeout=%d\n", timeout); + return -EIO; +} + +/* + * smi_write_enable - Enable the flash to do write operation + * @bank: bank number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_write_enable(int bank) +{ + u32 ctrlreg1; + int timeout = WMODE_TOUT; + + /* Store the CTRL REG1 state */ + ctrlreg1 = readl(&smicntl->smi_cr1); + + /* Program SMI in H/W Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + /* Give the Flash, Write Enable command */ + writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); + + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + /* Restore the CTRL REG1 state */ + writel(ctrlreg1, &smicntl->smi_cr1); + + while (timeout--) { + if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + break; + udelay(1000); + } + + if (timeout) + return 0; + + return -1; +} + +/* + * smi_init - SMI initialization routine + * + * SMI initialization routine. Sets SMI control register1. + */ +void smi_init(void) +{ + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +/* + * smi_sector_erase - Erase flash sector + * @info: flash_info structure pointer + * @sector: sector number + * + * Set write enable latch with Write Enable command. + * Returns negative if error occurred. + */ +static int smi_sector_erase(flash_info_t *info, unsigned int sector) +{ + int bank; + unsigned int sect_add; + unsigned int instruction; + + switch (info->start[0]) { + case SMIBANK0_BASE: + bank = BANK0; + break; + case SMIBANK1_BASE: + bank = BANK1; + break; + case SMIBANK2_BASE: + bank = BANK2; + break; + case SMIBANK3_BASE: + bank = BANK3; + break; + default: + return -1; + } + + sect_add = sector * (info->size / info->sector_count); + instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; + + writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); + + if (info->flash_id == ST_M25Pxx_ID) { + /* Wait until finished previous write command. */ + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Send write enable, before erase commands. */ + if (smi_write_enable(bank)) + return -EIO; + + /* Put SMI in SW mode */ + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + + /* Send Sector Erase command in SW Mode */ + writel(instruction, &smicntl->smi_tr); + writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, + &smicntl->smi_cr2); + smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; + + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + &smicntl->smi_cr1); + + return 0; + } else { + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + &smicntl->smi_cr1); + return -EINVAL; + } +} + +/* + * smi_write - Write to SMI flash + * @src_addr: source buffer + * @dst_addr: destination buffer + * @length: length to write in words + * @bank: bank base address + * + * Write to SMI flash + */ +static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, + unsigned int length, ulong bank_addr) +{ + int banknum; + + switch (bank_addr) { + case SMIBANK0_BASE: + banknum = BANK0; + break; + case SMIBANK1_BASE: + banknum = BANK1; + break; + case SMIBANK2_BASE: + banknum = BANK2; + break; + case SMIBANK3_BASE: + banknum = BANK3; + break; + default: + return -1; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + /* Set SMI in Hardware Mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); + + if (smi_write_enable(banknum)) + return -EIO; + + /* Perform the write command */ + while (length--) { + if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { + if (smi_wait_till_ready(banknum, + CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + if (smi_write_enable(banknum)) + return -EIO; + } + + *dst_addr++ = *src_addr++; + + if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) + return -EIO; + } + + if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) + return -EBUSY; + + writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); + + return 0; +} + +/* + * write_buff - Write to SMI flash + * @info: flash info structure + * @src: source buffer + * @dest_addr: destination buffer + * @length: length to write in words + * + * Write to SMI flash + */ +int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) +{ + return smi_write((unsigned int *)src, (unsigned int *)dest_addr, + (length + 3) / 4, info->start[0]); +} + +/* + * flash_init - SMI flash initialization + * + * SMI flash initialization + */ +unsigned long flash_init(void) +{ + unsigned long size = 0; + int i, j; + + smi_init(); + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size(bank_base[i], i); + } + + for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { + for (i = 1; i < flash_info[j].sector_count; i++) + flash_info[j].start[i] = + flash_info[j].start[i - 1] + + flash_info->size / flash_info->sector_count; + + } + + return size; +} + +/* + * flash_print_info - Print SMI flash information + * + * Print SMI flash information + */ +void flash_print_info(flash_info_t *info) +{ + int i; + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); + return; + } + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO + int size; + int erased; + u32 *flash; + + /* + * Check if whole sector is erased + */ + size = (info->size) / (info->sector_count); + flash = (u32 *) info->start[i]; + size = size / sizeof(int); + + while ((size--) && (*flash++ == ~0)) + ; + + size++; + if (size) + erased = 0; + else + erased = 1; + + if ((i % 5) == 0) + printf("\n"); + + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO) " : " "); +#endif + } + putc('\n'); + return; +} + +/* + * flash_erase - Erase SMI flash + * + * Erase SMI flash + */ +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot = 0; + flash_sect_t sect; + + if (info->flash_id != ST_M25Pxx_ID) { + puts("Can't erase unknown flash type - aborted\n"); + return 1; + } + + if ((s_first < 0) || (s_first > s_last)) { + puts("- no sectors to erase\n"); + return 1; + } + + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + putc('\n'); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { + if (smi_sector_erase(info, sect)) + rcode = 1; + else + putc('.'); + } + } + puts(" done\n"); + return rcode; +} +#endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 8d0f036..75cc5ff 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -55,10 +55,10 @@ #if defined(CONFIG_FLASH_PNOR) #define CONFIG_SPEAR_EMI 1 #else -#define CONFIG_SPEARSMI 1 +#define CONFIG_ST_SMI #endif -#if defined(CONFIG_SPEARSMI) +#if defined(CONFIG_ST_SMI) #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BASE (0xF8000000) @@ -125,7 +125,7 @@ * U-Boot Environment placing definitions. */ #if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_SPEARSMI +#ifdef CONFIG_ST_SMI /* * Environment is in serial NOR flash */ diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h new file mode 100644 index 0000000..b7a78ac --- /dev/null +++ b/include/linux/mtd/st_smi.h @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef ST_SMI_H +#define ST_SMI_H + +/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ +/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ + +#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE +#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE + +#define SMIBANK0_BASE (FLASH_START_ADDRESS) +#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) +#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) +#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) + +#define BANK0 0 +#define BANK1 1 +#define BANK2 2 +#define BANK3 3 + +struct smi_regs { + u32 smi_cr1; + u32 smi_cr2; + u32 smi_sr; + u32 smi_tr; + u32 smi_rr; +}; + +/* CONTROL REG 1 */ +#define BANK_EN 0x0000000F /* enables all banks */ +#define DSEL_TIME 0x00000060 /* Deselect time */ +#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ +#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ +#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ +#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ +#define SW_MODE 0x10000000 /* enables SW Mode */ +#define WB_MODE 0x20000000 /* Write Burst Mode */ +#define FAST_MODE 0x00008000 /* Fast Mode */ +#define HOLD1 0x00010000 + +/* CONTROL REG 2 */ +#define RD_STATUS_REG 0x00000400 /* reads status reg */ +#define WE 0x00000800 /* Write Enable */ +#define BANK0_SEL 0x00000000 /* Select Banck0 */ +#define BANK1_SEL 0x00001000 /* Select Banck1 */ +#define BANK2_SEL 0x00002000 /* Select Banck2 */ +#define BANK3_SEL 0x00003000 /* Select Banck3 */ +#define BANKSEL_SHIFT 12 +#define SEND 0x00000080 /* Send data */ +#define TX_LEN_1 0x00000001 /* data length = 1 byte */ +#define TX_LEN_2 0x00000002 /* data length = 2 byte */ +#define TX_LEN_3 0x00000003 /* data length = 3 byte */ +#define TX_LEN_4 0x00000004 /* data length = 4 byte */ +#define RX_LEN_1 0x00000010 /* data length = 1 byte */ +#define RX_LEN_2 0x00000020 /* data length = 2 byte */ +#define RX_LEN_3 0x00000030 /* data length = 3 byte */ +#define RX_LEN_4 0x00000040 /* data length = 4 byte */ +#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ +#define WCIE 0x00000200 /* WCF Interrupt Enable */ + +/* STATUS_REG */ +#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ +#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ +#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ +#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ +#define RSR 0x00000005 /* Read Status regiser */ +#define TFF 0x00000100 /* Transfer Finished FLag */ +#define WCF 0x00000200 /* Transfer Finished FLag */ +#define ERF1 0x00000400 /* Error Flag 1 */ +#define ERF2 0x00000800 /* Error Flag 2 */ +#define WM0 0x00001000 /* WM Bank 0 */ +#define WM1 0x00002000 /* WM Bank 1 */ +#define WM2 0x00004000 /* WM Bank 2 */ +#define WM3 0x00008000 /* WM Bank 3 */ +#define WM_SHIFT 12 + +/* TR REG */ +#define READ_ID 0x0000009F /* Read Identification */ +#define BULK_ERASE 0x000000C7 /* BULK erase */ +#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ +#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ + +struct flash_dev { + u32 density; + ulong size; + ushort sector_count; +}; + +#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ +#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ +#define WMODE_TOUT 2 /* write enable timeout */ + +extern void smi_init(void); + +#endif -- cgit v0.10.2 From 5c16c54124ba7a21979e1eb656e696b7b6d881ec Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:00:20 +0530 Subject: st_smi: Return error in case TFF is not set Curently the code makes wrong assumption that the Transfer finished flag shall be set within the stipulated time. However, there may occur a scenario in which the TFF flag is not set. Return error in that case. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index db08ab9..9769b28 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -58,13 +58,15 @@ static struct flash_dev flash_ids[] = { * * Wait until TFF is set in status register */ -static void smi_wait_xfer_finish(int timeout) +static int smi_wait_xfer_finish(int timeout) { - while (timeout--) { + do { if (readl(&smicntl->smi_sr) & TFF) - break; + return 0; udelay(1000); - } + } while (timeout--); + + return -1; } /* @@ -83,7 +85,8 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum) writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); @@ -151,7 +154,8 @@ static unsigned int smi_read_sr(int bank) /* Performing a RSR instruction in HW mode */ writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1; /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); @@ -211,7 +215,8 @@ static int smi_write_enable(int bank) /* Give the Flash, Write Enable command */ writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1; /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); @@ -292,7 +297,8 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) writel(instruction, &smicntl->smi_tr); writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) return -EBUSY; -- cgit v0.10.2 From 0e88ff08febcb88fc4081f0393c4fca02b847146 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:00:21 +0530 Subject: st_smi: Change SMI timeout values Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h index b7a78ac..04f81ea 100644 --- a/include/linux/mtd/st_smi.h +++ b/include/linux/mtd/st_smi.h @@ -109,8 +109,8 @@ struct flash_dev { }; #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ +#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ +#define WMODE_TOUT 15 /* write enable timeout(in ms) */ extern void smi_init(void); -- cgit v0.10.2 From 69fcb55f71c9e2c40a0f1de6f70b26a9ec02cfb8 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:00:22 +0530 Subject: st_smi: Enhance the error handling This commit does the following: - Reports error if SNOR flash is not found on the board - Changes smi_read_sr to return error using which a retry mechanism is implemented for reading flash status Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 9769b28..2c6d59d 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -108,11 +108,17 @@ static ulong flash_get_size(ulong base, int banknum) { flash_info_t *info = &flash_info[banknum]; struct flash_dev *dev; - unsigned int value; + int value; unsigned int density; int i; value = smi_read_id(info, banknum); + + if (value < 0) { + printf("Flash id could not be read\n"); + return 0; + } + density = (value >> 16) & 0xff; for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; @@ -140,7 +146,7 @@ static ulong flash_get_size(ulong base, int banknum) * This routine will get the status register of the flash chip present at the * given bank */ -static unsigned int smi_read_sr(int bank) +static int smi_read_sr(int bank) { u32 ctrlreg1; @@ -174,13 +180,11 @@ static unsigned int smi_read_sr(int bank) */ static int smi_wait_till_ready(int bank, int timeout) { - int count; - unsigned int sr; + int sr; /* One chip guarantees max 5 msec wait here after page writes, but potentially three seconds (!) after page erase. */ - for (count = 0; count < timeout; count++) { - + do { sr = smi_read_sr(bank); if (sr < 0) break; @@ -189,7 +193,8 @@ static int smi_wait_till_ready(int bank, int timeout) /* Try again after 1m-sec */ udelay(1000); - } + } while (timeout--); + printf("SMI controller is still in wait, timeout=%d\n", timeout); return -EIO; } @@ -205,6 +210,7 @@ static int smi_write_enable(int bank) { u32 ctrlreg1; int timeout = WMODE_TOUT; + int sr; /* Store the CTRL REG1 state */ ctrlreg1 = readl(&smicntl->smi_cr1); @@ -221,14 +227,16 @@ static int smi_write_enable(int bank) /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - while (timeout--) { - if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + do { + sr = smi_read_sr(bank); + if (sr < 0) break; - udelay(1000); - } + else if (sr & (1 << (bank + WM_SHIFT))) + return 0; - if (timeout) - return 0; + /* Try again after 1m-sec */ + udelay(1000); + } while (timeout--); return -1; } -- cgit v0.10.2 From 0befe7d7a396339067ccb7018ab69a097ff62cf4 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:00:23 +0530 Subject: st_smi: Read status until timeout happens SMI driver read status fails because the control register could not be overwritten. Instead, the read status should be tried until timeout. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 2c6d59d..088c7c7 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -187,7 +187,7 @@ static int smi_wait_till_ready(int bank, int timeout) do { sr = smi_read_sr(bank); if (sr < 0) - break; + continue; /* try until timeout */ else if (!(sr & WIP_BIT)) return 0; -- cgit v0.10.2 From a59c7b37b908639f9daa7fe50d4646b3947e2d62 Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Mon, 7 May 2012 13:00:24 +0530 Subject: st_smi: Move status register read before modifying ctrl register Signed-off-by: Shiraz Hashim Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 088c7c7..8c27603 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -148,7 +148,7 @@ static ulong flash_get_size(ulong base, int banknum) */ static int smi_read_sr(int bank) { - u32 ctrlreg1; + u32 ctrlreg1, val; /* store the CTRL REG1 state */ ctrlreg1 = readl(&smicntl->smi_cr1); @@ -163,10 +163,12 @@ static int smi_read_sr(int bank) if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) return -1; + val = readl(&smicntl->smi_sr); + /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - return readl(&smicntl->smi_sr); + return val; } /* -- cgit v0.10.2 From a5ad7ccd74de244f91d75fb3879eaa1929304e89 Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Mon, 7 May 2012 13:00:25 +0530 Subject: st_smi: Fix smi read status smi_read_sr fails sometimes because of TFF not getting set within assumed time. This condition may arise because of, for example, smi memory being in a erase mode. This fix is to enable reading the status register until timeout. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 8c27603..38f22b7 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -188,9 +188,7 @@ static int smi_wait_till_ready(int bank, int timeout) but potentially three seconds (!) after page erase. */ do { sr = smi_read_sr(bank); - if (sr < 0) - continue; /* try until timeout */ - else if (!(sr & WIP_BIT)) + if ((sr >= 0) && (!(sr & WIP_BIT))) return 0; /* Try again after 1m-sec */ @@ -231,9 +229,7 @@ static int smi_write_enable(int bank) do { sr = smi_read_sr(bank); - if (sr < 0) - break; - else if (sr & (1 << (bank + WM_SHIFT))) + if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) return 0; /* Try again after 1m-sec */ -- cgit v0.10.2 From ae3e0cc924579bcea0906a6888a7bc01a19157e4 Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Mon, 7 May 2012 13:00:26 +0530 Subject: st_smi: Removed no needed dependency on ST_M25Pxx_ID Since the smi erase code is very generic and works for any kind of flash, there is no need to test for ST_M25Pxx_ID flash types like m25p40 flashes). Signed-off-by: Armando Visconti Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 38f22b7..83a57d2 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -37,8 +37,6 @@ static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_ADDR_BASE; flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -#define ST_M25Pxx_ID 0x00002020 - static struct flash_dev flash_ids[] = { {0x10, 0x10000, 2}, /* 64K Byte */ {0x11, 0x20000, 4}, /* 128K Byte */ @@ -287,39 +285,32 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); - if (info->flash_id == ST_M25Pxx_ID) { - /* Wait until finished previous write command. */ - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; + /* Wait until finished previous write command. */ + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; - /* Send write enable, before erase commands. */ - if (smi_write_enable(bank)) - return -EIO; + /* Send write enable, before erase commands. */ + if (smi_write_enable(bank)) + return -EIO; - /* Put SMI in SW mode */ - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + /* Put SMI in SW mode */ + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - /* Send Sector Erase command in SW Mode */ - writel(instruction, &smicntl->smi_tr); - writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, + /* Send Sector Erase command in SW Mode */ + writel(instruction, &smicntl->smi_tr); + writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, &smicntl->smi_cr2); - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -EIO; + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - return 0; - } else { - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, - &smicntl->smi_cr1); - return -EINVAL; - } + return 0; } /* @@ -496,11 +487,6 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) int prot = 0; flash_sect_t sect; - if (info->flash_id != ST_M25Pxx_ID) { - puts("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { puts("- no sectors to erase\n"); return 1; -- cgit v0.10.2 From 6d6d23c143f50389018fd1f5091a7101247d79d5 Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Mon, 7 May 2012 13:00:27 +0530 Subject: st_smi: Change the flash probing method THis patch introduces a new methodology for flash probing in which flash_devices[] table, looked-up thru the dev_id, is used to locate the flash geometry and information. Signed-off-by: Armando Visconti Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 83a57d2..976b097 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -37,17 +37,61 @@ static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_ADDR_BASE; flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -static struct flash_dev flash_ids[] = { - {0x10, 0x10000, 2}, /* 64K Byte */ - {0x11, 0x20000, 4}, /* 128K Byte */ - {0x12, 0x40000, 4}, /* 256K Byte */ - {0x13, 0x80000, 8}, /* 512K Byte */ - {0x14, 0x100000, 16}, /* 1M Byte */ - {0x15, 0x200000, 32}, /* 2M Byte */ - {0x16, 0x400000, 64}, /* 4M Byte */ - {0x17, 0x800000, 128}, /* 8M Byte */ - {0x18, 0x1000000, 64}, /* 16M Byte */ - {0x00,} +/* data structure to maintain flash ids from different vendors */ +struct flash_device { + char *name; + u8 erase_cmd; + u32 device_id; + u32 pagesize; + unsigned long sectorsize; + unsigned long size_in_bytes; +}; + +#define FLASH_ID(n, es, id, psize, ssize, size) \ +{ \ + .name = n, \ + .erase_cmd = es, \ + .device_id = id, \ + .pagesize = psize, \ + .sectorsize = ssize, \ + .size_in_bytes = size \ +} + +/* + * List of supported flash devices. + * Currently the erase_cmd field is not used in this driver. + */ +static struct flash_device flash_devices[] = { + FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000), + FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000), + FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000), + FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000), + FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000), + FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000), + FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000), + FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000), + FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000), + FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000), + FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000), + FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000), + FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000), + FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000), + FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000), + FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000), + FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000), + FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000), + FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000), + FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000), + FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000), + FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), + FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), + FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000), + FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000), + FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000), + FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), + FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), + FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), + FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x1000, 0x10000, 0x1000000), }; /* @@ -105,9 +149,7 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum) static ulong flash_get_size(ulong base, int banknum) { flash_info_t *info = &flash_info[banknum]; - struct flash_dev *dev; int value; - unsigned int density; int i; value = smi_read_id(info, banknum); @@ -117,24 +159,20 @@ static ulong flash_get_size(ulong base, int banknum) return 0; } - density = (value >> 16) & 0xff; + /* Matches chip-id to entire list of 'serial-nor flash' ids */ + for (i = 0; i < ARRAY_SIZE(flash_devices); i++) { + if (flash_devices[i].device_id == value) { + info->size = flash_devices[i].size_in_bytes; + info->flash_id = value; + info->start[0] = base; + info->sector_count = + info->size/flash_devices[i].sectorsize; - for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; - i++, dev = &flash_ids[i]) { - if (dev->density == density) { - info->size = dev->size; - info->sector_count = dev->sector_count; - break; + return info->size; } } - if (dev->density == 0x0) - return 0; - - info->flash_id = value & 0xffff; - info->start[0] = base; - - return info->size; + return 0; } /* -- cgit v0.10.2 From cf9026deb8d83b00c37b19ec7b63491e9338d49f Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Mon, 7 May 2012 13:00:28 +0530 Subject: st_smi: Fix bug in flash_print_info() If the flash size was smaller than 1MB then flash_print_info() was erroneously reporting 0 MB. Signed-off-by: Armando Visconti Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 976b097..5378b57 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -471,8 +471,13 @@ void flash_print_info(flash_info_t *info) puts("missing or unknown FLASH type\n"); return; } - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); + + if (info->size >= 0x100000) + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); puts(" Sector Start Addresses:"); for (i = 0; i < info->sector_count; ++i) { -- cgit v0.10.2 From b5992fac88f8068f4f1af1de2e76889465e45693 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:00:29 +0530 Subject: st_smi: Change timeout loop implementation There are two problems in the current timeout loop implementation: 1. In case initial test failing, there will always be a delay of 1 ms 2. The delay duration is not tunable The new implementation addresses both these limitations. Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 5378b57..75ae9aa 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -102,11 +102,15 @@ static struct flash_device flash_devices[] = { */ static int smi_wait_xfer_finish(int timeout) { - do { + ulong start = get_timer(0); + + while (get_timer(start) < timeout) { if (readl(&smicntl->smi_sr) & TFF) return 0; - udelay(1000); - } while (timeout--); + + /* Try after 10 ms */ + udelay(10); + }; return -1; } @@ -219,16 +223,17 @@ static int smi_read_sr(int bank) static int smi_wait_till_ready(int bank, int timeout) { int sr; + ulong start = get_timer(0); /* One chip guarantees max 5 msec wait here after page writes, but potentially three seconds (!) after page erase. */ - do { + while (get_timer(start) < timeout) { sr = smi_read_sr(bank); if ((sr >= 0) && (!(sr & WIP_BIT))) return 0; - /* Try again after 1m-sec */ - udelay(1000); + /* Try again after 10 usec */ + udelay(10); } while (timeout--); printf("SMI controller is still in wait, timeout=%d\n", timeout); @@ -245,6 +250,7 @@ static int smi_wait_till_ready(int bank, int timeout) static int smi_write_enable(int bank) { u32 ctrlreg1; + u32 start; int timeout = WMODE_TOUT; int sr; @@ -263,14 +269,15 @@ static int smi_write_enable(int bank) /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - do { + start = get_timer(0); + while (get_timer(start) < timeout) { sr = smi_read_sr(bank); if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) return 0; - /* Try again after 1m-sec */ - udelay(1000); - } while (timeout--); + /* Try again after 10 usec */ + udelay(10); + }; return -1; } -- cgit v0.10.2 From 9264077635f4053a646d90bd8ebd5287c602d18d Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Mon, 7 May 2012 13:00:30 +0530 Subject: st_smi: Fixed page size for Winbond W25Q128FV flash Signed-off-by: Armando Visconti Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 75ae9aa..77e36af 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -91,7 +91,7 @@ static struct flash_device flash_devices[] = { FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), - FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x1000, 0x10000, 0x1000000), + FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000), }; /* -- cgit v0.10.2 From 5cca72f8b342c8a65eaebda22647572394d98535 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:06:39 +0530 Subject: SPEAr: Fix ARM relocation support While the u-boot code is running from the flash, it is essential that no access is made to the bss segment. This is due to the fact that .rel.dyn and .bss areas overlap and former contains information used in relocation. In SPEAr, this was not taken into consideration. As a result, while the relocation wasn't complete, dram_init populated an uninitialized global variable resulting in corruption of .rel.dyn area, which resulted in u-boot crash. This commit fixes this problem by removing code that accesses bss segment Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 0812c20..3ab278f 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -40,27 +40,9 @@ static struct chip_data chip_data; int dram_init(void) { - struct xloader_table *xloader_tb = - (struct xloader_table *)XLOADER_TABLE_ADDRESS; - struct xloader_table_1_1 *table_1_1; - struct xloader_table_1_2 *table_1_2; - struct chip_data *chip = &chip_data; - + /* Store complete RAM size and return */ gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); - if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { - table_1_1 = &xloader_tb->table.table_1_1; - chip->dramfreq = table_1_1->ddrfreq; - chip->dramtype = table_1_1->ddrtype; - - } else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { - table_1_2 = &xloader_tb->table.table_1_2; - chip->dramfreq = table_1_2->ddrfreq; - chip->dramtype = table_1_2->ddrtype; - } else { - chip->dramfreq = -1; - } - return 0; } -- cgit v0.10.2 From 70fdbefc6c50010cc56196b65a233369d2b2ce68 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:06:40 +0530 Subject: SPEAr: Eliminate dependency on Xloader table Xloader table was used primarily to inform u-boot about the DDR size. However, now the ddr size is calculated at runtime which eliminates any need for the Xloader table. So removing this unnecessary code. Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h index fa8412c..0ddce62 100644 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ b/arch/arm/include/asm/arch-spear/spr_defs.h @@ -28,13 +28,6 @@ extern int spear_board_init(ulong); extern void setfreq(unsigned int, unsigned int); extern unsigned int setfreq_sz; -struct chip_data { - int cpufreq; - int dramfreq; - int dramtype; - uchar version[32]; -}; - /* HW mac id in i2c memory definitions */ #define MAGIC_OFF 0x0 #define MAGIC_LEN 0x2 diff --git a/arch/arm/include/asm/arch-spear/spr_xloader_table.h b/arch/arm/include/asm/arch-spear/spr_xloader_table.h deleted file mode 100644 index 7e3da18..0000000 --- a/arch/arm/include/asm/arch-spear/spr_xloader_table.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPR_XLOADER_TABLE_H -#define _SPR_XLOADER_TABLE_H - -#define XLOADER_TABLE_VERSION_1_1 2 -#define XLOADER_TABLE_VERSION_1_2 3 - -#define XLOADER_TABLE_ADDRESS 0xD2801FF0 - -#define DDRMOBILE 1 -#define DDR2 2 - -#define REV_BA 1 -#define REV_AA 2 -#define REV_AB 3 - -struct xloader_table_1_1 { - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -struct xloader_table_1_2 { - unsigned const char *version; - - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -union table_contents { - struct xloader_table_1_1 table_1_1; - struct xloader_table_1_2 table_1_2; -}; - -struct xloader_table { - unsigned char table_version; - union table_contents table; -} __attribute__ ((packed)); - -#endif diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 3ab278f..be96c15 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #define CPU 0 @@ -36,7 +35,6 @@ #define SRAM_REL 0xD2801000 DECLARE_GLOBAL_DATA_PTR; -static struct chip_data chip_data; int dram_init(void) { @@ -127,25 +125,11 @@ void spear_emi_init(void) int spear_board_init(ulong mach_type) { - struct xloader_table *xloader_tb = - (struct xloader_table *)XLOADER_TABLE_ADDRESS; - struct xloader_table_1_2 *table_1_2; - struct chip_data *chip = &chip_data; - gd->bd->bi_arch_number = mach_type; /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; - /* CPU is initialized to work at 333MHz in Xloader */ - chip->cpufreq = 333; - - if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { - table_1_2 = &xloader_tb->table.table_1_2; - memcpy(chip->version, table_1_2->version, - sizeof(chip->version)); - } - #ifdef CONFIG_SPEAR_EMI spear_emi_init(); #endif @@ -195,7 +179,6 @@ static int write_mac(uchar *mac) int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); - struct chip_data *chip = &chip_data; unsigned char mac[6]; unsigned int reg, frequency; char *s, *e; @@ -218,13 +201,9 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!strcmp(argv[1], "cpufreq")) { sram_setfreq(CPU, frequency); printf("CPU frequency changed to %u\n", frequency); - - chip->cpufreq = frequency; } else { sram_setfreq(DDR, frequency); printf("DDR frequency changed to %u\n", frequency); - - chip->dramfreq = frequency; } return 0; @@ -240,24 +219,6 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } else if (!strcmp(argv[1], "print")) { - - if (chip->cpufreq == -1) - printf("CPU Freq = Not Known\n"); - else - printf("CPU Freq = %d MHz\n", chip->cpufreq); - - if (chip->dramfreq == -1) - printf("DDR Freq = Not Known\n"); - else - printf("DDR Freq = %d MHz\n", chip->dramfreq); - - if (chip->dramtype == DDRMOBILE) - printf("DDR Type = MOBILE\n"); - else if (chip->dramtype == DDR2) - printf("DDR Type = DDR2\n"); - else - printf("DDR Type = Not Known\n"); - if (!i2c_read_mac(mac)) { sprintf(i2c_mac, "%pM", mac); printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); @@ -265,8 +226,6 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Ethaddr (from i2c mem) = Not set\n"); } - printf("Xloader Rev = %s\n", chip->version); - return 0; } -- cgit v0.10.2 From 8026b1e42f533f14115bb629efeaaedec6eaf23b Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:41 +0530 Subject: SPEAr: Place ethaddr write and read within CONFIG_CMD_NET ethaddr can be optionally read from i2c memory. So, chip_config command supports reading/writing hw mac id into i2c memory. Placing this code within CONFIG_CMD_NET as this would only be needed when network interface is configured Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index be96c15..e2918ff 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -36,6 +36,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(uchar *buffer); +#endif + int dram_init(void) { /* Store complete RAM size and return */ @@ -136,6 +140,7 @@ int spear_board_init(ulong mach_type) return 0; } +#if defined(CONFIG_CMD_NET) static int i2c_read_mac(uchar *buffer) { u8 buf[2]; @@ -172,17 +177,18 @@ static int write_mac(uchar *mac) return 0; } - puts("I2C EEPROM writing failed \n"); + puts("I2C EEPROM writing failed\n"); return -1; } +#endif int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); + unsigned int frequency; +#if defined(CONFIG_CMD_NET) unsigned char mac[6]; - unsigned int reg, frequency; - char *s, *e; - char i2c_mac[20]; +#endif if ((argc > 3) || (argc < 2)) return cmd_usage(cmdtp); @@ -207,9 +213,12 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } return 0; + +#if defined(CONFIG_CMD_NET) } else if (!strcmp(argv[1], "ethaddr")) { - s = argv[2]; + u32 reg; + char *e, *s = argv[2]; for (reg = 0; reg < 6; ++reg) { mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; if (s) @@ -218,14 +227,15 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) write_mac(mac); return 0; +#endif } else if (!strcmp(argv[1], "print")) { +#if defined(CONFIG_CMD_NET) if (!i2c_read_mac(mac)) { - sprintf(i2c_mac, "%pM", mac); - printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); + printf("Ethaddr (from i2c mem) = %pM\n", mac); } else { printf("Ethaddr (from i2c mem) = Not set\n"); } - +#endif return 0; } @@ -235,4 +245,7 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(chip_config, 3, 1, do_chip_config, "configure chip", "chip_config cpufreq/ddrfreq frequency\n" +#if defined(CONFIG_CMD_NET) + "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" +#endif "chip_config print"); diff --git a/doc/README.spear b/doc/README.spear index a8b1052..a6ff7fd 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -46,3 +46,11 @@ Further options make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - This option generates a uboot image that supports emi controller for CFI compliant parallel NOR flash + +Mac id storage and retrieval in spear platforms + +Please read doc/README.enetaddr for the implementation guidelines for mac id +usage. Basically, environment has precedence over board specific storage. The +ethaddr beeing used for the network interface is always taken only from +environment variables. Although, we can check the mac id programmed in i2c +memory by using chip_config command -- cgit v0.10.2 From deb005622782bf568a4daa8daeb8adf95b606492 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:42 +0530 Subject: SPEAr: Configure network support for spear SoCs Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index a6517b2..70fc030 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -31,6 +31,7 @@ #define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) #define CONFIG_SPEAR_TIMERBASE (0xFC800000) #define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SPEAR_ETHBASE 0xE0800000 #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 72a3631..2283ad5 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -60,3 +61,12 @@ void board_nand_init() #endif return; } + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_DESIGNWARE_ETH) + return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); +#else + return -1; +#endif +} diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 14e666d..043a9f3 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -61,3 +62,12 @@ void board_nand_init() #endif return; } + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_DESIGNWARE_ETH) + return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); +#else + return -1; +#endif +} diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 994eb2b..1b6f362 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -62,3 +63,12 @@ void board_nand_init() return; } + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_DESIGNWARE_ETH) + return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); +#else + return -1; +#endif +} diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index ab0f760..d18d313 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -55,3 +56,12 @@ void board_nand_init() #endif return; } + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_DESIGNWARE_ETH) + return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); +#else + return -1; +#endif +} diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 75cc5ff..669d83e 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -27,6 +27,14 @@ * Common configurations used for both spear3xx as well as spear6xx */ +/* Ethernet driver configuration */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_DW0_PHY 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ + /* USBD driver configuration */ #define CONFIG_DW_UDC #define CONFIG_USB_DEVICE @@ -104,11 +112,13 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_RUN #define CONFIG_CMD_SAVES +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS /* * Default Environment Varible definitions diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 2a86c21..035b321 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -41,6 +41,9 @@ #include +/* Ethernet driver configuration */ +#define CONFIG_DW_ALTDESCRIPTOR 1 + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000 -- cgit v0.10.2 From 8eb0ee6a649d09a41155bf6c9dbd4d531ed41f9e Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:43 +0530 Subject: SPEAr: Add macb driver support for spear310 and spear320 SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The driver for this device is already supported by u-boot, so configuring board configuration file and defining base addresses etc to make use of the common driver Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 0000000..a45ec18 --- /dev/null +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 70fc030..0012dd7 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -56,6 +56,11 @@ #define CONFIG_SPEAR_EMIBASE (0x4F000000) #define CONFIG_SPEAR_RASBASE (0xB4000000) +#define CONFIG_SYS_MACB0_BASE 0xB0000000 +#define CONFIG_SYS_MACB1_BASE 0xB0800000 +#define CONFIG_SYS_MACB2_BASE 0xB1000000 +#define CONFIG_SYS_MACB3_BASE 0xB1800000 + #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) #define CONFIG_SYS_FSMC_BASE (0x4C000000) @@ -63,5 +68,7 @@ #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000) +#define CONFIG_SYS_MACB0_BASE 0xAA000000 + #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 043a9f3..c0e6829 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -65,9 +65,28 @@ void board_nand_init() int board_eth_init(bd_t *bis) { + int ret = 0; + #if defined(CONFIG_DESIGNWARE_ETH) - return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); -#else - return -1; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0) + ret += -1; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) < 0) + ret += -1; + + if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, + CONFIG_MACB1_PHY) < 0) + ret += -1; + + if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, + CONFIG_MACB2_PHY) < 0) + ret += -1; + + if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, + CONFIG_MACB3_PHY) < 0) + ret += -1; #endif + return ret; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 1b6f362..e101888 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -66,9 +66,15 @@ void board_nand_init() int board_eth_init(bd_t *bis) { + int ret = 0; #if defined(CONFIG_DESIGNWARE_ETH) - return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); -#else - return -1; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0) + ret += -1; #endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) < 0) + ret += -1; +#endif + return ret; } diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 035b321..f3e3354 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -44,6 +44,19 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR 1 +#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 + +#endif + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000 -- cgit v0.10.2 From 9afc1af01f2d4b033e0da5df105b399949976a12 Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Mon, 7 May 2012 13:06:44 +0530 Subject: SPEAr: Add interface information in initialization Few Designware peripheral registers need to be modified based on the ethernet interface selected by the board. This patch supports interface information in ethernet driver Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 2283ad5..f809c2d 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -64,9 +65,13 @@ void board_nand_init() int board_eth_init(bd_t *bis) { + int ret = 0; + #if defined(CONFIG_DESIGNWARE_ETH) - return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); -#else - return -1; + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; #endif + return ret; } diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index c0e6829..8609a59 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -68,25 +69,27 @@ int board_eth_init(bd_t *bis) int ret = 0; #if defined(CONFIG_DESIGNWARE_ETH) - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0) - ret += -1; + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; #endif #if defined(CONFIG_MACB) if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, - CONFIG_MACB0_PHY) < 0) - ret += -1; + CONFIG_MACB0_PHY) >= 0) + ret++; if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, - CONFIG_MACB1_PHY) < 0) - ret += -1; + CONFIG_MACB1_PHY) >= 0) + ret++; if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, - CONFIG_MACB2_PHY) < 0) - ret += -1; + CONFIG_MACB2_PHY) >= 0) + ret++; if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, - CONFIG_MACB3_PHY) < 0) - ret += -1; + CONFIG_MACB3_PHY) >= 0) + ret++; #endif return ret; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index e101888..54a2e10 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -31,10 +32,20 @@ #include #include +#define PLGPIO_SEL_36 0xb3000028 +#define PLGPIO_IO_36 0xb3000038 + static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; +static void spear_phy_reset(void) +{ + writel(0x10, PLGPIO_IO_36); + writel(0x10, PLGPIO_SEL_36); +} + int board_init(void) { + spear_phy_reset(); return spear_board_init(MACH_TYPE_SPEAR320); } @@ -67,14 +78,17 @@ void board_nand_init() int board_eth_init(bd_t *bis) { int ret = 0; + #if defined(CONFIG_DESIGNWARE_ETH) - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0) - ret += -1; + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; #endif #if defined(CONFIG_MACB) if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, - CONFIG_MACB0_PHY) < 0) - ret += -1; + CONFIG_MACB0_PHY) >= 0) + ret++; #endif return ret; } diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index d18d313..814f9cc 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -59,9 +60,16 @@ void board_nand_init() int board_eth_init(bd_t *bis) { + int ret = 0; + #if defined(CONFIG_DESIGNWARE_ETH) - return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); -#else - return -1; + u32 interface = PHY_INTERFACE_MODE_MII; +#if defined(CONFIG_DW_AUTONEG) + interface = PHY_INTERFACE_MODE_GMII; +#endif + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; #endif + return ret; } diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9b17db4..8f22e00 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -171,6 +171,13 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) if (priv->speed != SPEED_1000M) conf |= MII_PORTSELECT; + if ((priv->interface != PHY_INTERFACE_MODE_MII) && + (priv->interface != PHY_INTERFACE_MODE_GMII)) { + + if (priv->speed == SPEED_100M) + conf |= FES_100; + } + if (priv->duplex == FULL_DUPLEX) conf |= FULLDPLXMODE; @@ -531,7 +538,7 @@ static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) } #endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -565,6 +572,7 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) DW_DMA_BASE_OFFSET); priv->address = phy_addr; priv->phy_configured = 0; + priv->interface = interface; if (mac_reset(dev) < 0) return -1; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index abf729d..40020bf 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -234,6 +234,7 @@ struct dmamacdescr { struct dw_eth_dev { u32 address; + u32 interface; u32 speed; u32 duplex; u32 tx_currdescnum; diff --git a/include/netdev.h b/include/netdev.h index 4724717..d1aaf0c 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -52,7 +52,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr); +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); -- cgit v0.10.2 From 962d026b6aaf7d801d182f3188e4bbc106e057e3 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:45 +0530 Subject: SPEAr: Add basic arch related support for SPEAr SoCs Earlier, architecture specific init code was mixed with board initialization code in board/spear/... This patch updates architecture support for SPEAr in latest u-boot and prints the SoC information. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index f32ec4c..46923a4 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := reset.o \ +COBJS := cpu.o \ + reset.o \ timer.o SOBJS := diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c new file mode 100644 index 0000000..9e074bc --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int arch_cpu_init(void) +{ + struct misc_regs *const misc_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 periph1_clken; + + periph1_clken = readl(&misc_p->periph1_clken); + +#if defined(CONFIG_SPEAR3XX) + periph1_clken |= MISC_GPT2ENB; +#elif defined(CONFIG_SPEAR600) + periph1_clken |= MISC_GPT3ENB; +#endif + +#if defined(CONFIG_PL011_SERIAL) + periph1_clken |= MISC_UART0ENB; +#endif +#if defined(CONFIG_DESIGNWARE_ETH) + periph1_clken |= MISC_ETHENB; +#endif +#if defined(CONFIG_DW_UDC) + periph1_clken |= MISC_USBDENB; +#endif +#if defined(CONFIG_DW_I2C) + periph1_clken |= MISC_I2CENB; +#endif +#if defined(CONFIG_ST_SMI) + periph1_clken |= MISC_SMIENB; +#endif +#if defined(CONFIG_NAND_FSMC) + periph1_clken |= MISC_FSMCENB; +#endif + + writel(periph1_clken, &misc_p->periph1_clken); + return 0; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ +#ifdef CONFIG_SPEAR300 + printf("CPU: SPEAr300\n"); +#elif defined(CONFIG_SPEAR310) + printf("CPU: SPEAr310\n"); +#elif defined(CONFIG_SPEAR320) + printf("CPU: SPEAr320\n"); +#elif defined(CONFIG_SPEAR600) + printf("CPU: SPEAr600\n"); +#else +#error CPU not supported in spear platform +#endif + return 0; +} +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 8b96d9b..b10c726 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -126,5 +126,12 @@ struct misc_regs { /* PERIPH1_CLKEN, PERIPH1_RST value */ #define MISC_USBDENB 0x01000000 +#define MISC_ETHENB 0x00800000 +#define MISC_SMIENB 0x00200000 +#define MISC_GPT3ENB 0x00010000 +#define MISC_GPT2ENB 0x00000800 +#define MISC_FSMCENB 0x00000200 +#define MISC_I2CENB 0x00000080 +#define MISC_UART0ENB 0x00000008 #endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 669d83e..3a23894 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -183,6 +183,8 @@ #define CONFIG_ENV_SIZE 0x02000 /* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 -- cgit v0.10.2 From f273e5b2a6234f7fb486b8606258364a1cc655eb Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:46 +0530 Subject: SPEAr: Add configuration options for spear3xx and spear6xx boards This patch adds options for all the below mentioned configurations and subsequently renames the include/configs/spearxxx.h files to spear3xx_evb.h, spear6xx_evb.h etc to depict evaluation board configuration. SPEAr3xx and SPEAr6xx boards can be compiled in following configurations 1. Environment placed in NAND 2. Console on usb device 3. Console on usb device with environment placed in NAND 4. SPEAr310 and SPEAr320 support environment variables in parallel NOR flash. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk deleted file mode 100644 index 5848ef8..0000000 --- a/board/spear/spear300/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -CONFIG_SYS_TEXT_BASE = 0x00700000 - -ALL-y += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk deleted file mode 100644 index f8a6bdb..0000000 --- a/board/spear/spear310/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -CONFIG_SYS_TEXT_BASE = 0x00700000 - -ALL-y += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -# Support parallel flash -ifeq ($(FLASH),PNOR) -PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk deleted file mode 100644 index f8a6bdb..0000000 --- a/board/spear/spear320/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -CONFIG_SYS_TEXT_BASE = 0x00700000 - -ALL-y += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -# Support parallel flash -ifeq ($(FLASH),PNOR) -PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk deleted file mode 100644 index 5848ef8..0000000 --- a/board/spear/spear600/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -CONFIG_SYS_TEXT_BASE = 0x00700000 - -ALL-y += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/boards.cfg b/boards.cfg index a864ac5..f28cb31 100644 --- a/boards.cfg +++ b/boards.cfg @@ -178,10 +178,26 @@ omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon -spear300 arm arm926ejs spear300 spear spear spear3xx:spear300 -spear310 arm arm926ejs spear310 spear spear spear3xx:spear310 -spear320 arm arm926ejs spear320 spear spear spear3xx:spear320 -spear600 arm arm926ejs spear600 spear spear spear6xx:spear600 +spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300 +spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand +spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty +spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand +spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310 +spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR +spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand +spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty +spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR +spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand +spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320 +spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR +spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand +spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty +spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR +spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand +spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600 +spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand +spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty +spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB diff --git a/doc/README.spear b/doc/README.spear index a6ff7fd..0789b3f 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -6,9 +6,10 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic The SPEAr SoC family embeds a customizable logic that can be programmed one-time by a customer at silicon mask level (i.e. not at runtime!). -We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx. +U-Boot supports four SoCs: SPEAr600, SPEAr3xx -All 4 SoCs share common peripherals. +All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr300 and +SPEAr600 do not have EMI. 1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) @@ -22,7 +23,7 @@ All 4 SoCs share common peripherals. 10. others .. Everything is supported in Linux. -u-boot is not currently supporting all peripeharls (just a few as listed below). +u-boot is currently not supporting all peripeharls (just a few as listed below). 1. USB Device 2. NAND controller (FSMC) 3. Serial Memory Interface @@ -31,21 +32,38 @@ u-boot is not currently supporting all peripeharls (just a few as listed below). 5. UART Build options - make spear600_config + make spear320_config + spear320 build with environment variables placed at default + location i.e. Serial NOR device + make spear320_pnor_config + This option generates a uboot image that supports emi controller + for CFI compliant parallel NOR flash. Environment variables are + placed in Parallel NOR device + make spear320_nand_config + spear320 build with environment variables placed in NAND device + make spear320_usbtty_config + spear320 build with usbtty terminal as default and environment + placed at default location + make spear320_usbtty_pnor_config + spear320 build with usbtty terminal as default and environment + placed in pnor device + make spear320_usbtty_nand_config + Build with usbtty terminal as default and environment placed in + NAND device make spear300_config + make spear300_nand_config + make spear300_usbtty_config + make spear300_usbtty_nand_config make spear310_config - make spear320_config - -Further options - make ENV=NAND (supported by all 4 SoCs) - - This option generates a uboot image that saves environment inn NAND - - make CONSOLE=USB (supported by all 4 SoCs) - - This option generates a uboot image for using usbdevice as a tty i/f - - make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - - This option generates a uboot image that supports emi controller for - CFI compliant parallel NOR flash + make spear310_pnor_config + make spear310_nand_config + make spear310_usbtty_config + make spear310_usbtty_pnor_config + make spear310_usbtty_nand_config + make spear600_config + make spear600_nand_config + make spear600_usbtty_config + make spear600_usbtty_nand_config Mac id storage and retrieval in spear platforms diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 3a23894..2ba1090 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -27,6 +27,9 @@ * Common configurations used for both spear3xx as well as spear6xx */ +/* U-boot Load Address */ +#define CONFIG_SYS_TEXT_BASE 0x00700000 + /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h deleted file mode 100644 index f3e3354..0000000 --- a/include/configs/spear3xx.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#if defined(CONFIG_spear300) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR300 1 -#elif defined(CONFIG_spear310) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR310 1 -#elif defined(CONFIG_spear320) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR320 1 -#endif - -#include - -/* Ethernet driver configuration */ -#define CONFIG_DW_ALTDESCRIPTOR 1 - -#if defined(CONFIG_SPEAR310) -#define CONFIG_MACB 1 -#define CONFIG_MACB0_PHY 0x01 -#define CONFIG_MACB1_PHY 0x03 -#define CONFIG_MACB2_PHY 0x05 -#define CONFIG_MACB3_PHY 0x07 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_MACB 1 -#define CONFIG_MACB0_PHY 0x01 - -#endif - -/* Serial Configuration (PL011) */ -#define CONFIG_SYS_SERIAL0 0xD0000000 - -#if defined(CONFIG_SPEAR300) -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} - -#elif defined(CONFIG_SPEAR310) - -#if (CONFIG_CONS_INDEX) -#undef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) -#endif - -#define CONFIG_SYS_SERIAL1 0xB2000000 -#define CONFIG_SYS_SERIAL2 0xB2080000 -#define CONFIG_SYS_SERIAL3 0xB2100000 -#define CONFIG_SYS_SERIAL4 0xB2180000 -#define CONFIG_SYS_SERIAL5 0xB2200000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3, \ - (void *)CONFIG_SYS_SERIAL4, \ - (void *)CONFIG_SYS_SERIAL5 } -#elif defined(CONFIG_SPEAR320) - -#if (CONFIG_CONS_INDEX) -#undef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) -#endif - -#define CONFIG_SYS_SERIAL1 0xA3000000 -#define CONFIG_SYS_SERIAL2 0xA4000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2 } -#endif - -#if defined(CONFIG_SPEAR_EMI) - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#if defined(CONFIG_SPEAR310) -#define CONFIG_SYS_FLASH_BASE 0x50000000 -#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 -#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 -#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000 -#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000 -#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_CS1_FLASH_BASE, \ - CONFIG_SYS_CS2_FLASH_BASE, \ - CONFIG_SYS_CS3_FLASH_BASE, \ - CONFIG_SYS_CS4_FLASH_BASE, \ - CONFIG_SYS_CS5_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 6 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_FLASH_BASE 0x44000000 -#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 -#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 -#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_CS1_FLASH_BASE, \ - CONFIG_SYS_CS2_FLASH_BASE, \ - CONFIG_SYS_CS3_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 4 - -#endif - -#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) -#define CONFIG_SYS_FLASH_QUIET_TEST 1 - -#endif - -/* NAND flash configuration */ -#define CONFIG_SYS_FSMC_NAND_SP -#define CONFIG_SYS_FSMC_NAND_8BIT - -#if defined(CONFIG_SPEAR300) -#define CONFIG_SYS_NAND_BASE (0x80000000) - -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_NAND_BASE (0x40000000) - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_NAND_BASE (0x50000000) - -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h new file mode 100644 index 0000000..d6fdc09 --- /dev/null +++ b/include/configs/spear3xx_evb.h @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#if defined(CONFIG_spear300) +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR300 1 +#elif defined(CONFIG_spear310) +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR310 1 +#elif defined(CONFIG_spear320) +#define CONFIG_SPEAR3XX 1 +#define CONFIG_SPEAR320 1 +#endif + +#if defined(CONFIG_usbtty) +#define CONFIG_SPEAR_USBTTY +#endif + +#if defined(CONFIG_nand) +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH +#endif + +#include + +/* Ethernet driver configuration */ +#define CONFIG_DW_ALTDESCRIPTOR 1 + +#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 + +#endif + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 + +#if defined(CONFIG_SPEAR300) +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +#elif defined(CONFIG_SPEAR310) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xB2000000 +#define CONFIG_SYS_SERIAL2 0xB2080000 +#define CONFIG_SYS_SERIAL3 0xB2100000 +#define CONFIG_SYS_SERIAL4 0xB2180000 +#define CONFIG_SYS_SERIAL5 0xB2200000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3, \ + (void *)CONFIG_SYS_SERIAL4, \ + (void *)CONFIG_SYS_SERIAL5 } +#elif defined(CONFIG_SPEAR320) + +#if (CONFIG_CONS_INDEX) +#undef CONFIG_PL011_CLOCK +#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) +#endif + +#define CONFIG_SYS_SERIAL1 0xA3000000 +#define CONFIG_SYS_SERIAL2 0xA4000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2 } +#endif + +#if defined(CONFIG_SPEAR_EMI) + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#if defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FLASH_BASE 0x50000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000 +#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000 +#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE, \ + CONFIG_SYS_CS4_FLASH_BASE, \ + CONFIG_SYS_CS5_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 6 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_BASE 0x44000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 +#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 +#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE, \ + CONFIG_SYS_CS2_FLASH_BASE, \ + CONFIG_SYS_CS3_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 4 + +#endif + +#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) +#define CONFIG_SYS_FLASH_QUIET_TEST 1 + +#endif + +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT + +#if defined(CONFIG_SPEAR300) +#define CONFIG_SYS_NAND_BASE (0x80000000) + +#elif defined(CONFIG_SPEAR310) +#define CONFIG_SYS_NAND_BASE (0x40000000) + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_NAND_BASE (0x50000000) + +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h deleted file mode 100644 index c5bcc30..0000000 --- a/include/configs/spear6xx.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SPEAR600 1 - -#include - -/* Serial Configuration (PL011) */ -#define CONFIG_SYS_SERIAL0 0xD0000000 -#define CONFIG_SYS_SERIAL1 0xD0080000 -#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1 } - -/* NAND flash configuration */ -#define CONFIG_SYS_FSMC_NAND_SP -#define CONFIG_SYS_FSMC_NAND_8BIT -#define CONFIG_SYS_NAND_BASE (0xD2000000) - -#endif /* __CONFIG_H */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h new file mode 100644 index 0000000..18bd140 --- /dev/null +++ b/include/configs/spear6xx_evb.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 1 + +#if defined(CONFIG_usbtty) +#define CONFIG_SPEAR_USBTTY +#endif + +#if defined(CONFIG_nand) +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH +#endif + +#include + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } + +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_BASE (0xD2000000) + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 08166e19217cdcfd268760ecb7e94a3b1bdc4783 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:47 +0530 Subject: SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK) SPEAr doesn't need CONFIG_SYS_HZ_CLOCK. This commit removes it. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 2ba1090..dabd059 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -60,7 +60,6 @@ /* Timer, HZ specific defines */ #define CONFIG_SYS_HZ (1000) -#define CONFIG_SYS_HZ_CLOCK (8300000) /* Flash configuration */ #if defined(CONFIG_FLASH_PNOR) -- cgit v0.10.2 From 1b7935cd96f2295d5cdf144fa46696fb60a820ef Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:48 +0530 Subject: SPEAr: Change the default environment variables This patch modifies the default environment variables as: 1. Default bootargs: - console=ttyAMA0,115200 - For environment present in NOR flash root=/dev/mtdblock3 - For environment present in NAND flash root=/dev/mtdblock7 - Removes "mem=" option 2. Introduces CONFIG_EXTRA_ENV_USBTTY as default usbtty env var even when usbtty is not selected 3. Add default definitions for nfsboot and ramboot 4. Add a new default environment variable(CONFIG_EXTRA_ENV_UNLOCK) for SPEAr310 and SPEAr320 Signifacance of CONFIG_EXTRA_ENV_USBTTY: This environment variable is important for flashing utility to work. So if somebody accidently erases the env sector then also this variable must be preserved so that flashing utility functions properly. Signifacance of CONFIG_EXTRA_ENV_UNLOCK: This env variable is read by the cfi driver to unlock all flash sectors. This is necessary because the Parallel NOR flash connected on the spear310 and spear320 boards, M28W64, has all its sectors in locked state at reset and these have to be unlocked explicitly before being erased or written. Signed-off-by: Vipin Kumar Signed-off-by: Shiraz Hashim Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index dabd059..cf09090 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -46,9 +46,7 @@ #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" #define CONFIG_USBD_MANUFACTURER "ST Microelectronics" -#if defined(CONFIG_USB_TTY) #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" -#endif /* I2C driver configuration */ #define CONFIG_HARD_I2C @@ -143,7 +141,7 @@ */ #define CONFIG_SYS_MONITOR_LEN 0x00040000 #define CONFIG_ENV_SECT_SIZE 0x00010000 -#define CONFIG_FSMTDBLK "/dev/mtdblock8 " +#define CONFIG_FSMTDBLK "/dev/mtdblock3 " #define CONFIG_BOOTCOMMAND "bootm 0xf8050000" @@ -169,19 +167,33 @@ #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_RANGE 0x10000 -#define CONFIG_FSMTDBLK "/dev/mtdblock12 " +#define CONFIG_FSMTDBLK "/dev/mtdblock7 " #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ "0x80000 0x4C0000; " \ "bootm 0x1600000" #endif -#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ - "console=ttyS0 init=/bin/sh" -#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \ + "mem=128M " \ "root="CONFIG_FSMTDBLK \ "rootfstype=jffs2" +#define CONFIG_NFSBOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off " \ + "console=ttyAMA0,115200 $(othbootargs);" \ + "bootm; " + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=ttyAMA0,115200 $(othbootargs);" \ + CONFIG_BOOTCOMMAND + + #define CONFIG_ENV_SIZE 0x02000 /* Miscellaneous configurable options */ @@ -212,8 +224,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY - /* Stack sizes */ #define CONFIG_STACKSIZE (128*1024) diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index d6fdc09..d603785 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -158,4 +158,14 @@ #endif +/* Environment Settings */ +#if defined(CONFIG_SPEAR300) +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + +#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320) +#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0" +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \ + CONFIG_EXTRA_ENV_UNLOCK +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 18bd140..3e0f50b 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -53,4 +53,7 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE (0xD2000000) +/* Environment Settings */ +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 0b7ff3f4595f751ca796456f536c50cae498351d Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:06:49 +0530 Subject: SPEAr: Initialize SNOR in early_board_init_f flash reading is required earlier than flash_init is called since the env_init is called before flash_init. This makes the smi_init necessary before env_init being called. Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index e2918ff..043c72a 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,13 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = gd->ram_size; } +int board_early_init_f() +{ +#if defined(CONFIG_ST_SMI) + smi_init(); +#endif + return 0; +} int misc_init_r(void) { #if defined(CONFIG_CMD_NET) diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index cf09090..c2dff8b 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -198,6 +198,7 @@ /* Miscellaneous configurable options */ #define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG 1 -- cgit v0.10.2 From 507266845025e0ff44892130292d51345596b0ba Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:50 +0530 Subject: SPEAr: Enable usb device high speed support This patch enables the support for usb high speed device for spear platform SOCs Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index c2dff8b..ec97896 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -41,6 +41,7 @@ /* USBD driver configuration */ #define CONFIG_DW_UDC #define CONFIG_USB_DEVICE +#define CONFIG_USBD_HS #define CONFIG_USB_TTY #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" -- cgit v0.10.2 From b884236ec343ca1c24d4bf740fbf883ae16c1cd2 Mon Sep 17 00:00:00 2001 From: Vipin KUMAR Date: Mon, 7 May 2012 13:06:51 +0530 Subject: SPEAr: Enable udc and usb-console support only for usbtty configuration This patch enables the UDC and usb-console support only for usbtty configurations Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index ec97896..bd54a18 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -39,6 +39,7 @@ #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ /* USBD driver configuration */ +#if defined(CONFIG_SPEAR_USBTTY) #define CONFIG_DW_UDC #define CONFIG_USB_DEVICE #define CONFIG_USBD_HS @@ -47,6 +48,8 @@ #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" #define CONFIG_USBD_MANUFACTURER "ST Microelectronics" +#endif + #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" /* I2C driver configuration */ -- cgit v0.10.2 From 25b741a4efc280ab58e8a2d7b669de6d4ea4a7fb Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Mon, 7 May 2012 13:06:52 +0530 Subject: SPEAr: Enable autoneg for ethernet Enabling autoneg avoids situation on few phys with fixed configuration. For example, in one situation, nfs boot timed out when phy configuration is 100Mbps. In another situtation, when traffic is directed to SPEAr, either thru cross-cable or thru switch, the TFTP or DHCP command in u-boot starts to timeout very often. When Autoneg is ON, same phys started working perfectly. Reported-by: Deepak Sikri Reported-by: Armando Visconti Signed-off-by: Shiraz Hashim Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index bd54a18..09604c5 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -37,6 +37,7 @@ #define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ +#define CONFIG_DW_AUTONEG /* USBD driver configuration */ #if defined(CONFIG_SPEAR_USBTTY) -- cgit v0.10.2 From bda7f435a22c024959e831f089da19052cfff113 Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Mon, 7 May 2012 13:06:53 +0530 Subject: SPEAr: Enable dcache for fast file transfer Enable data cache with 1:1 mapping of DDR to enable fast file transfer over tty which was doing lot of copy. This feature is enabled only for flashing operation i.e. when CONFIG_SPEAR_USBTTY is enabled. This has been tested on SPEAr320, SPEAr600 and SPEAr900 evaluation boards. Following figures show an estimate on the performance improvements. The test setup was a Linux host (not Windows) and involved measurement of only binary transfer time, through kermit. The flash erase and flash copy time would be unaffected by these patches. Another thing is this that the timings remained more or less same across ARM9 and Cortex based devices, hence reporting only one of the cases. Before Enhancements =================== $ time ukermit.small -p /dev/ttyACM0 -f spear320_uImage.img Downloading file: 100.00% completed(2014080/2014080 bytes) real 0m41.228s user 0m0.002s sys 0m0.064s After Enhancements ================== $ time ukermit.large -p /dev/ttyACM0 -f spear320_uImage.img Downloading file: 100.00% completed(2014080/2014080 bytes) real 0m5.441s user 0m0.001s sys 0m0.001s Signed-off-by: Shiraz Hashim Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 043c72a..99a6595 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -76,6 +76,10 @@ int misc_init_r(void) setenv("stdin", "usbtty"); setenv("stdout", "usbtty"); setenv("stderr", "usbtty"); + +#ifndef CONFIG_SYS_NO_DCACHE + dcache_enable(); +#endif #endif return 0; } -- cgit v0.10.2 From 484e0b05f2dca43a827c950c91b31e151b48a8ef Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Mon, 7 May 2012 13:06:54 +0530 Subject: SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION This patch enables flash protection(lock/unlock) for CFI devices. This is necessary because the Parallel NOR flash connected on the spear boards, M28W64, can be locked/unlocked on a sector basis. Moreover, all its sectors are in locked state at reset and these have to be unlocked explicitly before being erased or written. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index d603785..242e648 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -111,6 +111,7 @@ #define CONFIG_FLASH_CFI_DRIVER #if defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_BASE 0x50000000 #define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 #define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 @@ -126,6 +127,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 6 #elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_BASE 0x44000000 #define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 #define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 -- cgit v0.10.2 From 0296f1599227280c24f53175ff04cce1faa10373 Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Mon, 7 May 2012 13:06:55 +0530 Subject: SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE The below text is copy pasted from README - CONFIG_SYS_MONITOR_BASE: Physical start address of boot monitor code (set by make config files to be same as the text base address (TEXT_BASE) used when linking) - same as CONFIG_SYS_FLASH_BASE when booting from flash. This patch corrects the definition of CONFIG_SYS_MONITOR_BASE and sets it to TEXT_BASE Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 09604c5..0443bc6 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -162,8 +162,7 @@ "0x4C0000; bootm 0x1600000" #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ CONFIG_SYS_MONITOR_LEN) #elif defined(CONFIG_ENV_IS_IN_NAND) /* @@ -200,6 +199,7 @@ #define CONFIG_ENV_SIZE 0x02000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Miscellaneous configurable options */ #define CONFIG_ARCH_CPU_INIT -- cgit v0.10.2 From cc4b5a34d294ba9fd8dad5a51bf84621310e685d Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Mon, 7 May 2012 13:06:56 +0530 Subject: SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro Enable CONFIG_SYS_FLASH_EMPTY_INFO macro to enable reporting of empty sector information through flinfo command. Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 0443bc6..4f067eb 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -81,7 +81,6 @@ CONFIG_SYS_CS1_FLASH_BASE} #define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) @@ -230,6 +229,8 @@ #define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO + /* Stack sizes */ #define CONFIG_STACKSIZE (128*1024) -- cgit v0.10.2 From bc912e78f4bad932096633815139cd003ad5c485 Mon Sep 17 00:00:00 2001 From: Vipin Kumar Date: Mon, 7 May 2012 13:06:57 +0530 Subject: SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb Signed-off-by: Vipin Kumar Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 4f067eb..aa9ec5d 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -106,6 +106,8 @@ #define CONFIG_NAND_FSMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_QUIET_TEST /* * Command support defines -- cgit v0.10.2 From 8337aa5c0b22bc9e1d8ae9d7b2270735670233bd Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:06:58 +0530 Subject: SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access When CONFIG_MTD_NAND_VERIFY_WRITE is defined, nand driver read back the data everytime it writes. This process unnecessarily slows down the nand access. Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index aa9ec5d..32e1fcc 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -105,7 +105,6 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_NAND_FSMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_QUIET_TEST -- cgit v0.10.2 From 7c885a0e5532abcd6bc802d21a7858420e5c127b Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Mon, 7 May 2012 13:06:59 +0530 Subject: SPEAr: explicitly select clk src for UART UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 9e074bc..e299de3 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -30,7 +30,7 @@ int arch_cpu_init(void) { struct misc_regs *const misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; - u32 periph1_clken; + u32 periph1_clken, periph_clk_cfg; periph1_clken = readl(&misc_p->periph1_clken); @@ -42,6 +42,11 @@ int arch_cpu_init(void) #if defined(CONFIG_PL011_SERIAL) periph1_clken |= MISC_UART0ENB; + + periph_clk_cfg = readl(&misc_p->periph_clk_cfg); + periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK; + periph_clk_cfg |= CONFIG_SPEAR_UART48M; + writel(periph_clk_cfg, &misc_p->periph_clk_cfg); #endif #if defined(CONFIG_DESIGNWARE_ETH) periph1_clken |= MISC_ETHENB; diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index b10c726..384944d 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -110,6 +110,8 @@ struct misc_regs { /* PERIPH_CLK_CFG value */ #define MISC_GPT3SYNTH 0x00000400 #define MISC_GPT4SYNTH 0x00000800 +#define CONFIG_SPEAR_UART48M 0 +#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4) /* PRSC_CLK_CFG value */ /* -- cgit v0.10.2 From f28e5c946d6c88b1c8639896863c7ad7d8889bf4 Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Mon, 7 May 2012 13:07:00 +0530 Subject: SPEAr: Correct SoC ID offset in misc configuration space SoC Core ID offset is 0x30 in miscellaneous configuration address space. It was wrongly mentioned as periph2 clk enable. Signed-off-by: Shiraz Hashim Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 384944d..b8fcf49 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -37,7 +37,7 @@ struct misc_regs { u32 amba_clk_cfg; /* 0x24 */ u32 periph_clk_cfg; /* 0x28 */ u32 periph1_clken; /* 0x2C */ - u32 periph2_clken; /* 0x30 */ + u32 soc_core_id; /* 0x30 */ u32 ras_clken; /* 0x34 */ u32 periph1_rst; /* 0x38 */ u32 periph2_rst; /* 0x3C */ -- cgit v0.10.2 From bc0bdf4c2296d02802ddfa76f349cbba3a869138 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:07:01 +0530 Subject: cleanup/SPEAr: Remove unnecessary parenthesis In SPEAr configuration files, unnecessary paranthesis are used in some \#defines. Remove them as they serve no purpose Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h index 965b5ab..d95ba52 100644 --- a/arch/arm/include/asm/arch-spear/spr_gpt.h +++ b/arch/arm/include/asm/arch-spear/spr_gpt.h @@ -79,7 +79,7 @@ struct gpt_regs { #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_SPEAR_HZ (1000) -#define CONFIG_SPEAR_HZ_CLOCK (8300000) +#define CONFIG_SPEAR_HZ 1000 +#define CONFIG_SPEAR_HZ_CLOCK 8300000 #endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 32e1fcc..0aa9551 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -62,7 +62,7 @@ #define CONFIG_I2C_CHIPADDRESS 0x50 /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ (1000) +#define CONFIG_SYS_HZ 1000 /* Flash configuration */ #if defined(CONFIG_FLASH_PNOR) @@ -74,9 +74,9 @@ #if defined(CONFIG_ST_SMI) #define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BASE (0xF8000000) -#define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000) -#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_BASE 0xF8000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_CS1_FLASH_BASE} #define CONFIG_SYS_MAX_FLASH_SECT 128 diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index 242e648..d63c9df 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -150,13 +150,13 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #if defined(CONFIG_SPEAR300) -#define CONFIG_SYS_NAND_BASE (0x80000000) +#define CONFIG_SYS_NAND_BASE 0x80000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_NAND_BASE (0x40000000) +#define CONFIG_SYS_NAND_BASE 0x40000000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_NAND_BASE (0x50000000) +#define CONFIG_SYS_NAND_BASE 0x50000000 #endif diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 3e0f50b..4a76134 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -51,7 +51,7 @@ /* NAND flash configuration */ #define CONFIG_SYS_FSMC_NAND_SP #define CONFIG_SYS_FSMC_NAND_8BIT -#define CONFIG_SYS_NAND_BASE (0xD2000000) +#define CONFIG_SYS_NAND_BASE 0xD2000000 /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY -- cgit v0.10.2 From 9b382b43a1db000a78822ad9e1814577dd2e1a19 Mon Sep 17 00:00:00 2001 From: Amit Virdi Date: Mon, 7 May 2012 13:07:02 +0530 Subject: cleanup/SPEAr: Define configuration flags more elegantly In SPEAr, some of the configuration flags eg. CONFIG_SPEAR_EMI, were given value "1", which isn't required. Define the flags without assigning any value Signed-off-by: Amit Virdi Acked-by: Stefan Roese Signed-off-by: Stefan Roese diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 0aa9551..36c2a8b 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -66,7 +66,7 @@ /* Flash configuration */ #if defined(CONFIG_FLASH_PNOR) -#define CONFIG_SPEAR_EMI 1 +#define CONFIG_SPEAR_EMI #else #define CONFIG_ST_SMI #endif @@ -206,11 +206,11 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_PROMPT \ "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay @@ -228,7 +228,7 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x00800000 -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_FLASH_EMPTY_INFO diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h index d63c9df..3cd56dc 100644 --- a/include/configs/spear3xx_evb.h +++ b/include/configs/spear3xx_evb.h @@ -29,14 +29,14 @@ * (easy to change) */ #if defined(CONFIG_spear300) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR300 1 +#define CONFIG_SPEAR3XX +#define CONFIG_SPEAR300 #elif defined(CONFIG_spear310) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR310 1 +#define CONFIG_SPEAR3XX +#define CONFIG_SPEAR310 #elif defined(CONFIG_spear320) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR320 1 +#define CONFIG_SPEAR3XX +#define CONFIG_SPEAR320 #endif #if defined(CONFIG_usbtty) @@ -52,17 +52,17 @@ #include /* Ethernet driver configuration */ -#define CONFIG_DW_ALTDESCRIPTOR 1 +#define CONFIG_DW_ALTDESCRIPTOR #if defined(CONFIG_SPEAR310) -#define CONFIG_MACB 1 +#define CONFIG_MACB #define CONFIG_MACB0_PHY 0x01 #define CONFIG_MACB1_PHY 0x03 #define CONFIG_MACB2_PHY 0x05 #define CONFIG_MACB3_PHY 0x07 #elif defined(CONFIG_SPEAR320) -#define CONFIG_MACB 1 +#define CONFIG_MACB #define CONFIG_MACB0_PHY 0x01 #endif @@ -141,7 +141,7 @@ #endif #define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) -#define CONFIG_SYS_FLASH_QUIET_TEST 1 +#define CONFIG_SYS_FLASH_QUIET_TEST #endif diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 4a76134..31b8725 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -28,7 +28,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SPEAR600 1 +#define CONFIG_SPEAR600 #if defined(CONFIG_usbtty) #define CONFIG_SPEAR_USBTTY -- cgit v0.10.2 From ef76025a99247cdb8f927a2c9f15400678dfb599 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 7 May 2012 12:04:25 +0200 Subject: net: Multiple updates/enhancements to designware.c This patch adds the following changes to designware ethernet driver found on the ST SPEAr SoC: - Don't init MAC & PHY upon startup. This causes a delay, waiting for the auto negotiation to complete. And we don't want this delay to always happen. Especially not on platforms where ethernet is not used at all (e.g. booting via flash). Instead postpone the MAC / PHY configuration to the stage, where ethernet is first used. - Add possibility for board specific PHY init code. This is needed for example on the X600 board, where the Vitesse PHY needs to be configured for GMII mode. This board specific PHY init is done via the function designware_board_phy_init(). And this driver now adds a weak default which can be overridden by board code. - Use common functions miiphy_speed() & miiphy_duplex() to read link status from PHY. - Print status and progress of auto negotiation. - Print link status (speed, dupex) upon first usage. Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar Cc: Joe Hershberger Acked-by: Joe Hershberger diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 8f22e00..326d550 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include "designware.h" @@ -153,6 +154,13 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) if (priv->phy_configured != 1) configure_phy(dev); + /* Print link status only once */ + if (!priv->link_printed) { + printf("ENET Speed is %d Mbps - %s duplex connection\n", + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); + priv->link_printed = 1; + } + /* Reset ethernet hardware */ if (mac_reset(dev) < 0) return -1; @@ -168,17 +176,17 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) conf = FRAMEBURSTENABLE | DISABLERXOWN; - if (priv->speed != SPEED_1000M) + if (priv->speed != 1000) conf |= MII_PORTSELECT; if ((priv->interface != PHY_INTERFACE_MODE_MII) && (priv->interface != PHY_INTERFACE_MODE_GMII)) { - if (priv->speed == SPEED_100M) + if (priv->speed == 100) conf |= FES_100; } - if (priv->duplex == FULL_DUPLEX) + if (priv->duplex == FULL) conf |= FULLDPLXMODE; writel(conf, &mac_p->conf); @@ -396,6 +404,16 @@ static int dw_reset_phy(struct eth_device *dev) return 0; } +/* + * Add weak default function for board specific PHY configuration + */ +int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + return 0; +} + static int configure_phy(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; @@ -405,9 +423,6 @@ static int configure_phy(struct eth_device *dev) u16 bmsr; u32 timeout; ulong start; - u16 anlpar, btsr; -#else - u16 ctrl; #endif #if defined(CONFIG_DW_SEARCH_PHY) @@ -419,6 +434,16 @@ static int configure_phy(struct eth_device *dev) #else phy_addr = priv->address; #endif + + /* + * Some boards need board specific PHY initialization. This is + * after the main driver init code but before the auto negotiation + * is run. + */ + if (designware_board_phy_init(dev, phy_addr, + eth_mdio_write, dw_reset_phy) < 0) + return -1; + if (dw_reset_phy(dev) < 0) return -1; @@ -444,72 +469,32 @@ static int configure_phy(struct eth_device *dev) #if defined(CONFIG_DW_AUTONEG) timeout = CONFIG_AUTONEG_TIMEOUT; start = get_timer(0); - + puts("Waiting for PHY auto negotiation to complete"); while (get_timer(start) < timeout) { eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) + if (bmsr & BMSR_ANEGCOMPLETE) { + priv->phy_configured = 1; break; - - /* Try again after 10usec */ - udelay(10); - }; - - eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); - eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); - - if (bmsr & BMSR_ANEGCOMPLETE) { - if (btsr & PHY_1000BTSR_1000FD) { - priv->speed = SPEED_1000M; - bmcr |= BMCR_SPEED1000; - priv->duplex = FULL_DUPLEX; - bmcr |= BMCR_FULLDPLX; - } else if (btsr & PHY_1000BTSR_1000HD) { - priv->speed = SPEED_1000M; - bmcr |= BMCR_SPEED1000; - priv->duplex = HALF_DUPLEX; - bmcr &= ~BMCR_FULLDPLX; - } else if (anlpar & LPA_100FULL) { - priv->speed = SPEED_100M; - bmcr |= BMCR_SPEED100; - priv->duplex = FULL_DUPLEX; - bmcr |= BMCR_FULLDPLX; - } else if (anlpar & LPA_100HALF) { - priv->speed = SPEED_100M; - bmcr |= BMCR_SPEED100; - priv->duplex = HALF_DUPLEX; - bmcr &= ~BMCR_FULLDPLX; - } else if (anlpar & LPA_10FULL) { - priv->speed = SPEED_10M; - bmcr &= ~BMCR_SPEED100; - priv->duplex = FULL_DUPLEX; - bmcr |= BMCR_FULLDPLX; - } else { - priv->speed = SPEED_10M; - bmcr &= ~BMCR_SPEED100; - priv->duplex = HALF_DUPLEX; - bmcr &= ~BMCR_FULLDPLX; } - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - } else - return -1; -#else - if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) - return -1; - if (ctrl & BMCR_FULLDPLX) - priv->duplex = FULL_DUPLEX; - else - priv->duplex = HALF_DUPLEX; + /* Print dot all 1s to show progress */ + if ((get_timer(start) % 1000) == 0) + putc('.'); + + /* Try again after 1msec */ + udelay(1000); + }; - if (ctrl & BMCR_SPEED1000) - priv->speed = SPEED_1000M; - else if (ctrl & BMCR_SPEED100) - priv->speed = SPEED_100M; + if (!(bmsr & BMSR_ANEGCOMPLETE)) + puts(" TIMEOUT!\n"); else - priv->speed = SPEED_10M; -#endif + puts(" done\n"); +#else priv->phy_configured = 1; +#endif + + priv->speed = miiphy_speed(dev->name, phy_addr); + priv->duplex = miiphy_duplex(dev->name, phy_addr); return 0; } @@ -574,11 +559,6 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) priv->phy_configured = 0; priv->interface = interface; - if (mac_reset(dev) < 0) - return -1; - - configure_phy(dev); - dev->init = dw_eth_init; dev->send = dw_eth_send; dev->recv = dw_eth_recv; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 40020bf..d668f8f 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -240,6 +240,7 @@ struct dw_eth_dev { u32 tx_currdescnum; u32 rx_currdescnum; u32 phy_configured; + int link_printed; u32 padding; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 36c2a8b..a6d1cfb 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -38,6 +38,7 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_DW_AUTONEG +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ #if defined(CONFIG_SPEAR_USBTTY) -- cgit v0.10.2 From 2cb06a4fda4e7a88c734adaec9eeb5059e50f76b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Feb 2012 14:01:36 +0100 Subject: GPIO: Add SPEAr GPIO driver Tested on x600 (SPEAr600). Signed-off-by: Stefan Roese diff --git a/arch/arm/include/asm/arch-spear/gpio.h b/arch/arm/include/asm/arch-spear/gpio.h new file mode 100644 index 0000000..c3697de --- /dev/null +++ b/arch/arm/include/asm/arch-spear/gpio.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_SPEAR_GPIO_H +#define __ASM_ARCH_SPEAR_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ + u32 gpiodir; /* 0x400 */ +}; + +#define SPEAR_GPIO_COUNT 8 +#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) + +#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 5ae68d5..32a2474 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_PCA9698) += pca9698.o COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS-$(CONFIG_SANDBOX_GPIO) += sandbox.o +COBJS-$(CONFIG_SPEAR_GPIO) += spear_gpio.o COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c new file mode 100644 index 0000000..d3c728e --- /dev/null +++ b/drivers/gpio/spear_gpio.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Driver for SPEAr600 GPIO controller + */ + +#include +#include +#include +#include +#include + +static int gpio_direction(unsigned gpio, + enum gpio_direction direction) +{ + struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; + u32 val; + + val = readl(®s->gpiodir); + + if (direction == GPIO_DIRECTION_OUT) + val |= 1 << gpio; + else + val &= ~(1 << gpio); + + writel(val, ®s->gpiodir); + + return 0; +} + +int gpio_set_value(unsigned gpio, int value) +{ + struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; + + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; + u32 val; + + val = readl(®s->gpiodata[DATA_REG_ADDR(gpio)]); + + return !!val; +} + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio >= SPEAR_GPIO_COUNT) + return -EINVAL; + + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +void gpio_toggle_value(unsigned gpio) +{ + gpio_set_value(gpio, !gpio_get_value(gpio)); +} + +int gpio_direction_input(unsigned gpio) +{ + return gpio_direction(gpio, GPIO_DIRECTION_IN); +} + +int gpio_direction_output(unsigned gpio, int value) +{ + int ret = gpio_direction(gpio, GPIO_DIRECTION_OUT); + + if (ret < 0) + return ret; + + gpio_set_value(gpio, value); + return 0; +} -- cgit v0.10.2 From fe901f2d9bd09292a67e562b8c96a1a496004c9e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 3 Mar 2012 12:33:15 -0800 Subject: arm: Don't use printf() in SPL builds raise() likes to call printf() if it is available, but in SPL builds it either is not available, or adds a large chunk to the resulting image size. So don't call it even if it is available. This change reduces SPL size from 10KB to 6.3KB on hawkboard, for example, using generic relocation. Signed-off-by: Simon Glass Acked-by: Stefan Roese diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 2028dbd..44eebe0 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -13,7 +13,8 @@ int raise (int signum) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + /* Even if printf() is available, it's large. Punt it for SPL builds */ +#if !defined(CONFIG_SPL_BUILD) printf("raise: Signal # %d caught\n", signum); #endif return 0; -- cgit v0.10.2 From 22b7cfff326b5de5bfe94d676d9051a115c6aad1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 5 Jan 2012 10:53:09 +0100 Subject: SPL: common/Makefile: Add image.c to SPL build This is needed for the SPEAr SPL support, as SPEAr uses the mkimage header to wrap and validate the images (SPL & U-Boot). Signed-off-by: Stefan Roese diff --git a/common/Makefile b/common/Makefile index 31175e3..483eb4d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -31,7 +31,6 @@ COBJS-y += main.o COBJS-y += command.o COBJS-y += exports.o COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o -COBJS-y += image.o COBJS-y += s_record.o COBJS-$(CONFIG_SERIAL_MULTI) += serial.o COBJS-y += xyzModem.o @@ -191,6 +190,7 @@ COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o endif COBJS-y += console.o COBJS-y += dlmalloc.o +COBJS-y += image.o COBJS-y += memsize.o COBJS-y += stdio.o -- cgit v0.10.2 From aca587b0dad5f760e7db0a49e928fd87affcd123 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 5 Jan 2012 10:57:20 +0100 Subject: SPL: lib/Makefile: Add crc32.c to SPL build This is needed for the SPEAr SPL support, as SPEAr uses the mkimage header to wrap and validate the images (SPL & U-Boot). Signed-off-by: Stefan Roese diff --git a/lib/Makefile b/lib/Makefile index 556601c..c60c380 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -37,7 +37,6 @@ COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o COBJS-$(CONFIG_USB_TTY) += circbuf.o COBJS-y += crc7.o COBJS-y += crc16.o -COBJS-y += crc32.o COBJS-y += display_options.o COBJS-y += errno.o COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o @@ -60,6 +59,7 @@ endif ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o endif +COBJS-y += crc32.o COBJS-y += ctype.o COBJS-y += div64.o COBJS-y += string.o -- cgit v0.10.2 From d014e033889f10d40d009cc7bad00893293b640e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 5 Jan 2012 11:23:45 +0100 Subject: SPL: ARM: spear: Remove some objects from SPL build Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 11f81e4..5c66c3f 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -29,8 +29,10 @@ endif LIB = $(obj)lib$(VENDOR).o +ifndef CONFIG_SPL_BUILD COBJS := spr_misc.o SOBJS := spr_lowlevel_init.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile index e2bd5ab..ee66fc6 100644 --- a/board/spear/spear600/Makefile +++ b/board/spear/spear600/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := spear600.o +endif SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -- cgit v0.10.2 From 94aebe6cc3111c7c9e3cd1311cc9793d01cc3ded Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 5 Jan 2012 11:19:50 +0100 Subject: Makefile: Add u-boot.spr build target (SPEAr) On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. Both images are created using mkimage (crc etc), so that the ROM bootloader can check its integrity. Padding needs to be done to the SPL image (with mkimage header) and not the binary. Otherwise the resulting image which is loaded/copied by the ROM bootloader to SRAM doesn't fit. The resulting image containing both U-Boot images is called u-boot.spr. Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar diff --git a/Makefile b/Makefile index 0197239..85e36ec 100644 --- a/Makefile +++ b/Makefile @@ -456,6 +456,22 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ -o $(obj)u-boot.sb +# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. +# Both images are created using mkimage (crc etc), so that the ROM +# bootloader can check its integrity. Padding needs to be done to the +# SPL image (with mkimage header) and not the binary. Otherwise the resulting image +# which is loaded/copied by the ROM bootloader to SRAM doesn't fit. +# The resulting image containing both U-Boot images is called u-boot.spr +$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin + $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ + -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img + tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \ + of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null + dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \ + conv=notrunc 2>/dev/null + cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@ + ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ @@ -775,6 +791,7 @@ clobber: tidy @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.sb + @rm -f $(obj)u-boot.spr @rm -f $(obj)tools/inca-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c diff --git a/config.mk b/config.mk index c239f23..3dcea6a 100644 --- a/config.mk +++ b/config.mk @@ -205,6 +205,10 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) endif +ifneq ($(CONFIG_SPL_PAD_TO),) +CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) +endif + ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD endif -- cgit v0.10.2 From 4ae8bc4392ec038566276e15c4dfe29f0fe9682f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 3 Jan 2012 16:49:01 +0100 Subject: SPL: ARM: spear: Add SPL support for SPEAr600 platform This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 46923a4..d06f03d 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -25,17 +25,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := cpu.o \ +COBJS-y := cpu.o \ reset.o \ timer.o -SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o spl_boot.o +COBJS-$(CONFIG_SPEAR600) += spear600.o +COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o +COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o +COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o +COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o +endif -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c new file mode 100644 index 0000000..ff52131 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spear600.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2000-2009 + * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define FALSE 0 +#define TRUE (!FALSE) + +static void sel_1v8(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddr1v8, ddr2v5; + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000003; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000010; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) + ; +} + +static void sel_2v5(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddr1v8, ddr2v5; + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000003; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000010; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) + ; +} + +/* + * plat_ddr_init: + */ +void plat_ddr_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddrpad; + u32 core3v3, ddr1v8, ddr2v5; + + /* DDR pad register configurations */ + ddrpad = readl(&misc_p->ddr_pad); + ddrpad &= ~DDR_PAD_CNF_MSK; + +#if (CONFIG_DDR_HCLK) + ddrpad |= 0xEAAB; +#elif (CONFIG_DDR_2HCLK) + ddrpad |= 0xEAAD; +#elif (CONFIG_DDR_PLL2) + ddrpad |= 0xEAAD; +#endif + writel(ddrpad, &misc_p->ddr_pad); + + /* Compensation register configurations */ + core3v3 = readl(&misc_p->core_3v3_compensation); + core3v3 &= 0x8080ffe0; + core3v3 |= 0x78000002; + writel(core3v3, &misc_p->core_3v3_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000004; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000004; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) { + /* Software memory configuration */ + if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL) + sel_1v8(); + else + sel_2v5(); + } else { + /* Hardware memory configuration */ + if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE) + sel_1v8(); + else + sel_2v5(); + } +} + +/* + * soc_init: + */ +void soc_init(void) +{ + /* Nothing to be done for SPEAr600 */ +} + +/* + * xxx_boot_selected: + * + * return TRUE if the particular booting option is selected + * return FALSE otherwise + */ +static u32 read_bootstrap(void) +{ + return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT) + & CONFIG_SPEAR_BOOTSTRAPMASK; +} + +int snor_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (SNOR_BOOT_SUPPORTED) { + /* Check whether SNOR boot is selected */ + if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == + CONFIG_SPEAR_ONLYSNORBOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND8BOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND16BOOT) + return TRUE; + } + + return FALSE; +} + +int nand_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (NAND_BOOT_SUPPORTED) { + /* Check whether NAND boot is selected */ + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND8BOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND16BOOT) + return TRUE; + } + + return FALSE; +} + +int pnor_boot_selected(void) +{ + /* Parallel NOR boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int usb_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (USB_BOOT_SUPPORTED) { + /* Check whether USB boot is selected */ + if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) + return TRUE; + } + + return FALSE; +} + +int tftp_boot_selected(void) +{ + /* TFTP boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int uart_boot_selected(void) +{ + /* UART boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int spi_boot_selected(void) +{ + /* SPI boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int i2c_boot_selected(void) +{ + /* I2C boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int mmc_boot_selected(void) +{ + return FALSE; +} + +void plat_late_init(void) +{ + spear_late_init(); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c new file mode 100644 index 0000000..48e6efb --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +inline void hang(void) +{ + serial_puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +static void ddr_clock_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 clkenb, ddrpll; + + clkenb = readl(&misc_p->periph1_clken); + clkenb &= ~PERIPH_MPMCMSK; + clkenb |= PERIPH_MPMC_WE; + + /* Intentionally done twice */ + writel(clkenb, &misc_p->periph1_clken); + writel(clkenb, &misc_p->periph1_clken); + + ddrpll = readl(&misc_p->pll_ctr_reg); + ddrpll &= ~MEM_CLK_SEL_MSK; +#if (CONFIG_DDR_HCLK) + ddrpll |= MEM_CLK_HCLK; +#elif (CONFIG_DDR_2HCLK) + ddrpll |= MEM_CLK_2HCLK; +#elif (CONFIG_DDR_PLL2) + ddrpll |= MEM_CLK_PLL2; +#else +#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)" +#endif + writel(ddrpll, &misc_p->pll_ctr_reg); + + writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN, + &misc_p->periph1_clken); +} + +static void mpmc_init_values(void) +{ + u32 i; + u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; + u32 *mpmc_val_p = &mpmc_conf_vals[0]; + + for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++) + writel(*mpmc_val_p, mpmc_reg_p); + + mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; + + /* + * MPMC controller start + * MPMC waiting for DLLLOCKREG high + */ + writel(0x01000100, &mpmc_reg_p[7]); + + while (!(readl(&mpmc_reg_p[3]) & 0x10000)) + ; +} + +static void mpmc_init(void) +{ + /* Clock related settings for DDR */ + ddr_clock_init(); + + /* + * DDR pad register bits are different for different SoCs + * Compensation values are also handled separately + */ + plat_ddr_init(); + + /* Initialize mpmc register values */ + mpmc_init_values(); +} + +static void pll_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Initialize PLLs */ + writel(FREQ_332, &misc_p->pll1_frq); + writel(0x1C0A, &misc_p->pll1_cntl); + writel(0x1C0E, &misc_p->pll1_cntl); + writel(0x1C06, &misc_p->pll1_cntl); + writel(0x1C0E, &misc_p->pll1_cntl); + + writel(FREQ_332, &misc_p->pll2_frq); + writel(0x1C0A, &misc_p->pll2_cntl); + writel(0x1C0E, &misc_p->pll2_cntl); + writel(0x1C06, &misc_p->pll2_cntl); + writel(0x1C0E, &misc_p->pll2_cntl); + + /* wait for pll locks */ + while (!(readl(&misc_p->pll1_cntl) & 0x1)) + ; + while (!(readl(&misc_p->pll2_cntl) & 0x1)) + ; +} + +static void mac_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC), + &misc_p->periph1_clken); + + writel(SYNTH23, &misc_p->gmac_synth_clk); + + switch (get_socrev()) { + case SOC_SPEAR600_AA: + case SOC_SPEAR600_AB: + case SOC_SPEAR600_BA: + case SOC_SPEAR600_BB: + case SOC_SPEAR600_BC: + case SOC_SPEAR600_BD: + writel(0x0, &misc_p->gmac_ctr_reg); + break; + + case SOC_SPEAR300: + case SOC_SPEAR310: + case SOC_SPEAR320: + writel(0x4, &misc_p->gmac_ctr_reg); + break; + } + + writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC, + &misc_p->periph1_clken); + + writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC, + &misc_p->periph1_rst); + writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC), + &misc_p->periph1_rst); +} + +static void sys_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct syscntl_regs *syscntl_p = + (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; + + /* Set system state to SLOW */ + writel(SLOW, &syscntl_p->scctrl); + writel(PLL_TIM << 3, &syscntl_p->scpllctrl); + + /* Initialize PLLs */ + pll_init(); + + /* + * Ethernet configuration + * To be done only if the tftp boot is not selected already + * Boot code ensures the correct configuration in tftp booting + */ + if (!tftp_boot_selected()) + mac_init(); + + writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg); + writel(0x555, &misc_p->amba_clk_cfg); + + writel(NORMAL, &syscntl_p->scctrl); + + /* Wait for system to switch to normal mode */ + while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK) + != NORMAL) + ; +} + +/* + * get_socrev + * + * Get SoC Revision. + * @return SOC_SPEARXXX + */ +int get_socrev(void) +{ +#if defined(CONFIG_SPEAR600) + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 soc_id = readl(&misc_p->soc_core_id); + u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF; + u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF; + + if ((pri_socid == 'B') && (sec_socid == 'B')) + return SOC_SPEAR600_BB; + else if ((pri_socid == 'B') && (sec_socid == 'C')) + return SOC_SPEAR600_BC; + else if ((pri_socid == 'B') && (sec_socid == 'D')) + return SOC_SPEAR600_BD; + else if (soc_id == 0) + return SOC_SPEAR600_BA; + else + return SOC_SPEAR_NA; +#elif defined(CONFIG_SPEAR300) + return SOC_SPEAR300; +#elif defined(CONFIG_SPEAR310) + return SOC_SPEAR310; +#elif defined(CONFIG_SPEAR320) + return SOC_SPEAR320; +#endif +} + +void lowlevel_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + const char *u_boot_rev = U_BOOT_VERSION; + + /* Initialize PLLs */ + sys_init(); + + /* Initialize UART */ + serial_init(); + + /* Print U-Boot SPL version string */ + serial_puts("\nU-Boot SPL "); + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + serial_puts(u_boot_rev); + serial_puts(" ("); + serial_puts(U_BOOT_DATE); + serial_puts(" - "); + serial_puts(U_BOOT_TIME); + serial_puts(")\n"); + +#if defined(CONFIG_OS_BOOT) + writel(readl(&misc_p->periph1_clken) | PERIPH_UART1, + &misc_p->periph1_clken); +#endif + + /* Enable IPs (release reset) */ + writel(PERIPH_RST_ALL, &misc_p->periph1_rst); + + /* Initialize MPMC */ + serial_puts("Configure DDR\n"); + mpmc_init(); + + /* SoC specific initialization */ + soc_init(); +} + +void spear_late_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(0x80000007, &misc_p->arb_icm_ml1); + writel(0x80000007, &misc_p->arb_icm_ml2); + writel(0x80000007, &misc_p->arb_icm_ml3); + writel(0x80000007, &misc_p->arb_icm_ml4); + writel(0x80000007, &misc_p->arb_icm_ml5); + writel(0x80000007, &misc_p->arb_icm_ml6); + writel(0x80000007, &misc_p->arb_icm_ml7); + writel(0x80000007, &misc_p->arb_icm_ml8); + writel(0x80000007, &misc_p->arb_icm_ml9); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c new file mode 100644 index 0000000..f2f9a49 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +static const char kernel_name[] = "Linux"; +static const char loader_name[] = "U-Boot"; + +int image_check_header(image_header_t *hdr, const char *name) +{ + if (image_check_magic(hdr) && + (!strncmp(image_get_name(hdr), name, strlen(name))) && + image_check_hcrc(hdr)) { + return 1; + } + return 0; +} + +int image_check_data(image_header_t *hdr) +{ + if (image_check_dcrc(hdr)) + return 1; + + return 0; +} + +/* + * SNOR (Serial NOR flash) related functions + */ +void snor_init(void) +{ + struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; + + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +static int snor_image_load(u8 *load_addr, void (**image_p)(void), + const char *image_name) +{ + image_header_t *header; + + /* + * Since calculating the crc in the SNOR flash does not + * work, we copy the image to the destination address + * minus the header size. And point the header to this + * new destination. This will not work for address 0 + * of course. + */ + header = (image_header_t *)load_addr; + memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)), + (const ulong *)load_addr, + image_get_data_size(header) + sizeof(image_header_t)); + header = (image_header_t *)(image_get_load(header) - + sizeof(image_header_t)); + + if (image_check_header(header, image_name)) { + if (image_check_data(header)) { + /* Jump to boot image */ + *image_p = (void *)image_get_load(header); + return 1; + } + } + + return 0; +} + +static void boot_image(void (*image)(void)) +{ + void (*funcp)(void) __noreturn = (void *)image; + + (*funcp)(); +} + +/* + * spl_boot: + * + * All supported booting types of all supported SoCs are listed here. + * Generic readback APIs are provided for each supported booting type + * eg. nand_read_skip_bad + */ +u32 spl_boot(void) +{ + void (*image)(void); + +#ifdef CONFIG_SPEAR_USBTTY + plat_late_init(); + return 1; +#endif + + /* + * All the supported booting devices are listed here. Each of + * the booting type supported by the platform would define the + * macro xxx_BOOT_SUPPORTED to TRUE. + */ + + if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { + /* SNOR-SMI initialization */ + snor_init(); + + serial_puts("Booting via SNOR\n"); + /* Serial NOR booting */ + if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE, + &image, loader_name)) { + /* Platform related late initialasations */ + plat_late_init(); + + /* Jump to boot image */ + serial_puts("Jumping to U-Boot\n"); + boot_image(image); + return 1; + } + } + + if (NAND_BOOT_SUPPORTED && nand_boot_selected()) { + /* NAND booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) { + /* PNOR booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) { + /* MMC booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (SPI_BOOT_SUPPORTED && spi_boot_selected()) { + /* SPI booting */ + /* Not supported for any platform as of now */ + return 0; + } + + if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) { + /* I2C booting */ + /* Not supported for any platform as of now */ + return 0; + } + + /* + * All booting types without memory are listed as below + * Control has to be returned to BootROM in case of all + * the following booting scenarios + */ + + if (USB_BOOT_SUPPORTED && usb_boot_selected()) { + plat_late_init(); + return 1; + } + + if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) { + plat_late_init(); + return 1; + } + + if (UART_BOOT_SUPPORTED && uart_boot_selected()) { + plat_late_init(); + return 1; + } + + /* Ideally, the control should not reach here. */ + hang(); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c new file mode 100644 index 0000000..5edc115 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_DDR_PLL2) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x00000001, + 0x00000000, + 0x01000000, + 0x00000101, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000003, + 0x01000201, + 0x06000202, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000404, + 0x02030202, + 0x03000204, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x08080a01, + 0x0000023f, + 0x00040800, + 0x00000000, + 0x00000f02, + 0x00001b1b, + 0x7f000000, + 0x005f0000, + 0x1c040b6a, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x000007ff, + 0x00000000, + 0x47ec00c8, + 0x00c8001f, + 0x00000000, + 0x0000cd98, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00270000, + 0x00250027, + 0x00300000, + 0x008900b7, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c new file mode 100644 index 0000000..616b861 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if (CONFIG_DDR_PLL2) + 0x00000001, + 0x00000000, +#elif (CONFIG_DDR_2HCLK) + 0x02020201, + 0x02020202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x01010001, + 0x00000201, + 0x01000101, + 0x06000002, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000405, + 0x03040202, + 0x04000305, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x0a0a0a01, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00000A0A, + 0x72000000, + 0x00550000, + 0x2b050e86, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000a24, + 0x43C20000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00210000, + 0x00010021, + 0x00200000, + 0x006c0090, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c new file mode 100644 index 0000000..b89f77d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_DDR_HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x03030301, + 0x03030303, + 0x01000000, + 0x00000101, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000003, + 0x01000201, + 0x06000202, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000404, + 0x02020202, + 0x03000203, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x08080a01, + 0x0000023f, + 0x00030600, + 0x00000000, + 0x00000a02, + 0x00001c1c, + 0x7f000000, + 0x005f0000, + 0x12030743, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x0000050e, + 0x00000000, + 0x2d8900c8, + 0x00c80014, + 0x00000000, + 0x00008236, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00400000, + 0x003a0040, + 0x00680000, + 0x00d80120, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c new file mode 100644 index 0000000..0c39cd1 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if (CONFIG_DDR_PLL2) + 0x00000001, + 0x00000000, +#elif (CONFIG_DDR_2HCLK) + 0x02020201, + 0x02020202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x01010001, + 0x00000201, + 0x01000101, + 0x06000002, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, +#ifdef CONFIG_X600 + 0x02030206, +#else + 0x02010106, +#endif + 0x03000405, + 0x03040202, + 0x04000305, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x0a0a0a01, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00000A0A, +#ifdef CONFIG_X600 + 0x7f000000, + 0x005c0000, +#else + 0x72000000, + 0x00550000, +#endif + 0x2b050e86, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000a24, + 0x43C20000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00210000, + 0x00010021, + 0x00200000, + 0x006c0090, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S new file mode 100644 index 0000000..a103c0f --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -0,0 +1,122 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: +_software_interrupt: +_prefetch_abort: +_data_abort: +_not_used: +_irq: +_fiq: + .word infinite_loop + +infinite_loop: + b infinite_loop + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * Below are the critical initializations already taken place in BootROM. + * So, these are not taken care in Xloader + * 1. Relocation to RAM + * 2. Initializing stacks + * + ************************************************************************* + */ + +/* + * the actual reset code + */ + +reset: +/* + * Xloader has to return back to BootROM in a few cases. + * eg. Ethernet boot, UART boot, USB boot + * Saving registers for returning back + */ + stmdb sp!, {r0-r12,r14} + bl cpu_init_crit +/* + * Clearing bss area is not done in Xloader. + * BSS area lies in the DDR location which is not yet initialized + * bss is assumed to be uninitialized. + */ + bl spl_boot + ldmia sp!, {r0-r12,pc} + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * enable instruction cache + */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + stmdb sp!, {lr} + bl lowlevel_init /* go setup pll,mux,memory */ + ldmia sp!, {pc} diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds new file mode 100644 index 0000000..afd3381 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm926ejs/spear/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } + + _end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 0012dd7..8150911 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -24,37 +24,54 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) -#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) -#define CONFIG_SPEAR_TIMERBASE (0xFC800000) -#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_USBD_BASE 0xE1100000 +#define CONFIG_SYS_PLUG_BASE 0xE1200000 +#define CONFIG_SYS_FIFO_BASE 0xE1000800 +#define CONFIG_SYS_SMI_BASE 0xFC000000 +#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 +#define CONFIG_SPEAR_TIMERBASE 0xFC800000 +#define CONFIG_SPEAR_MISCBASE 0xFCA80000 #define CONFIG_SPEAR_ETHBASE 0xE0800000 +#define CONFIG_SPEAR_MPMCBASE 0xFC600000 +#define CONFIG_SSP1_BASE 0xD0100000 +#define CONFIG_SSP2_BASE 0xD0180000 +#define CONFIG_SSP3_BASE 0xD8180000 +#define CONFIG_GPIO_BASE 0xD8100000 #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SYS_FSMC_BASE (0xD1800000) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#define CONFIG_SYS_FSMC_BASE 0xD1800000 +#define CONFIG_FSMC_NAND_BASE 0xD2000000 + +#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 +#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 +#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB +#define CONFIG_SPEAR_ONLYSNORBOOT 0xA +#define CONFIG_SPEAR_NORNANDBOOT 0xB +#define CONFIG_SPEAR_NORNAND8BOOT 0x8 +#define CONFIG_SPEAR_NORNAND16BOOT 0x9 +#define CONFIG_SPEAR_USBBOOT 0x8 + +#define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SYS_FSMC_BASE (0x94000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SYS_FSMC_BASE (0x44000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE #define CONFIG_SYS_NAND_CLE (1 << 17) #define CONFIG_SYS_NAND_ALE (1 << 16) -#define CONFIG_SPEAR_EMIBASE (0x4F000000) -#define CONFIG_SPEAR_RASBASE (0xB4000000) +#define CONFIG_SPEAR_EMIBASE 0x4F000000 +#define CONFIG_SPEAR_RASBASE 0xB4000000 #define CONFIG_SYS_MACB0_BASE 0xB0000000 #define CONFIG_SYS_MACB1_BASE 0xB0800000 @@ -62,11 +79,11 @@ #define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SYS_FSMC_BASE (0x4C000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x4C000000 -#define CONFIG_SPEAR_EMIBASE (0x40000000) -#define CONFIG_SPEAR_RASBASE (0xB3000000) +#define CONFIG_SPEAR_EMIBASE 0x40000000 +#define CONFIG_SPEAR_RASBASE 0xB3000000 #define CONFIG_SYS_MACB0_BASE 0xAA000000 diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h index 0ddce62..71d64a1 100644 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ b/arch/arm/include/asm/arch-spear/spr_defs.h @@ -28,6 +28,30 @@ extern int spear_board_init(ulong); extern void setfreq(unsigned int, unsigned int); extern unsigned int setfreq_sz; +void plat_ddr_init(void); +void soc_init(void); +void spear_late_init(void); +void plat_late_init(void); + +int snor_boot_selected(void); +int nand_boot_selected(void); +int pnor_boot_selected(void); +int usb_boot_selected(void); +int uart_boot_selected(void); +int tftp_boot_selected(void); +int i2c_boot_selected(void); +int spi_boot_selected(void); +int mmc_boot_selected(void); + +extern u32 mpmc_conf_vals[]; + +struct chip_data { + int cpufreq; + int dramfreq; + int dramtype; + uchar version[32]; +}; + /* HW mac id in i2c memory definitions */ #define MAGIC_OFF 0x0 #define MAGIC_LEN 0x2 @@ -36,4 +60,10 @@ extern unsigned int setfreq_sz; #define MAC_OFF 0x2 #define MAC_LEN 0x6 +#define PNOR_WIDTH_8 0 +#define PNOR_WIDTH_16 1 +#define PNOR_WIDTH_32 2 +#define PNOR_WIDTH_NUM 3 +#define PNOR_WIDTH_SEARCH 0xff + #endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index b8fcf49..5f67a5f 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -46,7 +46,7 @@ struct misc_regs { u32 prsc2_clk_cfg; /* 0x48 */ u32 prsc3_clk_cfg; /* 0x4C */ u32 amem_cfg_ctrl; /* 0x50 */ - u32 port_cfg_ctrl; /* 0x54 */ + u32 expi_clk_cfg; /* 0x54 */ u32 reserved_1; /* 0x58 */ u32 clcd_synth_clk; /* 0x5C */ u32 irda_synth_clk; /* 0x60 */ @@ -101,6 +101,37 @@ struct misc_regs { u32 ras_gpp2_out; /* 0x800C */ }; +/* SYNTH_CLK value*/ +#define SYNTH23 0x00020003 + +/* PLLx_FRQ value */ +#if defined(CONFIG_SPEAR3XX) +#define FREQ_332 0xA600010C +#define FREQ_266 0x8500010C +#elif defined(CONFIG_SPEAR600) +#define FREQ_332 0xA600010F +#define FREQ_266 0x8500010F +#endif + +/* PLL_CTR_REG */ +#define MEM_CLK_SEL_MSK 0x70000000 +#define MEM_CLK_HCLK 0x00000000 +#define MEM_CLK_2HCLK 0x10000000 +#define MEM_CLK_PLL2 0x30000000 + +#define EXPI_CLK_CFG_LOW_COMPR 0x2000 +#define EXPI_CLK_CFG_CLK_EN 0x0400 +#define EXPI_CLK_CFG_RST 0x0200 +#define EXPI_CLK_SYNT_EN 0x0010 +#define EXPI_CLK_CFG_SEL_PLL2 0x0004 +#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 + +#define PLL2_CNTL_6UA 0x1c00 +#define PLL2_CNTL_SAMPLE 0x0008 +#define PLL2_CNTL_ENABLE 0x0004 +#define PLL2_CNTL_RESETN 0x0002 +#define PLL2_CNTL_LOCK 0x0001 + /* AUTO_CFG_REG value */ #define MISC_SOCCFGMSK 0x0000003F #define MISC_SOCCFG30 0x0000000C @@ -131,9 +162,112 @@ struct misc_regs { #define MISC_ETHENB 0x00800000 #define MISC_SMIENB 0x00200000 #define MISC_GPT3ENB 0x00010000 +#define MISC_GPIO4ENB 0x00002000 #define MISC_GPT2ENB 0x00000800 #define MISC_FSMCENB 0x00000200 #define MISC_I2CENB 0x00000080 +#define MISC_SSP2ENB 0x00000070 #define MISC_UART0ENB 0x00000008 +/* PERIPH_CLK_CFG */ +#define XTALTIMEEN 0x00000001 +#define PLLTIMEEN 0x00000002 +#define CLCDCLK_SYNTH 0x00000000 +#define CLCDCLK_48MHZ 0x00000004 +#define CLCDCLK_EXT 0x00000008 +#define UARTCLK_MASK (0x1 << 4) +#define UARTCLK_48MHZ 0x00000000 +#define UARTCLK_SYNTH 0x00000010 +#define IRDACLK_48MHZ 0x00000000 +#define IRDACLK_SYNTH 0x00000020 +#define IRDACLK_EXT 0x00000040 +#define RTC_DISABLE 0x00000080 +#define GPT1CLK_48MHZ 0x00000000 +#define GPT1CLK_SYNTH 0x00000100 +#define GPT2CLK_48MHZ 0x00000000 +#define GPT2CLK_SYNTH 0x00000200 +#define GPT3CLK_48MHZ 0x00000000 +#define GPT3CLK_SYNTH 0x00000400 +#define GPT4CLK_48MHZ 0x00000000 +#define GPT4CLK_SYNTH 0x00000800 +#define GPT5CLK_48MHZ 0x00000000 +#define GPT5CLK_SYNTH 0x00001000 +#define GPT1_FREEZE 0x00002000 +#define GPT2_FREEZE 0x00004000 +#define GPT3_FREEZE 0x00008000 +#define GPT4_FREEZE 0x00010000 +#define GPT5_FREEZE 0x00020000 + +/* PERIPH1_CLKEN bits */ +#define PERIPH_ARM1_WE 0x00000001 +#define PERIPH_ARM1 0x00000002 +#define PERIPH_ARM2 0x00000004 +#define PERIPH_UART1 0x00000008 +#define PERIPH_UART2 0x00000010 +#define PERIPH_SSP1 0x00000020 +#define PERIPH_SSP2 0x00000040 +#define PERIPH_I2C 0x00000080 +#define PERIPH_JPEG 0x00000100 +#define PERIPH_FSMC 0x00000200 +#define PERIPH_FIRDA 0x00000400 +#define PERIPH_GPT4 0x00000800 +#define PERIPH_GPT5 0x00001000 +#define PERIPH_GPIO4 0x00002000 +#define PERIPH_SSP3 0x00004000 +#define PERIPH_ADC 0x00008000 +#define PERIPH_GPT3 0x00010000 +#define PERIPH_RTC 0x00020000 +#define PERIPH_GPIO3 0x00040000 +#define PERIPH_DMA 0x00080000 +#define PERIPH_ROM 0x00100000 +#define PERIPH_SMI 0x00200000 +#define PERIPH_CLCD 0x00400000 +#define PERIPH_GMAC 0x00800000 +#define PERIPH_USBD 0x01000000 +#define PERIPH_USBH1 0x02000000 +#define PERIPH_USBH2 0x04000000 +#define PERIPH_MPMC 0x08000000 +#define PERIPH_RAMW 0x10000000 +#define PERIPH_MPMC_EN 0x20000000 +#define PERIPH_MPMC_WE 0x40000000 +#define PERIPH_MPMCMSK 0x60000000 + +#define PERIPH_CLK_ALL 0x0FFFFFF8 +#define PERIPH_RST_ALL 0x00000004 + +/* DDR_PAD values */ +#define DDR_PAD_CNF_MSK 0x0000ffff +#define DDR_PAD_SW_CONF 0x00060000 +#define DDR_PAD_SSTL_SEL 0x00000001 +#define DDR_PAD_DRAM_TYPE 0x00008000 + +/* DDR_COMP values */ +#define DDR_COMP_ACCURATE 0x00000010 + +/* SoC revision stuff */ +#define SOC_PRI_SHFT 16 +#define SOC_SEC_SHFT 8 + +/* Revision definitions */ +#define SOC_SPEAR_NA 0 + +/* + * The definitons have started from + * 101 for SPEAr6xx + * 201 for SPEAr3xx + * 301 for SPEAr13xx + */ +#define SOC_SPEAR600_AA 101 +#define SOC_SPEAR600_AB 102 +#define SOC_SPEAR600_BA 103 +#define SOC_SPEAR600_BB 104 +#define SOC_SPEAR600_BC 105 +#define SOC_SPEAR600_BD 106 + +#define SOC_SPEAR300 201 +#define SOC_SPEAR310 202 +#define SOC_SPEAR320 203 + +extern int get_socrev(void); + #endif diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h new file mode 100644 index 0000000..4f144ee --- /dev/null +++ b/arch/arm/include/asm/arch-spear/spr_ssp.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Stefan Roese + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_SSP_H +#define _SPR_SSP_H + +struct ssp_regs { + u32 sspcr0; + u32 sspcr1; + u32 sspdr; + u32 sspsr; + u32 sspcpsr; + u32 sspimsc; + u32 sspicr; + u32 sspdmacr; +}; + +#define SSPCR0_FRF_MOT_SPI 0x0000 +#define SSPCR0_DSS_16BITS 0x000f + +#define SSPCR1_SSE 0x0002 + +#define SSPSR_TNF 0x2 +#define SSPSR_TFE 0x1 + +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h index 3c92f09..2393d89 100644 --- a/arch/arm/include/asm/arch-spear/spr_syscntl.h +++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __SYSCTRL_H +#define __SYSCTRL_H + struct syscntl_regs { u32 scctrl; u32 scsysstat; @@ -36,3 +39,14 @@ struct syscntl_regs { const u32 scperclken; const u32 scperstat; }; + +#define MODE_SHIFT 0x00000003 + +#define NORMAL 0x00000004 +#define SLOW 0x00000002 +#define DOZE 0x00000001 +#define SLEEP 0x00000000 + +#define PLL_TIM 0x01FFFFFF + +#endif -- cgit v0.10.2 From 038f3c54ba9a7ab4552943f47efe8f05736b1732 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Jan 2012 11:47:47 +0100 Subject: rtc/m41t62: Add support for M41T82 with HT (Halt Update) Add support for the M41T82 RTC to the m41t62 driver. The only difference that needs to be handled by this driver, is to clear the HT (Halt Update) bit upon reset. This bit is not used on the M41T62, so its save to clear this bit always. The M41T82 support will be used by the X600 (SPEAr600) board support. Signed-off-by: Stefan Roese diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 62c2446..8721e74 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -63,6 +63,8 @@ #define M41T62_FEATURE_HT (1 << 0) #define M41T62_FEATURE_BL (1 << 1) +#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ + int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; @@ -132,9 +134,15 @@ int rtc_set(struct rtc_time *tm) void rtc_reset(void) { + u8 val; + /* - * Nothing to do + * M41T82: Make sure HT (Halt Update) bit is cleared. + * This bit is 0 in M41T62 so its save to clear it always. */ + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + val &= ~M41T80_ALHOUR_HT; + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } #endif -- cgit v0.10.2 From 496ba48f5ec60187d9ff7e4298e3d37677d74530 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 20 Jan 2012 11:52:33 +0100 Subject: i2c: designware_i2c.c: Add support for the "i2c probe" command i2c_probe() is changed to reinit the i2c bus upon read failure. This is naturally the case upon i2c bus probing. Also, some printf messages upon read failure are removed. As they would interfere with the "i2c probe" command. Additionally, i2c_set_bus_speed() now returns 0, so that the "i2c speed" command can be used. Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 6d118ac..bf64a2a 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -90,7 +90,7 @@ static void set_speed(int i2c_spd) * * Set the i2c speed. */ -void i2c_set_bus_speed(int speed) +int i2c_set_bus_speed(int speed) { if (speed >= I2C_MAX_SPEED) set_speed(IC_SPEED_MODE_MAX); @@ -98,6 +98,8 @@ void i2c_set_bus_speed(int speed) set_speed(IC_SPEED_MODE_FAST); else set_speed(IC_SPEED_MODE_STANDARD); + + return 0; } /* @@ -215,10 +217,8 @@ static int check_params(uint addr, int alen, uchar *buffer, int len) static int i2c_xfer_init(uchar chip, uint addr) { - if (i2c_wait_for_bb()) { - printf("Timed out waiting for bus\n"); + if (i2c_wait_for_bb()) return 1; - } i2c_setaddress(chip); writel(addr, &i2c_regs_p->ic_cmd_data); @@ -282,7 +282,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) start_time_rx = get_timer(0); } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { - printf("Timed out. i2c read Failed\n"); return 1; } } @@ -334,9 +333,14 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_probe(uchar chip) { u32 tmp; + int ret; /* * Try to read the first location of the chip. */ - return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + if (ret) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return ret; } -- cgit v0.10.2 From 185b3b76a6a2e4eacb9e74a633950231e6787384 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 2 Feb 2012 13:25:45 +0100 Subject: MTD: SPEAr SMI: Add write support for length < 4 bytes Needed for redundant environment for example. Signed-off-by: Stefan Roese Cc: Amit Virdi Cc: Vipin Kumar diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 77e36af..7507e5d 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -362,7 +362,7 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) * smi_write - Write to SMI flash * @src_addr: source buffer * @dst_addr: destination buffer - * @length: length to write in words + * @length: length to write in bytes * @bank: bank base address * * Write to SMI flash @@ -370,7 +370,10 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, unsigned int length, ulong bank_addr) { + u8 *src_addr8 = (u8 *)src_addr; + u8 *dst_addr8 = (u8 *)dst_addr; int banknum; + int i; switch (bank_addr) { case SMIBANK0_BASE: @@ -399,7 +402,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -EIO; /* Perform the write command */ - while (length--) { + for (i = 0; i < length; i += 4) { if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) @@ -409,7 +412,18 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -EIO; } - *dst_addr++ = *src_addr++; + if (length < 4) { + int k; + + /* + * Handle special case, where length < 4 (redundant env) + */ + for (k = 0; k < length; k++) + *dst_addr8++ = *src_addr8++; + } else { + /* Normal 32bit write */ + *dst_addr++ = *src_addr++; + } if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) return -EIO; @@ -435,7 +449,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) { return smi_write((unsigned int *)src, (unsigned int *)dest_addr, - (length + 3) / 4, info->start[0]); + length, info->start[0]); } /* -- cgit v0.10.2 From 4324c75fccf1e87a58b216300e396dc1eb55a5f6 Mon Sep 17 00:00:00 2001 From: "esw@bus-elektronik.de" Date: Mon, 16 Jan 2012 00:22:02 +0000 Subject: add new board vl_ma2sc * add support for board VL+MA2SC * adds vl_ma2sc_config for standard NOR boot configuration * adds vl_ma2sc_ram_config for RAM load configuration Signed-off-by: Jens Scharsig diff --git a/MAINTAINERS b/MAINTAINERS index e42a327..6893a0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -848,6 +848,7 @@ Steve Sakoman Jens Scharsig eb_cpux9k2 ARM920T (AT91RM9200 SoC) + vl_ma2sc ARM926EJS (AT91SAM9263 SoC) Heiko Schocher diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile new file mode 100644 index 0000000..1cadfb3 --- /dev/null +++ b/board/BuS/vl_ma2sc/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009-2012 +# Jens Scharsig +# BuS Elektronik GmbH & Co. KG +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS += vl_ma2sc.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c new file mode 100644 index 0000000..62ed6fb --- /dev/null +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -0,0 +1,551 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig + * BuS Elektronik GmbH & Co. KG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static void vl_ma2sc_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + /* Configure RDY/BSY */ +#ifdef CONFIG_SYS_NAND_READY_PIN + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void vl_ma2sc_macb_hw_init(void) +{ + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 240, + .vl_clk = 6500000, + .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED | + ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVVD_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5), + .vl_tft = 1, + .vl_hsync_len = 5, /* Horiz Sync Pulse Width */ + .vl_left_margin = 68, /* horiz back porch */ + .vl_right_margin = 20, /* horiz front porch */ + .vl_vsync_len = 2, /* vert Sync Pulse Width */ + .vl_upper_margin = 18, /* vert back porch */ + .vl_lower_margin = 4, /* vert front porch */ + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ +} + +void lcd_disable(void) +{ +} + +static void vl_ma2sc_lcd_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ + at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ + at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ + at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ + at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ + + at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + gd->fb_base = ATMEL_BASE_SRAM0; +} +#endif /* Config LCD */ + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + at91_seriald_hw_init(); + + return 0; +} +#endif + +int board_init(void) +{ + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + pin = 0x1F000001; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + writel((1 << 25), &pio->pioa.codr); + + pin = 0x1F000100; + writel(pin, &pio->piob.idr); + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.codr); + writel((1 << 24), &pio->piob.sodr); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + + pin = 0x0000000F; /* HWversion als Input */ + writel(pin, &pio->piod.idr); + writel(pin, &pio->piod.puer); + writel(pin, &pio->piod.per); + writel(pin, &pio->piod.odr); + writel(pin, &pio->piod.owdr); + + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); + writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); + writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); + writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); + +#ifdef CONFIG_CMD_NAND + vl_ma2sc_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + vl_ma2sc_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + vl_ma2sc_lcd_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + uchar buffer[8]; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + buffer[0] = 0x04; + buffer[1] = 0x00; + if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) + puts("error reseting rtc clock\n\0"); + + /* read hardware version */ + + pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; + printf("Board: revision %c\n", pin); + buffer[0] = pin; + buffer[1] = 0; + setenv("revision", (char *) buffer); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); +#endif + return rc; +} + +#ifdef CONFIG_SOFT_I2C +void i2c_init_board(void) +{ + u32 pin; + + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u8 sda = (1<<4); + u8 scl = (1<<5); + + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + pin = sda | scl; + writel(pin, &pio->piob.idr); /* Disable Interupt */ + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.sodr); +} +#endif + +void watchdog_reset(void) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin = 0x1; /* PA0 */ + + if ((readl(&pio->pioa.odsr) & pin) > 0) + writel(pin, &pio->pioa.codr); + else + writel(pin, &pio->pioa.sodr); +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +/*---------------------------------------------------------------------------*/ + +int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + int col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ + + pins = 0x1F000000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.oer); + writel(pins, &pio->pioa.sodr); + + pinz = 0x1F000000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.sodr); + + for (row = 0; row < 5; row++) { + for (col = 0; col < 5; col++) { + writel((0x01000000 << col), &pio->piob.sodr); + writel((0x01000000 << row), &pio->pioa.codr); + printf("LED Test %d x %d\n", row, col); + udelay(1000000); + writel(pinz, &pio->piob.codr); + writel(pins, &pio->pioa.sodr); + } + } + return rcode; +} + +void poweroff(void) +{ + watchdog_reset(); + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ + udelay(100); + while (1) + watchdog_reset(); +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + poweroff(); + return rcode; +} + +int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + u32 freq; + u32 durate; + int rcode = 1; + + freq = 1000; + durate = 2; + switch (argc) { + case 3: + durate = simple_strtoul(argv[2], NULL, 10); + case 2: + freq = simple_strtoul(argv[1], NULL, 10); + case 1: + break; + default: + cmd_usage(cmdtp); + rcode = 1; + break; + } + durate = durate * freq; + freq = 500000 / freq; + for (i = 0; i < durate; i++) { + at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ + udelay(freq); + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + udelay(freq); + } + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + return rcode; +} + +int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + u32 col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + writel((1 << ATMEL_ID_PIOA), &pmc->pcer); + + pins = 0x001F0000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.odr); + + pinz = 0x000F0000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.codr); + + while (1) { + col = 0; + for (row = 0; row < 4; row++) { + writel((0x00010000 << row), &pio->piob.sodr); + udelay(10000); + col <<= 4; + col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; + writel(pinz, &pio->piob.codr); + } + printf("Matix: "); + for (row = 0; row < 16; row++) { + printf("%1.1d", col & 1); + col >>= 1; + } + printf(" SP %d\r ", + 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { + /* SHUTDOWN */ + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) + row++; + udelay(100); + } + udelay(100000); + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { + row++; + udelay(1000); + } + } + poweroff(); + while (1) + ; + } + } + return rcode; +} + +/*****************************************************************************/ + +U_BOOT_CMD( + ledtest, 1, 0, do_ledtest, + "test ledmatrix", + "\n" + ); + +U_BOOT_CMD( + keytest, 1, 0, do_keytest, + "test keymatix and special keys, poweroff on pressing ON key", + "\n" + ); + +U_BOOT_CMD( + poweroff, 1, 0, do_poweroff, + "power off", + "\n" + ); + +U_BOOT_CMD( + beep, 3, 0, do_beep, + "[freq [duration]]", + "freq frequence of beep\nduration duration of beep\n" + ); + +/*****************************************************************************/ diff --git a/boards.cfg b/boards.cfg index f28cb31..52375d5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,8 @@ at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +vl_ma2sc arm arm926ejs vl_ma2sc BuS at91 +vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h new file mode 100644 index 0000000..24f89c9 --- /dev/null +++ b/include/configs/vl_ma2sc.h @@ -0,0 +1,463 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig + * BuS Elektronik GmbH & Co. KG + * + * Configuation settings for the VL_MA2SC board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*--------------------------------------------------------------------------*/ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ +#define CONFIG_AT91FAMILY +#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_MISC_INIT_R + +#include + +#define MACH_TYPE_VL_MA2SC 2412 +#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC + +#define CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_RAMLOAD +#define CONFIG_SYS_TEXT_BASE 0x21000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_IDENT_STRING " on MiS Activ 2" +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AT91_GPIO + +#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) +#define CONFIG_SYS_USE_NORFLASH +#define CONFIG_SYS_USE_BOOT_NORFLASH +#endif + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Hardware drivers + */ + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_WATCHDOG + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LCD */ +#define CONFIG_LCD +#define CONFIG_ATMEL_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_BLACK_ON_WHITE +#define LCD_BPP LCD_COLOR8 +#define CONFIG_ATMEL_LCD_BGR555 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_SHA1SUM +/* +#define CONFIG_CMD_SPI +*/ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_LONGHELP +#define CONFIG_MD5 +#define CONFIG_SHA1 + +/*---------------------------------------------------------------------------- + * Hardware confuguration + *---------------------------------------------------------------------------*/ + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_AT91C_PQFP_UHPBUG + +/* I2C-Bus */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ + +#ifndef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C + +/* Software I2C driver configuration */ + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) + +#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ +#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); +#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); +#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SDA, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SDA, &pio->piob.codr); \ + } while (0); +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SCL, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SCL, &pio->piob.codr); \ + } while (0); +#endif + +/* I2C-RTC */ + +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif + +/* EEPROM */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 + +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_MR_URSTEN | \ + AT91_RSTC_MR_ERSTL(15)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xFFF) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xFFF)) + +/* clocks */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define MHZ180 +#if defined(MHZ199) +/* 199,8994 MHZ */ +#define MASTER_PLL_MUL 911 +#define MASTER_PLL_DIV 56 +#define MASTER_PLL_OUT 2 +#elif defined(MHZ180) +/* 180 MHZ */ +#define MASTER_PLL_MUL 1875 +#define MASTER_PLL_DIV 128 +#define MASTER_PLL_OUT 2 +#elif defined(MHZTEST) +/* Test MHZ */ +#define CONFIG_DISPLAY_CPUINFO +#define MASTER_PLL_MUL 8 +#define MASTER_PLL_DIV 1 +#define MASTER_PLL_OUT 2 +#else +/* 176.9472 MHZ */ +#define MASTER_PLL_MUL 72 +#define MASTER_PLL_DIV 5 +#define MASTER_PLL_OUT 2 +#endif + +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) + +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ + +#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CONFIG_SYS_SDRC_TR_VAL1 700 +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* NOR flash */ + +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +/* Address and size of Primary Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ + 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifndef CONFIG_RAMLOAD +#define CONFIG_BOOTCOMMAND "run nfsboot" +#endif +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 15 + +#define CONFIG_NFSBOOTCOMMAND \ + "dhcp $(copy_addr) $(kernelname);" \ + "run bootargsdefaults;" \ + "set bootargs $(bootargs) boot=nfs " \ + ";echo $(bootargs)" \ + ";bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootaddr=10000000\0" \ + "splashimage=10080000\0" \ + "kerneladdr=100A0000\0" \ + "kernelsize=00800000\0" \ + "minifsaddr=108A0000\0" \ + "minifssize=00060000\0" \ + "rootfsaddr=10900000\0" \ + "copy_addr=20200000\0" \ + "rootfssize=01700000\0" \ + "kernelname=uImage_vl_ma2sc\0" \ + "bootargsdefaults=set bootargs " \ + "console=ttyS0,115200 " \ + "video=atmel_lcdfb " \ + "mem=62M " \ + "panic=10 " \ + "boardrevison=\\\"${revision}\\\" " \ + "uboot=\\\"${ver}\\\" " \ + "\0" \ + "update_all=run update_kernel;run update_root;" \ + "run update_splash; run update_uboot\0" \ + "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ + "dhcp $(copy_addr) $(kernelname);" \ + "erase $(kerneladdr) +$(kernelsize);" \ + "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ + "protect on $(kerneladdr) +$(kernelsize)" \ + "\0" \ + "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ + "dhcp $(copy_addr) vl_ma2sc.root;" \ + "erase $(rootfsaddr) +$(rootfssize);" \ + "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ + "\0" \ + "update_splash=protect off $(splashimage) +20000;" \ + "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ + "erase $(splashimage) +20000;" \ + "cp.b $(fileaddr) 10080000 $(filesize);" \ + "protect on $(splashimage) +20000\0" \ + "update_uboot=protect off 10000000 1005FFFF;" \ + "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ + "erase 10000000 1005FFFF;" \ + "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ + "protect on 10000000 1005FFFF;reset\0" \ + "emergency=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(kerneladdr)\0" \ + "netemergency=run bootargsdefaults;" \ + "dhcp $(copy_addr) $(kernelname);" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(copy_addr)\0" \ + "norboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=local quiet " \ + ";bootm $(kerneladdr)\0" \ + "nandboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=nand " \ + ";bootm $(kerneladdr)\0" \ + "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ + "clearenv=protect off 10060000 1007FFFF;" \ + "erase 10060000 1007FFFF;reset\0" \ + " " + +/*--------------------------------------------------------------------------*/ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit v0.10.2 From 5427d29c26bd980c37e449687fa8456598a57c91 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 1 Mar 2012 04:02:39 +0000 Subject: No need to define CONFIG_ARCH_CPU_INIT. All mx6 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 90f2088..84b458c 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -43,7 +43,6 @@ u32 get_cpu_rev(void) return system_rev; } -#ifdef CONFIG_ARCH_CPU_INIT void init_aips(void) { struct aipstz_regs *aips1, *aips2; @@ -113,7 +112,6 @@ int arch_cpu_init(void) return 0; } -#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index a155c77..a9c1b15 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -37,7 +37,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 5b566a8..fd25faf 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -40,7 +40,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO -- cgit v0.10.2 From c27c07b86b0a9ff71e3c4788d74cee50c7ed2283 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 1 Mar 2012 04:02:40 +0000 Subject: ARM: mx28: Remove CONFIG_ARCH_CPU_INIT No need to define CONFIG_ARCH_CPU_INIT. All mx28 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index a82ff25..ff25772 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -153,7 +153,6 @@ int arch_misc_init(void) } #endif -#ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { struct mx28_clkctrl_regs *clkctrl_regs = @@ -187,7 +186,6 @@ int arch_cpu_init(void) return 0; } -#endif #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index a0e90ca..f12d927 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -40,7 +40,6 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT /* diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 640dcb4..8f60496 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT /* -- cgit v0.10.2 From aac316a8b025a93295b0a82822313503976e85be Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Mar 2012 05:41:23 +0000 Subject: PXA: Enable CONFIG_PREBOOT on zipitz2 Signed-off-by: Marek Vasut diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index a330bd0..8e63770 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -32,6 +32,7 @@ #undef CONFIG_BOARD_LATE_INIT #undef CONFIG_USE_IRQ #undef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_PREBOOT /* * Environment settings -- cgit v0.10.2 From d519b4bc0a1216eb273c76c129b779fa1ba2beb5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 2 Apr 2012 11:19:45 +0000 Subject: ARM: introduce arch_early_init_r() Introduce arch_early_init_r() function, which can be useful for doing early initialization after relocation has happened. Signed-off-by: Fabio Estevam diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 4ca75f9..9f3cae5 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -52,6 +52,7 @@ void cpu_init_cp15(void); /* cpu/.../arch/cpu.c */ int arch_cpu_init(void); int arch_misc_init(void); +int arch_early_init_r(void); /* board/.../... */ int board_init(void); diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 024646c..f21591d 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -500,6 +500,10 @@ void board_init_r(gd_t *id, ulong dest_addr) malloc_start = dest_addr - TOTAL_MALLOC_LEN; mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); +#ifdef CONFIG_ARCH_EARLY_INIT_R + arch_early_init_r(); +#endif + #if !defined(CONFIG_SYS_NO_FLASH) puts("Flash: "); -- cgit v0.10.2 From d702b0811df53a1fc2d8049e35431e4591d093c6 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Wed, 16 May 2012 23:52:54 +0000 Subject: ARM: cache: Move the cp15 CR register read before flushing the cache. The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c int cleanup_before_linux(void) { ... ... dcache_disable(); v7_outer_cache_disable(); invalidate_dcache_all(); } 1) invalidate_dcache_all call expects that all the caches has been flushed, invalidated and there are no dirty entries prior to its execution. In the above sequence dcache_disable() flushes, invalidates the caches and turns off the mmu. But after it cleanups the cache and before the mmu is disabled there is a cp_delay() function which has STR instruction. On certain cores like the cortex-a15, cache hit and a write can happen to a cache line even when the dcache is disabled. So the above mentioned STR instruction creates a dirty entry after cleaning. The mmu gets disabled after this. 2) invalidate_dcache_all invalidates the cache lines. Again on cores like cortex-a15, invalidate instruction flushes the dirty line as well. So some times the dirty line from sequence 1 can corrupt the memory resulting in a crash. Fixing this by moving the get_cr() and cp_delay() calls before cleaning up the cache, thus avoiding the dirty entry. Signed-off-by: R Sricharan diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e6c3eae..939de10 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit) { uint32_t reg; + reg = get_cr(); + cp_delay(); + if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ - reg = get_cr(); if ((reg & CR_C) != CR_C) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; flush_dcache_all(); } - reg = get_cr(); - cp_delay(); set_cr(reg & ~cache_bit); } #endif -- cgit v0.10.2