From 33daf5b7858807cb4ce4158c2c56524671c14c08 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 24 Nov 2007 21:13:59 +0100 Subject: drivers/block : move block drivers to drivers/block Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD diff --git a/Makefile b/Makefile index cde4490..1b27290 100644 --- a/Makefile +++ b/Makefile @@ -207,6 +207,7 @@ LIBS += net/libnet.a LIBS += disk/libdisk.a LIBS += drivers/libdrivers.a LIBS += drivers/bios_emulator/libatibiosemu.a +LIBS += drivers/block/libblock.a LIBS += drivers/hwmon/libhwmon.a LIBS += drivers/i2c/libi2c.a LIBS += drivers/input/libinput.a diff --git a/drivers/Makefile b/drivers/Makefile index d4882f5..6a623e3 100755 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,15 +34,10 @@ COBJS-y += status_led.o # # Block and Flash Drivers # -COBJS-y += ahci.o COBJS-y += at45.o -COBJS-y += ata_piix.o COBJS-y += cfi_flash.o COBJS-y += dataflash.o COBJS-y += mw_eeprom.o -COBJS-y += sil680.o -COBJS-y += sym53c8xx.o -COBJS-y += systemace.o # # Miscellaneous Drivers diff --git a/drivers/ahci.c b/drivers/ahci.c deleted file mode 100644 index 3d82c62..0000000 --- a/drivers/ahci.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. - * Author: Jason Jin - * Zhang Wei - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * with the reference on libata and ahci drvier in kernel - * - */ -#include - -#ifdef CONFIG_SCSI_AHCI - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct ahci_probe_ent *probe_ent = NULL; -hd_driveid_t *ataid[AHCI_MAX_PORTS]; - -#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) - - -static inline u32 ahci_port_base(u32 base, u32 port) -{ - return base + 0x100 + (port * 0x80); -} - - -static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, - unsigned int port_idx) -{ - base = ahci_port_base(base, port_idx); - - port->cmd_addr = base; - port->scr_addr = base + PORT_SCR; -} - - -#define msleep(a) udelay(a * 1000) -#define ssleep(a) msleep(a * 1000) - -static int waiting_for_cmd_completed(volatile u8 *offset, - int timeout_msec, - u32 sign) -{ - int i; - u32 status; - - for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) - msleep(1); - - return (i < timeout_msec) ? 0 : -1; -} - - -static int ahci_host_init(struct ahci_probe_ent *probe_ent) -{ - pci_dev_t pdev = probe_ent->dev; - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; - u32 tmp, cap_save; - u16 tmp16; - int i, j; - volatile u8 *port_mmio; - unsigned short vendor; - - cap_save = readl(mmio + HOST_CAP); - cap_save &= ((1 << 28) | (1 << 17)); - cap_save |= (1 << 27); - - /* global controller reset */ - tmp = readl(mmio + HOST_CTL); - if ((tmp & HOST_RESET) == 0) - writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); - - /* reset must complete within 1 second, or - * the hardware should be considered fried. - */ - ssleep(1); - - tmp = readl(mmio + HOST_CTL); - if (tmp & HOST_RESET) { - debug("controller reset failed (0x%x)\n", tmp); - return -1; - } - - writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); - writel(cap_save, mmio + HOST_CAP); - writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); - - pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); - - if (vendor == PCI_VENDOR_ID_INTEL) { - u16 tmp16; - pci_read_config_word(pdev, 0x92, &tmp16); - tmp16 |= 0xf; - pci_write_config_word(pdev, 0x92, tmp16); - } - - probe_ent->cap = readl(mmio + HOST_CAP); - probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); - probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; - - debug("cap 0x%x port_map 0x%x n_ports %d\n", - probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); - - for (i = 0; i < probe_ent->n_ports; i++) { - probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); - port_mmio = (u8 *) probe_ent->port[i].port_mmio; - ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); - - /* make sure port is not active */ - tmp = readl(port_mmio + PORT_CMD); - if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | - PORT_CMD_FIS_RX | PORT_CMD_START)) { - tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | - PORT_CMD_FIS_RX | PORT_CMD_START); - writel_with_flush(tmp, port_mmio + PORT_CMD); - - /* spec says 500 msecs for each bit, so - * this is slightly incorrect. - */ - msleep(500); - } - - writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); - - j = 0; - while (j < 100) { - msleep(10); - tmp = readl(port_mmio + PORT_SCR_STAT); - if ((tmp & 0xf) == 0x3) - break; - j++; - } - - tmp = readl(port_mmio + PORT_SCR_ERR); - debug("PORT_SCR_ERR 0x%x\n", tmp); - writel(tmp, port_mmio + PORT_SCR_ERR); - - /* ack any pending irq events for this port */ - tmp = readl(port_mmio + PORT_IRQ_STAT); - debug("PORT_IRQ_STAT 0x%x\n", tmp); - if (tmp) - writel(tmp, port_mmio + PORT_IRQ_STAT); - - writel(1 << i, mmio + HOST_IRQ_STAT); - - /* set irq mask (enables interrupts) */ - writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - - /*register linkup ports */ - tmp = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: 0x%x\n", i, tmp); - if ((tmp & 0xf) == 0x03) - probe_ent->link_port_map |= (0x01 << i); - } - - tmp = readl(mmio + HOST_CTL); - debug("HOST_CTL 0x%x\n", tmp); - writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); - tmp = readl(mmio + HOST_CTL); - debug("HOST_CTL 0x%x\n", tmp); - - pci_read_config_word(pdev, PCI_COMMAND, &tmp16); - tmp |= PCI_COMMAND_MASTER; - pci_write_config_word(pdev, PCI_COMMAND, tmp16); - - return 0; -} - - -static void ahci_print_info(struct ahci_probe_ent *probe_ent) -{ - pci_dev_t pdev = probe_ent->dev; - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; - u32 vers, cap, impl, speed; - const char *speed_s; - u16 cc; - const char *scc_s; - - vers = readl(mmio + HOST_VERSION); - cap = probe_ent->cap; - impl = probe_ent->port_map; - - speed = (cap >> 20) & 0xf; - if (speed == 1) - speed_s = "1.5"; - else if (speed == 2) - speed_s = "3"; - else - speed_s = "?"; - - pci_read_config_word(pdev, 0x0a, &cc); - if (cc == 0x0101) - scc_s = "IDE"; - else if (cc == 0x0106) - scc_s = "SATA"; - else if (cc == 0x0104) - scc_s = "RAID"; - else - scc_s = "unknown"; - - printf("AHCI %02x%02x.%02x%02x " - "%u slots %u ports %s Gbps 0x%x impl %s mode\n", - (vers >> 24) & 0xff, - (vers >> 16) & 0xff, - (vers >> 8) & 0xff, - vers & 0xff, - ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); - - printf("flags: " - "%s%s%s%s%s%s" - "%s%s%s%s%s%s%s\n", - cap & (1 << 31) ? "64bit " : "", - cap & (1 << 30) ? "ncq " : "", - cap & (1 << 28) ? "ilck " : "", - cap & (1 << 27) ? "stag " : "", - cap & (1 << 26) ? "pm " : "", - cap & (1 << 25) ? "led " : "", - cap & (1 << 24) ? "clo " : "", - cap & (1 << 19) ? "nz " : "", - cap & (1 << 18) ? "only " : "", - cap & (1 << 17) ? "pmp " : "", - cap & (1 << 15) ? "pio " : "", - cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : ""); -} - -static int ahci_init_one(pci_dev_t pdev) -{ - u32 iobase; - u16 vendor; - int rc; - - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); - - probe_ent = malloc(sizeof(struct ahci_probe_ent)); - memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); - probe_ent->dev = pdev; - - pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); - iobase &= ~0xf; - - probe_ent->host_flags = ATA_FLAG_SATA - | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO - | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - probe_ent->pio_mask = 0x1f; - probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - - probe_ent->mmio_base = iobase; - - /* Take from kernel: - * JMicron-specific fixup: - * make sure we're in AHCI mode - */ - pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); - if (vendor == 0x197b) - pci_write_config_byte(pdev, 0x41, 0xa1); - - /* initialize adapter */ - rc = ahci_host_init(probe_ent); - if (rc) - goto err_out; - - ahci_print_info(probe_ent); - - return 0; - - err_out: - return rc; -} - - -#define MAX_DATA_BYTE_COUNT (4*1024*1024) - -static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) -{ - struct ahci_ioports *pp = &(probe_ent->port[port]); - struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; - u32 sg_count; - int i; - - sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; - if (sg_count > AHCI_MAX_SG) { - printf("Error:Too much sg!\n"); - return -1; - } - - for (i = 0; i < sg_count; i++) { - ahci_sg->addr = - cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); - ahci_sg->addr_hi = 0; - ahci_sg->flags_size = cpu_to_le32(0x3fffff & - (buf_len < MAX_DATA_BYTE_COUNT - ? (buf_len - 1) - : (MAX_DATA_BYTE_COUNT - 1))); - ahci_sg++; - buf_len -= MAX_DATA_BYTE_COUNT; - } - - return sg_count; -} - - -static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) -{ - pp->cmd_slot->opts = cpu_to_le32(opts); - pp->cmd_slot->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); - pp->cmd_slot->tbl_addr_hi = 0; -} - - -static void ahci_set_feature(u8 port) -{ - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; - u32 cmd_fis_len = 5; /* five dwords */ - u8 fis[20]; - - /*set feature */ - memset(fis, 0, 20); - fis[0] = 0x27; - fis[1] = 1 << 7; - fis[2] = ATA_CMD_SETF; - fis[3] = SETFEATURES_XFER; - fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; - - memcpy((unsigned char *)pp->cmd_tbl, fis, 20); - ahci_fill_cmd_slot(pp, cmd_fis_len); - writel(1, port_mmio + PORT_CMD_ISSUE); - readl(port_mmio + PORT_CMD_ISSUE); - - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { - printf("set feature error!\n"); - } -} - - -static int ahci_port_start(u8 port) -{ - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; - u32 port_status; - u32 mem; - - debug("Enter start port: %d\n", port); - port_status = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: %x\n", port, port_status); - if ((port_status & 0xf) != 0x03) { - printf("No Link on this port!\n"); - return -1; - } - - mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); - if (!mem) { - free(pp); - printf("No mem for table!\n"); - return -ENOMEM; - } - - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ - memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); - - /* - * First item in chunk of DMA memory: 32-slot command table, - * 32 bytes each in size - */ - pp->cmd_slot = (struct ahci_cmd_hdr *)mem; - debug("cmd_slot = 0x%x\n", pp->cmd_slot); - mem += (AHCI_CMD_SLOT_SZ + 224); - - /* - * Second item: Received-FIS area - */ - pp->rx_fis = mem; - mem += AHCI_RX_FIS_SZ; - - /* - * Third item: data area for storing a single command - * and its scatter-gather table - */ - pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); - - mem += AHCI_CMD_TBL_HDR; - pp->cmd_tbl_sg = (struct ahci_sg *)mem; - - writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); - - writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); - - writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | - PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | - PORT_CMD_START, port_mmio + PORT_CMD); - - debug("Exit start port %d\n", port); - - return 0; -} - - -static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, - int buf_len) -{ - - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; - u32 opts; - u32 port_status; - int sg_count; - - debug("Enter get_ahci_device_data: for port %d\n", port); - - if (port > probe_ent->n_ports) { - printf("Invaild port number %d\n", port); - return -1; - } - - port_status = readl(port_mmio + PORT_SCR_STAT); - if ((port_status & 0xf) != 0x03) { - debug("No Link on port %d!\n", port); - return -1; - } - - memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); - - sg_count = ahci_fill_sg(port, buf, buf_len); - opts = (fis_len >> 2) | (sg_count << 16); - ahci_fill_cmd_slot(pp, opts); - - writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); - - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { - printf("timeout exit!\n"); - return -1; - } - debug("get_ahci_device_data: %d byte transferred.\n", - pp->cmd_slot->status); - - return 0; -} - - -static char *ata_id_strcpy(u16 *target, u16 *src, int len) -{ - int i; - for (i = 0; i < len / 2; i++) - target[i] = le16_to_cpu(src[i]); - return (char *)target; -} - - -static void dump_ataid(hd_driveid_t *ataid) -{ - debug("(49)ataid->capability = 0x%x\n", ataid->capability); - debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); - debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); - debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); - debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); - debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); - debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); - debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); - debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); - debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); - debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); - debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); - debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); - debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); - debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); -} - - -/* - * SCSI INQUIRY command operation. - */ -static int ata_scsiop_inquiry(ccb *pccb) -{ - u8 hdr[] = { - 0, - 0, - 0x5, /* claim SPC-3 version compatibility */ - 2, - 95 - 4, - }; - u8 fis[20]; - u8 *tmpid; - u8 port; - - /* Clean ccb data buffer */ - memset(pccb->pdata, 0, pccb->datalen); - - memcpy(pccb->pdata, hdr, sizeof(hdr)); - - if (pccb->datalen <= 35) - return 0; - - memset(fis, 0, 20); - /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_IDENT; /* Command byte. */ - - /* Read id from sata */ - port = pccb->target; - if (!(tmpid = malloc(sizeof(hd_driveid_t)))) - return -ENOMEM; - - if (get_ahci_device_data(port, (u8 *) & fis, 20, - tmpid, sizeof(hd_driveid_t))) { - debug("scsi_ahci: SCSI inquiry command failure.\n"); - return -EIO; - } - - if (ataid[port]) - free(ataid[port]); - ataid[port] = (hd_driveid_t *) tmpid; - - memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); - ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); - - dump_ataid(ataid[port]); - return 0; -} - - -/* - * SCSI READ10 command operation. - */ -static int ata_scsiop_read10(ccb * pccb) -{ - u64 lba = 0; - u32 len = 0; - u8 fis[20]; - - lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) - | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); - len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); - - /* For 10-byte and 16-byte SCSI R/W commands, transfer - * length 0 means transfer 0 block of data. - * However, for ATA R/W commands, sector count 0 means - * 256 or 65536 sectors, not 0 sectors as in SCSI. - * - * WARNING: one or two older ATA drives treat 0 as 0... - */ - if (!len) - return 0; - memset(fis, 0, 20); - - /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ - - /* LBA address, only support LBA28 in this driver */ - fis[4] = pccb->cmd[5]; - fis[5] = pccb->cmd[4]; - fis[6] = pccb->cmd[3]; - fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; - - /* Sector Count */ - fis[12] = pccb->cmd[8]; - fis[13] = pccb->cmd[7]; - - /* Read from ahci */ - if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, - pccb->pdata, pccb->datalen)) { - debug("scsi_ahci: SCSI READ10 command failure.\n"); - return -EIO; - } - - return 0; -} - - -/* - * SCSI READ CAPACITY10 command operation. - */ -static int ata_scsiop_read_capacity10(ccb *pccb) -{ - u8 buf[8]; - - if (!ataid[pccb->target]) { - printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " - "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); - return -EPERM; - } - - memset(buf, 0, 8); - - *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); - - buf[6] = 512 >> 8; - buf[7] = 512 & 0xff; - - memcpy(pccb->pdata, buf, 8); - - return 0; -} - - -/* - * SCSI TEST UNIT READY command operation. - */ -static int ata_scsiop_test_unit_ready(ccb *pccb) -{ - return (ataid[pccb->target]) ? 0 : -EPERM; -} - - -int scsi_exec(ccb *pccb) -{ - int ret; - - switch (pccb->cmd[0]) { - case SCSI_READ10: - ret = ata_scsiop_read10(pccb); - break; - case SCSI_RD_CAPAC: - ret = ata_scsiop_read_capacity10(pccb); - break; - case SCSI_TST_U_RDY: - ret = ata_scsiop_test_unit_ready(pccb); - break; - case SCSI_INQUIRY: - ret = ata_scsiop_inquiry(pccb); - break; - default: - printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); - return FALSE; - } - - if (ret) { - debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); - return FALSE; - } - return TRUE; - -} - - -void scsi_low_level_init(int busdevfunc) -{ - int i; - u32 linkmap; - - ahci_init_one(busdevfunc); - - linkmap = probe_ent->link_port_map; - - for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { - if (((linkmap >> i) & 0x01)) { - if (ahci_port_start((u8) i)) { - printf("Can not start port %d\n", i); - continue; - } - ahci_set_feature((u8) i); - } - } -} - - -void scsi_bus_reset(void) -{ - /*Not implement*/ -} - - -void scsi_print_error(ccb * pccb) -{ - /*The ahci error info can be read in the ahci driver*/ -} -#endif diff --git a/drivers/ata_piix.c b/drivers/ata_piix.c deleted file mode 100644 index 42456d7..0000000 --- a/drivers/ata_piix.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (C) Procsys. All rights reserved. - * Author: Mushtaq Khan - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * with the reference to ata_piix driver in kernel 2.4.32 - */ - -/* - * This file contains SATA controller and SATA drive initialization functions - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CFG_ATA_PIIX /*ata_piix driver */ - -#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ - -#define DRV_DECL /*For file specific declarations */ -#include -#undef DRV_DECL - -/*Macros realted to PCI*/ -#define PCI_SATA_BUS 0x00 -#define PCI_SATA_DEV 0x1f -#define PCI_SATA_FUNC 0x02 - -#define PCI_SATA_BASE1 0x10 -#define PCI_SATA_BASE2 0x14 -#define PCI_SATA_BASE3 0x18 -#define PCI_SATA_BASE4 0x1c -#define PCI_SATA_BASE5 0x20 -#define PCI_PMR 0x90 -#define PCI_PI 0x09 -#define PCI_PCS 0x92 -#define PCI_DMA_CTL 0x48 - -#define PORT_PRESENT (1<<0) -#define PORT_ENABLED (1<<4) - -u32 bdf; -u32 iobase1 = 0; /*Primary cmd block */ -u32 iobase2 = 0; /*Primary ctl block */ -u32 iobase3 = 0; /*Sec cmd block */ -u32 iobase4 = 0; /*sec ctl block */ -u32 iobase5 = 0; /*BMDMA*/ -int -pci_sata_init (void) -{ - u32 bus = PCI_SATA_BUS; - u32 dev = PCI_SATA_DEV; - u32 fun = PCI_SATA_FUNC; - u16 cmd = 0; - u8 lat = 0, pcibios_max_latency = 0xff; - u8 pmr; /*Port mapping reg */ - u8 pi; /*Prgming Interface reg */ - - bdf = PCI_BDF (bus, dev, fun); - pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1); - pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2); - pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3); - pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4); - pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5); - - if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) || - (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) || - (iobase5 == 0xFFFFFFFF)) { - printf ("error no base addr for SATA controller\n"); - return 1; - /*ERROR*/} - - iobase1 &= 0xFFFFFFFE; - iobase2 &= 0xFFFFFFFE; - iobase3 &= 0xFFFFFFFE; - iobase4 &= 0xFFFFFFFE; - iobase5 &= 0xFFFFFFFE; - - /*check for mode */ - pci_read_config_byte (bdf, PCI_PMR, &pmr); - if (pmr > 1) { - printf ("combined mode not supported\n"); - return 1; - } - - pci_read_config_byte (bdf, PCI_PI, &pi); - if ((pi & 0x05) != 0x05) { - printf ("Sata is in Legacy mode\n"); - return 1; - } else { - printf ("sata is in Native mode\n"); - } - - /*MASTER CFG AND IO CFG */ - pci_read_config_word (bdf, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; - pci_write_config_word (bdf, PCI_COMMAND, cmd); - pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat); - - if (lat < 16) - lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; - else if (lat > pcibios_max_latency) - lat = pcibios_max_latency; - pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat); - - return 0; -} - -int -sata_bus_probe (int port_no) -{ - int orig_mask, mask; - u16 pcs; - - mask = (PORT_PRESENT << port_no); - pci_read_config_word (bdf, PCI_PCS, &pcs); - orig_mask = (int) pcs & 0xff; - if ((orig_mask & mask) != mask) - return 0; - else - return 1; -} - -int -init_sata (void) -{ - u8 i, rv = 0; - - for (i = 0; i < CFG_SATA_MAXDEVICES; i++) { - sata_dev_desc[i].type = DEV_TYPE_UNKNOWN; - sata_dev_desc[i].if_type = IF_TYPE_IDE; - sata_dev_desc[i].dev = i; - sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; - sata_dev_desc[i].blksz = 0; - sata_dev_desc[i].lba = 0; - sata_dev_desc[i].block_read = sata_read; - } - - rv = pci_sata_init (); - if (rv == 1) { - printf ("pci initialization failed\n"); - return 1; - } - - port[0].port_no = 0; - port[0].ioaddr.cmd_addr = iobase1; - port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr = - iobase2 | ATA_PCI_CTL_OFS; - port[0].ioaddr.bmdma_addr = iobase5; - - port[1].port_no = 1; - port[1].ioaddr.cmd_addr = iobase3; - port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr = - iobase4 | ATA_PCI_CTL_OFS; - port[1].ioaddr.bmdma_addr = iobase5 + 0x8; - - for (i = 0; i < CFG_SATA_MAXBUS; i++) - sata_port (&port[i].ioaddr); - - for (i = 0; i < CFG_SATA_MAXBUS; i++) { - if (!(sata_bus_probe (i))) { - port[i].port_state = 0; - printf ("SATA#%d port is not present \n", i); - } else { - printf ("SATA#%d port is present\n", i); - if (sata_bus_softreset (i)) { - port[i].port_state = 0; - } else { - port[i].port_state = 1; - } - } - } - - for (i = 0; i < CFG_SATA_MAXBUS; i++) { - u8 j, devno; - - if (port[i].port_state == 0) - continue; - for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) { - sata_identify (i, j); - set_Feature_cmd (i, j); - devno = i * CFG_SATA_DEVS_PER_BUS + j; - if ((sata_dev_desc[devno].lba > 0) && - (sata_dev_desc[devno].blksz > 0)) { - dev_print (&sata_dev_desc[devno]); - /* initialize partition type */ - init_part (&sata_dev_desc[devno]); - if (curr_dev < 0) - curr_dev = - i * CFG_SATA_DEVS_PER_BUS + j; - } - } - } - return 0; -} -#endif diff --git a/drivers/block/Makefile b/drivers/block/Makefile new file mode 100644 index 0000000..e069969 --- /dev/null +++ b/drivers/block/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libblock.a + +COBJS-y += ahci.o +COBJS-y += ata_piix.o +COBJS-y += sil680.o +COBJS-y += sym53c8xx.o +COBJS-y += systemace.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c new file mode 100644 index 0000000..3d82c62 --- /dev/null +++ b/drivers/block/ahci.c @@ -0,0 +1,703 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ +#include + +#ifdef CONFIG_SCSI_AHCI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ahci_probe_ent *probe_ent = NULL; +hd_driveid_t *ataid[AHCI_MAX_PORTS]; + +#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) + + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, + unsigned int port_idx) +{ + base = ahci_port_base(base, port_idx); + + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; +} + + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) + +static int waiting_for_cmd_completed(volatile u8 *offset, + int timeout_msec, + u32 sign) +{ + int i; + u32 status; + + for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + msleep(1); + + return (i < timeout_msec) ? 0 : -1; +} + + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 tmp, cap_save; + u16 tmp16; + int i, j; + volatile u8 *port_mmio; + unsigned short vendor; + + cap_save = readl(mmio + HOST_CAP); + cap_save &= ((1 << 28) | (1 << 17)); + cap_save |= (1 << 27); + + /* global controller reset */ + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); + + /* reset must complete within 1 second, or + * the hardware should be considered fried. + */ + ssleep(1); + + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_RESET) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); + writel(cap_save, mmio + HOST_CAP); + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); + + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + + if (vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + pci_read_config_word(pdev, 0x92, &tmp16); + tmp16 |= 0xf; + pci_write_config_word(pdev, 0x92, tmp16); + } + + probe_ent->cap = readl(mmio + HOST_CAP); + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + port_mmio = (u8 *) probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); + + /* make sure port is not active */ + tmp = readl(port_mmio + PORT_CMD); + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START)) { + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START); + writel_with_flush(tmp, port_mmio + PORT_CMD); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + msleep(500); + } + + writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); + + j = 0; + while (j < 100) { + msleep(10); + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + break; + j++; + } + + tmp = readl(port_mmio + PORT_SCR_ERR); + debug("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* ack any pending irq events for this port */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + debug("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << i, mmio + HOST_IRQ_STAT); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); + + /*register linkup ports */ + tmp = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01 << i); + } + + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + + pci_read_config_word(pdev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, tmp16); + + return 0; +} + + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + u16 cc; + const char *scc_s; + + vers = readl(mmio + HOST_VERSION); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + pci_read_config_word(pdev, 0x0a, &cc); + if (cc == 0x0101) + scc_s = "IDE"; + else if (cc == 0x0106) + scc_s = "SATA"; + else if (cc == 0x0104) + scc_s = "RAID"; + else + scc_s = "unknown"; + + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); +} + +static int ahci_init_one(pci_dev_t pdev) +{ + u32 iobase; + u16 vendor; + int rc; + + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + + probe_ent = malloc(sizeof(struct ahci_probe_ent)); + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); + probe_ent->dev = pdev; + + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); + iobase &= ~0xf; + + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ + + probe_ent->mmio_base = iobase; + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + if (vendor == 0x197b) + pci_write_config_byte(pdev, 0x41, 0xa1); + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + return 0; + + err_out: + return rc; +} + + +#define MAX_DATA_BYTE_COUNT (4*1024*1024) + +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count; + int i; + + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; + if (sg_count > AHCI_MAX_SG) { + printf("Error:Too much sg!\n"); + return -1; + } + + for (i = 0; i < sg_count; i++) { + ahci_sg->addr = + cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg++; + buf_len -= MAX_DATA_BYTE_COUNT; + } + + return sg_count; +} + + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) +{ + pp->cmd_slot->opts = cpu_to_le32(opts); + pp->cmd_slot->status = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr_hi = 0; +} + + +static void ahci_set_feature(u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + u8 fis[20]; + + /*set feature */ + memset(fis, 0, 20); + fis[0] = 0x27; + fis[1] = 1 << 7; + fis[2] = ATA_CMD_SETF; + fis[3] = SETFEATURES_XFER; + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; + + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel(1, port_mmio + PORT_CMD_ISSUE); + readl(port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("set feature error!\n"); + } +} + + +static int ahci_port_start(u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 port_status; + u32 mem; + + debug("Enter start port: %d\n", port); + port_status = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); + + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n", pp->cmd_slot); + mem += (AHCI_CMD_SLOT_SZ + 224); + + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + mem += AHCI_RX_FIS_SZ; + + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + + writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); + + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); + + debug("Exit start port %d\n", port); + + return 0; +} + + +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, + int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 opts; + u32 port_status; + int sg_count; + + debug("Enter get_ahci_device_data: for port %d\n", port); + + if (port > probe_ent->n_ports) { + printf("Invaild port number %d\n", port); + return -1; + } + + port_status = readl(port_mmio + PORT_SCR_STAT); + if ((port_status & 0xf) != 0x03) { + debug("No Link on port %d!\n", port); + return -1; + } + + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); + + sg_count = ahci_fill_sg(port, buf, buf_len); + opts = (fis_len >> 2) | (sg_count << 16); + ahci_fill_cmd_slot(pp, opts); + + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("timeout exit!\n"); + return -1; + } + debug("get_ahci_device_data: %d byte transferred.\n", + pp->cmd_slot->status); + + return 0; +} + + +static char *ata_id_strcpy(u16 *target, u16 *src, int len) +{ + int i; + for (i = 0; i < len / 2; i++) + target[i] = le16_to_cpu(src[i]); + return (char *)target; +} + + +static void dump_ataid(hd_driveid_t *ataid) +{ + debug("(49)ataid->capability = 0x%x\n", ataid->capability); + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); +} + + +/* + * SCSI INQUIRY command operation. + */ +static int ata_scsiop_inquiry(ccb *pccb) +{ + u8 hdr[] = { + 0, + 0, + 0x5, /* claim SPC-3 version compatibility */ + 2, + 95 - 4, + }; + u8 fis[20]; + u8 *tmpid; + u8 port; + + /* Clean ccb data buffer */ + memset(pccb->pdata, 0, pccb->datalen); + + memcpy(pccb->pdata, hdr, sizeof(hdr)); + + if (pccb->datalen <= 35) + return 0; + + memset(fis, 0, 20); + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ + + /* Read id from sata */ + port = pccb->target; + if (!(tmpid = malloc(sizeof(hd_driveid_t)))) + return -ENOMEM; + + if (get_ahci_device_data(port, (u8 *) & fis, 20, + tmpid, sizeof(hd_driveid_t))) { + debug("scsi_ahci: SCSI inquiry command failure.\n"); + return -EIO; + } + + if (ataid[port]) + free(ataid[port]); + ataid[port] = (hd_driveid_t *) tmpid; + + memcpy(&pccb->pdata[8], "ATA ", 8); + ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + + dump_ataid(ataid[port]); + return 0; +} + + +/* + * SCSI READ10 command operation. + */ +static int ata_scsiop_read10(ccb * pccb) +{ + u64 lba = 0; + u32 len = 0; + u8 fis[20]; + + lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) + | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); + len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); + + /* For 10-byte and 16-byte SCSI R/W commands, transfer + * length 0 means transfer 0 block of data. + * However, for ATA R/W commands, sector count 0 means + * 256 or 65536 sectors, not 0 sectors as in SCSI. + * + * WARNING: one or two older ATA drives treat 0 as 0... + */ + if (!len) + return 0; + memset(fis, 0, 20); + + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + + /* LBA address, only support LBA28 in this driver */ + fis[4] = pccb->cmd[5]; + fis[5] = pccb->cmd[4]; + fis[6] = pccb->cmd[3]; + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; + + /* Sector Count */ + fis[12] = pccb->cmd[8]; + fis[13] = pccb->cmd[7]; + + /* Read from ahci */ + if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, + pccb->pdata, pccb->datalen)) { + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + + return 0; +} + + +/* + * SCSI READ CAPACITY10 command operation. + */ +static int ata_scsiop_read_capacity10(ccb *pccb) +{ + u8 buf[8]; + + if (!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + memset(buf, 0, 8); + + *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + + buf[6] = 512 >> 8; + buf[7] = 512 & 0xff; + + memcpy(pccb->pdata, buf, 8); + + return 0; +} + + +/* + * SCSI TEST UNIT READY command operation. + */ +static int ata_scsiop_test_unit_ready(ccb *pccb) +{ + return (ataid[pccb->target]) ? 0 : -EPERM; +} + + +int scsi_exec(ccb *pccb) +{ + int ret; + + switch (pccb->cmd[0]) { + case SCSI_READ10: + ret = ata_scsiop_read10(pccb); + break; + case SCSI_RD_CAPAC: + ret = ata_scsiop_read_capacity10(pccb); + break; + case SCSI_TST_U_RDY: + ret = ata_scsiop_test_unit_ready(pccb); + break; + case SCSI_INQUIRY: + ret = ata_scsiop_inquiry(pccb); + break; + default: + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); + return FALSE; + } + + if (ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); + return FALSE; + } + return TRUE; + +} + + +void scsi_low_level_init(int busdevfunc) +{ + int i; + u32 linkmap; + + ahci_init_one(busdevfunc); + + linkmap = probe_ent->link_port_map; + + for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { + if (((linkmap >> i) & 0x01)) { + if (ahci_port_start((u8) i)) { + printf("Can not start port %d\n", i); + continue; + } + ahci_set_feature((u8) i); + } + } +} + + +void scsi_bus_reset(void) +{ + /*Not implement*/ +} + + +void scsi_print_error(ccb * pccb) +{ + /*The ahci error info can be read in the ahci driver*/ +} +#endif diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c new file mode 100644 index 0000000..42456d7 --- /dev/null +++ b/drivers/block/ata_piix.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to ata_piix driver in kernel 2.4.32 + */ + +/* + * This file contains SATA controller and SATA drive initialization functions + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CFG_ATA_PIIX /*ata_piix driver */ + +#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ + +#define DRV_DECL /*For file specific declarations */ +#include +#undef DRV_DECL + +/*Macros realted to PCI*/ +#define PCI_SATA_BUS 0x00 +#define PCI_SATA_DEV 0x1f +#define PCI_SATA_FUNC 0x02 + +#define PCI_SATA_BASE1 0x10 +#define PCI_SATA_BASE2 0x14 +#define PCI_SATA_BASE3 0x18 +#define PCI_SATA_BASE4 0x1c +#define PCI_SATA_BASE5 0x20 +#define PCI_PMR 0x90 +#define PCI_PI 0x09 +#define PCI_PCS 0x92 +#define PCI_DMA_CTL 0x48 + +#define PORT_PRESENT (1<<0) +#define PORT_ENABLED (1<<4) + +u32 bdf; +u32 iobase1 = 0; /*Primary cmd block */ +u32 iobase2 = 0; /*Primary ctl block */ +u32 iobase3 = 0; /*Sec cmd block */ +u32 iobase4 = 0; /*sec ctl block */ +u32 iobase5 = 0; /*BMDMA*/ +int +pci_sata_init (void) +{ + u32 bus = PCI_SATA_BUS; + u32 dev = PCI_SATA_DEV; + u32 fun = PCI_SATA_FUNC; + u16 cmd = 0; + u8 lat = 0, pcibios_max_latency = 0xff; + u8 pmr; /*Port mapping reg */ + u8 pi; /*Prgming Interface reg */ + + bdf = PCI_BDF (bus, dev, fun); + pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1); + pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2); + pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3); + pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4); + pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5); + + if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) || + (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) || + (iobase5 == 0xFFFFFFFF)) { + printf ("error no base addr for SATA controller\n"); + return 1; + /*ERROR*/} + + iobase1 &= 0xFFFFFFFE; + iobase2 &= 0xFFFFFFFE; + iobase3 &= 0xFFFFFFFE; + iobase4 &= 0xFFFFFFFE; + iobase5 &= 0xFFFFFFFE; + + /*check for mode */ + pci_read_config_byte (bdf, PCI_PMR, &pmr); + if (pmr > 1) { + printf ("combined mode not supported\n"); + return 1; + } + + pci_read_config_byte (bdf, PCI_PI, &pi); + if ((pi & 0x05) != 0x05) { + printf ("Sata is in Legacy mode\n"); + return 1; + } else { + printf ("sata is in Native mode\n"); + } + + /*MASTER CFG AND IO CFG */ + pci_read_config_word (bdf, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (bdf, PCI_COMMAND, cmd); + pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat); + + if (lat < 16) + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; + else if (lat > pcibios_max_latency) + lat = pcibios_max_latency; + pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat); + + return 0; +} + +int +sata_bus_probe (int port_no) +{ + int orig_mask, mask; + u16 pcs; + + mask = (PORT_PRESENT << port_no); + pci_read_config_word (bdf, PCI_PCS, &pcs); + orig_mask = (int) pcs & 0xff; + if ((orig_mask & mask) != mask) + return 0; + else + return 1; +} + +int +init_sata (void) +{ + u8 i, rv = 0; + + for (i = 0; i < CFG_SATA_MAXDEVICES; i++) { + sata_dev_desc[i].type = DEV_TYPE_UNKNOWN; + sata_dev_desc[i].if_type = IF_TYPE_IDE; + sata_dev_desc[i].dev = i; + sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; + sata_dev_desc[i].blksz = 0; + sata_dev_desc[i].lba = 0; + sata_dev_desc[i].block_read = sata_read; + } + + rv = pci_sata_init (); + if (rv == 1) { + printf ("pci initialization failed\n"); + return 1; + } + + port[0].port_no = 0; + port[0].ioaddr.cmd_addr = iobase1; + port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr = + iobase2 | ATA_PCI_CTL_OFS; + port[0].ioaddr.bmdma_addr = iobase5; + + port[1].port_no = 1; + port[1].ioaddr.cmd_addr = iobase3; + port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr = + iobase4 | ATA_PCI_CTL_OFS; + port[1].ioaddr.bmdma_addr = iobase5 + 0x8; + + for (i = 0; i < CFG_SATA_MAXBUS; i++) + sata_port (&port[i].ioaddr); + + for (i = 0; i < CFG_SATA_MAXBUS; i++) { + if (!(sata_bus_probe (i))) { + port[i].port_state = 0; + printf ("SATA#%d port is not present \n", i); + } else { + printf ("SATA#%d port is present\n", i); + if (sata_bus_softreset (i)) { + port[i].port_state = 0; + } else { + port[i].port_state = 1; + } + } + } + + for (i = 0; i < CFG_SATA_MAXBUS; i++) { + u8 j, devno; + + if (port[i].port_state == 0) + continue; + for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) { + sata_identify (i, j); + set_Feature_cmd (i, j); + devno = i * CFG_SATA_DEVS_PER_BUS + j; + if ((sata_dev_desc[devno].lba > 0) && + (sata_dev_desc[devno].blksz > 0)) { + dev_print (&sata_dev_desc[devno]); + /* initialize partition type */ + init_part (&sata_dev_desc[devno]); + if (curr_dev < 0) + curr_dev = + i * CFG_SATA_DEVS_PER_BUS + j; + } + } + } + return 0; +} +#endif diff --git a/drivers/block/sil680.c b/drivers/block/sil680.c new file mode 100644 index 0000000..a6143df --- /dev/null +++ b/drivers/block/sil680.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2007 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* sil680.c - ide support functions for the Sil0680A controller */ + +/* + * The following parameters must be defined in the configuration file + * of the target board: + * + * #define CFG_IDE_SIL680 + * + * #define CONFIG_PCI_PNP + * NOTE it may also be necessary to define this if the default of 8 is + * incorrect for the target board (e.g. the sequoia board requires 0). + * #define CFG_PCI_CACHE_LINE_SIZE 0 + * + * #define CONFIG_CMD_IDE + * #undef CONFIG_IDE_8xx_DIRECT + * #undef CONFIG_IDE_LED + * #undef CONFIG_IDE_RESET + * #define CONFIG_IDE_PREINIT + * #define CFG_IDE_MAXBUS 2 - modify to suit + * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit + * #define CFG_ATA_BASE_ADDR 0 + * #define CFG_ATA_IDE0_OFFSET 0 + * #define CFG_ATA_IDE1_OFFSET 0 + * #define CFG_ATA_DATA_OFFSET 0 + * #define CFG_ATA_REG_OFFSET 0 + * #define CFG_ATA_ALT_OFFSET 0x0004 + * + * The mapping for PCI IO-space. + * NOTE this is the value for the sequoia board. Modify to suit. + * #define CFG_PCI0_IO_SPACE 0xE8000000 + */ + +#include +#if defined(CFG_IDE_SIL680) +#include +#include +#include + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1095, 0x0680, 0); + if (devbusfn != -1) { + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) &ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffff8; + ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffff8; + ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + /* init various things - taken from the Linux driver */ + /* set PIO mode */ + pci_write_config_byte(devbusfn, 0x80, 0x00); + pci_write_config_byte(devbusfn, 0x84, 0x00); + /* IDE0 */ + pci_write_config_byte(devbusfn, 0xA1, 0x02); + pci_write_config_word(devbusfn, 0xA2, 0x328A); + pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xA8, 0x43924392); + pci_write_config_dword(devbusfn, 0xAC, 0x40094009); + /* IDE1 */ + pci_write_config_byte(devbusfn, 0xB1, 0x02); + pci_write_config_word(devbusfn, 0xB2, 0x328A); + pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD); + pci_write_config_dword(devbusfn, 0xB8, 0x43924392); + pci_write_config_dword(devbusfn, 0xBC, 0x40094009); + } + return (status); +} + +void ide_set_reset (int flag) { + return; +} + +#endif /* CFG_IDE_SIL680 */ diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c new file mode 100644 index 0000000..29eeccd --- /dev/null +++ b/drivers/block/sym53c8xx.c @@ -0,0 +1,793 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * partly derived from + * linux/drivers/scsi/sym53c8xx.c + * + */ + +/* + * SCSI support based on the chip sym53C810. + * + * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH + * The local version of this driver for the BAB750 board does not + * use interrupts but polls the chip instead (see the call of + * 'handle_scsi_int()' in 'scsi_issue()'. + */ + +#include + +#ifdef CONFIG_SCSI_SYM53C8XX + +#include +#include +#include +#include +#include + +#undef SYM53C8XX_DEBUG + +#ifdef SYM53C8XX_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) + +#undef SCSI_SINGLE_STEP +/* + * Single Step is only used for debug purposes + */ +#ifdef SCSI_SINGLE_STEP +static unsigned long start_script_select; +static unsigned long start_script_msgout; +static unsigned long start_script_msgin; +static unsigned long start_script_msg_ext; +static unsigned long start_script_cmd; +static unsigned long start_script_data_in; +static unsigned long start_script_data_out; +static unsigned long start_script_status; +static unsigned long start_script_complete; +static unsigned long start_script_error; +static unsigned long start_script_reselection; +static unsigned int len_script_select; +static unsigned int len_script_msgout; +static unsigned int len_script_msgin; +static unsigned int len_script_msg_ext; +static unsigned int len_script_cmd; +static unsigned int len_script_data_in; +static unsigned int len_script_data_out; +static unsigned int len_script_status; +static unsigned int len_script_complete; +static unsigned int len_script_error; +static unsigned int len_script_reselection; +#endif + + +static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ +static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ +static unsigned long script_select[8]; /* script for selection */ +static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ +static unsigned long script_msgin[14]; /* script for message in phase */ +static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ +static unsigned long script_cmd[18]; /* script for command phase */ +static unsigned long script_data_in[8]; /* script for data in phase */ +static unsigned long script_data_out[8]; /* script for data out phase */ +static unsigned long script_status[6]; /* script for status phase */ +static unsigned long script_complete[10]; /* script for complete */ +static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ +static unsigned long script_error[2]; /* script for error handling */ + +static unsigned long int_stat[3]; /* interrupt status */ +static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ + +#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a)) +#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a)) + +#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ + +#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ +#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ + +/********************************************************************************* + * forward declerations + */ + +void scsi_chip_init(void); +void handle_scsi_int(void); + + +/******************************************************************************** + * reports SCSI errors to the user + */ +void scsi_print_error(ccb *pccb) +{ + int i; + printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); + printf(" CCB: "); + for(i=0;icmdlen;i++) + printf("%02X ",pccb->cmd[i]); + printf("(len=%d)\n",pccb->cmdlen); + printf(" Cntrl: "); + switch(pccb->contr_stat) { + case SIR_COMPLETE: printf("Complete (no Error)\n"); break; + case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; + case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; + case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; + case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; + case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; + case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; + case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; + case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; + case INT_ON_FY: printf("Interrupt on fly\n"); break; + case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; + case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; + case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; + case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; + default: printf("unknown status %lx\n",pccb->contr_stat); break; + } + printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: printf("No Sense)"); break; + case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; + case SENSE_NOT_READY: printf("Not Ready)"); break; + case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; + case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; + case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; + case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; + case SENSE_DATA_PROTECT: printf("Data Protect)"); break; + case SENSE_BLANK_CHECK: printf("Blank check)"); break; + case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; + case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; + case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; + case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; + case SENSE_MISCOMPARE: printf("Misscompare\n"); break; + default: printf("Illegal Sensecode\n"); break; + } + printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); + printf(" Status: "); + switch(pccb->status) { + case S_GOOD : printf("Good\n"); break; + case S_CHECK_COND: printf("Check condition\n"); break; + case S_COND_MET: printf("Condition Met\n"); break; + case S_BUSY: printf("Busy\n"); break; + case S_INT: printf("Intermediate\n"); break; + case S_INT_COND_MET: printf("Intermediate condition met\n"); break; + case S_CONFLICT: printf("Reservation conflict\n"); break; + case S_TERMINATED: printf("Command terminated\n"); break; + case S_QUEUE_FULL: printf("Task set full\n"); break; + default: printf("unknown: %02X\n",pccb->status); break; + } + +} + + +/****************************************************************************** + * sets-up the SCSI controller + * the base memory address is retrived via the pci_read_config_dword + */ +void scsi_low_level_init(int busdevfunc) +{ + unsigned int cmd; + unsigned int addr; + unsigned char vec; + + pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec); + pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr); + + addr = bus_to_phys(addr & ~0xf); + + /* + * Enable bus mastering in case this has not been done, yet. + */ + pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd); + + scsi_mem_addr = addr; + + scsi_chip_init(); + scsi_bus_reset(); +} + + +/************************************************************************************ + * Low level Part of SCSI Driver + */ + +/* + * big-endian -> little endian conversion for the script + */ +unsigned long swap_script(unsigned long val) +{ + unsigned long tmp; + tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); + return tmp; +} + + +void scsi_write_byte(ulong offset,unsigned char val) +{ + out8(scsi_mem_addr+offset,val); +} + + +unsigned char scsi_read_byte(ulong offset) +{ + return(in8(scsi_mem_addr+offset)); +} + + +/******************************************************************************** + * interrupt handler + */ +void handle_scsi_int(void) +{ + unsigned char stat,stat1,stat2; + unsigned short sstat; + int i; +#ifdef SCSI_SINGLE_STEP + unsigned long tt; +#endif + stat=scsi_read_byte(ISTAT); + if((stat & DIP)==DIP) { /* DMA Interrupt pending */ + stat1=scsi_read_byte(DSTAT); +#ifdef SCSI_SINGLE_STEP + if((stat1 & SSI)==SSI) + { + tt=in32r(scsi_mem_addr+DSP); + if(((tt)>=start_script_select) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgout) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgin) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msg_ext) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_cmd) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_in) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_out) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_status) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_complete) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_error) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_reselection) && ((tt)>2); + goto end_single; + } + printf("sc: %lx\n",tt); +end_single: + stat2=scsi_read_byte(DCNTL); + stat2|=STD; + scsi_write_byte(DCNTL,stat2); + } +#endif + if((stat1 & SIR)==SIR) /* script interrupt */ + { + int_stat[0]=in32(scsi_mem_addr+DSPS); + } + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & SIP)==SIP) { /* scsi interrupt */ + sstat = (unsigned short)scsi_read_byte(SIST+1); + sstat <<=8; + sstat |= (unsigned short)scsi_read_byte(SIST); + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=SCSI_INT_STATE | sstat; + stat1=scsi_read_byte(DSTAT); + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & INTF)==INTF) { /* interrupt on Fly */ + scsi_write_byte(ISTAT,stat); /* clear it */ + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=INT_ON_FY; + } +} + +void scsi_bus_reset(void) +{ + unsigned char t; + int i; + int end = CFG_SCSI_SPIN_UP_TIME*1000; + + t=scsi_read_byte(SCNTL1); + scsi_write_byte(SCNTL1,(t | CRST)); + udelay(50); + scsi_write_byte(SCNTL1,t); + + puts("waiting for devices to spin up"); + for(i=0;i>8)); + scsi_write_byte(DIEN,script_int_mask); +} + +void scsi_write_dsp(unsigned long start) +{ + unsigned long val; +#ifdef SCSI_SINGLE_STEP + unsigned char t; +#endif + val = start; + out32r(scsi_mem_addr + DSP,start); +#ifdef SCSI_SINGLE_STEP + t=scsi_read_byte(DCNTL); + t|=STD; + scsi_write_byte(DCNTL,t); +#endif +} + +/* only used for debug purposes */ +void scsi_print_script(void) +{ + printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); + printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); + printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); + printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); + printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); + printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); + printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); + printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); + printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); + printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); +} + + +void scsi_set_script(ccb *pccb) +{ + int busdevfunc = pccb->priv; + int i; + i=0; + script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); + script_select[i++]=0; /* LED ON */ + script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ + script_select[i++]=0; + /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ + script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); + script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */ + script_select[i++]=swap_script(SCR_JUMP); /* next section */ + /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ + script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */ + +#ifdef SCSI_SINGLE_STEP + start_script_select=(unsigned long)&script_select[0]; + len_script_select=i*4; +#endif + + i=0; + script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); + script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; + script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); + script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0])); + script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ + script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */ + script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_msgout[i++]=SIR_MSG_OUT_NO_CMD; + +#ifdef SCSI_SINGLE_STEP + start_script_msgout=(unsigned long)&script_msgout[0]; + len_script_msgout=i*4; +#endif + i=0; + script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); + script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_status[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_cmd[i++]=SIR_CMD_OUT_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_cmd=(unsigned long)&script_cmd[0]; + len_script_cmd=i*4; +#endif + i=0; + script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ + script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_out[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_out[i++]=swap_script(SCR_INT); + script_data_out[i++]=SIR_DATA_OUT_ERR; + +#ifdef SCSI_SINGLE_STEP + start_script_data_out=(unsigned long)&script_data_out[0]; + len_script_data_out=i*4; +#endif + i=0; + script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ + script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_in[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_in[i++]=swap_script(SCR_INT); + script_data_in[i++]=SIR_DATA_IN_ERR; +#ifdef SCSI_SINGLE_STEP + start_script_data_in=(unsigned long)&script_data_in[0]; + len_script_data_in=i*4; +#endif + i=0; + script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); + script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); + script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0])); + script_msgin[i++]=swap_script(SCR_INT); + script_msgin[i++]=SIR_MSG_RECEIVED; +#ifdef SCSI_SINGLE_STEP + start_script_msgin=(unsigned long)&script_msgin[0]; + len_script_msgin=i*4; +#endif + i=0; + script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ + script_msg_ext[i++]=0; + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_INT); + script_msg_ext[i++]=SIR_MSG_OVER7; +#ifdef SCSI_SINGLE_STEP + start_script_msg_ext=(unsigned long)&script_msg_ext[0]; + len_script_msg_ext=i*4; +#endif + i=0; + script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); + script_status[i++]=swap_script(phys_to_bus(&pccb->status)); + script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); + script_status[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_status[i++]=swap_script(SCR_INT); + script_status[i++]=SIR_STATUS_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_status=(unsigned long)&script_status[0]; + len_script_status=i*4; +#endif + i=0; + script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_WAIT_DISC); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); + script_complete[i++]=0; /* LED OFF */ + script_complete[i++]=swap_script(SCR_INT); + script_complete[i++]=SIR_COMPLETE; +#ifdef SCSI_SINGLE_STEP + start_script_complete=(unsigned long)&script_complete[0]; + len_script_complete=i*4; +#endif + i=0; + script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ + script_error[i++]=SIR_SCRIPT_ERROR; +#ifdef SCSI_SINGLE_STEP + start_script_error=(unsigned long)&script_error[0]; + len_script_error=i*4; +#endif + i=0; + script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ + script_reselection[i++]=0; + script_reselection[i++]=swap_script(SCR_WAIT_RESEL); + script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */ +#ifdef SCSI_SINGLE_STEP + start_script_reselection=(unsigned long)&script_reselection[0]; + len_script_reselection=i*4; +#endif +} + + +void scsi_issue(ccb *pccb) +{ + int busdevfunc = pccb->priv; + int i; + unsigned short sstat; + int retrycnt; /* retry counter */ + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + /* struct pccb must be set-up correctly */ + retrycnt=0; + PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); + pccb->trans_bytes=0; /* no bytes transfered yet */ + scsi_set_script(pccb); /* fill in SCRIPT */ + scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */ + script_int_mask=0xff; /* enable all Ints */ + scsi_int_enable(); + scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */ + /* now we have to wait for IRQs */ +retry: + /* + * This version of the driver is _not_ interrupt driven, + * but polls the chip's interrupt registers (ISTAT, DSTAT). + */ + while(int_stat[0]==0) + handle_scsi_int(); + + if(int_stat[0]==SIR_COMPLETE) { + if(pccb->msgin[0]==M_DISCONNECT) { + PRINTF("Wait for reselection\n"); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */ + goto retry; + } + pccb->contr_stat=SIR_COMPLETE; + return; + } + if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ + sstat=(unsigned short)int_stat[0]; + if((sstat & STO)==STO) { /* selection timeout */ + pccb->contr_stat=SCSI_SEL_TIME_OUT; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Selection Timeout\n",pccb->target); + return; + } + if((sstat & UDC)==UDC) { /* unexpected disconnect */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if((sstat & RSL)==RSL) { /* reselection */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ + if(retrycnttrans_bytes=pccb->datalen - + ((unsigned long)scsi_read_byte(DBC) | + ((unsigned long)scsi_read_byte(DBC+1)<<8) | + ((unsigned long)scsi_read_byte(DBC+2)<<16)); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + retrycnt++; + PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", + pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); + scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */ + goto retry; + } + if((sstat & MA)==MA) + pccb->contr_stat=SCSI_MA_TIME_OUT; + else + pccb->contr_stat=SCSI_HNS_TIME_OUT; + PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); + return; + } /* no phase int */ +/* if((sstat & CMP)==CMP) { + pccb->contr_stat=SIR_COMPLETE; + return; + } +*/ + PRINTF("SCSI INT %lX\n",int_stat[0]); + pccb->contr_stat=int_stat[0]; + return; + } /* end scsi int */ + PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); + pccb->contr_stat=int_stat[0]; + return; +} + +int scsi_exec(ccb *pccb) +{ + unsigned char tmpcmd[16],tmpstat; + int i,retrycnt,t; + unsigned long transbytes,datalen; + unsigned char *tmpptr; + retrycnt=0; +retry: + scsi_issue(pccb); + if(pccb->contr_stat!=SIR_COMPLETE) + return FALSE; + if(pccb->status==S_GOOD) + return TRUE; + if(pccb->status==S_CHECK_COND) { /* check condition */ + for(i=0;i<16;i++) + tmpcmd[i]=pccb->cmd[i]; + pccb->cmd[0]=SCSI_REQ_SENSE; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + pccb->cmd[4]=14; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; + transbytes=pccb->trans_bytes; + tmpptr=pccb->pdata; + pccb->pdata=&pccb->sense_buf[0]; + datalen=pccb->datalen; + pccb->datalen=14; + tmpstat=pccb->status; + scsi_issue(pccb); + for(i=0;i<16;i++) + pccb->cmd[i]=tmpcmd[i]; + pccb->trans_bytes=transbytes; + pccb->pdata=tmpptr; + pccb->datalen=datalen; + pccb->status=tmpstat; + PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, + pccb->sense_buf[12],pccb->sense_buf[13]); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: + case SENSE_RECOVERED_ERROR: + /* seems to be ok */ + return TRUE; + break; + case SENSE_NOT_READY: + if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { + /* if device is not in process of becoming ready */ + return FALSE; + break; + } /* else fall through */ + case SENSE_UNIT_ATTENTION: + if(retrycnttarget,retrycnt); + for(t=0;ttarget,retrycnt); + return FALSE; + default: + return FALSE; + } + } + PRINTF("Status = %X\n",pccb->status); + return FALSE; +} + + +void scsi_chip_init(void) +{ + /* first we issue a soft reset */ + scsi_write_byte(ISTAT,SRST); + udelay(1000); + scsi_write_byte(ISTAT,0); + /* setup chip */ + scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ + scsi_write_byte(SCNTL1,0x00); + scsi_write_byte(SCNTL2,0x00); +#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ + scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ +#else + scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ +#endif + scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ + scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ + scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ + scsi_int_mask=0x0000; /* no Interrupt is enabled */ + script_int_mask=0x00; + scsi_int_enable(); + scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ + scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ + scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ + scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ + scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ + scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ + scsi_write_byte(STEST3,0x80); /* enable tolerANT */ + scsi_write_byte(CTEST3,0x04); /* clear FIFO */ + scsi_write_byte(CTEST4,0x00); + scsi_write_byte(CTEST5,0x00); +#ifdef SCSI_SINGLE_STEP +/* scsi_write_byte(DCNTL,IRQM | SSM); */ + scsi_write_byte(DCNTL,IRQD | SSM); + scsi_write_byte(DMODE,MAN); +#else +/* scsi_write_byte(DCNTL,IRQM); */ + scsi_write_byte(DCNTL,IRQD); + scsi_write_byte(DMODE,0x00); +#endif +} +#endif + + +#endif /* CONFIG_SCSI_SYM53C8XX */ diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c new file mode 100644 index 0000000..7d82c27 --- /dev/null +++ b/drivers/block/systemace.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (XXXXXXXXXXXXXXXX) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * The Xilinx SystemACE chip support is activated by defining + * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE + * to set the base address of the device. This code currently + * assumes that the chip is connected via a byte-wide bus. + * + * The CONFIG_SYSTEMACE also adds to fat support the device class + * "ace" that allows the user to execute "fatls ace 0" and the + * like. This works by making the systemace_get_dev function + * available to cmd_fat.c:get_dev and filling in a block device + * description that has all the bits needed for FAT support to + * read sectors. + * + * According to Xilinx technical support, before accessing the + * SystemACE CF you need to set the following control bits: + * FORCECFGMODE : 1 + * CFGMODE : 0 + * CFGSTART : 0 + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYSTEMACE + +/* + * The ace_readw and writew functions read/write 16bit words, but the + * offset value is the BYTE offset as most used in the Xilinx + * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined + * to be the base address for the chip, usually in the local + * peripheral bus. + */ +#if (CFG_SYSTEMACE_WIDTH == 8) +#if !defined(__BIG_ENDIAN) +#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ + (readb(CFG_SYSTEMACE_BASE+off+1))) +#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ + writeb(val, CFG_SYSTEMACE_BASE+off+1);} +#else +#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ + (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) +#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ + writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} +#endif +#else +#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off)) +#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val)) +#endif + +/* */ + +static unsigned long systemace_read(int dev, unsigned long start, + unsigned long blkcnt, void *buffer); + +static block_dev_desc_t systemace_dev = { 0 }; + +static int get_cf_lock(void) +{ + int retry = 10; + + /* CONTROLREG = LOCKREG */ + unsigned val = ace_readw(0x18); + val |= 0x0002; + ace_writew((val & 0xffff), 0x18); + + /* Wait for MPULOCK in STATUSREG[15:0] */ + while (!(ace_readw(0x04) & 0x0002)) { + + if (retry < 0) + return -1; + + udelay(100000); + retry -= 1; + } + + return 0; +} + +static void release_cf_lock(void) +{ + unsigned val = ace_readw(0x18); + val &= ~(0x0002); + ace_writew((val & 0xffff), 0x18); +} + +block_dev_desc_t *systemace_get_dev(int dev) +{ + /* The first time through this, the systemace_dev object is + not yet initialized. In that case, fill it in. */ + if (systemace_dev.blksz == 0) { + systemace_dev.if_type = IF_TYPE_UNKNOWN; + systemace_dev.dev = 0; + systemace_dev.part_type = PART_TYPE_UNKNOWN; + systemace_dev.type = DEV_TYPE_HARDDISK; + systemace_dev.blksz = 512; + systemace_dev.removable = 1; + systemace_dev.block_read = systemace_read; + + /* + * Ensure the correct bus mode (8/16 bits) gets enabled + */ + ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); + + init_part(&systemace_dev); + + } + + return &systemace_dev; +} + +/* + * This function is called (by dereferencing the block_read pointer in + * the dev_desc) to read blocks of data. The return value is the + * number of blocks read. A zero return indicates an error. + */ +static unsigned long systemace_read(int dev, unsigned long start, + unsigned long blkcnt, void *buffer) +{ + int retry; + unsigned blk_countdown; + unsigned char *dp = buffer; + unsigned val; + + if (get_cf_lock() < 0) { + unsigned status = ace_readw(0x04); + + /* If CFDETECT is false, card is missing. */ + if (!(status & 0x0010)) { + printf("** CompactFlash card not present. **\n"); + return 0; + } + + printf("**** ACE locked away from me (STATUSREG=%04x)\n", + status); + return 0; + } +#ifdef DEBUG_SYSTEMACE + printf("... systemace read %lu sectors at %lu\n", blkcnt, start); +#endif + + retry = 2000; + for (;;) { + val = ace_readw(0x04); + + /* If CFDETECT is false, card is missing. */ + if (!(val & 0x0010)) { + printf("**** ACE CompactFlash not found.\n"); + release_cf_lock(); + return 0; + } + + /* If RDYFORCMD, then we are ready to go. */ + if (val & 0x0100) + break; + + if (retry < 0) { + printf("**** SystemACE not ready.\n"); + release_cf_lock(); + return 0; + } + + udelay(1000); + retry -= 1; + } + + /* The SystemACE can only transfer 256 sectors at a time, so + limit the current chunk of sectors. The blk_countdown + variable is the number of sectors left to transfer. */ + + blk_countdown = blkcnt; + while (blk_countdown > 0) { + unsigned trans = blk_countdown; + + if (trans > 256) + trans = 256; + +#ifdef DEBUG_SYSTEMACE + printf("... transfer %lu sector in a chunk\n", trans); +#endif + /* Write LBA block address */ + ace_writew((start >> 0) & 0xffff, 0x10); + ace_writew((start >> 16) & 0x0fff, 0x12); + + /* NOTE: in the Write Sector count below, a count of 0 + causes a transfer of 256, so &0xff gives the right + value for whatever transfer count we want. */ + + /* Write sector count | ReadMemCardData. */ + ace_writew((trans & 0xff) | 0x0300, 0x14); + +/* + * For FPGA configuration via SystemACE is reset unacceptable + * CFGDONE bit in STATUSREG is not set to 1. + */ +#ifndef SYSTEMACE_CONFIG_FPGA + /* Reset the configruation controller */ + val = ace_readw(0x18); + val |= 0x0080; + ace_writew(val, 0x18); +#endif + + retry = trans * 16; + while (retry > 0) { + int idx; + + /* Wait for buffer to become ready. */ + while (!(ace_readw(0x04) & 0x0020)) { + udelay(100); + } + + /* Read 16 words of 2bytes from the sector buffer. */ + for (idx = 0; idx < 16; idx += 1) { + unsigned short val = ace_readw(0x40); + *dp++ = val & 0xff; + *dp++ = (val >> 8) & 0xff; + } + + retry -= 1; + } + + /* Clear the configruation controller reset */ + val = ace_readw(0x18); + val &= ~0x0080; + ace_writew(val, 0x18); + + /* Count the blocks we transfer this time. */ + start += trans; + blk_countdown -= trans; + } + + release_cf_lock(); + + return blkcnt; +} +#endif /* CONFIG_SYSTEMACE */ diff --git a/drivers/sil680.c b/drivers/sil680.c deleted file mode 100644 index a6143df..0000000 --- a/drivers/sil680.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2007 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* sil680.c - ide support functions for the Sil0680A controller */ - -/* - * The following parameters must be defined in the configuration file - * of the target board: - * - * #define CFG_IDE_SIL680 - * - * #define CONFIG_PCI_PNP - * NOTE it may also be necessary to define this if the default of 8 is - * incorrect for the target board (e.g. the sequoia board requires 0). - * #define CFG_PCI_CACHE_LINE_SIZE 0 - * - * #define CONFIG_CMD_IDE - * #undef CONFIG_IDE_8xx_DIRECT - * #undef CONFIG_IDE_LED - * #undef CONFIG_IDE_RESET - * #define CONFIG_IDE_PREINIT - * #define CFG_IDE_MAXBUS 2 - modify to suit - * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit - * #define CFG_ATA_BASE_ADDR 0 - * #define CFG_ATA_IDE0_OFFSET 0 - * #define CFG_ATA_IDE1_OFFSET 0 - * #define CFG_ATA_DATA_OFFSET 0 - * #define CFG_ATA_REG_OFFSET 0 - * #define CFG_ATA_ALT_OFFSET 0x0004 - * - * The mapping for PCI IO-space. - * NOTE this is the value for the sequoia board. Modify to suit. - * #define CFG_PCI0_IO_SPACE 0xE8000000 - */ - -#include -#if defined(CFG_IDE_SIL680) -#include -#include -#include - -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; - -int ide_preinit (void) -{ - int status; - pci_dev_t devbusfn; - int l; - - status = 1; - for (l = 0; l < CFG_IDE_MAXBUS; l++) { - ide_bus_offset[l] = -ATA_STATUS; - } - devbusfn = pci_find_device (0x1095, 0x0680, 0); - if (devbusfn != -1) { - status = 0; - - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (u32 *) &ide_bus_offset[0]); - ide_bus_offset[0] &= 0xfffffff8; - ide_bus_offset[0] += CFG_PCI0_IO_SPACE; - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) &ide_bus_offset[1]); - ide_bus_offset[1] &= 0xfffffff8; - ide_bus_offset[1] += CFG_PCI0_IO_SPACE; - /* init various things - taken from the Linux driver */ - /* set PIO mode */ - pci_write_config_byte(devbusfn, 0x80, 0x00); - pci_write_config_byte(devbusfn, 0x84, 0x00); - /* IDE0 */ - pci_write_config_byte(devbusfn, 0xA1, 0x02); - pci_write_config_word(devbusfn, 0xA2, 0x328A); - pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD); - pci_write_config_dword(devbusfn, 0xA8, 0x43924392); - pci_write_config_dword(devbusfn, 0xAC, 0x40094009); - /* IDE1 */ - pci_write_config_byte(devbusfn, 0xB1, 0x02); - pci_write_config_word(devbusfn, 0xB2, 0x328A); - pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD); - pci_write_config_dword(devbusfn, 0xB8, 0x43924392); - pci_write_config_dword(devbusfn, 0xBC, 0x40094009); - } - return (status); -} - -void ide_set_reset (int flag) { - return; -} - -#endif /* CFG_IDE_SIL680 */ diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c deleted file mode 100644 index 29eeccd..0000000 --- a/drivers/sym53c8xx.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * partly derived from - * linux/drivers/scsi/sym53c8xx.c - * - */ - -/* - * SCSI support based on the chip sym53C810. - * - * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH - * The local version of this driver for the BAB750 board does not - * use interrupts but polls the chip instead (see the call of - * 'handle_scsi_int()' in 'scsi_issue()'. - */ - -#include - -#ifdef CONFIG_SCSI_SYM53C8XX - -#include -#include -#include -#include -#include - -#undef SYM53C8XX_DEBUG - -#ifdef SYM53C8XX_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) - -#undef SCSI_SINGLE_STEP -/* - * Single Step is only used for debug purposes - */ -#ifdef SCSI_SINGLE_STEP -static unsigned long start_script_select; -static unsigned long start_script_msgout; -static unsigned long start_script_msgin; -static unsigned long start_script_msg_ext; -static unsigned long start_script_cmd; -static unsigned long start_script_data_in; -static unsigned long start_script_data_out; -static unsigned long start_script_status; -static unsigned long start_script_complete; -static unsigned long start_script_error; -static unsigned long start_script_reselection; -static unsigned int len_script_select; -static unsigned int len_script_msgout; -static unsigned int len_script_msgin; -static unsigned int len_script_msg_ext; -static unsigned int len_script_cmd; -static unsigned int len_script_data_in; -static unsigned int len_script_data_out; -static unsigned int len_script_status; -static unsigned int len_script_complete; -static unsigned int len_script_error; -static unsigned int len_script_reselection; -#endif - - -static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ -static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ -static unsigned long script_select[8]; /* script for selection */ -static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ -static unsigned long script_msgin[14]; /* script for message in phase */ -static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ -static unsigned long script_cmd[18]; /* script for command phase */ -static unsigned long script_data_in[8]; /* script for data in phase */ -static unsigned long script_data_out[8]; /* script for data out phase */ -static unsigned long script_status[6]; /* script for status phase */ -static unsigned long script_complete[10]; /* script for complete */ -static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ -static unsigned long script_error[2]; /* script for error handling */ - -static unsigned long int_stat[3]; /* interrupt status */ -static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ - -#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a)) -#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a)) - -#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ - -#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ -#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ - -/********************************************************************************* - * forward declerations - */ - -void scsi_chip_init(void); -void handle_scsi_int(void); - - -/******************************************************************************** - * reports SCSI errors to the user - */ -void scsi_print_error(ccb *pccb) -{ - int i; - printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); - printf(" CCB: "); - for(i=0;icmdlen;i++) - printf("%02X ",pccb->cmd[i]); - printf("(len=%d)\n",pccb->cmdlen); - printf(" Cntrl: "); - switch(pccb->contr_stat) { - case SIR_COMPLETE: printf("Complete (no Error)\n"); break; - case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; - case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; - case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; - case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; - case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; - case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; - case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; - case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; - case INT_ON_FY: printf("Interrupt on fly\n"); break; - case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; - case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; - case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; - case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; - default: printf("unknown status %lx\n",pccb->contr_stat); break; - } - printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); - switch(pccb->sense_buf[2]&0xf) { - case SENSE_NO_SENSE: printf("No Sense)"); break; - case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; - case SENSE_NOT_READY: printf("Not Ready)"); break; - case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; - case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; - case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; - case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; - case SENSE_DATA_PROTECT: printf("Data Protect)"); break; - case SENSE_BLANK_CHECK: printf("Blank check)"); break; - case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; - case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; - case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; - case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; - case SENSE_MISCOMPARE: printf("Misscompare\n"); break; - default: printf("Illegal Sensecode\n"); break; - } - printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); - printf(" Status: "); - switch(pccb->status) { - case S_GOOD : printf("Good\n"); break; - case S_CHECK_COND: printf("Check condition\n"); break; - case S_COND_MET: printf("Condition Met\n"); break; - case S_BUSY: printf("Busy\n"); break; - case S_INT: printf("Intermediate\n"); break; - case S_INT_COND_MET: printf("Intermediate condition met\n"); break; - case S_CONFLICT: printf("Reservation conflict\n"); break; - case S_TERMINATED: printf("Command terminated\n"); break; - case S_QUEUE_FULL: printf("Task set full\n"); break; - default: printf("unknown: %02X\n",pccb->status); break; - } - -} - - -/****************************************************************************** - * sets-up the SCSI controller - * the base memory address is retrived via the pci_read_config_dword - */ -void scsi_low_level_init(int busdevfunc) -{ - unsigned int cmd; - unsigned int addr; - unsigned char vec; - - pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec); - pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr); - - addr = bus_to_phys(addr & ~0xf); - - /* - * Enable bus mastering in case this has not been done, yet. - */ - pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER; - pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd); - - scsi_mem_addr = addr; - - scsi_chip_init(); - scsi_bus_reset(); -} - - -/************************************************************************************ - * Low level Part of SCSI Driver - */ - -/* - * big-endian -> little endian conversion for the script - */ -unsigned long swap_script(unsigned long val) -{ - unsigned long tmp; - tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); - return tmp; -} - - -void scsi_write_byte(ulong offset,unsigned char val) -{ - out8(scsi_mem_addr+offset,val); -} - - -unsigned char scsi_read_byte(ulong offset) -{ - return(in8(scsi_mem_addr+offset)); -} - - -/******************************************************************************** - * interrupt handler - */ -void handle_scsi_int(void) -{ - unsigned char stat,stat1,stat2; - unsigned short sstat; - int i; -#ifdef SCSI_SINGLE_STEP - unsigned long tt; -#endif - stat=scsi_read_byte(ISTAT); - if((stat & DIP)==DIP) { /* DMA Interrupt pending */ - stat1=scsi_read_byte(DSTAT); -#ifdef SCSI_SINGLE_STEP - if((stat1 & SSI)==SSI) - { - tt=in32r(scsi_mem_addr+DSP); - if(((tt)>=start_script_select) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_msgout) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_msgin) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_msg_ext) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_cmd) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_data_in) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_data_out) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_status) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_complete) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_error) && ((tt)>2); - goto end_single; - } - if(((tt)>=start_script_reselection) && ((tt)>2); - goto end_single; - } - printf("sc: %lx\n",tt); -end_single: - stat2=scsi_read_byte(DCNTL); - stat2|=STD; - scsi_write_byte(DCNTL,stat2); - } -#endif - if((stat1 & SIR)==SIR) /* script interrupt */ - { - int_stat[0]=in32(scsi_mem_addr+DSPS); - } - if((stat1 & DFE)==0) { /* fifo not epmty */ - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ - stat2=scsi_read_byte(STEST3); - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ - } - } - if((stat & SIP)==SIP) { /* scsi interrupt */ - sstat = (unsigned short)scsi_read_byte(SIST+1); - sstat <<=8; - sstat |= (unsigned short)scsi_read_byte(SIST); - for(i=0;i<3;i++) { - if(int_stat[i]==0) - break; /* found an empty int status */ - } - int_stat[i]=SCSI_INT_STATE | sstat; - stat1=scsi_read_byte(DSTAT); - if((stat1 & DFE)==0) { /* fifo not epmty */ - scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ - stat2=scsi_read_byte(STEST3); - scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ - } - } - if((stat & INTF)==INTF) { /* interrupt on Fly */ - scsi_write_byte(ISTAT,stat); /* clear it */ - for(i=0;i<3;i++) { - if(int_stat[i]==0) - break; /* found an empty int status */ - } - int_stat[i]=INT_ON_FY; - } -} - -void scsi_bus_reset(void) -{ - unsigned char t; - int i; - int end = CFG_SCSI_SPIN_UP_TIME*1000; - - t=scsi_read_byte(SCNTL1); - scsi_write_byte(SCNTL1,(t | CRST)); - udelay(50); - scsi_write_byte(SCNTL1,t); - - puts("waiting for devices to spin up"); - for(i=0;i>8)); - scsi_write_byte(DIEN,script_int_mask); -} - -void scsi_write_dsp(unsigned long start) -{ - unsigned long val; -#ifdef SCSI_SINGLE_STEP - unsigned char t; -#endif - val = start; - out32r(scsi_mem_addr + DSP,start); -#ifdef SCSI_SINGLE_STEP - t=scsi_read_byte(DCNTL); - t|=STD; - scsi_write_byte(DCNTL,t); -#endif -} - -/* only used for debug purposes */ -void scsi_print_script(void) -{ - printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); - printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); - printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); - printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); - printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); - printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); - printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); - printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); - printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); - printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); -} - - -void scsi_set_script(ccb *pccb) -{ - int busdevfunc = pccb->priv; - int i; - i=0; - script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); - script_select[i++]=0; /* LED ON */ - script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ - script_select[i++]=0; - /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ - script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); - script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */ - script_select[i++]=swap_script(SCR_JUMP); /* next section */ - /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ - script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */ - -#ifdef SCSI_SINGLE_STEP - start_script_select=(unsigned long)&script_select[0]; - len_script_select=i*4; -#endif - - i=0; - script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); - script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; - script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); - script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0])); - script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ - script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */ - script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ - script_msgout[i++]=SIR_MSG_OUT_NO_CMD; - -#ifdef SCSI_SINGLE_STEP - start_script_msgout=(unsigned long)&script_msgout[0]; - len_script_msgout=i*4; -#endif - i=0; - script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); - script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_status[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0])); - script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ - script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); - script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ - script_cmd[i++]=SIR_CMD_OUT_ILL_PH; -#ifdef SCSI_SINGLE_STEP - start_script_cmd=(unsigned long)&script_cmd[0]; - len_script_cmd=i*4; -#endif - i=0; - script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ - script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ - script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); - script_data_out[i++]=swap_script(phys_to_bus(&script_status[0])); - script_data_out[i++]=swap_script(SCR_INT); - script_data_out[i++]=SIR_DATA_OUT_ERR; - -#ifdef SCSI_SINGLE_STEP - start_script_data_out=(unsigned long)&script_data_out[0]; - len_script_data_out=i*4; -#endif - i=0; - script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ - script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ - script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); - script_data_in[i++]=swap_script(phys_to_bus(&script_status[0])); - script_data_in[i++]=swap_script(SCR_INT); - script_data_in[i++]=SIR_DATA_IN_ERR; -#ifdef SCSI_SINGLE_STEP - start_script_data_in=(unsigned long)&script_data_in[0]; - len_script_data_in=i*4; -#endif - i=0; - script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); - script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); - script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); - script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); - script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0])); - script_msgin[i++]=swap_script(SCR_INT); - script_msgin[i++]=SIR_MSG_RECEIVED; -#ifdef SCSI_SINGLE_STEP - start_script_msgin=(unsigned long)&script_msgin[0]; - len_script_msgin=i*4; -#endif - i=0; - script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ - script_msg_ext[i++]=0; - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ - script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7])); - script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); - script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ - script_msg_ext[i++]=swap_script(SCR_INT); - script_msg_ext[i++]=SIR_MSG_OVER7; -#ifdef SCSI_SINGLE_STEP - start_script_msg_ext=(unsigned long)&script_msg_ext[0]; - len_script_msg_ext=i*4; -#endif - i=0; - script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); - script_status[i++]=swap_script(phys_to_bus(&pccb->status)); - script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); - script_status[i++]=swap_script(phys_to_bus(&script_msgin[0])); - script_status[i++]=swap_script(SCR_INT); - script_status[i++]=SIR_STATUS_ILL_PH; -#ifdef SCSI_SINGLE_STEP - start_script_status=(unsigned long)&script_status[0]; - len_script_status=i*4; -#endif - i=0; - script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_WAIT_DISC); - script_complete[i++]=0; - script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); - script_complete[i++]=0; /* LED OFF */ - script_complete[i++]=swap_script(SCR_INT); - script_complete[i++]=SIR_COMPLETE; -#ifdef SCSI_SINGLE_STEP - start_script_complete=(unsigned long)&script_complete[0]; - len_script_complete=i*4; -#endif - i=0; - script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ - script_error[i++]=SIR_SCRIPT_ERROR; -#ifdef SCSI_SINGLE_STEP - start_script_error=(unsigned long)&script_error[0]; - len_script_error=i*4; -#endif - i=0; - script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ - script_reselection[i++]=0; - script_reselection[i++]=swap_script(SCR_WAIT_RESEL); - script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */ -#ifdef SCSI_SINGLE_STEP - start_script_reselection=(unsigned long)&script_reselection[0]; - len_script_reselection=i*4; -#endif -} - - -void scsi_issue(ccb *pccb) -{ - int busdevfunc = pccb->priv; - int i; - unsigned short sstat; - int retrycnt; /* retry counter */ - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - /* struct pccb must be set-up correctly */ - retrycnt=0; - PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); - pccb->trans_bytes=0; /* no bytes transfered yet */ - scsi_set_script(pccb); /* fill in SCRIPT */ - scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */ - script_int_mask=0xff; /* enable all Ints */ - scsi_int_enable(); - scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */ - /* now we have to wait for IRQs */ -retry: - /* - * This version of the driver is _not_ interrupt driven, - * but polls the chip's interrupt registers (ISTAT, DSTAT). - */ - while(int_stat[0]==0) - handle_scsi_int(); - - if(int_stat[0]==SIR_COMPLETE) { - if(pccb->msgin[0]==M_DISCONNECT) { - PRINTF("Wait for reselection\n"); - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */ - goto retry; - } - pccb->contr_stat=SIR_COMPLETE; - return; - } - if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ - sstat=(unsigned short)int_stat[0]; - if((sstat & STO)==STO) { /* selection timeout */ - pccb->contr_stat=SCSI_SEL_TIME_OUT; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Selection Timeout\n",pccb->target); - return; - } - if((sstat & UDC)==UDC) { /* unexpected disconnect */ - pccb->contr_stat=SCSI_UNEXP_DIS; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); - return; - } - if((sstat & RSL)==RSL) { /* reselection */ - pccb->contr_stat=SCSI_UNEXP_DIS; - scsi_write_byte(GPREG,0x01); - PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); - return; - } - if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ - if(retrycnttrans_bytes=pccb->datalen - - ((unsigned long)scsi_read_byte(DBC) | - ((unsigned long)scsi_read_byte(DBC+1)<<8) | - ((unsigned long)scsi_read_byte(DBC+2)<<16)); - for(i=0;i<3;i++) - int_stat[i]=0; /* delete all int status */ - retrycnt++; - PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", - pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); - scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */ - goto retry; - } - if((sstat & MA)==MA) - pccb->contr_stat=SCSI_MA_TIME_OUT; - else - pccb->contr_stat=SCSI_HNS_TIME_OUT; - PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); - return; - } /* no phase int */ -/* if((sstat & CMP)==CMP) { - pccb->contr_stat=SIR_COMPLETE; - return; - } -*/ - PRINTF("SCSI INT %lX\n",int_stat[0]); - pccb->contr_stat=int_stat[0]; - return; - } /* end scsi int */ - PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); - pccb->contr_stat=int_stat[0]; - return; -} - -int scsi_exec(ccb *pccb) -{ - unsigned char tmpcmd[16],tmpstat; - int i,retrycnt,t; - unsigned long transbytes,datalen; - unsigned char *tmpptr; - retrycnt=0; -retry: - scsi_issue(pccb); - if(pccb->contr_stat!=SIR_COMPLETE) - return FALSE; - if(pccb->status==S_GOOD) - return TRUE; - if(pccb->status==S_CHECK_COND) { /* check condition */ - for(i=0;i<16;i++) - tmpcmd[i]=pccb->cmd[i]; - pccb->cmd[0]=SCSI_REQ_SENSE; - pccb->cmd[1]=pccb->lun<<5; - pccb->cmd[2]=0; - pccb->cmd[3]=0; - pccb->cmd[4]=14; - pccb->cmd[5]=0; - pccb->cmdlen=6; - pccb->msgout[0]=SCSI_IDENTIFY; - transbytes=pccb->trans_bytes; - tmpptr=pccb->pdata; - pccb->pdata=&pccb->sense_buf[0]; - datalen=pccb->datalen; - pccb->datalen=14; - tmpstat=pccb->status; - scsi_issue(pccb); - for(i=0;i<16;i++) - pccb->cmd[i]=tmpcmd[i]; - pccb->trans_bytes=transbytes; - pccb->pdata=tmpptr; - pccb->datalen=datalen; - pccb->status=tmpstat; - PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, - pccb->sense_buf[12],pccb->sense_buf[13]); - switch(pccb->sense_buf[2]&0xf) { - case SENSE_NO_SENSE: - case SENSE_RECOVERED_ERROR: - /* seems to be ok */ - return TRUE; - break; - case SENSE_NOT_READY: - if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { - /* if device is not in process of becoming ready */ - return FALSE; - break; - } /* else fall through */ - case SENSE_UNIT_ATTENTION: - if(retrycnttarget,retrycnt); - for(t=0;ttarget,retrycnt); - return FALSE; - default: - return FALSE; - } - } - PRINTF("Status = %X\n",pccb->status); - return FALSE; -} - - -void scsi_chip_init(void) -{ - /* first we issue a soft reset */ - scsi_write_byte(ISTAT,SRST); - udelay(1000); - scsi_write_byte(ISTAT,0); - /* setup chip */ - scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ - scsi_write_byte(SCNTL1,0x00); - scsi_write_byte(SCNTL2,0x00); -#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ - scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ -#else - scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ -#endif - scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ - scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ - scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ - scsi_int_mask=0x0000; /* no Interrupt is enabled */ - script_int_mask=0x00; - scsi_int_enable(); - scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ - scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ - scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ - scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ - scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ - scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ - scsi_write_byte(STEST3,0x80); /* enable tolerANT */ - scsi_write_byte(CTEST3,0x04); /* clear FIFO */ - scsi_write_byte(CTEST4,0x00); - scsi_write_byte(CTEST5,0x00); -#ifdef SCSI_SINGLE_STEP -/* scsi_write_byte(DCNTL,IRQM | SSM); */ - scsi_write_byte(DCNTL,IRQD | SSM); - scsi_write_byte(DMODE,MAN); -#else -/* scsi_write_byte(DCNTL,IRQM); */ - scsi_write_byte(DCNTL,IRQD); - scsi_write_byte(DMODE,0x00); -#endif -} -#endif - - -#endif /* CONFIG_SCSI_SYM53C8XX */ diff --git a/drivers/systemace.c b/drivers/systemace.c deleted file mode 100644 index 7d82c27..0000000 --- a/drivers/systemace.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (XXXXXXXXXXXXXXXX) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -/* - * The Xilinx SystemACE chip support is activated by defining - * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE - * to set the base address of the device. This code currently - * assumes that the chip is connected via a byte-wide bus. - * - * The CONFIG_SYSTEMACE also adds to fat support the device class - * "ace" that allows the user to execute "fatls ace 0" and the - * like. This works by making the systemace_get_dev function - * available to cmd_fat.c:get_dev and filling in a block device - * description that has all the bits needed for FAT support to - * read sectors. - * - * According to Xilinx technical support, before accessing the - * SystemACE CF you need to set the following control bits: - * FORCECFGMODE : 1 - * CFGMODE : 0 - * CFGSTART : 0 - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SYSTEMACE - -/* - * The ace_readw and writew functions read/write 16bit words, but the - * offset value is the BYTE offset as most used in the Xilinx - * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined - * to be the base address for the chip, usually in the local - * peripheral bus. - */ -#if (CFG_SYSTEMACE_WIDTH == 8) -#if !defined(__BIG_ENDIAN) -#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ - (readb(CFG_SYSTEMACE_BASE+off+1))) -#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ - writeb(val, CFG_SYSTEMACE_BASE+off+1);} -#else -#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ - (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) -#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ - writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} -#endif -#else -#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off)) -#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val)) -#endif - -/* */ - -static unsigned long systemace_read(int dev, unsigned long start, - unsigned long blkcnt, void *buffer); - -static block_dev_desc_t systemace_dev = { 0 }; - -static int get_cf_lock(void) -{ - int retry = 10; - - /* CONTROLREG = LOCKREG */ - unsigned val = ace_readw(0x18); - val |= 0x0002; - ace_writew((val & 0xffff), 0x18); - - /* Wait for MPULOCK in STATUSREG[15:0] */ - while (!(ace_readw(0x04) & 0x0002)) { - - if (retry < 0) - return -1; - - udelay(100000); - retry -= 1; - } - - return 0; -} - -static void release_cf_lock(void) -{ - unsigned val = ace_readw(0x18); - val &= ~(0x0002); - ace_writew((val & 0xffff), 0x18); -} - -block_dev_desc_t *systemace_get_dev(int dev) -{ - /* The first time through this, the systemace_dev object is - not yet initialized. In that case, fill it in. */ - if (systemace_dev.blksz == 0) { - systemace_dev.if_type = IF_TYPE_UNKNOWN; - systemace_dev.dev = 0; - systemace_dev.part_type = PART_TYPE_UNKNOWN; - systemace_dev.type = DEV_TYPE_HARDDISK; - systemace_dev.blksz = 512; - systemace_dev.removable = 1; - systemace_dev.block_read = systemace_read; - - /* - * Ensure the correct bus mode (8/16 bits) gets enabled - */ - ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); - - init_part(&systemace_dev); - - } - - return &systemace_dev; -} - -/* - * This function is called (by dereferencing the block_read pointer in - * the dev_desc) to read blocks of data. The return value is the - * number of blocks read. A zero return indicates an error. - */ -static unsigned long systemace_read(int dev, unsigned long start, - unsigned long blkcnt, void *buffer) -{ - int retry; - unsigned blk_countdown; - unsigned char *dp = buffer; - unsigned val; - - if (get_cf_lock() < 0) { - unsigned status = ace_readw(0x04); - - /* If CFDETECT is false, card is missing. */ - if (!(status & 0x0010)) { - printf("** CompactFlash card not present. **\n"); - return 0; - } - - printf("**** ACE locked away from me (STATUSREG=%04x)\n", - status); - return 0; - } -#ifdef DEBUG_SYSTEMACE - printf("... systemace read %lu sectors at %lu\n", blkcnt, start); -#endif - - retry = 2000; - for (;;) { - val = ace_readw(0x04); - - /* If CFDETECT is false, card is missing. */ - if (!(val & 0x0010)) { - printf("**** ACE CompactFlash not found.\n"); - release_cf_lock(); - return 0; - } - - /* If RDYFORCMD, then we are ready to go. */ - if (val & 0x0100) - break; - - if (retry < 0) { - printf("**** SystemACE not ready.\n"); - release_cf_lock(); - return 0; - } - - udelay(1000); - retry -= 1; - } - - /* The SystemACE can only transfer 256 sectors at a time, so - limit the current chunk of sectors. The blk_countdown - variable is the number of sectors left to transfer. */ - - blk_countdown = blkcnt; - while (blk_countdown > 0) { - unsigned trans = blk_countdown; - - if (trans > 256) - trans = 256; - -#ifdef DEBUG_SYSTEMACE - printf("... transfer %lu sector in a chunk\n", trans); -#endif - /* Write LBA block address */ - ace_writew((start >> 0) & 0xffff, 0x10); - ace_writew((start >> 16) & 0x0fff, 0x12); - - /* NOTE: in the Write Sector count below, a count of 0 - causes a transfer of 256, so &0xff gives the right - value for whatever transfer count we want. */ - - /* Write sector count | ReadMemCardData. */ - ace_writew((trans & 0xff) | 0x0300, 0x14); - -/* - * For FPGA configuration via SystemACE is reset unacceptable - * CFGDONE bit in STATUSREG is not set to 1. - */ -#ifndef SYSTEMACE_CONFIG_FPGA - /* Reset the configruation controller */ - val = ace_readw(0x18); - val |= 0x0080; - ace_writew(val, 0x18); -#endif - - retry = trans * 16; - while (retry > 0) { - int idx; - - /* Wait for buffer to become ready. */ - while (!(ace_readw(0x04) & 0x0020)) { - udelay(100); - } - - /* Read 16 words of 2bytes from the sector buffer. */ - for (idx = 0; idx < 16; idx += 1) { - unsigned short val = ace_readw(0x40); - *dp++ = val & 0xff; - *dp++ = (val >> 8) & 0xff; - } - - retry -= 1; - } - - /* Clear the configruation controller reset */ - val = ace_readw(0x18); - val &= ~0x0080; - ace_writew(val, 0x18); - - /* Count the blocks we transfer this time. */ - start += trans; - blk_countdown -= trans; - } - - release_cf_lock(); - - return blkcnt; -} -#endif /* CONFIG_SYSTEMACE */ -- cgit v0.10.2