From ac9c4912c07e0aba1f8b1c993f2fc8051a34fea2 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 20 Feb 2017 14:24:13 +0300 Subject: mmc: pci: Add CONFIG_MMC_PCI We don't want pci_mmc to compile every time x86 compiles, only when there's a platform that needs it. For that reason, we're adding a new CONFIG_MMC_PCI which platforms can choose to enable. Suggested-by: Jaehoon Chung Reviewed-by: Bin Meng Signed-off-by: Felipe Balbi Signed-off-by: Andy Shevchenko diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index c6aa24f..d2f9f24 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -48,6 +48,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 890d28c..d96bfcb 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -50,6 +50,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 6e4cd84..1642bf2 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 13a00c2..4a88f5f 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -37,6 +37,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index ce447f5..d5bd66f 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -47,6 +47,7 @@ CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_NUVOTON_NCT6102D=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 570f9ea..f60abc3 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -42,6 +42,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 5f61f2a..8dac1d7 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -47,6 +47,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index cde33bb..1703cee 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -47,6 +47,7 @@ CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_NUVOTON_NCT6102D=y CONFIG_MMC=y +CONFIG_MMC_PCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_SPI_FLASH=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ddef59a..78091cc 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -122,6 +122,14 @@ config MMC_MXS If unsure, say N. +config MMC_PCI + bool "Support for MMC controllers on PCI" + help + This selects PCI-based MMC controllers. + If you have an MMC controller on a PCI bus, say Y here. + + If unsure, say N. + config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" help diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 6a488f1..1e8d23f 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxsmmc.o -obj-$(CONFIG_X86) += pci_mmc.o +obj-$(CONFIG_MMC_PCI) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o -- cgit v0.10.2 From aff32df522e5b1a7e4391fd00ffe14a3f107fcd3 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 20 Feb 2017 14:24:14 +0300 Subject: mmc: tangier: Add Intel Tangier eMMC/SDHCI driver This patch adds Intel Tangier eMMC/SDHCI driver. Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI controller is one of the devices which are *not* on a PCI and, hence, cannot be enumerated by standard PCI means. This driver, allows for SDHCI controller on Tangier SoC to work in U-Boot. Signed-off-by: Vincent Tinelli Signed-off-by: Felipe Balbi Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 78091cc..05e0b10 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -325,6 +325,20 @@ config MMC_SDHCI_XENON If unsure, say N. +config MMC_SDHCI_TANGIER + bool "Tangier SDHCI controller support" + depends on DM_MMC && BLK + depends on MMC_SDHCI + help + This selects support for SDHCI controller on Tanginer + SoC. Note that this controller does not sit on PCI bus and, + hence, cannot be enumerated by standard PCI means. + + If you're using an Intel Tangier SoC (available on Intel + Edison board), say Y here. + + If unsure, say N. + config MMC_SDHCI_TEGRA bool "SDHCI platform support for the Tegra SD/MMC Controller" depends on TEGRA diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 1e8d23f..6a26a52 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o +obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c new file mode 100644 index 0000000..77b18e7 --- /dev/null +++ b/drivers/mmc/tangier_sdhci.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define SDHCI_TANGIER_FMAX 200000000 +#define SDHCI_TANGIER_FMIN 400000 + +struct sdhci_tangier_plat { + struct mmc_config cfg; + struct mmc mmc; + void __iomem *ioaddr; +}; + +static int sdhci_tangier_bind(struct udevice *dev) +{ + struct sdhci_tangier_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sdhci_tangier_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct sdhci_tangier_plat *plat = dev_get_platdata(dev); + struct sdhci_host *host = dev_get_priv(dev); + fdt_addr_t base; + int ret; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->ioaddr = devm_ioremap(dev, base, SZ_1K); + if (!plat->ioaddr) + return -ENOMEM; + + host->name = dev->name; + host->ioaddr = plat->ioaddr; + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD; + + /* MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195 */ + host->voltages = MMC_VDD_165_195; + + ret = sdhci_setup_cfg(&plat->cfg, host, SDHCI_TANGIER_FMAX, + SDHCI_TANGIER_FMIN); + if (ret) + return ret; + + upriv->mmc = &plat->mmc; + host->mmc = &plat->mmc; + host->mmc->priv = host; + + return sdhci_probe(dev); +} + +static const struct udevice_id sdhci_tangier_match[] = { + { .compatible = "intel,sdhci-tangier" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sdhci_tangier) = { + .name = "sdhci-tangier", + .id = UCLASS_MMC, + .of_match = sdhci_tangier_match, + .bind = sdhci_tangier_bind, + .probe = sdhci_tangier_probe, + .ops = &sdhci_ops, + .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct sdhci_tangier_plat), +}; -- cgit v0.10.2 From 5b3e5b56969cb61d73a7c293679ba1536a94e70e Mon Sep 17 00:00:00 2001 From: Kevin Liu Date: Wed, 8 Mar 2017 15:16:44 +0800 Subject: mmc: sdhci: only flush cache for data command No need to flush cache for command without data. Signed-off-by: Kevin Liu diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 93cefd8..c94d58d 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -242,8 +242,10 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); #ifdef CONFIG_MMC_SDHCI_SDMA - trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); - flush_cache(start_addr, trans_bytes); + if (data != 0) { + trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); + flush_cache(start_addr, trans_bytes); + } #endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); start = get_timer(0); -- cgit v0.10.2 From 6f730459d93985298f13087af24c5313e492146b Mon Sep 17 00:00:00 2001 From: Xu Ziyuan Date: Sun, 12 Mar 2017 14:19:04 +0800 Subject: mmc: drop unnecessary send_status request It's redundant to send cmd13 after cmd9 whose response is not R1b. The card devices will not be busy w/ cmd9. Signed-off-by: Ziyuan Xu diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 3648950..72fc177 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1111,7 +1111,6 @@ static int mmc_startup(struct mmc *mmc) struct mmc_cmd cmd; ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); - int timeout = 1000; bool has_parts = false; bool part_completed; struct blk_desc *bdesc; @@ -1167,9 +1166,6 @@ static int mmc_startup(struct mmc *mmc) err = mmc_send_cmd(mmc, &cmd, NULL); - /* Waiting for the ready status */ - mmc_send_status(mmc, timeout); - if (err) return err; -- cgit v0.10.2 From 7a92652346b0a06566c2ed00107fae24efc386ba Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Mar 2017 17:00:32 +0100 Subject: mmc: xenon_sdhci: Add missing host->max_clk to Xenon SDHCI driver The Xenon SDHCI driver just missed the integration of this patch: git ID 6d0e34bf mmc: sdhci: Distinguish between base clock and maximum peripheral frequency With this patch applied, the SDHCI subsystem complains now with this warning while probing: sdhci_setup_cfg: Hardware doesn't specify base clock frequency This patch fixes this issue, by providing the missing host->max_clk variable to the SDHCI subsystem. Signed-off-by: Stefan Roese Cc: Hu Ziji Cc: Victor Gu Cc: Konstantin Porotchkin Cc: Nadav Haklai Cc: Stefan Herbrechtsmeier Cc: Jaehoon Chung diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index f678110..2a0d8b4 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -422,7 +422,8 @@ static int xenon_sdhci_probe(struct udevice *dev) host->ops = &xenon_sdhci_ops; - ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0); + host->max_clk = XENON_MMC_MAX_CLK; + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) return ret; -- cgit v0.10.2 From d666558042a0272de3f38607ce15088e0d4c88b0 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 13 Feb 2017 09:21:22 +0530 Subject: dm: core: Fix Handling of global_data moving in SPL commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL") handles relocation of GD in SPL if spl_init() is called before board_init_r(). So, uclass_root.next need not be initialized always and accessing uclass_root.next->prev gives an abort. Update the uclass_root only if it is available. Reviewed-by: Simon Glass Signed-off-by: Lokesh Vutla diff --git a/drivers/core/root.c b/drivers/core/root.c index 93ab568..33cfde6 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -44,8 +44,10 @@ struct udevice *dm_root(void) void dm_fixup_for_gd_move(struct global_data *new_gd) { /* The sentinel node has moved, so update things that point to it */ - new_gd->uclass_root.next->prev = &new_gd->uclass_root; - new_gd->uclass_root.prev->next = &new_gd->uclass_root; + if (gd->dm_root) { + new_gd->uclass_root.next->prev = &new_gd->uclass_root; + new_gd->uclass_root.prev->next = &new_gd->uclass_root; + } } fdt_addr_t dm_get_translation_offset(void) -- cgit v0.10.2 From 5c8ef359804536e57eb2fff7fd5035ea74a4c40e Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 13 Feb 2017 16:17:48 +0100 Subject: regmap: use fdt address translation In the DTS, the addresses are defined relative to the parent bus. We need to translate them to get the address as seen by the CPU core. Signed-off-by: Jean-Jacques Hiblot diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 833cd78..3bec3df 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -70,6 +70,7 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp) int addr_len, size_len, both_len; int parent; int len; + int index; parent = dev_of_offset(dev->parent); addr_len = fdt_address_cells(blob, parent); @@ -86,13 +87,14 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp) if (!map) return -ENOMEM; - map->base = fdtdec_get_number(cell, addr_len); - - for (range = map->range; count > 0; - count--, cell += both_len, range++) { - range->start = fdtdec_get_number(cell, addr_len); - range->size = fdtdec_get_number(cell + addr_len, size_len); + for (range = map->range, index = 0; count > 0; + count--, cell += both_len, range++, index++) { + fdt_size_t sz; + range->start = fdtdec_get_addr_size_fixed(blob, dev->of_offset, + "reg", index, addr_len, size_len, &sz, true); + range->size = sz; } + map->base = map->range[0].start; *mapp = map; -- cgit v0.10.2 From 1fb6921e1978d322ede538e5423faf2c27ece9c5 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 13 Feb 2017 16:17:49 +0100 Subject: drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register We used to get the address of the optionnal ctrl_mod_mmap register as the third memory range of the "reg" property. the linux driver moved to use a syscon instead. In order to keep the DTS as close as possible to that of linux, we move to using a syscon as well. If SYSCON is not supported, the driver reverts to the old way of getting the address from the 3rd memory range Signed-off-by: Jean-Jacques Hiblot diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 79955d7..3c4c9dd 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -549,21 +551,56 @@ static int ti_qspi_probe(struct udevice *bus) return 0; } +static void *map_syscon_chipselects(struct udevice *bus) +{ +#if CONFIG_IS_ENABLED(SYSCON) + struct udevice *syscon; + struct regmap *regmap; + const fdt32_t *cell; + int len, err; + + err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus, + "syscon-chipselects", &syscon); + if (err) { + debug("%s: unable to find syscon device (%d)\n", __func__, + err); + return NULL; + } + + regmap = syscon_get_regmap(syscon); + if (IS_ERR(regmap)) { + debug("%s: unable to find regmap (%ld)\n", __func__, + PTR_ERR(regmap)); + return NULL; + } + + cell = fdt_getprop(gd->fdt_blob, bus->of_offset, "syscon-chipselects", + &len); + if (len < 2*sizeof(fdt32_t)) { + debug("%s: offset not available\n", __func__); + return NULL; + } + + return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0); +#else + fdt_addr_t addr; + addr = dev_get_addr_index(bus, 2); + return (addr == FDT_ADDR_T_NONE) ? NULL : + map_physmem(addr, 0, MAP_NOCACHE); +#endif +} + static int ti_qspi_ofdata_to_platdata(struct udevice *bus) { struct ti_qspi_priv *priv = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); - fdt_addr_t addr; - void *mmap; + priv->ctrl_mod_mmap = map_syscon_chipselects(bus); priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs), MAP_NOCACHE); priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0, MAP_NOCACHE); - addr = dev_get_addr_index(bus, 2); - mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE); - priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap; priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { -- cgit v0.10.2 From 524dd45e0d10ece227457ec88517f58000c2a24b Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 22 Feb 2017 19:06:04 +0100 Subject: dtoc: make ScanTree recurse into subnodes Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */ }; }; }; This introduces a recursive helper method ScanNode, which is used by ScanTree to recursively parse the entire tree hierarchy. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index bf67ec8..afc5171 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -172,6 +172,21 @@ class DtbPlatdata: """ self.fdt = fdt_select.FdtScan(self._dtb_fname) + def ScanNode(self, root): + for node in root.subnodes: + if 'compatible' in node.props: + status = node.props.get('status') + if (not options.include_disabled and not status or + status.value != 'disabled'): + self._valid_nodes.append(node) + phandle_prop = node.props.get('phandle') + if phandle_prop: + phandle = phandle_prop.GetPhandle() + self._phandle_node[phandle] = node + + # recurse to handle any subnodes + self.ScanNode(node); + def ScanTree(self): """Scan the device tree for useful information @@ -180,8 +195,10 @@ class DtbPlatdata: _valid_nodes: A list of nodes we wish to consider include in the platform data """ - node_list = [] self._phandle_node = {} + self._valid_nodes = [] + return self.ScanNode(self.fdt.GetRoot()); + for node in self.fdt.GetRoot().subnodes: if 'compatible' in node.props: status = node.props.get('status') -- cgit v0.10.2 From 995a9f425db5613e8f257f324c7987bf24582c22 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Wed, 8 Feb 2017 17:34:11 +0200 Subject: arm64: mvebu: gpio: Add GPIO nodes to A8K family devices Add GPIO nodes to AP-806 and CP-110-master DTSI files. Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Nadav Haklai Cc: Igal Liberman Cc: Haim Boot Signed-off-by: Stefan Roese diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi index 78d995d..b5be0c4 100644 --- a/arch/arm/dts/armada-7040.dtsi +++ b/arch/arm/dts/armada-7040.dtsi @@ -45,6 +45,7 @@ * one CP110. */ +#include #include "armada-ap806-quad.dtsi" #include "armada-cp110-master.dtsi" diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi index 9c1b28c..96cc112 100644 --- a/arch/arm/dts/armada-8040.dtsi +++ b/arch/arm/dts/armada-8040.dtsi @@ -45,6 +45,7 @@ * two CP110. */ +#include #include "armada-ap806-quad.dtsi" #include "armada-cp110-master.dtsi" #include "armada-cp110-slave.dtsi" diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index 3042cb1..e0d3016 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -158,6 +158,14 @@ }; }; + ap_gpio0: gpio@6F5040 { + compatible = "marvell,orion-gpio"; + reg = <0x6F5040 0x40>; + ngpios = <20>; + gpio-controller; + #gpio-cells = <2>; + }; + xor@400000 { compatible = "marvell,mv-xor-v2"; reg = <0x400000 0x1000>, diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 661a696..6095609 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -113,6 +113,24 @@ }; }; + cpm_gpio0: gpio@440100 { + compatible = "marvell,orion-gpio"; + reg = <0x440100 0x40>; + ngpios = <32>; + gpiobase = <20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cpm_gpio1: gpio@440140 { + compatible = "marvell,orion-gpio"; + reg = <0x440140 0x40>; + ngpios = <31>; + gpiobase = <52>; + gpio-controller; + #gpio-cells = <2>; + }; + cpm_sata0: sata@540000 { compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index 92ef55c..ff3fbed 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -100,6 +100,24 @@ }; }; + cps_gpio0: gpio@440100 { + compatible = "marvell,orion-gpio"; + reg = <0x440100 0x40>; + ngpios = <32>; + gpiobase = <20>; + gpio-controller; + #gpio-cells = <2>; + }; + + cps_gpio1: gpio@440140 { + compatible = "marvell,orion-gpio"; + reg = <0x440140 0x40>; + ngpios = <31>; + gpiobase = <52>; + gpio-controller; + #gpio-cells = <2>; + }; + cps_sata0: sata@540000 { compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; -- cgit v0.10.2 From 7c4f91551898fcd3eff9bbdf295a04fac9e2dc3d Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Wed, 8 Feb 2017 17:34:12 +0200 Subject: arm64: mvebu: dts: Add i2c1 pin definitions to CPM Add i2c-1 pin mappings to CP0(master) DTSI file Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0 Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Igal Liberman Cc: Haim Boot Signed-off-by: Stefan Roese diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 6095609..1f0edde 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -94,6 +94,10 @@ marvell,pins = < 37 38 >; marvell,function = <2>; }; + cpm_i2c1_pins: cpm-i2c-pins-1 { + marvell,pins = < 35 36 >; + marvell,function = <2>; + }; cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 { marvell,pins = < 44 45 46 47 48 49 50 51 52 53 54 55 >; -- cgit v0.10.2 From 6cc102be055a9f89cb7daa7870dff9b0d33da9a1 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Wed, 8 Feb 2017 17:34:13 +0200 Subject: mvebu: pcie: Add support for GPIO reset for PCIe device Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: Konstantin Porotchkin Signed-off-by: Rabeeh Khoury Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Igal Liberman Cc: Haim Boot Signed-off-by: Stefan Roese diff --git a/doc/device-tree-bindings/pci/armada8k-pcie.txt b/doc/device-tree-bindings/pci/armada8k-pcie.txt new file mode 100644 index 0000000..7230f10 --- /dev/null +++ b/doc/device-tree-bindings/pci/armada8k-pcie.txt @@ -0,0 +1,49 @@ +Armada-8K PCIe DT details: +========================== + +Armada-8k uses synopsis designware PCIe controller. + +Required properties: +- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie". +- reg: base addresses and lengths of the pcie control and global control registers. + "ctrl" registers points to the global control registers, while the "config" space + points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below. +- interrupt-map-mask and interrupt-map, standard PCI properties to + define the mapping of the PCIe interface to interrupt numbers. +- All other definitions as per generic PCI bindings +See Linux kernel documentation: +"Documentation/devicetree/bindings/pci/designware-pcie.txt" + +Optional properties: +PHY support is still not supported for armada-8k, once it will, the following parameters can be used: +- phys : phandle to phy node associated with pcie controller. +- phy-names : must be "pcie-phy" +- marvell,reset-gpio : specifies a gpio that needs to be activated for plug-in + card reset signal release. +Example: + +cpm_pcie0: pcie@f2600000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf2600000 0 0x10000>, + <0 0xf6f00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; + num-lanes = <1>; + clocks = <&cpm_syscon0 1 13>; + marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 17fa024..d4776a9 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -461,6 +462,25 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) struct pcie_dw_mvebu *pcie = dev_get_priv(dev); struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); +#ifdef CONFIG_DM_GPIO + struct gpio_desc reset_gpio; + + gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio, + GPIOD_IS_OUT); + /* + * Issue reset to add-in card trough the dedicated GPIO. + * Some boards are connecting the card reset pin to common system + * reset wire and others are using separate GPIO port. + * In the last case we have to release a reset of the addon card + * using this GPIO. + */ + if (dm_gpio_is_valid(&reset_gpio)) { + dm_gpio_set_value(&reset_gpio, 1); + mdelay(200); + } +#else + debug("PCIE Reset on GPIO support is missing\n"); +#endif /* CONFIG_DM_GPIO */ pcie->first_busno = dev->seq; -- cgit v0.10.2 From a0c89dac2c3377eb8a5aea73a84e9717d5d5eac7 Mon Sep 17 00:00:00 2001 From: Rabeeh Khoury Date: Thu, 9 Feb 2017 12:39:10 +0200 Subject: arm64: mvebu: dts: Add DTS file for MACCHIATOBin board Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin Signed-off-by: Rabeeh Khoury Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Igal Liberman Cc: Haim Boot Signed-off-by: Stefan Roese diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index afeb43f..a1190ab 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-385-amc.dtb \ armada-7040-db.dtb \ armada-8040-db.dtb \ + armada-8040-mcbin.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts new file mode 100644 index 0000000..e42b092 --- /dev/null +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -0,0 +1,293 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include "armada-8040.dtsi" /* include SoC device tree */ + +/ { + model = "MACCHIATOBin-8040"; + compatible = "marvell,armada8040-mcbin", + "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cpm_i2c0; + i2c1 = &cpm_i2c1; + spi0 = &cps_spi1; + gpio0 = &ap_gpio0; + gpio1 = &cpm_gpio0; + gpio2 = &cpm_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + simple-bus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb3h0_vbus: usb3-vbus0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_xhci_vbus_pins>; + regulator-name = "reg-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <500000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status = "okay"; +}; + +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width= <8>; + status = "okay"; +}; + +&cpm_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins: + * [11] CLKOUT_MPP_11 (out) + * [23] LINK_RD_IN_CP2CP (in) + * [25] CLKOUT_MPP_25 (out) + * [29] AVS_FB_IN_CP2CP (in) + * [32,34] SMI + * [33] MSS power down + * [35-38] CP0 I2C1 and I2C0 + * [39] MSS CKE Enable + * [40,41] CP0 UART1 TX/RX + * [42,43] XSMI (controls two 10G phys) + * [47] USB VBUS EN + * [48] FAN PWM + * [49] 10G port 1 interrupt + * [50] 10G port 0 interrupt + * [51] 2.5G SFP TX fault + * [52] PCIe reset out + * [53] 2.5G SFP mode + * [54] 2.5G SFP LOS + * [55] Micro SD card detect + * [56-61] Micro SD + * [62] CP1 KR SFP FAULT + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0 7 0xa 7 2 2 2 2 0xa + 7 7 8 8 0 0 0 0 0 0 + 0 0 0 0 0 0 0xe 0xe 0xe 0xe + 0xe 0xe 0 >; + + cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + marvell,pins = < 47 >; + marvell,function = <0>; + }; + + cpm_pcie_reset_pins: cpm-pcie-reset-pins { + marvell,pins = < 52 >; + marvell,function = <0>; + }; +}; + +/* uSD slot */ +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width= <4>; + status = "okay"; +}; + +/* PCIe x4 */ +&cpm_pcie0 { + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_pcie_reset_pins>; + marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */ + status = "okay"; +}; + +&cpm_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_sata0 { + status = "okay"; +}; + +&cpm_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0: PCIe0 (x4) + * Lane 1: PCIe0 (x4) + * Lane 2: PCIe0 (x4) + * Lane 3: PCIe0 (x4) + * Lane 4: KR (10G) + * Lane 5: SATA1 + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + }; + phy5 { + phy-type = ; + }; +}; + +&cps_sata0 { + status = "okay"; +}; + +&cps_usb3_0 { + vbus-supply = <®_usb3h0_vbus>; + status = "okay"; +}; + +&cps_utmi0 { + status = "okay"; +}; + +&cps_pinctl { + /* + * MPP Bus: + * [0-5] TDM + * [6,7] CP1_UART 0 + * [8] CP1 10G SFP LOS + * [9] CP1 10G PHY RESET + * [10] CP1 10G SFP TX Disable + * [11] CP1 10G SFP Mode + * [12] SPI1 CS1n + * [13] SPI1 MISO (TDM and SPI ROM shared) + * [14] SPI1 CS0n + * [15] SPI1 MOSI (TDM and SPI ROM shared) + * [16] SPI1 CLK (TDM and SPI ROM shared) + * [24] CP1 2.5G SFP TX Disable + * [26] CP0 10G SFP TX Fault + * [27] CP0 10G SFP Mode + * [28] CP0 10G SFP LOS + * [29] CP0 10G SFP TX Disable + * [30] USB Over current indication + * [31] 10G Port 0 phy reset + * [32-62] = 0xff: Keep default CP1_shared_pins: + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 + 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; +}; + +&cps_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cps_spi1_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +&cps_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: SGMII2 + * Lane 1: SATA 0 + * Lane 2: USB HOST 0 + * Lane 3: SATA1 + * Lane 4: KR (10G) + * Lane 5: SGMII3 + */ + phy0 { + phy-type = ; + phy-speed = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + }; + phy5 { + phy-type = ; + }; +}; -- cgit v0.10.2 From e562e51ee2cf82383aa60aea49f81753529c0433 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 9 Feb 2017 12:39:37 +0200 Subject: arm64: mvebu: Add default configuraton for MACCHIATOBin board Add default configuration for MACHHIATOBin community board based on Aramda-8040 SoC. Change-Id: Ic6b562065c0929ec338492452f765115c15a6188 Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Igal Liberman Cc: Haim Boot Signed-off-by: Stefan Roese diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig new file mode 100644 index 0000000..0de3d9e --- /dev/null +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_8K=y +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_REGULATOR=y +CONFIG_BLOCK_CACHE=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_DM_GPIO=y +CONFIG_MVEBU_GPIO=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_SMBIOS_MANUFACTURER="" -- cgit v0.10.2 From 137b1883e756f60ef4b1e1720dafcbf7d76d87c5 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Sun, 12 Feb 2017 11:10:30 +0200 Subject: mvebu: usb: xhci: Add VBUS regulator supply to the host driver The USB device should linked to VBUS regulator through "vbus-supply" DTS property. This patch adds handling for "vbus-supply" property inside the USB device entry for turning on the VBUS regulator upon the host adapter probe. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Marek Vasut Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Igal Liberman Cc: Haim Boot Acked-by: Marek Vasut Signed-off-by: Stefan Roese diff --git a/doc/device-tree-bindings/usb/marvell.xhci-usb.txt b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt new file mode 100644 index 0000000..e042d1b --- /dev/null +++ b/doc/device-tree-bindings/usb/marvell.xhci-usb.txt @@ -0,0 +1,28 @@ +Marvell SOC USB controllers + +This controller is integrated in Armada 3700/8K. +It uses the same properties as a generic XHCI host controller + +Required properties : + - compatible: should be one or more of: + - "marvell,armada3700-xhci", "generic-xhci" for Armada 37xx SoCs + - "marvell,armada-8k-xhci", "generic-xhci" for Armada A8K SoCs + - reg: should contain address and length of the standard XHCI + register set for the device. + - interrupts: one XHCI interrupt should be described here. + +Optional properties: + - clocks: phandle to system controller clock driving this unit + - vbus-supply : If present, specifies the fixed regulator to be turned on + for providing power to the USB VBUS rail. + +Example: + cpm_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x500000 0x4000>; + interrupts = ; + clocks = <&cpm_syscon0 1 22>; + vbus-supply = <®_usb3h0_vbus>; + status = "disabled"; + }; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5129a57..0bf8274 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -25,6 +25,7 @@ config USB_XHCI_MVEBU bool "MVEBU USB 3.0 support" default y depends on ARCH_MVEBU + select DM_REGULATOR help Choose this option to add support for USB 3.0 driver on mvebu SoCs, which includes Armada8K, Armada3700 and other Armada diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index 46eb937..d880af1 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "xhci.h" @@ -44,12 +45,22 @@ static int xhci_usb_probe(struct udevice *dev) struct mvebu_xhci_platdata *plat = dev_get_platdata(dev); struct mvebu_xhci *ctx = dev_get_priv(dev); struct xhci_hcor *hcor; - int len; + int len, ret; + struct udevice *regulator; ctx->hcd = (struct xhci_hccr *)plat->hcd_base; len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)); hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len); + ret = device_get_supply_regulator(dev, "vbus-supply", ®ulator); + if (!ret) { + ret = regulator_set_enable(regulator, true); + if (ret) { + printf("Failed to turn ON the VBUS regulator\n"); + return ret; + } + } + /* Enable USB xHCI (VBUS, reset etc) in board specific code */ board_xhci_enable(); -- cgit v0.10.2 From 40991a95bb113aadbb1714c6f6c7b9a4fb2225e4 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:22 +0200 Subject: arm64: mvebu: Rename the db-88f3720 to armada-37xx platform Modify the file names and deifinitions relater to Marvell db-77f3720 board support. Convert these names to more generic armada-37xx platform for future addition of more boards based on the same SoC family. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 412bda4..a256c2f 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -74,8 +74,8 @@ config TARGET_CLEARFOG bool "Support ClearFog" select 88F6820 -config TARGET_MVEBU_DB_88F3720 - bool "Support DB-88F3720 Armada 3720" +config TARGET_MVEBU_ARMADA_37XX + bool "Support Armada 37xx platforms" select ARMADA_3700 config TARGET_DB_88F6720 @@ -116,7 +116,7 @@ endchoice config SYS_BOARD default "clearfog" if TARGET_CLEARFOG - default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720 + default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP default "db-88f6820-amc" if TARGET_DB_88F6820_AMC @@ -128,7 +128,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG - default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720 + default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP default "db-88f6820-amc" if TARGET_DB_88F6820_AMC @@ -140,7 +140,7 @@ config SYS_CONFIG_NAME config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP - default "Marvell" if TARGET_MVEBU_DB_88F3720 + default "Marvell" if TARGET_MVEBU_ARMADA_37XX default "Marvell" if TARGET_DB_88F6720 default "Marvell" if TARGET_DB_88F6820_GP default "Marvell" if TARGET_DB_88F6820_AMC diff --git a/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS new file mode 100644 index 0000000..52a3869 --- /dev/null +++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS @@ -0,0 +1,6 @@ +MVEBU_DB_88F3720 BOARD +M: Stefan Roese +S: Maintained +F: board/Marvell/mvebu_armada-37xx/ +F: include/configs/mvebu_armada-37xx.h +F: configs/mvebu_db-88f3720_defconfig diff --git a/board/Marvell/mvebu_armada-37xx/Makefile b/board/Marvell/mvebu_armada-37xx/Makefile new file mode 100644 index 0000000..ed39738 --- /dev/null +++ b/board/Marvell/mvebu_armada-37xx/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2016 Stefan Roese +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c new file mode 100644 index 0000000..edf88c7 --- /dev/null +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2016 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* IO expander I2C device */ +#define I2C_IO_EXP_ADDR 0x22 +#define I2C_IO_CFG_REG_0 0x6 +#define I2C_IO_DATA_OUT_REG_0 0x2 +#define I2C_IO_REG_0_SATA_OFF 2 +#define I2C_IO_REG_0_USB_H_OFF 1 + +int board_early_init_f(void) +{ + /* Nothing to do (yet), perhaps later some pin-muxing etc */ + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* Board specific AHCI / SATA enable code */ +int board_ahci_enable(void) +{ + struct udevice *dev; + int ret; + u8 buf[8]; + + /* Configure IO exander PCA9555: 7bit address 0x22 */ + ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); + if (ret) { + printf("Cannot find PCA9555: %d\n", ret); + return 0; + } + + ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1); + if (ret) { + printf("Failed to read IO expander value via I2C\n"); + return -EIO; + } + + /* + * Enable SATA power via IO expander connected via I2C by setting + * the corresponding bit to output mode to enable power for SATA + */ + buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF); + ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1); + if (ret) { + printf("Failed to set IO expander via I2C\n"); + return -EIO; + } + + return 0; +} + +/* Board specific xHCI enable code */ +int board_xhci_enable(void) +{ + struct udevice *dev; + int ret; + u8 buf[8]; + + /* Configure IO exander PCA9555: 7bit address 0x22 */ + ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); + if (ret) { + printf("Cannot find PCA9555: %d\n", ret); + return 0; + } + + printf("Enable USB VBUS\n"); + + /* + * Read configuration (direction) and set VBUS pin as output + * (reset pin = output) + */ + ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1); + if (ret) { + printf("Failed to read IO expander value via I2C\n"); + return -EIO; + } + buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF); + ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1); + if (ret) { + printf("Failed to set IO expander via I2C\n"); + return -EIO; + } + + /* Read VBUS output value and disable it */ + ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); + if (ret) { + printf("Failed to read IO expander value via I2C\n"); + return -EIO; + } + buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF); + ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); + if (ret) { + printf("Failed to set IO expander via I2C\n"); + return -EIO; + } + + /* + * Required delay for configuration to settle - must wait for + * power on port is disabled in case VBUS signal was high, + * required 3 seconds delay to let VBUS signal fully settle down + */ + mdelay(3000); + + /* Enable VBUS power: Set output value of VBUS pin as enabled */ + buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF); + ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); + if (ret) { + printf("Failed to set IO expander via I2C\n"); + return -EIO; + } + + mdelay(500); /* required delay to let output value settle */ + + return 0; +} diff --git a/board/Marvell/mvebu_db-88f3720/MAINTAINERS b/board/Marvell/mvebu_db-88f3720/MAINTAINERS deleted file mode 100644 index 4e80917..0000000 --- a/board/Marvell/mvebu_db-88f3720/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVEBU_DB_88F3720 BOARD -M: Stefan Roese -S: Maintained -F: board/Marvell/mvebu_db-88f3720/ -F: include/configs/mvebu_db-88f3720.h -F: configs/mvebu_db-88f3720_defconfig diff --git a/board/Marvell/mvebu_db-88f3720/Makefile b/board/Marvell/mvebu_db-88f3720/Makefile deleted file mode 100644 index ed39738..0000000 --- a/board/Marvell/mvebu_db-88f3720/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2016 Stefan Roese -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := board.o diff --git a/board/Marvell/mvebu_db-88f3720/board.c b/board/Marvell/mvebu_db-88f3720/board.c deleted file mode 100644 index edf88c7..0000000 --- a/board/Marvell/mvebu_db-88f3720/board.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2016 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* IO expander I2C device */ -#define I2C_IO_EXP_ADDR 0x22 -#define I2C_IO_CFG_REG_0 0x6 -#define I2C_IO_DATA_OUT_REG_0 0x2 -#define I2C_IO_REG_0_SATA_OFF 2 -#define I2C_IO_REG_0_USB_H_OFF 1 - -int board_early_init_f(void) -{ - /* Nothing to do (yet), perhaps later some pin-muxing etc */ - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* Board specific AHCI / SATA enable code */ -int board_ahci_enable(void) -{ - struct udevice *dev; - int ret; - u8 buf[8]; - - /* Configure IO exander PCA9555: 7bit address 0x22 */ - ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); - if (ret) { - printf("Cannot find PCA9555: %d\n", ret); - return 0; - } - - ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1); - if (ret) { - printf("Failed to read IO expander value via I2C\n"); - return -EIO; - } - - /* - * Enable SATA power via IO expander connected via I2C by setting - * the corresponding bit to output mode to enable power for SATA - */ - buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF); - ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1); - if (ret) { - printf("Failed to set IO expander via I2C\n"); - return -EIO; - } - - return 0; -} - -/* Board specific xHCI enable code */ -int board_xhci_enable(void) -{ - struct udevice *dev; - int ret; - u8 buf[8]; - - /* Configure IO exander PCA9555: 7bit address 0x22 */ - ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); - if (ret) { - printf("Cannot find PCA9555: %d\n", ret); - return 0; - } - - printf("Enable USB VBUS\n"); - - /* - * Read configuration (direction) and set VBUS pin as output - * (reset pin = output) - */ - ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1); - if (ret) { - printf("Failed to read IO expander value via I2C\n"); - return -EIO; - } - buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF); - ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1); - if (ret) { - printf("Failed to set IO expander via I2C\n"); - return -EIO; - } - - /* Read VBUS output value and disable it */ - ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); - if (ret) { - printf("Failed to read IO expander value via I2C\n"); - return -EIO; - } - buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF); - ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); - if (ret) { - printf("Failed to set IO expander via I2C\n"); - return -EIO; - } - - /* - * Required delay for configuration to settle - must wait for - * power on port is disabled in case VBUS signal was high, - * required 3 seconds delay to let VBUS signal fully settle down - */ - mdelay(3000); - - /* Enable VBUS power: Set output value of VBUS pin as enabled */ - buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF); - ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); - if (ret) { - printf("Failed to set IO expander via I2C\n"); - return -EIO; - } - - mdelay(500); /* required delay to let output value settle */ - - return 0; -} diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 80f2599..4286695 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_MVEBU_DB_88F3720=y +CONFIG_TARGET_MVEBU_ARMADA_37XX=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h new file mode 100644 index 0000000..7eefdb2 --- /dev/null +++ b/include/configs/mvebu_armada-37xx.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2016 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_MVEBU_ARMADA_37XX_H +#define _CONFIG_MVEBU_ARMADA_37XX_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x00000000 + +/* additions for new ARM relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* auto boot */ +#define CONFIG_PREBOOT + +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400, 460800, 921600 } + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ +#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ + +#define CONFIG_SYS_ALT_MEMTEST + +/* End of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) + +/* + * I2C + */ +#define CONFIG_I2C_MV +#define CONFIG_SYS_I2C_SLAVE 0x0 + +/* + * SPI Flash configuration + */ +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +/* + * Ethernet Driver configuration + */ +#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + +/* USB 2.0 */ +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* USB 3.0 */ +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3 + +#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \ + CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) + +/* USB ethernet */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_RTL8152 +#define CONFIG_USB_ETHER_SMSC95XX + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_LIBATA +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define CONFIG_SUPPORT_VFAT + +#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */ diff --git a/include/configs/mvebu_db-88f3720.h b/include/configs/mvebu_db-88f3720.h deleted file mode 100644 index 6bb78e0..0000000 --- a/include/configs/mvebu_db-88f3720.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_MVEBU_DB_88F3720_H -#define _CONFIG_MVEBU_DB_88F3720_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_DISPLAY_BOARDINFO_LATE - -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_NR_DRAM_BANKS 1 - -/* auto boot */ -#define CONFIG_PREBOOT - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_ALT_MEMTEST - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) - -/* - * I2C - */ -#define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 - -/* - * SPI Flash configuration - */ -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 - -/* SPI NOR flash default params, used by sf commands */ -#define CONFIG_SF_DEFAULT_SPEED 1000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ -#define CONFIG_ARP_TIMEOUT 200 -#define CONFIG_NET_RETRY_COUNT 50 - -/* USB 2.0 */ -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 - -/* USB 3.0 */ -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3 - -#define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \ - CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) - -/* USB ethernet */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 -#define CONFIG_USB_ETHER_RTL8152 -#define CONFIG_USB_ETHER_SMSC95XX - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI -#define CONFIG_SCSI_AHCI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_LIBATA -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#define CONFIG_SUPPORT_VFAT - -#endif /* _CONFIG_MVEBU_DB_88F3720_H */ -- cgit v0.10.2 From 3a232c8293a31d7bb487eeeb27612f46c4fe8b99 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:23 +0200 Subject: arm64: a37xx: Enable Marvell ETH PHY support Enable support for Marvell Ethernet PHYs on A37xx platforms Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 7eefdb2..5408490 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -92,6 +92,7 @@ #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 +#define CONFIG_PHY_MARVELL /* USB 2.0 */ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -- cgit v0.10.2 From e5b48b972af6fadbf896b2152232feb47f3ad89d Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:24 +0200 Subject: arm64: a37xx: Enable bubt command support on A3720-DB Enable mvebu bubt command support on A3720 DB Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 4286695..bdb96e9 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -33,6 +33,9 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_BLOCK_CACHE=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y -- cgit v0.10.2 From 67de49e6adc8ccade1d7a15c2880634c23630a5b Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:25 +0200 Subject: arm64: a37xx: dts: Add pin control nodes to DT Add pin control nodes for North and South bridges to Armada-37xx DT Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 062f2a6..5bea63b 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -193,6 +193,20 @@ status = "disabled"; }; + pinctl0: pinctl@13830 { /* north bridge */ + compatible = "marvell,armada-3700-pinctl"; + bank-name = "armada-3700-nb"; + reg = <0x13830 0x4>; + pin-count = <36>; + }; + + pinctl1: pinctl@18830 { /* south bridge */ + compatible = "marvell,armada-3700-pinctl"; + bank-name = "armada-3700-sb"; + reg = <0x18830 0x4>; + pin-count = <30>; + }; + comphy: comphy@18300 { compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; reg = <0x18300 0x28>, -- cgit v0.10.2 From ce0c79372d62544fa8dda30756dcde74abf5bb02 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:26 +0200 Subject: arm64: a37xx: Handle pin controls in early board init Fix the default pin control values in a board-specific function on early board init stage. This fix allows the NETA driver to work in RGMII mode until the full-featured pin control driver gets introduced. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index edf88c7..3337f3f 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -19,9 +19,33 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_IO_REG_0_SATA_OFF 2 #define I2C_IO_REG_0_USB_H_OFF 1 +#define PINCTRL_NB_REG_VALUE 0x000173fa +#define PINCTRL_SB_REG_VALUE 0x00007a23 + int board_early_init_f(void) { - /* Nothing to do (yet), perhaps later some pin-muxing etc */ + const void *blob = gd->fdt_blob; + const char *bank_name; + const char *compat = "marvell,armada-3700-pinctl"; + int off, len; + void __iomem *addr; + + /* FIXME + * Temporary WA for setting correct pin control values + * until the real pin control driver is awailable. + */ + off = fdt_node_offset_by_compatible(blob, -1, compat); + while (off != -FDT_ERR_NOTFOUND) { + bank_name = fdt_getprop(blob, off, "bank-name", &len); + addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( + blob, off, "reg", 0, NULL, true); + if (!strncmp(bank_name, "armada-3700-nb", len)) + writel(PINCTRL_NB_REG_VALUE, addr); + else if (!strncmp(bank_name, "armada-3700-sb", len)) + writel(PINCTRL_SB_REG_VALUE, addr); + + off = fdt_node_offset_by_compatible(blob, off, compat); + } return 0; } -- cgit v0.10.2 From 2a4d94dd6cf4abf3dbd3854a803fd4fd6aa47307 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:27 +0200 Subject: mvebu: neta: Add support for board init function Add ability to use board-specific initialization flow to NETA driver (for instance Ethernet switch bring-up) Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 674075f..a1e2136 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -404,6 +404,15 @@ static struct buffer_location buffer_loc; */ #define BD_SPACE (1 << 20) +/* + * Dummy implementation that can be overwritten by a board + * specific function + */ +__weak int board_network_enable(struct mii_dev *bus) +{ + return 0; +} + /* Utility/helper methods */ /* Write helper method */ @@ -1615,6 +1624,7 @@ static int mvneta_probe(struct udevice *dev) struct mii_dev *bus; unsigned long addr; void *bd_space; + int ret; /* * Allocate buffer area for descs and rx_buffers. This is only @@ -1664,7 +1674,11 @@ static int mvneta_probe(struct udevice *dev) bus->priv = (void *)pp; pp->bus = bus; - return mdio_register(bus); + ret = mdio_register(bus); + if (ret) + return ret; + + return board_network_enable(bus); } static void mvneta_stop(struct udevice *dev) -- cgit v0.10.2 From 3fbeb52bda8aefc716c240ea5799b319ef18e2af Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:28 +0200 Subject: mvebu: neta: a37xx: Add fixed link support to neta driver Add support for fixed link to NETA driver. This feature requreed for proper support of SFP modules and onboard connected devices like Ethernet switches Signed-off-by: Konstantin Porotchkin Signed-off-by: Terry Zhou Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index a1e2136..8881cc7 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -191,11 +191,16 @@ DECLARE_GLOBAL_DATA_PTR; #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) +#define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1)) +#define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3) #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) #define MVNETA_GMAC_AN_SPEED_EN BIT(7) +#define MVNETA_GMAC_SET_FC_EN BIT(8) +#define MVNETA_GMAC_ADVERT_FC_EN BIT(9) #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) +#define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15) #define MVNETA_MIB_COUNTERS_BASE 0x3080 #define MVNETA_MIB_LATE_COLLISION 0x7c #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 @@ -566,6 +571,13 @@ static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); } +static int mvneta_port_is_fixed_link(struct mvneta_port *pp) +{ + /* phy_addr is set to invalid value for fixed link */ + return pp->phyaddr > PHY_MAX_ADDR; +} + + /* Start the Ethernet port RX and TX activity */ static void mvneta_port_up(struct mvneta_port *pp) { @@ -816,10 +828,12 @@ static void mvneta_defaults_set(struct mvneta_port *pp) /* Assign port SDMA configuration */ mvreg_write(pp, MVNETA_SDMA_CONFIG, val); - /* Enable PHY polling in hardware for U-Boot */ - val = mvreg_read(pp, MVNETA_UNIT_CONTROL); - val |= MVNETA_PHY_POLLING_ENABLE; - mvreg_write(pp, MVNETA_UNIT_CONTROL, val); + /* Enable PHY polling in hardware if not in fixed-link mode */ + if (!mvneta_port_is_fixed_link(pp)) { + val = mvreg_read(pp, MVNETA_UNIT_CONTROL); + val |= MVNETA_PHY_POLLING_ENABLE; + mvreg_write(pp, MVNETA_UNIT_CONTROL, val); + } mvneta_set_ucast_table(pp, -1); mvneta_set_special_mcast_table(pp, -1); @@ -1137,6 +1151,11 @@ static void mvneta_adjust_link(struct udevice *dev) struct phy_device *phydev = pp->phydev; int status_change = 0; + if (mvneta_port_is_fixed_link(pp)) { + debug("Using fixed link, skip link adjust\n"); + return; + } + if (phydev->link) { if ((pp->speed != phydev->speed) || (pp->duplex != phydev->duplex)) { @@ -1507,28 +1526,54 @@ static int mvneta_start(struct udevice *dev) mvneta_port_power_up(pp, pp->phy_interface); if (!pp->init || pp->link == 0) { - /* Set phy address of the port */ - mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); - phydev = phy_connect(pp->bus, pp->phyaddr, dev, - pp->phy_interface); - - pp->phydev = phydev; - phy_config(phydev); - phy_startup(phydev); - if (!phydev->link) { - printf("%s: No link.\n", phydev->dev->name); - return -1; - } + if (mvneta_port_is_fixed_link(pp)) { + u32 val; - /* Full init on first call */ - mvneta_init(dev); - pp->init = 1; - } else { - /* Upon all following calls, this is enough */ - mvneta_port_up(pp); - mvneta_port_enable(pp); + pp->init = 1; + pp->link = 1; + mvneta_init(dev); + + val = MVNETA_GMAC_FORCE_LINK_UP | + MVNETA_GMAC_IB_BYPASS_AN_EN | + MVNETA_GMAC_SET_FC_EN | + MVNETA_GMAC_ADVERT_FC_EN | + MVNETA_GMAC_SAMPLE_TX_CFG_EN; + + if (pp->duplex) + val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; + + if (pp->speed == SPEED_1000) + val |= MVNETA_GMAC_CONFIG_GMII_SPEED; + else if (pp->speed == SPEED_100) + val |= MVNETA_GMAC_CONFIG_MII_SPEED; + + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); + } else { + /* Set phy address of the port */ + mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); + + phydev = phy_connect(pp->bus, pp->phyaddr, dev, + pp->phy_interface); + + pp->phydev = phydev; + phy_config(phydev); + phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -1; + } + + /* Full init on first call */ + mvneta_init(dev); + pp->init = 1; + return 0; + } } + /* Upon all following calls, this is enough */ + mvneta_port_up(pp); + mvneta_port_enable(pp); + return 0; } @@ -1625,6 +1670,7 @@ static int mvneta_probe(struct udevice *dev) unsigned long addr; void *bd_space; int ret; + int fl_node; /* * Allocate buffer area for descs and rx_buffers. This is only @@ -1657,10 +1703,19 @@ static int mvneta_probe(struct udevice *dev) /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ pp->phy_interface = pdata->phy_interface; - /* Now read phyaddr from DT */ - addr = fdtdec_get_int(blob, node, "phy", 0); - addr = fdt_node_offset_by_phandle(blob, addr); - pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); + /* fetch 'fixed-link' property from 'neta' node */ + fl_node = fdt_subnode_offset(blob, node, "fixed-link"); + if (fl_node != -FDT_ERR_NOTFOUND) { + /* set phy_addr to invalid value for fixed link */ + pp->phyaddr = PHY_MAX_ADDR + 1; + pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex"); + pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0); + } else { + /* Now read phyaddr from DT */ + addr = fdtdec_get_int(blob, node, "phy", 0); + addr = fdt_node_offset_by_phandle(blob, addr); + pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); + } bus = mdio_alloc(); if (!bus) { -- cgit v0.10.2 From 47d85dddd1e783aa06012ca423577f15bd4bf81a Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:29 +0200 Subject: mvebu: a37xx: Add init for ESPRESSBin Topaz switch Implement the board-specific network init function for ESPRESSOBin community board, setting the on-board Topaz switch port to forward mode and allow network connection through any of the available Etherenet ports. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Cc: Joe Hershberger Reviewed-by: Joe Hershberger Signed-off-by: Stefan Roese diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 3337f3f..b9878bf 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -5,7 +5,9 @@ */ #include +#include #include +#include #include #include #include @@ -22,6 +24,29 @@ DECLARE_GLOBAL_DATA_PTR; #define PINCTRL_NB_REG_VALUE 0x000173fa #define PINCTRL_SB_REG_VALUE 0x00007a23 +/* Ethernet switch registers */ +/* SMI addresses for multi-chip mode */ +#define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p)) +#define MVEBU_SW_G2_SMI_ADDR (28) + +/* Multi-chip mode */ +#define MVEBU_SW_SMI_DATA_REG (1) +#define MVEBU_SW_SMI_CMD_REG (0) + #define SW_SMI_CMD_REG_ADDR_OFF 0 + #define SW_SMI_CMD_DEV_ADDR_OFF 5 + #define SW_SMI_CMD_SMI_OP_OFF 10 + #define SW_SMI_CMD_SMI_MODE_OFF 12 + #define SW_SMI_CMD_SMI_BUSY_OFF 15 + +/* Single-chip mode */ +/* Switch Port Registers */ +#define MVEBU_SW_LINK_CTRL_REG (1) +#define MVEBU_SW_PORT_CTRL_REG (4) + +/* Global 2 Registers */ +#define MVEBU_G2_SMI_PHY_CMD_REG (24) +#define MVEBU_G2_SMI_PHY_DATA_REG (25) + int board_early_init_f(void) { const void *blob = gd->fdt_blob; @@ -156,3 +181,69 @@ int board_xhci_enable(void) return 0; } + +/* Helper function for accessing switch devices in multi-chip connection mode */ +static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr, + int smi_addr, int reg, u16 value) +{ + u16 smi_cmd = 0; + + if (bus->write(bus, dev_smi_addr, 0, + MVEBU_SW_SMI_DATA_REG, value) != 0) { + printf("Error writing to the PHY addr=%02x reg=%02x\n", + smi_addr, reg); + return -EFAULT; + } + + smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) | + (1 << SW_SMI_CMD_SMI_MODE_OFF) | + (1 << SW_SMI_CMD_SMI_OP_OFF) | + (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) | + (reg << SW_SMI_CMD_REG_ADDR_OFF); + if (bus->write(bus, dev_smi_addr, 0, + MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) { + printf("Error writing to the PHY addr=%02x reg=%02x\n", + smi_addr, reg); + return -EFAULT; + } + + return 0; +} + +/* Bring-up board-specific network stuff */ +int board_network_enable(struct mii_dev *bus) +{ + if (!of_machine_is_compatible("marvell,armada-3720-espressobin")) + return 0; + + /* + * FIXME: remove this code once Topaz driver gets available + * A3720 Community Board Only + * Configure Topaz switch (88E6341) + * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers) + */ + mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0), + MVEBU_SW_PORT_CTRL_REG, 0x7f); + mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1), + MVEBU_SW_PORT_CTRL_REG, 0x7f); + mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2), + MVEBU_SW_PORT_CTRL_REG, 0x7f); + mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3), + MVEBU_SW_PORT_CTRL_REG, 0x7f); + + /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */ + mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0), + MVEBU_SW_LINK_CTRL_REG, 0xe002); + + /* Power up PHY 1, 2, 3 (through Global 2 registers) */ + mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, + MVEBU_G2_SMI_PHY_DATA_REG, 0x1140); + mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, + MVEBU_G2_SMI_PHY_CMD_REG, 0x9620); + mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, + MVEBU_G2_SMI_PHY_CMD_REG, 0x9640); + mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, + MVEBU_G2_SMI_PHY_CMD_REG, 0x9660); + + return 0; +} -- cgit v0.10.2 From a7223f3ec965b8c0ef6e021bf7efca169239bed1 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:30 +0200 Subject: arm64: dts: Add device tree for ESPRESSOBin board Initial DTS file for Marvell ESPRESSOBin comunity board based on Armada-3720 SoC. The Marvell ESPRESSOBin is a tiny board made by Globalscale and available on KickStarter site. It has dual core Armv8 Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM, mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0 interfaces, Gigabit Ethernet switch with 3 ports, micro-SD socket and two 46-pin GPIO connectors. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a1190ab..5f1df2a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ + armada-3720-espressobin.dtb \ armada-375-db.dtb \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts new file mode 100644 index 0000000..aa6587a --- /dev/null +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -0,0 +1,135 @@ +/* + * Device Tree file for Marvell Armada 3720 community board + * (ESPRESSOBin) + * Copyright (C) 2016 Marvell + * + * Gregory CLEMENT + * Konstantin Porotchkin + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "armada-372x.dtsi" + +/ { + model = "Marvell Armada 3720 Community Board ESPRESSOBin"; + compatible = "marvell,armada-3720-espressobin", "marvell,armada3720", "marvell,armada3710"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð0; + i2c0 = &i2c0; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; +}; + +&comphy { + max-lanes = <3>; + phy0 { + phy-type = ; + phy-speed = ; + }; + + phy1 { + phy-type = ; + phy-speed = ; + }; + + phy2 { + phy-type = ; + phy-speed = ; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "rgmii"; + phy_addr = <0x1>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c0 { + status = "okay"; +}; + +/* CON3 */ +&sata { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "spi-flash"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +/* Exported on the micro USB connector CON32 through an FTDI */ +&uart0 { + status = "okay"; +}; + +/* CON29 */ +&usb2 { + status = "okay"; +}; + +/* CON31 */ +&usb3 { + status = "okay"; +}; -- cgit v0.10.2 From 9c4cb43b1fa5daeae672bdb435cbfb7391d7b7b1 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:31 +0200 Subject: arm64: mvebu: Add default config for ESPRESSOBin board Add initial default configuration for Marvell ESPRESSOBin community board based on Aramda-3720 SoC Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig new file mode 100644 index 0000000..d1749bc --- /dev/null +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_37XX=y +CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_BLOCK_CACHE=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_MVEBU_A3700_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=25804800 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_MVEBU_A3700_UART=y +CONFIG_MVEBU_A3700_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y -- cgit v0.10.2 From fc2d466764f3f20ba13388fb438e22e74a05a056 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:32 +0200 Subject: arm64: a37xx: Disable DB configurations on ESPRESSOBin board Bypass XHCI and AHCi board configuration flow on ESPRESSOBin community board. The community board does not have i2c expander and USB VBUS is always on, so the scan for AHCi and USB devices can be faster without unneded configurations. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index b9878bf..8dc1f46 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -21,6 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_IO_REG_0_SATA_OFF 2 #define I2C_IO_REG_0_USB_H_OFF 1 +/* The pin control values are the same for DB and Espressobin */ #define PINCTRL_NB_REG_VALUE 0x000173fa #define PINCTRL_SB_REG_VALUE 0x00007a23 @@ -90,6 +91,10 @@ int board_ahci_enable(void) int ret; u8 buf[8]; + /* Only DB requres this configuration */ + if (!of_machine_is_compatible("marvell,armada-3720-db")) + return 0; + /* Configure IO exander PCA9555: 7bit address 0x22 */ ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); if (ret) { @@ -124,6 +129,10 @@ int board_xhci_enable(void) int ret; u8 buf[8]; + /* Only DB requres this configuration */ + if (!of_machine_is_compatible("marvell,armada-3720-db")) + return 0; + /* Configure IO exander PCA9555: 7bit address 0x22 */ ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); if (ret) { -- cgit v0.10.2 From edd40229d975df48c89bb88b606a0aae16f947fc Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Feb 2017 13:52:33 +0200 Subject: arm64: a37xx: Remove DM_I2C_COMPAT from the board config Remove DM_I2C_COMPAT from the board configurations for Armada 37xx platform boards for supressing the buid tim warning. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Igal Liberman Cc: Nadav Haklai Signed-off-by: Stefan Roese diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index bdb96e9..3e548a8 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -38,7 +38,6 @@ CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_BLOCK_CACHE=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index d1749bc..f02ae64 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -38,7 +38,6 @@ CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_BLOCK_CACHE=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y -- cgit v0.10.2 From 6bbe0924a799d33c1a8c9de38b60a5e0251f2aea Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Mar 2017 15:40:30 +0100 Subject: arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: Stefan Roese Suggested-by: Adam Shobash Cc: Adam Shobash Cc: Nadav Haklai Cc: Konstantin Porotchkin Signed-off-by: Stefan Roese diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index afc0cef..5925bae 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -230,6 +230,20 @@ static int serdes_max_lines_get(void) return 0; } +/* + * Tests have shown that on some boards the default width of the + * configuration pulse for the PEX link detection might lead to + * non-established PCIe links (link down). Especially under certain + * conditions (higher temperature) and with specific PCIe devices. + * To enable a board-specific detection pulse width this weak + * array "serdes_pex_pulse_width[4]" is introduced which can be + * overwritten if needed by a board-specific version. If the board + * code does not provide a non-weak version of this variable, the + * default value will be used. So nothing is changed from the + * current setup on the supported board. + */ +__weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 }; + int serdes_phy_config(void) { int status = MV_OK; @@ -891,6 +905,23 @@ int serdes_phy_config(void) pex_unit = line_num >> 2; pex_line_num = line_num % 4; if (0 == pex_line_num) { + /* + * Configure the detection pulse with before + * the reset is deasserted + */ + + /* Read the old value (indirect access) */ + reg_write(PEX_PHY_ACCESS_REG(pex_unit), + (0x48 << 16) | (1 << 31) | + (pex_line_num << 24)); + tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit)); + tmp &= ~(1 << 31); /* Clear read */ + tmp &= ~(3 << 6); /* Mask width */ + /* Insert new detection pulse width */ + tmp |= serdes_pex_pulse_width[pex_unit] << 6; + /* Write value back */ + reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp); + reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x24); DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), -- cgit v0.10.2 From 9627ce2dab35acd7f64bbd492c599423f87c26bf Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Mar 2017 15:40:31 +0100 Subject: arm: mvebu: theadorable: Add board-specific PEX detection pulse width Define a board-specific detection pulse-width array for the SerDes PCIe interfaces. If not defined in the board code, the default of currently 2 is used. Values from 0...3 are possible (2 bits). In this case of the theadorable board, PEX interface 0 needs a value of 0 for the detection pulse width so that the PCIe device (Atheros WLAN PCIe device) is consistantly detected. Signed-off-by: Stefan Roese Cc: Adam Shobash Cc: Nadav Haklai Cc: Konstantin Porotchkin Signed-off-by: Stefan Roese diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index d621682..d424217 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { }, }; +/* + * Define a board-specific detection pulse-width array for the SerDes PCIe + * interfaces. If not defined in the board code, the default of currently 2 + * is used. Values from 0...3 are possible (2 bits). + */ +u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 }; + MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) { /* Only one mode supported for this board */ -- cgit v0.10.2 From 55e0306c92ea33721aeb0946eecf82f702954513 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Mar 2017 15:40:32 +0100 Subject: arm: mvebu: theadorable: Add 'pcie' test command This board specific command tests for the presence of a specified PCIe device (via vendor-ID and device-ID). If the device is not detected, this will get printed. If the device is detected, the board will get resetted so that an easy loop test can be done. The board will reboot until the PCIe device is not detected. Signed-off-by: Stefan Roese diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index d424217..9b56620 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -294,3 +294,44 @@ int board_late_init(void) return 0; } #endif + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI) +int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + pci_dev_t bdf; + u16 ven_id, dev_id; + + if (argc != 3) + return cmd_usage(cmdtp); + + ven_id = simple_strtoul(argv[1], NULL, 16); + dev_id = simple_strtoul(argv[2], NULL, 16); + + printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n", + ven_id, dev_id); + + /* + * Check if the PCIe device is detected (somtimes its not available + * on the PCIe bus) + */ + bdf = pci_find_device(ven_id, dev_id, 0); + if (bdf == -1) { + /* PCIe device not found! */ + printf("Failed to find PCIe device\n"); + } else { + /* PCIe device found! */ + printf("PCIe device found, resetting board...\n"); + + /* default handling: SOFT reset */ + do_reset(NULL, 0, 0, NULL); + } + + return 0; +} + +U_BOOT_CMD( + pcie, 3, 0, do_pcie_test, + "Test for presence of a PCIe device", + " " +); +#endif -- cgit v0.10.2 From 0db4cd257f03b907feb52c827197ff875172e785 Mon Sep 17 00:00:00 2001 From: "mario.six@gdsys.cc" Date: Wed, 22 Feb 2017 16:07:22 +0100 Subject: dm: Add callback to modify the device tree Certain boards come in different variations by way of utilizing daughter boards, for example. These boards might contain additional chips, which are added to the main board's busses, e.g. I2C. The device tree support for such boards would either, quite naturally, employ the overlay mechanism to add such chips to the tree, or would use one large default device tree, and delete the devices that are actually not present. Regardless of approach, even on the U-Boot level, a modification of the device tree is a prerequisite to have such modular families of boards supported properly. Therefore, we add an option to make the U-Boot device tree (the actual copy later used by the driver model) writeable, and add a callback method that allows boards to modify the device tree at an early stage, at which, hopefully, also the application of device tree overlays will be possible. Signed-off-by: Mario Six Reviewed-by: Simon Glass Signed-off-by: Stefan Roese diff --git a/common/board_f.c b/common/board_f.c index 7d1ede0..bb24a63 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -751,6 +751,13 @@ static int setup_reloc(void) return 0; } +#ifdef CONFIG_OF_BOARD_FIXUP +static int fix_fdt(void) +{ + return board_fix_fdt((void *)gd->fdt_blob); +} +#endif + /* ARM calls relocate_code from its crt0.S */ #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ !CONFIG_IS_ENABLED(X86_64) @@ -1012,6 +1019,9 @@ static const init_fnc_t init_sequence_f[] = { #ifdef CONFIG_SYS_EXTBDINFO setup_board_extra, #endif +#ifdef CONFIG_OF_BOARD_FIXUP + fix_fdt, +#endif INIT_FUNC_WATCHDOG_RESET reloc_fdt, setup_reloc, diff --git a/doc/driver-model/fdt-fixup.txt b/doc/driver-model/fdt-fixup.txt new file mode 100644 index 0000000..70344bd --- /dev/null +++ b/doc/driver-model/fdt-fixup.txt @@ -0,0 +1,132 @@ +Pre-relocation device tree manipulation +======================================= + +Contents: + +1. Purpose +2. Implementation +3. Example +4. Work to be done + +1. Purpose +---------- + +In certain markets, it is beneficial for manufacturers of embedded devices to +offer certain ranges of products, where the functionality of the devices within +one series either don't differ greatly from another, or can be thought of as +"extensions" of each other, where one device only differs from another in the +addition of a small number of features (e.g. an additional output connector). + +To realize this in hardware, one method is to have a motherboard, and several +possible daughter boards that can be attached to this mother board. Different +daughter boards then either offer the slightly different functionality, or the +addition of the daughter board to the device realizes the "extension" of +functionality to the device described previously. + +For the software, we obviously want to reuse components for all these +variations of the device. This means that the software somehow needs to cope +with the situation that certain ICs may or may not be present on any given +system, depending on which daughter boards are connected to the motherboard. + +In the Linux kernel, one possible solution to this problem is to employ the +device tree overlay mechanism: There exists one "base" device tree, which +features only the components guaranteed to exist in all varieties of the +device. At the start of the kernel, the presence and type of the daughter +boards is then detected, and the corresponding device tree overlays are applied +to support the components on the daughter boards. + +Note that the components present on every variety of the board must, of course, +provide a way to find out if and which daughter boards are installed for this +mechanism to work. + +In the U-Boot boot loader, support for device tree overlays has recently been +integrated, and is used on some boards to alter the device tree that is later +passed to Linux. But since U-Boot's driver model, which is device tree-based as +well, is being used in more and more drivers, the same problem of altering the +device tree starts cropping up in U-Boot itself as well. + +An additional problem with the device tree in U-Boot is that it is read-only, +and the current mechanisms don't allow easy manipulation of the device tree +after the driver model has been initialized. While migrating to a live device +tree (at least after the relocation) would greatly simplify the solution of +this problem, it is a non-negligible task to implement it, an a interim +solution is needed to address the problem at least in the medium-term. + +Hence, we propose a solution to this problem by offering a board-specific +call-back function, which is passed a writeable pointer to the device tree. +This function is called before the device tree is relocated, and specifically +before the main U-Boot's driver model is instantiated, hence the main U-Boot +"sees" all modifications to the device tree made in this function. Furthermore, +we have the pre-relocation driver model at our disposal at this stage, which +means that we can query the hardware for the existence and variety of the +components easily. + +2. Implementation +----------------- + +To take advantage of the pre-relocation device tree manipulation mechanism, +boards have to implement the function board_fix_fdt, which has the following +signature: + +int board_fix_fdt (void *rw_fdt_blob) + +The passed-in void pointer is a writeable pointer to the device tree, which can +be used to manipulate the device tree using e.g. functions from +include/fdt_support.h. The return value should either be 0 in case of +successful execution of the device tree manipulation or something else for a +failure. Note that returning a non-null value from the function will +unrecoverably halt the boot process, as with any function from init_sequence_f +(in common/board_f.c). + +Furthermore, the Kconfig option OF_BOARD_FIXUP has to be set for the function +to be called: + +Device Tree Control +-> [*] Board-specific manipulation of Device Tree + ++----------------------------------------------------------+ +| WARNING: The actual manipulation of the device tree has | +| to be the _last_ set of operations in board_fix_fdt! | +| Since the pre-relocation driver model does not adapt to | +| changes made to the device tree either, its references | +| into the device tree will be invalid after manipulating | +| it, and unpredictable behavior might occur when | +| functions that rely on them are executed! | ++----------------------------------------------------------+ + +Hence, the recommended layout of the board_fixup_fdt call-back function is the +following: + +int board_fix_fdt(void *rw_fdt_blob) +{ + /* Collect information about device's hardware and store them in e.g. + local variables */ + + /* Do device tree manipulation using the values previously collected */ + + /* Return 0 on successful manipulation and non-zero otherwise */ +} + +If this convention is kept, both an "additive" approach, meaning that nodes for +detected components are added to the device tree, as well as a "subtractive" +approach, meaning that nodes for absent components are removed from the tree, +as well as a combination of both approaches should work. + +3. Example +---------- + +The controlcenterdc board (board/gdsys/a38x/controlcenterdc.c) features a +board_fix_fdt function, in which six GPIO expanders (which might be present or +not, since they are on daughter boards) on a I2C bus are queried for, and +subsequently deactivated in the device tree if they are not present. + +Note that the dm_i2c_simple_probe function does not use the device tree, hence +it is safe to call it after the tree has already been manipulated. + +4. Work to be done +------------------ + +* The application of device tree overlay should be possible in board_fixup_fdt, + but has not been tested at this stage. + +2017-01-06, Mario Six diff --git a/dts/Kconfig b/dts/Kconfig index 4b7d8b1..3f64eda 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -14,6 +14,16 @@ config OF_CONTROL This feature provides for run-time configuration of U-Boot via a flattened device tree. +config OF_BOARD_FIXUP + bool "Board-specific manipulation of Device Tree" + help + In certain circumstances it is necessary to be able to modify + U-Boot's device tree (e.g. to delete device from it). This option + make the Device Tree writeable and provides a board-specific + "board_fix_fdt" callback (called during pre-relocation time), which + enables the board initialization to modifiy the Device Tree. The + modified copy is subsequently used by U-Boot after relocation. + config SPL_OF_CONTROL bool "Enable run-time configuration via Device Tree in SPL" depends on SPL && OF_CONTROL diff --git a/include/common.h b/include/common.h index fbbc2cb..2cbbd5a 100644 --- a/include/common.h +++ b/include/common.h @@ -497,6 +497,7 @@ extern ssize_t spi_write (uchar *, int, uchar *, int); /* $(BOARD)/$(BOARD).c */ int board_early_init_f (void); +int board_fix_fdt (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */ int board_late_init (void); int board_postclk_init (void); /* after clocks/timebase, before env/serial */ int board_early_init_r (void); -- cgit v0.10.2 From 15f05610438981297ff628bb87e6d5789ee3fad0 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 22 Feb 2017 16:07:23 +0100 Subject: arm: mvebu: Add gdsys ControlCenter-Compact board The gdsys ControlCenter Digital board is based on a Marvell Armada 38x SOC. It boots from SPI-Flash but can be configured to boot from SD-card for factory programming and testing. On board peripherals include: - 2 x GbE - Xilinx Kintex-7 FPGA connected via PCIe - mSATA - USB3 host - Atmel TPM Signed-off-by: Dirk Eibach Signed-off-by: Mario Six Signed-off-by: Stefan Roese diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1eb373f..dacfe9a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1284,6 +1284,7 @@ source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" source "board/freescale/mx53smd/Kconfig" source "board/freescale/s32v234evb/Kconfig" +source "board/gdsys/a38x/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f1df2a..0fbbb9b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -82,7 +82,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ - armada-xp-theadorable.dtb + armada-xp-theadorable.dtb \ + armada-38x-controlcenterdc.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-ref.dtb diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts new file mode 100644 index 0000000..d183fd7 --- /dev/null +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -0,0 +1,589 @@ +/* + * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board + * + * Copyright (C) 2016 Mario Six + * + * based on the Device Tree file for Marvell Armada 388 evaluation board + * (DB-88F6820), which is + * + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "armada-388.dtsi" + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +/ { + model = "Controlcenter Digital Compact"; + compatible = "marvell,a385-db", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; + + chosen { + bootargs = "console=ttyS1,115200 earlyprintk"; + stdout-path = "/soc/internal-regs/serial@12100"; + }; + + aliases { + ethernet0 = ð0; + ethernet2 = ð2; + mdio-gpio0 = &MDIO0; + mdio-gpio1 = &MDIO1; + mdio-gpio2 = &MDIO2; + spi0 = &spi0; + spi1 = &spi1; + i2c0 = &I2C0; + i2c1 = &I2C1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; /* 256 MB */ + }; + + clocks { + sc16isclk: sc16isclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11059200>; + }; + }; + + soc { + ranges = ; + + internal-regs { + spi0: spi@10600 { + status = "okay"; + sc16is741: sc16is741@0 { + compatible = "nxp,sc16is741"; + reg = <0>; + clocks = <&sc16isclk>; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio0>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + spi1: spi@10680 { + status = "okay"; + u-boot,dm-pre-reloc; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q016a"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11"; + reg = <1>; /* Chip select 1 */ + spi-max-frequency = <108000000>; + u-boot,dm-pre-reloc; + }; + }; + + I2C0: i2c@11000 { + status = "okay"; + clock-frequency = <1000000>; + u-boot,dm-pre-reloc; + PCA21: pca9698@21 { + compatible = "nxp,pca9698"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + PCA22: pca9698@22 { + compatible = "nxp,pca9698"; + u-boot,dm-pre-reloc; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + }; + PCA23: pca9698@23 { + compatible = "nxp,pca9698"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + }; + PCA24: pca9698@24 { + compatible = "nxp,pca9698"; + reg = <0x24>; + #gpio-cells = <2>; + gpio-controller; + }; + PCA25: pca9698@25 { + compatible = "nxp,pca9698"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + }; + PCA26: pca9698@26 { + compatible = "nxp,pca9698"; + reg = <0x26>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + I2C1: i2c@11100 { + status = "okay"; + clock-frequency = <400000>; + at97sc3205t@29 { + compatible = "atmel,at97sc3204t"; + reg = <0x29>; + u-boot,i2c-offset-len = <0>; + }; + emc2305@2d { + compatible = "smsc,emc2305"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d>; + fan@0 { + reg = <0>; + }; + fan@1 { + reg = <1>; + }; + fan@2 { + reg = <2>; + }; + fan@3 { + reg = <3>; + }; + fan@4 { + reg = <4>; + }; + }; + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + lm77@4a { + compatible = "national,lm77"; + reg = <0x4a>; + }; + ads1015@4b { + compatible = "ti,ads1015"; + reg = <0x4b>; + }; + emc2305@4c { + compatible = "smsc,emc2305"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4c>; + fan@0 { + reg = <0>; + }; + fan@1 { + reg = <1>; + }; + fan@2 { + reg = <2>; + }; + fan@3 { + reg = <3>; + }; + fan@4 { + reg = <4>; + }; + }; + at24c512@54 { + compatible = "atmel,24c512"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; + ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + }; + + serial@12000 { + status = "okay"; + }; + + serial@12100 { + status = "okay"; + }; + + ethernet@34000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + + usb@58000 { + status = "ok"; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + + mdio@72004 { + phy0: ethernet-phy@0 { + reg = <1>; + }; + + phy1: ethernet-phy@1 { + reg = <0>; + }; + }; + + sata@a8000 { + status = "okay"; + }; + + sdhci@d8000 { + broken-cd; + wp-inverted; + bus-width = <4>; + status = "okay"; + no-1-8-v; + }; + + usb3@f0000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * standard PCIe slots on the board. + */ + pcie@3,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + + MDIO0: mdio0 { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = < /*MDC*/ &gpio0 13 0 + /*MDIO*/ &gpio0 14 0>; + mv88e1240@0 { + reg = <0x0>; + }; + mv88e1240@1 { + reg = <0x1>; + }; + mv88e1240@2 { + reg = <0x2>; + }; + mv88e1240@3 { + reg = <0x3>; + }; + mv88e1240@4 { + reg = <0x4>; + }; + mv88e1240@5 { + reg = <0x5>; + }; + mv88e1240@6 { + reg = <0x6>; + }; + mv88e1240@7 { + reg = <0x7>; + }; + mv88e1240@8 { + reg = <0x8>; + }; + mv88e1240@9 { + reg = <0x9>; + }; + mv88e1240@a { + reg = <0xa>; + }; + mv88e1240@b { + reg = <0xb>; + }; + mv88e1240@c { + reg = <0xc>; + }; + mv88e1240@d { + reg = <0xd>; + }; + mv88e1240@e { + reg = <0xe>; + }; + mv88e1240@f { + reg = <0xf>; + }; + mv88e1240@10 { + reg = <0x10>; + }; + mv88e1240@11 { + reg = <0x11>; + }; + mv88e1240@12 { + reg = <0x12>; + }; + mv88e1240@13 { + reg = <0x13>; + }; + mv88e1240@14 { + reg = <0x14>; + }; + mv88e1240@15 { + reg = <0x15>; + }; + mv88e1240@16 { + reg = <0x16>; + }; + mv88e1240@17 { + reg = <0x17>; + }; + mv88e1240@18 { + reg = <0x18>; + }; + mv88e1240@19 { + reg = <0x19>; + }; + mv88e1240@1a { + reg = <0x1a>; + }; + mv88e1240@1b { + reg = <0x1b>; + }; + mv88e1240@1c { + reg = <0x1c>; + }; + mv88e1240@1d { + reg = <0x1d>; + }; + mv88e1240@1e { + reg = <0x1e>; + }; + mv88e1240@1f { + reg = <0x1f>; + }; + }; + + MDIO1: mdio1 { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = < /*MDC*/ &gpio0 25 0 + /*MDIO*/ &gpio1 13 0>; + mv88e1240@0 { + reg = <0x0>; + }; + mv88e1240@1 { + reg = <0x1>; + }; + mv88e1240@2 { + reg = <0x2>; + }; + mv88e1240@3 { + reg = <0x3>; + }; + mv88e1240@4 { + reg = <0x4>; + }; + mv88e1240@5 { + reg = <0x5>; + }; + mv88e1240@6 { + reg = <0x6>; + }; + mv88e1240@7 { + reg = <0x7>; + }; + mv88e1240@8 { + reg = <0x8>; + }; + mv88e1240@9 { + reg = <0x9>; + }; + mv88e1240@a { + reg = <0xa>; + }; + mv88e1240@b { + reg = <0xb>; + }; + mv88e1240@c { + reg = <0xc>; + }; + mv88e1240@d { + reg = <0xd>; + }; + mv88e1240@e { + reg = <0xe>; + }; + mv88e1240@f { + reg = <0xf>; + }; + mv88e1240@10 { + reg = <0x10>; + }; + mv88e1240@11 { + reg = <0x11>; + }; + mv88e1240@12 { + reg = <0x12>; + }; + mv88e1240@13 { + reg = <0x13>; + }; + mv88e1240@14 { + reg = <0x14>; + }; + mv88e1240@15 { + reg = <0x15>; + }; + mv88e1240@16 { + reg = <0x16>; + }; + mv88e1240@17 { + reg = <0x17>; + }; + mv88e1240@18 { + reg = <0x18>; + }; + mv88e1240@19 { + reg = <0x19>; + }; + mv88e1240@1a { + reg = <0x1a>; + }; + mv88e1240@1b { + reg = <0x1b>; + }; + mv88e1240@1c { + reg = <0x1c>; + }; + mv88e1240@1d { + reg = <0x1d>; + }; + mv88e1240@1e { + reg = <0x1e>; + }; + mv88e1240@1f { + reg = <0x1f>; + }; + }; + + MDIO2: mdio2 { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = < /*MDC*/ &gpio1 14 0 + /*MDIO*/ &gpio0 24 0>; + mv88e1240@0 { + reg = <0x0>; + }; + mv88e1240@1 { + reg = <0x1>; + }; + mv88e1240@2 { + reg = <0x2>; + }; + mv88e1240@3 { + reg = <0x3>; + }; + mv88e1240@4 { + reg = <0x4>; + }; + mv88e1240@5 { + reg = <0x5>; + }; + mv88e1240@6 { + reg = <0x6>; + }; + mv88e1240@7 { + reg = <0x7>; + }; + mv88e1240@8 { + reg = <0x8>; + }; + mv88e1240@9 { + reg = <0x9>; + }; + mv88e1240@a { + reg = <0xa>; + }; + mv88e1240@b { + reg = <0xb>; + }; + mv88e1240@c { + reg = <0xc>; + }; + mv88e1240@d { + reg = <0xd>; + }; + mv88e1240@e { + reg = <0xe>; + }; + mv88e1240@f { + reg = <0xf>; + }; + mv88e1240@10 { + reg = <0x10>; + }; + mv88e1240@11 { + reg = <0x11>; + }; + mv88e1240@12 { + reg = <0x12>; + }; + mv88e1240@13 { + reg = <0x13>; + }; + mv88e1240@14 { + reg = <0x14>; + }; + mv88e1240@15 { + reg = <0x15>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + finder_led { + label = "finder-led"; + gpios = <&PCA22 25 0>; + }; + + status_led { + label = "status-led"; + gpios = <&gpio0 29 0>; + }; + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a256c2f..6ae54ef 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -112,6 +112,10 @@ config TARGET_THEADORABLE select BOARD_LATE_INIT if USB select MV78260 +config TARGET_CONTROLCENTERDC + bool "Support CONTROLCENTERDC" + select 88F6820 + endchoice config SYS_BOARD diff --git a/board/gdsys/a38x/.gitignore b/board/gdsys/a38x/.gitignore new file mode 100644 index 0000000..775b934 --- /dev/null +++ b/board/gdsys/a38x/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/gdsys/a38x/Kconfig b/board/gdsys/a38x/Kconfig new file mode 100644 index 0000000..3fdef64 --- /dev/null +++ b/board/gdsys/a38x/Kconfig @@ -0,0 +1,36 @@ +if TARGET_CONTROLCENTERDC + +config SYS_BOARD + default "a38x" + +config SYS_VENDOR + default "gdsys" + +config SYS_SOC + default "mvebu" + +config SYS_CONFIG_NAME + default "controlcenterdc" + +menu "Controlcenter DC board options" + +choice + prompt "Select boot method" + +config SPL_BOOT_DEVICE_SPI + bool "SPI" + +config SPL_BOOT_DEVICE_MMC + bool "MMC" + select SPL_LIBDISK_SUPPORT + +endchoice + +#config SPL_BOOT_DEVICE +# int +# default 1 if SPL_BOOT_DEVICE_SPI +# default 2 if SPL_BOOT_DEVICE_MMC + +endmenu + +endif diff --git a/board/gdsys/a38x/MAINTAINERS b/board/gdsys/a38x/MAINTAINERS new file mode 100644 index 0000000..3cb9b63 --- /dev/null +++ b/board/gdsys/a38x/MAINTAINERS @@ -0,0 +1,7 @@ +A38X BOARD +M: Dirk Eibach +M: Mario Six +S: Maintained +F: board/gdsys/a38x/ +F: include/configs/controlcenterdc.h +F: configs/controlcenterdc_defconfig diff --git a/board/gdsys/a38x/Makefile b/board/gdsys/a38x/Makefile new file mode 100644 index 0000000..e1f0bd8 --- /dev/null +++ b/board/gdsys/a38x/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2015 Stefan Roese +# Copyright (C) 2015 Reinhard Pfau +# Copyright (C) 2016 Mario Six +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o spl.o keyprogram.o dt_helpers.o + +ifeq ($(CONFIG_SPL_BUILD),) + +obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o + +extra-$(CONFIG_TARGET_CONTROLCENTERDC) += kwbimage.cfg + +KWB_REPLACE += BOOT_FROM +ifneq ($(CONFIG_SPL_BOOT_DEVICE_SPI),) + KWB_CFG_BOOT_FROM=spi +endif +ifneq ($(CONFIG_SPL_BOOT_DEVICE_MMC),) + KWB_CFG_BOOT_FROM=sdio +endif + +ifneq ($(CONFIG_SECURED_MODE_IMAGE),) +KWB_REPLACE += CSK_INDEX +KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX) + +KWB_REPLACE += SEC_BOOT_DEV +KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \ + $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \ + $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \ + ) + +KWB_REPLACE += SEC_FUSE_DUMP +KWB_CFG_SEC_FUSE_DUMP = a38x +endif + +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \ + <$< >$(dir $<)$(@F) + +endif diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c new file mode 100644 index 0000000..f0efb53 --- /dev/null +++ b/board/gdsys/a38x/controlcenterdc.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2015 Stefan Roese + * Copyright (C) 2016 Mario Six + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" +#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h" + +#include "keyprogram.h" +#include "dt_helpers.h" +#include "hydra.h" +#include "ihs_phys.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +#define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff +#define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff + +#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0 +#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000 +#define DB_GP_88F68XX_GPP_POL_LOW 0x0 +#define DB_GP_88F68XX_GPP_POL_MID 0x0 + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct hws_topology_map ddr_topology_map = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_533, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_LOW} }, /* temperature */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +static struct serdes_map serdes_topology_map[] = { + {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + /* SATA tx polarity is inverted */ + {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1}, + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0} +}; + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + *serdes_map_array = serdes_topology_map; + *count = ARRAY_SIZE(serdes_topology_map); + return 0; +} + +void board_pex_config(void) +{ +#ifdef CONFIG_SPL_BUILD + uint k; + struct gpio_desc gpio = {}; + + if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) { + /* prepare FPGA reconfiguration */ + dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT); + dm_gpio_set_value(&gpio, 0); + + /* give lunatic PCIe clock some time to stabilize */ + mdelay(500); + + /* start FPGA reconfiguration */ + dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN); + } + + /* wait for FPGA done */ + if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) { + for (k = 0; k < 20; ++k) { + if (dm_gpio_get_value(&gpio)) { + printf("FPGA done after %u rounds\n", k); + break; + } + mdelay(100); + } + } + + /* disable FPGA reset */ + if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) { + dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT); + dm_gpio_set_value(&gpio, 1); + } + + /* wait for FPGA ready */ + if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) { + for (k = 0; k < 2; ++k) { + if (!dm_gpio_get_value(&gpio)) + break; + mdelay(100); + } + } +#endif +} + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + return &ddr_topology_map; +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_SPL_BUILD + /* Configure MPP */ + writel(0x00111111, MVEBU_MPP_BASE + 0x00); + writel(0x40040000, MVEBU_MPP_BASE + 0x04); + writel(0x00466444, MVEBU_MPP_BASE + 0x08); + writel(0x00043300, MVEBU_MPP_BASE + 0x0c); + writel(0x44400000, MVEBU_MPP_BASE + 0x10); + writel(0x20000334, MVEBU_MPP_BASE + 0x14); + writel(0x40000000, MVEBU_MPP_BASE + 0x18); + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); +#endif + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +void init_host_phys(struct mii_dev *bus) +{ + uint k; + + for (k = 0; k < 2; ++k) { + struct phy_device *phydev; + + phydev = phy_find_by_mask(bus, 1 << k, + PHY_INTERFACE_MODE_SGMII); + + if (phydev) + phy_config(phydev); + } +} + +int ccdc_eth_init(void) +{ + uint k; + uint octo_phy_mask = 0; + int ret; + struct mii_dev *bus; + + /* Init SoC's phys */ + bus = miiphy_get_dev_by_name("ethernet@34000"); + + if (bus) + init_host_phys(bus); + + bus = miiphy_get_dev_by_name("ethernet@70000"); + + if (bus) + init_host_phys(bus); + + /* Init octo phys */ + octo_phy_mask = calculate_octo_phy_mask(); + + printf("IHS PHYS: %08x", octo_phy_mask); + + ret = init_octo_phys(octo_phy_mask); + + if (ret) + return ret; + + printf("\n"); + + if (!get_fpga()) { + puts("fpga was NULL\n"); + return 1; + } + + /* reset all FPGA-QSGMII instances */ + for (k = 0; k < 80; ++k) + writel(1 << 31, get_fpga()->qsgmii_port_state[k]); + + udelay(100); + + for (k = 0; k < 80; ++k) + writel(0, get_fpga()->qsgmii_port_state[k]); + return 0; +} + +#endif + +int board_late_init(void) +{ +#ifndef CONFIG_SPL_BUILD + hydra_initialize(); +#endif + return 0; +} + +int board_fix_fdt(void *rw_fdt_blob) +{ + struct udevice *bus = NULL; + uint k; + char name[64]; + int err; + + err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus); + + if (err) { + printf("Could not get I2C bus.\n"); + return err; + } + + for (k = 0x21; k <= 0x26; k++) { + snprintf(name, 64, + "/soc/internal-regs/i2c@11000/pca9698@%02x", k); + + if (!dm_i2c_simple_probe(bus, k)) + fdt_disable_by_ofname(rw_fdt_blob, name); + } + + return 0; +} + +int last_stage_init(void) +{ +#ifndef CONFIG_SPL_BUILD + ccdc_eth_init(); +#endif + if (tpm_init() || tpm_startup(TPM_ST_CLEAR) || + tpm_continue_self_test()) { + return 1; + } + + mdelay(37); + + flush_keys(); + load_and_run_keyprog(); + + return 0; +} diff --git a/board/gdsys/a38x/dt_helpers.c b/board/gdsys/a38x/dt_helpers.c new file mode 100644 index 0000000..759d82a --- /dev/null +++ b/board/gdsys/a38x/dt_helpers.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2016 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname) +{ + int offset = fdt_path_offset(rw_fdt_blob, ofname); + + return fdt_status_disabled(rw_fdt_blob, offset); +} + +bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr) +{ + struct udevice *dev; + + return !dm_i2c_probe(bus, chip_addr, DM_I2C_CHIP_RD_ADDRESS | + DM_I2C_CHIP_WR_ADDRESS, &dev); +} + +int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name, + uint offset, char *gpio_name) +{ + struct udevice *gpio_dev = NULL; + + if (uclass_get_device_by_name(UCLASS_GPIO, gpio_dev_name, &gpio_dev)) + return 1; + + gpio->dev = gpio_dev; + gpio->offset = offset; + gpio->flags = 0; + + return dm_gpio_request(gpio, gpio_name); +} + diff --git a/board/gdsys/a38x/dt_helpers.h b/board/gdsys/a38x/dt_helpers.h new file mode 100644 index 0000000..1b95262 --- /dev/null +++ b/board/gdsys/a38x/dt_helpers.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2016 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_HELPERS_H +#define __DT_HELPERS_H + +int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname); +bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr); +int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name, + uint offset, char *gpio_name); + +#endif /* __DT_HELPERS_H */ diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c new file mode 100644 index 0000000..1689d44 --- /dev/null +++ b/board/gdsys/a38x/hre.c @@ -0,0 +1,516 @@ +/* + * (C) Copyright 2013 + * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hre.h" + +/* other constants */ +enum { + ESDHC_BOOT_IMAGE_SIG_OFS = 0x40, + ESDHC_BOOT_IMAGE_SIZE_OFS = 0x48, + ESDHC_BOOT_IMAGE_ADDR_OFS = 0x50, + ESDHC_BOOT_IMAGE_TARGET_OFS = 0x58, + ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60, +}; + +enum { + I2C_SOC_0 = 0, + I2C_SOC_1 = 1, +}; + +enum access_mode { + HREG_NONE = 0, + HREG_RD = 1, + HREG_WR = 2, + HREG_RDWR = 3, +}; + +/* register constants */ +enum { + FIX_HREG_DEVICE_ID_HASH = 0, + FIX_HREG_UNUSED1 = 1, + FIX_HREG_UNUSED2 = 2, + FIX_HREG_VENDOR = 3, + COUNT_FIX_HREGS +}; + +static struct h_reg pcr_hregs[24]; +static struct h_reg fix_hregs[COUNT_FIX_HREGS]; +static struct h_reg var_hregs[8]; + +/* hre opcodes */ +enum { + /* opcodes w/o data */ + HRE_NOP = 0x00, + HRE_SYNC = HRE_NOP, + HRE_CHECK0 = 0x01, + /* opcodes w/o data, w/ sync dst */ + /* opcodes w/ data */ + HRE_LOAD = 0x81, + /* opcodes w/data, w/sync dst */ + HRE_XOR = 0xC1, + HRE_AND = 0xC2, + HRE_OR = 0xC3, + HRE_EXTEND = 0xC4, + HRE_LOADKEY = 0xC5, +}; + +/* hre errors */ +enum { + HRE_E_OK = 0, + HRE_E_TPM_FAILURE, + HRE_E_INVALID_HREG, +}; + +static uint64_t device_id; +static uint64_t device_cl; +static uint64_t device_type; + +static uint32_t platform_key_handle; + +static uint32_t hre_tpm_err; +static int hre_err = HRE_E_OK; + +#define IS_PCR_HREG(spec) ((spec) & 0x20) +#define IS_FIX_HREG(spec) (((spec) & 0x38) == 0x08) +#define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10) +#define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7)) + +static const uint8_t vendor[] = "Guntermann & Drunck"; + +/** + * @brief get the size of a given (TPM) NV area + * @param index NV index of the area to get size for + * @param size pointer to the size + * @return 0 on success, != 0 on error + */ +static int get_tpm_nv_size(uint32_t index, uint32_t *size) +{ + uint32_t err; + uint8_t info[72]; + uint8_t *ptr; + uint16_t v16; + + err = tpm_get_capability(TPM_CAP_NV_INDEX, index, + info, sizeof(info)); + if (err) { + printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n", + index, err); + return 1; + } + + /* skip tag and nvIndex */ + ptr = info + 6; + /* skip 2 pcr info fields */ + v16 = get_unaligned_be16(ptr); + ptr += 2 + v16 + 1 + 20; + v16 = get_unaligned_be16(ptr); + ptr += 2 + v16 + 1 + 20; + /* skip permission and flags */ + ptr += 6 + 3; + + *size = get_unaligned_be32(ptr); + return 0; +} + +/** + * @brief search for a key by usage auth and pub key hash. + * @param auth usage auth of the key to search for + * @param pubkey_digest (SHA1) hash of the pub key structure of the key + * @param[out] handle the handle of the key iff found + * @return 0 if key was found in TPM; != 0 if not. + */ +static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], + uint32_t *handle) +{ + uint16_t key_count; + uint32_t key_handles[10]; + uint8_t buf[288]; + uint8_t *ptr; + uint32_t err; + uint8_t digest[20]; + size_t buf_len; + unsigned int i; + + /* fetch list of already loaded keys in the TPM */ + err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf)); + if (err) + return -1; + key_count = get_unaligned_be16(buf); + ptr = buf + 2; + for (i = 0; i < key_count; ++i, ptr += 4) + key_handles[i] = get_unaligned_be32(ptr); + + /* now search a(/ the) key which we can access with the given auth */ + for (i = 0; i < key_count; ++i) { + buf_len = sizeof(buf); + err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len); + if (err && err != TPM_AUTHFAIL) + return -1; + if (err) + continue; + sha1_csum(buf, buf_len, digest); + if (!memcmp(digest, pubkey_digest, 20)) { + *handle = key_handles[i]; + return 0; + } + } + return 1; +} + +/** + * @brief read CCDM common data from TPM NV + * @return 0 if CCDM common data was found and read, !=0 if something failed. + */ +static int read_common_data(void) +{ + uint32_t size = 0; + uint32_t err; + uint8_t buf[256]; + sha1_context ctx; + + if (get_tpm_nv_size(NV_COMMON_DATA_INDEX, &size) || + size < NV_COMMON_DATA_MIN_SIZE) + return 1; + err = tpm_nv_read_value(NV_COMMON_DATA_INDEX, + buf, min(sizeof(buf), size)); + if (err) { + printf("tpm_nv_read_value() failed: %u\n", err); + return 1; + } + + device_id = get_unaligned_be64(buf); + device_cl = get_unaligned_be64(buf + 8); + device_type = get_unaligned_be64(buf + 16); + + sha1_starts(&ctx); + sha1_update(&ctx, buf, 24); + sha1_finish(&ctx, fix_hregs[FIX_HREG_DEVICE_ID_HASH].digest); + fix_hregs[FIX_HREG_DEVICE_ID_HASH].valid = true; + + platform_key_handle = get_unaligned_be32(buf + 24); + + return 0; +} + +/** + * @brief get pointer to hash register by specification + * @param spec specification of a hash register + * @return pointer to hash register or NULL if @a spec does not qualify a + * valid hash register; NULL else. + */ +static struct h_reg *get_hreg(uint8_t spec) +{ + uint8_t idx; + + idx = HREG_IDX(spec); + if (IS_FIX_HREG(spec)) { + if (idx < ARRAY_SIZE(fix_hregs)) + return fix_hregs + idx; + hre_err = HRE_E_INVALID_HREG; + } else if (IS_PCR_HREG(spec)) { + if (idx < ARRAY_SIZE(pcr_hregs)) + return pcr_hregs + idx; + hre_err = HRE_E_INVALID_HREG; + } else if (IS_VAR_HREG(spec)) { + if (idx < ARRAY_SIZE(var_hregs)) + return var_hregs + idx; + hre_err = HRE_E_INVALID_HREG; + } + return NULL; +} + +/** + * @brief get pointer of a hash register by specification and usage. + * @param spec specification of a hash register + * @param mode access mode (read or write or read/write) + * @return pointer to hash register if found and valid; NULL else. + * + * This func uses @a get_reg() to determine the hash register for a given spec. + * If a register is found it is validated according to the desired access mode. + * The value of automatic registers (PCR register and fixed registers) is + * loaded or computed on read access. + */ +static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode) +{ + struct h_reg *result; + + result = get_hreg(spec); + if (!result) + return NULL; + + if (mode & HREG_WR) { + if (IS_FIX_HREG(spec)) { + hre_err = HRE_E_INVALID_HREG; + return NULL; + } + } + if (mode & HREG_RD) { + if (!result->valid) { + if (IS_PCR_HREG(spec)) { + hre_tpm_err = tpm_pcr_read(HREG_IDX(spec), + result->digest, 20); + result->valid = (hre_tpm_err == TPM_SUCCESS); + } else if (IS_FIX_HREG(spec)) { + switch (HREG_IDX(spec)) { + case FIX_HREG_DEVICE_ID_HASH: + read_common_data(); + break; + case FIX_HREG_VENDOR: + memcpy(result->digest, vendor, 20); + result->valid = true; + break; + } + } else { + result->valid = true; + } + } + if (!result->valid) { + hre_err = HRE_E_INVALID_HREG; + return NULL; + } + } + + return result; +} + +static void *compute_and(void *_dst, const void *_src, size_t n) +{ + uint8_t *dst = _dst; + const uint8_t *src = _src; + size_t i; + + for (i = n; i-- > 0; ) + *dst++ &= *src++; + + return _dst; +} + +static void *compute_or(void *_dst, const void *_src, size_t n) +{ + uint8_t *dst = _dst; + const uint8_t *src = _src; + size_t i; + + for (i = n; i-- > 0; ) + *dst++ |= *src++; + + return _dst; +} + +static void *compute_xor(void *_dst, const void *_src, size_t n) +{ + uint8_t *dst = _dst; + const uint8_t *src = _src; + size_t i; + + for (i = n; i-- > 0; ) + *dst++ ^= *src++; + + return _dst; +} + +static void *compute_extend(void *_dst, const void *_src, size_t n) +{ + uint8_t digest[20]; + sha1_context ctx; + + sha1_starts(&ctx); + sha1_update(&ctx, _dst, n); + sha1_update(&ctx, _src, n); + sha1_finish(&ctx, digest); + memcpy(_dst, digest, min(n, sizeof(digest))); + + return _dst; +} + +static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg, + const void *key, size_t key_size) +{ + uint32_t parent_handle; + uint32_t key_handle; + + if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid) + return -1; + if (find_key(src_reg->digest, dst_reg->digest, &parent_handle)) + return -1; + hre_tpm_err = tpm_load_key2_oiap(parent_handle, key, key_size, + src_reg->digest, &key_handle); + if (hre_tpm_err) { + hre_err = HRE_E_TPM_FAILURE; + return -1; + } + + return 0; +} + +/** + * @brief executes the next opcode on the hash register engine. + * @param[in,out] ip pointer to the opcode (instruction pointer) + * @param[in,out] code_size (remaining) size of the code + * @return new instruction pointer on success, NULL on error. + */ +static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size) +{ + bool dst_modified = false; + uint32_t ins; + uint8_t opcode; + uint8_t src_spec; + uint8_t dst_spec; + uint16_t data_size; + struct h_reg *src_reg, *dst_reg; + uint8_t buf[20]; + const uint8_t *src_buf, *data; + uint8_t *ptr; + int i; + void * (*bin_func)(void *, const void *, size_t); + + if (*code_size < 4) + return NULL; + + ins = get_unaligned_be32(*ip); + opcode = **ip; + data = *ip + 4; + src_spec = (ins >> 18) & 0x3f; + dst_spec = (ins >> 12) & 0x3f; + data_size = (ins & 0x7ff); + + debug("HRE: ins=%08x (op=%02x, s=%02x, d=%02x, L=%d)\n", ins, + opcode, src_spec, dst_spec, data_size); + + if ((opcode & 0x80) && (data_size + 4) > *code_size) + return NULL; + + src_reg = access_hreg(src_spec, HREG_RD); + if (hre_err || hre_tpm_err) + return NULL; + dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR); + if (hre_err || hre_tpm_err) + return NULL; + + switch (opcode) { + case HRE_NOP: + goto end; + case HRE_CHECK0: + if (src_reg) { + for (i = 0; i < 20; ++i) { + if (src_reg->digest[i]) + return NULL; + } + } + break; + case HRE_LOAD: + bin_func = memcpy; + goto do_bin_func; + case HRE_XOR: + bin_func = compute_xor; + goto do_bin_func; + case HRE_AND: + bin_func = compute_and; + goto do_bin_func; + case HRE_OR: + bin_func = compute_or; + goto do_bin_func; + case HRE_EXTEND: + bin_func = compute_extend; +do_bin_func: + if (!dst_reg) + return NULL; + if (src_reg) { + src_buf = src_reg->digest; + } else { + if (!data_size) { + memset(buf, 0, 20); + src_buf = buf; + } else if (data_size == 1) { + memset(buf, *data, 20); + src_buf = buf; + } else if (data_size >= 20) { + src_buf = data; + } else { + src_buf = buf; + for (ptr = (uint8_t *)src_buf, i = 20; i > 0; + i -= data_size, ptr += data_size) + memcpy(ptr, data, + min_t(size_t, i, data_size)); + } + } + bin_func(dst_reg->digest, src_buf, 20); + dst_reg->valid = true; + dst_modified = true; + break; + case HRE_LOADKEY: + if (hre_op_loadkey(src_reg, dst_reg, data, data_size)) + return NULL; + break; + default: + return NULL; + } + + if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) { + hre_tpm_err = tpm_extend(HREG_IDX(dst_spec), dst_reg->digest, + dst_reg->digest); + if (hre_tpm_err) { + hre_err = HRE_E_TPM_FAILURE; + return NULL; + } + } +end: + *ip += 4; + *code_size -= 4; + if (opcode & 0x80) { + *ip += data_size; + *code_size -= data_size; + } + + return *ip; +} + +/** + * @brief runs a program on the hash register engine. + * @param code pointer to the (HRE) code. + * @param code_size size of the code (in bytes). + * @return 0 on success, != 0 on failure. + */ +int hre_run_program(const uint8_t *code, size_t code_size) +{ + size_t code_left; + const uint8_t *ip = code; + + code_left = code_size; + hre_tpm_err = 0; + hre_err = HRE_E_OK; + while (code_left > 0) + if (!hre_execute_op(&ip, &code_left)) + return -1; + + return hre_err; +} + +int hre_verify_program(struct key_program *prg) +{ + uint32_t crc; + + crc = crc32(0, prg->code, prg->code_size); + + if (crc != prg->code_crc) { + printf("HRC crc mismatch: %08x != %08x\n", + crc, prg->code_crc); + return 1; + } + return 0; +} diff --git a/board/gdsys/a38x/hre.h b/board/gdsys/a38x/hre.h new file mode 100644 index 0000000..84ce279 --- /dev/null +++ b/board/gdsys/a38x/hre.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2013 + * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HRE_H +#define __HRE_H + +struct key_program { + uint32_t magic; + uint32_t code_crc; + uint32_t code_size; + uint8_t code[]; +}; + +struct h_reg { + bool valid; + uint8_t digest[20]; +}; + +/* CCDM specific contants */ +enum { + /* NV indices */ + NV_COMMON_DATA_INDEX = 0x40000001, + /* magics for key blob chains */ + MAGIC_KEY_PROGRAM = 0x68726500, + MAGIC_HMAC = 0x68616300, + MAGIC_END_OF_CHAIN = 0x00000000, + /* sizes */ + NV_COMMON_DATA_MIN_SIZE = 3 * sizeof(uint64_t) + 2 * sizeof(uint16_t), +}; + +int hre_verify_program(struct key_program *prg); +int hre_run_program(const uint8_t *code, size_t code_size); + +#endif /* __HRE_H */ diff --git a/board/gdsys/a38x/hydra.c b/board/gdsys/a38x/hydra.c new file mode 100644 index 0000000..fa50ad2 --- /dev/null +++ b/board/gdsys/a38x/hydra.c @@ -0,0 +1,138 @@ +#include +#include /* ctrlc */ +#include + +#include "hydra.h" + +enum { + HWVER_100 = 0, + HWVER_110 = 1, + HWVER_120 = 2, +}; + +static struct pci_device_id hydra_supported[] = { + { 0x6d5e, 0xcdc1 }, + {} +}; + +static struct ihs_fpga *fpga; + +struct ihs_fpga *get_fpga(void) +{ + return fpga; +} + +void print_hydra_version(uint index) +{ + u32 versions = readl(&fpga->versions); + u32 fpga_version = readl(&fpga->fpga_version); + + uint hardware_version = versions & 0xf; + + printf("FPGA%u: mapped to %p\n ", index, fpga); + + switch (hardware_version) { + case HWVER_100: + printf("HW-Ver 1.00\n"); + break; + + case HWVER_110: + printf("HW-Ver 1.10\n"); + break; + + case HWVER_120: + printf("HW-Ver 1.20\n"); + break; + + default: + printf("HW-Ver %d(not supported)\n", + hardware_version); + break; + } + + printf(" FPGA V %d.%02d\n", + fpga_version / 100, fpga_version % 100); +} + +void hydra_initialize(void) +{ + uint i; + pci_dev_t devno; + + /* Find and probe all the matching PCI devices */ + for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) { + u32 val; + + /* Try to enable I/O accesses and bus-mastering */ + val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config_dword(devno, PCI_COMMAND, val); + + /* Make sure it worked */ + pci_read_config_dword(devno, PCI_COMMAND, &val); + if (!(val & PCI_COMMAND_MEMORY)) { + puts("Can't enable I/O memory\n"); + continue; + } + if (!(val & PCI_COMMAND_MASTER)) { + puts("Can't enable bus-mastering\n"); + continue; + } + + /* read FPGA details */ + fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + + print_hydra_version(i); + } +} + +#define REFL_PATTERN (0xdededede) +#define REFL_PATTERN_INV (~REFL_PATTERN) + +int do_hydrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint k = 0; + void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE + + 0x4000); + + if (!fpga) + return -1; + + while (1) { + u32 res; + + writel(REFL_PATTERN, &fpga->reflection_low); + res = readl(&fpga->reflection_low); + if (res != REFL_PATTERN_INV) + printf("round %u: read %08x, expected %08x\n", + k, res, REFL_PATTERN_INV); + writel(REFL_PATTERN_INV, &fpga->reflection_low); + res = readl(&fpga->reflection_low); + if (res != REFL_PATTERN) + printf("round %u: read %08x, expected %08x\n", + k, res, REFL_PATTERN); + + res = readl(pcie2_base + 0x118) & 0x1f; + if (res) + printf("FrstErrPtr %u\n", res); + res = readl(pcie2_base + 0x104); + if (res) { + printf("Uncorrectable Error Status 0x%08x\n", res); + writel(res, pcie2_base + 0x104); + } + + if (!(++k % 10000)) + printf("round %u\n", k); + + if (ctrlc()) + break; + } + + return 0; +} + +U_BOOT_CMD( + hydrate, 1, 0, do_hydrate, + "hydra reflection test", + "hydra reflection test" +); diff --git a/board/gdsys/a38x/hydra.h b/board/gdsys/a38x/hydra.h new file mode 100644 index 0000000..26562a5 --- /dev/null +++ b/board/gdsys/a38x/hydra.h @@ -0,0 +1,14 @@ +struct ihs_fpga { + u32 reflection_low; /* 0x0000 */ + u32 versions; /* 0x0004 */ + u32 fpga_version; /* 0x0008 */ + u32 fpga_features; /* 0x000c */ + u32 reserved0[4]; /* 0x0010 */ + u32 control; /* 0x0020 */ + u32 reserved1[375]; /* 0x0024 */ + u32 qsgmii_port_state[80]; /* 0x0600 */ +}; + +void print_hydra_version(uint index); +void hydra_initialize(void); +struct ihs_fpga *get_fpga(void); diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c new file mode 100644 index 0000000..494de18 --- /dev/null +++ b/board/gdsys/a38x/ihs_phys.c @@ -0,0 +1,355 @@ +#include +#include +#include +#include + +#include "ihs_phys.h" +#include "dt_helpers.h" + +enum { + PORTTYPE_MAIN_CAT, + PORTTYPE_TOP_CAT, + PORTTYPE_16C_16F, + PORTTYPE_UNKNOWN +}; + +static struct porttype { + bool phy_invert_in_pol; + bool phy_invert_out_pol; +} porttypes[] = { + { true, false }, + { false, true }, + { false, false }, +}; + +static void ihs_phy_config(struct phy_device *phydev, bool qinpn, bool qoutpn) +{ + u16 reg; + + phy_config(phydev); + + /* enable QSGMII autonegotiation with flow control */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); + reg |= (3 << 6); + phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); + + /* + * invert QSGMII Q_INP/N and Q_OUTP/N if required + * and perform global reset + */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, 26); + if (qinpn) + reg |= (1 << 13); + if (qoutpn) + reg |= (1 << 12); + reg |= (1 << 15); + phy_write(phydev, MDIO_DEVAD_NONE, 26, reg); + + /* advertise 1000BASE-T full-duplex only */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 4); + reg &= ~0x1e0; + phy_write(phydev, MDIO_DEVAD_NONE, 4, reg); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 9); + reg = (reg & ~0x300) | 0x200; + phy_write(phydev, MDIO_DEVAD_NONE, 9, reg); + + /* copper power up */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); + reg &= ~0x0004; + phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); +} + +uint calculate_octo_phy_mask(void) +{ + uint k; + uint octo_phy_mask = 0; + struct gpio_desc gpio = {}; + char gpio_name[64]; + static const char * const dev_name[] = {"pca9698@23", "pca9698@21", + "pca9698@24", "pca9698@25", + "pca9698@26"}; + + /* mark all octo phys that should be present */ + for (k = 0; k < 5; ++k) { + snprintf(gpio_name, 64, "cat-gpio-%u", k); + + if (request_gpio_by_name(&gpio, dev_name[k], 0x20, gpio_name)) + continue; + + /* check CAT flag */ + if (dm_gpio_get_value(&gpio)) + octo_phy_mask |= (1 << (k * 2)); + else + /* If CAT == 0, there's no second octo phy -> skip */ + continue; + + snprintf(gpio_name, 64, "second-octo-gpio-%u", k); + + if (request_gpio_by_name(&gpio, dev_name[k], 0x27, gpio_name)) { + /* default: second octo phy is present */ + octo_phy_mask |= (1 << (k * 2 + 1)); + continue; + } + + if (dm_gpio_get_value(&gpio) == 0) + octo_phy_mask |= (1 << (k * 2 + 1)); + } + + return octo_phy_mask; +} + +int register_miiphy_bus(uint k, struct mii_dev **bus) +{ + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + char *name = bb_miiphy_buses[k].name; + + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, + name, + MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; + *bus = miiphy_get_dev_by_name(name); + + return 0; +} + +struct porttype *get_porttype(uint octo_phy_mask, uint k) +{ + uint octo_index = k * 4; + + if (!k) { + if (octo_phy_mask & 0x01) + return &porttypes[PORTTYPE_MAIN_CAT]; + else if (!(octo_phy_mask & 0x03)) + return &porttypes[PORTTYPE_16C_16F]; + } else { + if (octo_phy_mask & (1 << octo_index)) + return &porttypes[PORTTYPE_TOP_CAT]; + } + + return NULL; +} + +int init_single_phy(struct porttype *porttype, struct mii_dev *bus, + uint bus_idx, uint m, uint phy_idx) +{ + struct phy_device *phydev = phy_find_by_mask( + bus, 1 << (m * 8 + phy_idx), + PHY_INTERFACE_MODE_MII); + + printf(" %u", bus_idx * 32 + m * 8 + phy_idx); + + if (!phydev) + puts("!"); + else + ihs_phy_config(phydev, porttype->phy_invert_in_pol, + porttype->phy_invert_out_pol); + + return 0; +} + +int init_octo_phys(uint octo_phy_mask) +{ + uint bus_idx; + + /* there are up to four octo-phys on each mdio bus */ + for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) { + uint m; + uint octo_index = bus_idx * 4; + struct mii_dev *bus = NULL; + struct porttype *porttype = NULL; + int ret; + + porttype = get_porttype(octo_phy_mask, bus_idx); + + if (!porttype) + continue; + + for (m = 0; m < 4; ++m) { + uint phy_idx; + + /** + * Register a bus device if there is at least one phy + * on the current bus + */ + if (!m && octo_phy_mask & (0xf << octo_index)) { + ret = register_miiphy_bus(bus_idx, &bus); + if (ret) + return ret; + } + + if (!(octo_phy_mask & BIT(octo_index + m))) + continue; + + for (phy_idx = 0; phy_idx < 8; ++phy_idx) + init_single_phy(porttype, bus, bus_idx, m, + phy_idx); + } + } + + return 0; +} + +/* + * MII GPIO bitbang implementation + * MDC MDIO bus + * 13 14 PHY1-4 + * 25 45 PHY5-8 + * 46 24 PHY9-10 + */ + +struct gpio_mii { + int index; + struct gpio_desc mdc_gpio; + struct gpio_desc mdio_gpio; + int mdc_num; + int mdio_num; + int mdio_value; +} gpio_mii_set[] = { + { 0, {}, {}, 13, 14, 1 }, + { 1, {}, {}, 25, 45, 1 }, + { 2, {}, {}, 46, 24, 1 }, +}; + +static int mii_mdio_init(struct bb_miiphy_bus *bus) +{ + struct gpio_mii *gpio_mii = bus->priv; + char name[32] = {}; + struct udevice *gpio_dev1 = NULL; + struct udevice *gpio_dev2 = NULL; + + if (uclass_get_device_by_name(UCLASS_GPIO, "gpio@18100", &gpio_dev1) || + uclass_get_device_by_name(UCLASS_GPIO, "gpio@18140", &gpio_dev2)) { + printf("Could not get GPIO device.\n"); + return 1; + } + + if (gpio_mii->mdc_num > 31) { + gpio_mii->mdc_gpio.dev = gpio_dev2; + gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num - 32; + } else { + gpio_mii->mdc_gpio.dev = gpio_dev1; + gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num; + } + gpio_mii->mdc_gpio.flags = 0; + snprintf(name, 32, "bb_miiphy_bus-%d-mdc", gpio_mii->index); + dm_gpio_request(&gpio_mii->mdc_gpio, name); + + if (gpio_mii->mdio_num > 31) { + gpio_mii->mdio_gpio.dev = gpio_dev2; + gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num - 32; + } else { + gpio_mii->mdio_gpio.dev = gpio_dev1; + gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num; + } + gpio_mii->mdio_gpio.flags = 0; + snprintf(name, 32, "bb_miiphy_bus-%d-mdio", gpio_mii->index); + dm_gpio_request(&gpio_mii->mdio_gpio, name); + + dm_gpio_set_dir_flags(&gpio_mii->mdc_gpio, GPIOD_IS_OUT); + dm_gpio_set_value(&gpio_mii->mdc_gpio, 1); + + return 0; +} + +static int mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct gpio_mii *gpio_mii = bus->priv; + + dm_gpio_set_value(&gpio_mii->mdc_gpio, gpio_mii->mdio_value); + + return 0; +} + +static int mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct gpio_mii *gpio_mii = bus->priv; + + dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN); + + return 0; +} + +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct gpio_mii *gpio_mii = bus->priv; + + dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_OUT); + dm_gpio_set_value(&gpio_mii->mdio_gpio, v); + gpio_mii->mdio_value = v; + + return 0; +} + +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct gpio_mii *gpio_mii = bus->priv; + + dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN); + *v = (dm_gpio_get_value(&gpio_mii->mdio_gpio)); + + return 0; +} + +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct gpio_mii *gpio_mii = bus->priv; + + dm_gpio_set_value(&gpio_mii->mdc_gpio, v); + + return 0; +} + +static int mii_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "ihs0", + .init = mii_mdio_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &gpio_mii_set[0], + }, + { + .name = "ihs1", + .init = mii_mdio_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &gpio_mii_set[1], + }, + { + .name = "ihs2", + .init = mii_mdio_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &gpio_mii_set[2], + }, +}; + +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/a38x/ihs_phys.h b/board/gdsys/a38x/ihs_phys.h new file mode 100644 index 0000000..c4bec4d --- /dev/null +++ b/board/gdsys/a38x/ihs_phys.h @@ -0,0 +1,2 @@ +uint calculate_octo_phy_mask(void); +int init_octo_phys(uint octo_phy_mask); diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c new file mode 100644 index 0000000..a4a6f1c --- /dev/null +++ b/board/gdsys/a38x/keyprogram.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2016 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include "hre.h" + +int flush_keys(void) +{ + u16 key_count; + u8 buf[288]; + u8 *ptr; + u32 err; + uint i; + + /* fetch list of already loaded keys in the TPM */ + err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf)); + if (err) + return -1; + key_count = get_unaligned_be16(buf); + ptr = buf + 2; + for (i = 0; i < key_count; ++i, ptr += 4) { + err = tpm_flush_specific(get_unaligned_be32(ptr), TPM_RT_KEY); + if (err && err != TPM_KEY_OWNER_CONTROL) + return err; + } + + return 0; +} + +int decode_hexstr(char *hexstr, u8 **result) +{ + int len = strlen(hexstr); + int bytes = len / 2; + int i; + u8 acc = 0; + + if (len % 2 == 1) + return 1; + + *result = (u8 *)malloc(bytes); + + for (i = 0; i < len; i++) { + char cur = tolower(hexstr[i]); + u8 val; + + if ((cur >= 'a' && cur <= 'f') || (cur >= '0' && cur <= '9')) { + val = cur - (cur > '9' ? 87 : 48); + + if (i % 2 == 0) + acc = 16 * val; + else + (*result)[i / 2] = acc + val; + } else { + free(*result); + return 1; + } + } + + return 0; +} + +int extract_subprogram(u8 **progdata, u32 expected_magic, + struct key_program **result) +{ + struct key_program *prog = *result; + u32 magic, code_crc, code_size; + + magic = get_unaligned_be32(*progdata); + code_crc = get_unaligned_be32(*progdata + 4); + code_size = get_unaligned_be32(*progdata + 8); + + *progdata += 12; + + if (magic != expected_magic) + return -1; + + *result = malloc(sizeof(struct key_program) + code_size); + + if (!*result) + return -1; + + prog->magic = magic; + prog->code_crc = code_crc; + prog->code_size = code_size; + memcpy(prog->code, *progdata, code_size); + + *progdata += code_size; + + if (hre_verify_program(prog)) { + free(prog); + return -1; + } + + return 0; +} + +struct key_program *parse_and_check_keyprog(u8 *progdata) +{ + struct key_program *result = NULL, *hmac = NULL; + + /* Part 1: Load key program */ + + if (extract_subprogram(&progdata, MAGIC_KEY_PROGRAM, &result)) + return NULL; + + /* Part 2: Load hmac program */ + + if (extract_subprogram(&progdata, MAGIC_HMAC, &hmac)) + return NULL; + + free(hmac); + + return result; +} + +int load_and_run_keyprog(void) +{ + char *cmd = NULL; + u8 *binprog = NULL; + char *hexprog; + struct key_program *prog; + + cmd = getenv("loadkeyprogram"); + + if (!cmd || run_command(cmd, 0)) + return 1; + + hexprog = getenv("keyprogram"); + + if (decode_hexstr(hexprog, &binprog)) + return 1; + + prog = parse_and_check_keyprog(binprog); + free(binprog); + + if (!prog) + return 1; + + if (hre_run_program(prog->code, prog->code_size)) { + free(prog); + return 1; + } + + printf("\nSD code ran successfully\n"); + + free(prog); + + return 0; +} diff --git a/board/gdsys/a38x/keyprogram.h b/board/gdsys/a38x/keyprogram.h new file mode 100644 index 0000000..a5ea7d3 --- /dev/null +++ b/board/gdsys/a38x/keyprogram.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2016 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KEYPROGRAM_H +#define __KEYPROGRAM_H + +int load_and_run_keyprog(void); +int flush_keys(void); + +#endif /* __KEYPROGRAM_H */ diff --git a/board/gdsys/a38x/kwbimage.cfg.in b/board/gdsys/a38x/kwbimage.cfg.in new file mode 100644 index 0000000..72e67d7 --- /dev/null +++ b/board/gdsys/a38x/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese +# + +# Armada 38x uses version 1 image format +VERSION 1 + +# Boot Media configurations +#@BOOT_FROM + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/board/gdsys/a38x/spl.c b/board/gdsys/a38x/spl.c new file mode 100644 index 0000000..2d05a9c --- /dev/null +++ b/board/gdsys/a38x/spl.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2016 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void spl_board_init(void) +{ +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH + u32 *bootrom_save = (u32 *)CONFIG_SPL_BOOTROM_SAVE; + u32 *regs = (u32 *)(*bootrom_save); + + printf("Returning to BootROM (return address %08x)...\n", regs[13]); + return_to_bootrom(); +#endif +} diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig new file mode 100644 index 0000000..e1c4f0c --- /dev/null +++ b/configs/controlcenterdc_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_CONTROLCENTERDC=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="armada-38x-controlcenterdc" +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_MV=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_TPM_ATMEL_TWI=y +CONFIG_TPM_AUTH_SESSIONS=y +CONFIG_TPM_FLUSH_RESOURCES=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_TPM=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h new file mode 100644 index 0000000..add5f90 --- /dev/null +++ b/include/configs/controlcenterdc.h @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2014 Stefan Roese + * Copyright (C) 2016 Mario Six + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_CONTROLCENTERDC_H +#define _CONFIG_CONTROLCENTERDC_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_CUSTOMER_BOARD_SUPPORT + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_LAST_STAGE_INIT +#define CONFIG_SPL_BOARD_INIT + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 + +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +#define CONFIG_LOADADDR 1000000 + +/* + * Commands configuration + */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_SPI + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_LIBATA +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Software (bit-bang) MII driver configuration + */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII_MULTI + +/* SPL */ +/* + * Select the boot device here + * + * Currently supported are: + * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash + * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) + */ +#define SPL_BOOT_SPI_NOR_FLASH 1 +#define SPL_BOOT_SDIO_MMC_CARD 2 +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SIZE (160 << 10) + +#if defined(CONFIG_SECURED_MODE_IMAGE) +#define CONFIG_SPL_TEXT_BASE 0x40002614 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) +#else +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) +#endif + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +/* SPL related MMC defines */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +#endif +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_HOSTNAME ccdc +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "ccdc.img" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth1\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile_addr=1000000\0" \ + "keyprogram_addr=3000000\0" \ + "keyprogram_file=keyprogram.img\0" \ + "fdtfile=controlcenterdc.dtb\0" \ + "load=tftpboot ${loadaddr} ${u-boot}\0" \ + "mmcdev=0:2\0" \ + "update=sf probe 1:0;" \ + " sf erase 0 +${filesize};" \ + " sf write ${fileaddr} 0 ${filesize}\0" \ + "upd=run load update\0" \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" \ + "loadkeyprogram=tpm flush_keys;" \ + " mmc rescan;" \ + " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ + " source ${keyprogram_addr}:script@1\0" \ + "gpio1=gpio@22_25\0" \ + "gpio2=A29\0" \ + "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ + "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ + "bootfail=for i in ${blinkseq}; do" \ + " if test $i -eq 0; then" \ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " elif test $i -eq 1; then" \ + " gpio clear ${gpio1}; gpio clear ${gpio2};" \ + " elif test $i -eq 2; then" \ + " gpio set ${gpio1}; gpio set ${gpio2};" \ + " else;" \ + " gpio clear ${gpio1}; gpio set ${gpio2};" \ + " fi; sleep 0.12; done\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "tftpboot ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=${consoledev},${baudrate} ${othbootargs}; " \ + "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ + "bootm ${bootfile_addr}" + +#define CONFIG_BOOTCOMMAND \ + "if env exists keyprogram; then;" \ + " setenv keyprogram; run nfsboot;" \ + " fi;" \ + " run dobootfail" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_CONTROLCENTERDC_H */ -- cgit v0.10.2 From 20699e6b7949c1eb174d8315807c050cfd03da9a Mon Sep 17 00:00:00 2001 From: Vlad Zakharov Date: Tue, 21 Mar 2017 14:49:47 +0300 Subject: drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov Reviewed-by: Simon Glass diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index cf999b0..54a9b00 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -33,6 +33,10 @@ #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ +#define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ +#define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ +#define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ + #define ARC_AUX_INTR_VEC_BASE 0x25 /* Data cache related auxiliary registers */ diff --git a/doc/device-tree-bindings/timer/arc_timer.txt b/doc/device-tree-bindings/timer/arc_timer.txt new file mode 100644 index 0000000..5493b21 --- /dev/null +++ b/doc/device-tree-bindings/timer/arc_timer.txt @@ -0,0 +1,24 @@ +ARC Timer + +Required properties: + +- compatible : should be "snps,arc-timer". +- reg : Specifies timer ID, could be either 0 or 1. +- clocks : Specifies clocks that drives the counter. + +Examples: + +timer@0 { + compatible = "snps,arc-timer"; + clocks = <&core_clk>; + reg = <0>; +}; + +timer@1 { + compatible = "snps,arc-timer"; + clocks = <&core_clk>; + reg = <1>; +}; + +NOTE: if you specify both timers, clocks always should be the same +as each timer is driven by the same core clock. diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 72c1416..e038523 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -65,4 +65,13 @@ config STI_TIMER help Select this to enable a timer for STi devices. +config ARC_TIMER + bool "ARC timer support" + depends on TIMER && ARC && CLK + help + Select this to enable built-in ARC timers. + ARC cores may have up to 2 built-in timers: timer0 and timer1, + usually at least one of them exists. Either of them is supported + in U-Boot. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index ae94be8..bfe65fc 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o +obj-$(CONFIG_ARC_TIMER) += arc_timer.o diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c new file mode 100644 index 0000000..e94e4a4 --- /dev/null +++ b/drivers/timer/arc_timer.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define NH_MODE (1 << 1) + +/* + * ARC timer control registers are mapped to auxiliary address space. + * There are special ARC asm command to access that addresses. + * Therefore we use built-in functions to read from and write to timer + * control register. + */ + +/* Driver private data. Contains timer id. Could be either 0 or 1. */ +struct arc_timer_priv { + uint timer_id; +}; + +static int arc_timer_get_count(struct udevice *dev, u64 *count) +{ + u32 val = 0; + struct arc_timer_priv *priv = dev_get_priv(dev); + + switch (priv->timer_id) { + case 0: + val = read_aux_reg(ARC_AUX_TIMER0_CNT); + break; + case 1: + val = read_aux_reg(ARC_AUX_TIMER1_CNT); + break; + } + *count = timer_conv_64(val); + + return 0; +} + +static int arc_timer_probe(struct udevice *dev) +{ + int id; + struct arc_timer_priv *priv = dev_get_priv(dev); + + /* Get registers offset and size */ + id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); + if (id < 0) + return -EINVAL; + + if (id > 1) + return -ENXIO; + + priv->timer_id = (uint)id; + + /* + * In ARC core there're special registers (Auxiliary or AUX) in its + * separate memory space that are used for accessing some hardware + * features of the core. They are not mapped in normal memory space + * and also always have the same location regardless core configuration. + * Thus to simplify understanding of the programming model we chose to + * access AUX regs of Timer0 and Timer1 separately instead of using + * offsets from some base address. + */ + + switch (priv->timer_id) { + case 0: + /* Disable timer if CPU is halted */ + write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); + /* Set max value for counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); + /* Set initial count value and restart counter/timer */ + write_aux_reg(ARC_AUX_TIMER0_CNT, 0); + break; + case 1: + /* Disable timer if CPU is halted */ + write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE); + /* Set max value for counter/timer */ + write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff); + /* Set initial count value and restart counter/timer */ + write_aux_reg(ARC_AUX_TIMER1_CNT, 0); + break; + } + + return 0; +} + + +static const struct timer_ops arc_timer_ops = { + .get_count = arc_timer_get_count, +}; + +static const struct udevice_id arc_timer_ids[] = { + { .compatible = "snps,arc-timer" }, + {} +}; + +U_BOOT_DRIVER(arc_timer) = { + .name = "arc_timer", + .id = UCLASS_TIMER, + .of_match = arc_timer_ids, + .probe = arc_timer_probe, + .ops = &arc_timer_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct arc_timer_priv), +}; -- cgit v0.10.2 From 7c760f6021b7a7a37f8a4b8741ce032bb0afc620 Mon Sep 17 00:00:00 2001 From: Vlad Zakharov Date: Tue, 21 Mar 2017 14:49:48 +0300 Subject: arc: dts: separate single axs10x.dts file We want to use the same device tree blobs in both Linux and U-Boot for ARC boards. Earlier device tree sources in U-Boot were very simplified and hadn't been updated for quite a long period of time. So this commit is the first step on the road to unified device tree blobs. First of all we re-organize device tree sources for AXS10X boards. As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and AXC003 cpu tiles respectively we add corresponding device tree source files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for cpu tiles and axs101.dts and axs103.dts to represent actual boards. Also we delete axs10x.dts as it is no longer used. One more important change - we add timer device to ARC skeleton device tree sources as both ARC700 and ARCHS cores contain such timer. We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree sources as it is referenced via phandle from timer node in common skeleton.dtsi file. Signed-off-by: Vlad Zakharov Reviewed-by: Simon Glass diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 4c5696b..6e4b1d0 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -118,7 +118,7 @@ config SYS_DCACHE_OFF choice prompt "Target select" - default TARGET_AXS10X + default TARGET_AXS103 config TARGET_TB100 bool "Support tb100" @@ -126,8 +126,11 @@ config TARGET_TB100 config TARGET_NSIM bool "Support standalone nSIM & Free nSIM" -config TARGET_AXS10X - bool "Support Synopsys Designware SDP board (AXS101 & AXS103)" +config TARGET_AXS101 + bool "Support Synopsys Designware SDP board AXS101" + +config TARGET_AXS103 + bool "Support Synopsys Designware SDP board AXS103" endchoice diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 1d94c08..218a647 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -2,7 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-$(CONFIG_TARGET_AXS10X) += axs10x.dtb +dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb +dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb diff --git a/arch/arc/dts/abilis_tb100.dts b/arch/arc/dts/abilis_tb100.dts index cf395c4..23329ec 100644 --- a/arch/arc/dts/abilis_tb100.dts +++ b/arch/arc/dts/abilis_tb100.dts @@ -8,13 +8,19 @@ #include "skeleton.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - aliases { console = &uart0; }; + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + u-boot,dm-pre-reloc; + }; + }; + uart0: serial@ff100000 { compatible = "snps,dw-apb-uart"; reg = <0xff100000 0x1000>; diff --git a/arch/arc/dts/axc001.dtsi b/arch/arc/dts/axc001.dtsi new file mode 100644 index 0000000..1cf630d --- /dev/null +++ b/arch/arc/dts/axc001.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <750000000>; + u-boot,dm-pre-reloc; + }; + }; +}; + diff --git a/arch/arc/dts/axc003.dtsi b/arch/arc/dts/axc003.dtsi new file mode 100644 index 0000000..5e9270a --- /dev/null +++ b/arch/arc/dts/axc003.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; + }; + }; +}; + diff --git a/arch/arc/dts/axs101.dts b/arch/arc/dts/axs101.dts new file mode 100644 index 0000000..ec7b8b7 --- /dev/null +++ b/arch/arc/dts/axs101.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +/include/ "axc001.dtsi" +/include/ "axs10x_mb.dtsi" + + +/ { + chosen { + stdout-path = &uart0; + }; +}; + diff --git a/arch/arc/dts/axs103.dts b/arch/arc/dts/axs103.dts new file mode 100644 index 0000000..8f7a76f --- /dev/null +++ b/arch/arc/dts/axs103.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +/include/ "axc003.dtsi" +/include/ "axs10x_mb.dtsi" + + +/ { + chosen { + stdout-path = &uart0; + }; +}; + diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts deleted file mode 100644 index 391d067..0000000 --- a/arch/arc/dts/axs10x.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2015 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/dts-v1/; - -#include "skeleton.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - console = &uart0; - }; - - clocks { - apbclk: apbclk { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - }; - - uart0: serial0@e0022000 { - compatible = "snps,dw-apb-uart"; - reg = <0xe0022000 0x1000>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - ethernet@e0018000 { - #interrupt-cells = <1>; - compatible = "altr,socfpga-stmmac"; - reg = < 0xe0018000 0x2000 >; - interrupts = < 25 >; - interrupt-names = "macirq"; - phy-mode = "gmii"; - snps,pbl = < 32 >; - clocks = <&apbclk>; - clock-names = "stmmaceth"; - max-speed = <100>; - }; - - ehci@0xe0040000 { - compatible = "generic-ehci"; - reg = < 0xe0040000 0x100 >; - interrupts = < 8 >; - }; - - ohci@0xe0060000 { - compatible = "generic-ohci"; - reg = < 0xe0060000 0x100 >; - interrupts = < 8 >; - }; -}; diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi new file mode 100644 index 0000000..b74d3c8 --- /dev/null +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2017 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + axs10x_mb@e0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0xe0000000 0x10000000>; + u-boot,dm-pre-reloc; + + clocks { + compatible = "simple-bus"; + u-boot,dm-pre-reloc; + + apbclk: apbclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + uartclk: uartclk { + compatible = "fixed-clock"; + clock-frequency = <33333333>; + #clock-cells = <0>; + u-boot,dm-pre-reloc; + }; + }; + + ethernet@18000 { + #interrupt-cells = <1>; + compatible = "altr,socfpga-stmmac"; + reg = < 0x18000 0x2000 >; + interrupts = < 25 >; + interrupt-names = "macirq"; + phy-mode = "gmii"; + snps,pbl = < 32 >; + clocks = <&apbclk>; + clock-names = "stmmaceth"; + max-speed = <100>; + }; + + ehci@0x40000 { + compatible = "generic-ehci"; + reg = < 0x40000 0x100 >; + interrupts = < 8 >; + }; + + ohci@0x60000 { + compatible = "generic-ohci"; + reg = < 0x60000 0x100 >; + interrupts = < 8 >; + }; + + uart0: serial0@22000 { + compatible = "snps,dw-apb-uart"; + reg = <0x22000 0x100>; + clocks = <&uartclk>; + reg-shift = <2>; + reg-io-width = <4>; + }; + }; +}; diff --git a/arch/arc/dts/nsim.dts b/arch/arc/dts/nsim.dts index 69e16c2..491c46d 100644 --- a/arch/arc/dts/nsim.dts +++ b/arch/arc/dts/nsim.dts @@ -8,17 +8,23 @@ #include "skeleton.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - aliases { console = &arcuart0; }; + cpu_card { + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <70000000>; + u-boot,dm-pre-reloc; + }; + }; + arcuart0: serial@0xc0fc1000 { compatible = "snps,arc-uart"; reg = <0xc0fc1000 0x100>; - clock-frequency = <80000000>; + clock-frequency = <70000000>; }; }; diff --git a/arch/arc/dts/skeleton.dtsi b/arch/arc/dts/skeleton.dtsi index b41d241..279fc6c 100644 --- a/arch/arc/dts/skeleton.dtsi +++ b/arch/arc/dts/skeleton.dtsi @@ -9,5 +9,22 @@ #size-cells = <1>; chosen { }; aliases { }; - memory { device_type = "memory"; reg = <0 0>; }; + + cpu_card { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + timer@0 { + compatible = "snps,arc-timer"; + clocks = <&core_clk>; + reg = <0 1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256M */ + }; }; diff --git a/board/synopsys/axs10x/Kconfig b/board/synopsys/axs10x/Kconfig index c60b6a2..dd1305a 100644 --- a/board/synopsys/axs10x/Kconfig +++ b/board/synopsys/axs10x/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AXS10X +if TARGET_AXS101 || TARGET_AXS103 config SYS_BOARD default "axs10x" diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index aed41aa..b2d4bca 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,8 +1,9 @@ CONFIG_ARC=y CONFIG_SYS_DCACHE_OFF=y +CONFIG_TARGET_AXS101=y CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_SYS_CLK_FREQ=750000000 -CONFIG_DEFAULT_DEVICE_TREE="axs10x" +CONFIG_DEFAULT_DEVICE_TREE="axs101" CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="AXS# " diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index b62e0ad..431eaa4 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -2,7 +2,7 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_SYS_CLK_FREQ=100000000 -CONFIG_DEFAULT_DEVICE_TREE="axs10x" +CONFIG_DEFAULT_DEVICE_TREE="axs103" CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="AXS# " -- cgit v0.10.2 From 1c694102a56895b7aea636f026955cc5d7ee340d Mon Sep 17 00:00:00 2001 From: Vlad Zakharov Date: Tue, 21 Mar 2017 14:49:49 +0300 Subject: arc: use timer driver for ARC boards This commit replaces legacy timer code with usage of arc timer driver. It removes arch/arc/lib/time.c file and selects CONFIG_CLK, CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default. Therefore we remove CONFIG_CLK option from less common axs101 and axs103 defconfigs. Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from axs10x.h, tb100.h and nsim.h configs files as it is no longer required. Signed-off-by: Vlad Zakharov Reviewed-by: Simon Glass diff --git a/arch/Kconfig b/arch/Kconfig index 76c690f..308c6ea 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -13,6 +13,9 @@ config ARC select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL select ARCH_EARLY_INIT_R + select CLK + select TIMER + select ARC_TIMER config ARM bool "ARM architecture" diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index eb62b3c..12097bf 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -18,7 +18,6 @@ obj-y += memcmp.o obj-y += memcpy-700.o obj-y += memset.o obj-y += reset.o -obj-y += timer.o obj-y += ints_low.o obj-y += init_helpers.o diff --git a/arch/arc/lib/timer.c b/arch/arc/lib/timer.c deleted file mode 100644 index a0acbbc..0000000 --- a/arch/arc/lib/timer.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */ - -int timer_init(void) -{ - write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); - /* Set max value for counter/timer */ - write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); - /* Set initial count value and restart counter/timer */ - write_aux_reg(ARC_AUX_TIMER0_CNT, 0); - return 0; -} - -unsigned long timer_read_counter(void) -{ - return read_aux_reg(ARC_AUX_TIMER0_CNT); -} diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index b2d4bca..1af505d 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -19,7 +19,6 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -CONFIG_CLK=y CONFIG_SYS_I2C_DW=y CONFIG_MMC=y CONFIG_MMC_DW=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 431eaa4..fb8e72f 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -18,7 +18,6 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -CONFIG_CLK=y CONFIG_SYS_I2C_DW=y CONFIG_MMC=y CONFIG_MMC_DW=y diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index d60db65..768e8fb 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -11,8 +11,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 #define ARC_APB_PERIPHERAL_BASE 0xF0000000 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) diff --git a/include/configs/nsim.h b/include/configs/nsim.h index 0cc55b7..d6d26c7 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -10,11 +10,6 @@ #include /* - * CPU configuration - */ -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - -/* * Memory configuration */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/tb100.h b/include/configs/tb100.h index b719943..115b3b3 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -10,11 +10,6 @@ #include /* - * CPU configuration - */ -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - -/* * Memory configuration */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -- cgit v0.10.2 From e1b27d27a64d3b007c877f48a1aa106d228db7fc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Feb 2017 16:50:26 +0100 Subject: bitops.h: Include bitsperlong.h as needed for GENMASK_ULL The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is defined in the bitsperlong.h header. Lets include this header as the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver uses this macro. Signed-off-by: Stefan Roese Reviewed-by: Tom Rini Reviewed-by: Joe Hershberger diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 1b2e491..576b15d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,6 +2,7 @@ #define _LINUX_BITOPS_H #include +#include #include #define BIT(nr) (1UL << (nr)) -- cgit v0.10.2 From f811e04ad76019fccb79c8ac2c84a4e84ebef5fd Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Feb 2017 13:58:37 +0100 Subject: net: mvpp2: Round up top tx buffer boundaries for dcache ops check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail. This gets rid of the warnings: CACHE: Misaligned operation at range ... Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 88e88b9..93eb1f2 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3972,7 +3972,8 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length) | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; /* Flush tx data */ - flush_dcache_range((u32)packet, (u32)packet + length); + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + ALIGN(length, PKTALIGN)); /* Enable transmit */ mb(); -- cgit v0.10.2 From f1060f0dd05c9b11bf99878c0e83455960d8ffb5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 12:13:43 +0100 Subject: net: mvpp2: simplify mvpp2_bm_bufs_add() The mvpp2_bm_bufs_add() currently creates a fake cookie by calling mvpp2_bm_cookie_pool_set(), just to be able to call mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID. Instead of doing this convoluted thing, just call mvpp2_bm_pool_put() directly, since we have the BM pool ID. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 93eb1f2..365180d 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2390,7 +2390,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port, struct mvpp2_bm_pool *bm_pool, int buf_num) { int i; - u32 bm; if (buf_num < 0 || (buf_num + bm_pool->buf_num > bm_pool->size)) { @@ -2400,10 +2399,11 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port, return 0; } - bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id); for (i = 0; i < buf_num; i++) { - mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i], + mvpp2_bm_pool_put(port, bm_pool->id, + (u32)buffer_loc.rx_buffer[i], (u32)buffer_loc.rx_buffer[i]); + } /* Update BM driver with number of buffers added to pool */ -- cgit v0.10.2 From dbeb6de136f8f1321e366a1db3558030a2fe55a7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 12:15:01 +0100 Subject: net: mvpp2: remove unused register definitions Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 365180d..42df1b7 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -294,10 +294,6 @@ do { \ #define MVPP2_SRC_ADDR_HIGH 0x28 #define MVPP2_PHY_AN_CFG0_REG 0x34 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) -#define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \ - 0x400 + (port) * 0x400) -#define MVPP2_MIB_LATE_COLLISION 0x7c -#define MVPP2_ISR_SUM_MASK_REG 0x220c #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 -- cgit v0.10.2 From 6b28f42a51b29134aa204c72b4f952cf61e4cfd2 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 12:16:23 +0100 Subject: net: mvpp2: fix indentation of MVPP2_EXT_GLOBAL_CTRL_DEFAULT Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 42df1b7..74ae1a2 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -295,7 +295,7 @@ do { \ #define MVPP2_PHY_AN_CFG0_REG 0x34 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c -#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 +#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 /* Per-port registers */ #define MVPP2_GMAC_CTRL_0_REG 0x0 -- cgit v0.10.2 From c0abc761b12bfa3a19dc9291a6213982b1db4b3b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 12:19:36 +0100 Subject: net: mvpp2: simplify MVPP2_PRS_RI_* definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which doesn't compile nicely on 64-bit. Moreover, those definitions are in fact unneeded, since they are always used in combination with a bit mask that ensures only the appropriate bits are modified. Therefore, such definitions should just be set to 0x0. In addition, as suggested by Russell King, we change the _MASK definitions to also use the BIT() macro so that it is clear they are related to the values defined afterwards. For example: #define MVPP2_PRS_RI_L2_CAST_MASK 0x600 #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) becomes #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) #define MVPP2_PRS_RI_L2_UCAST 0x0 #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and MVPP2_PRS_RI_L2_BCAST) are always applied with MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)). It fixes the following warnings when building the driver on a 64-bit platform (which is not possible as of this commit, but will be enabled in a follow-up commit): drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’: drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow] #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) ^ drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 74ae1a2..769680a 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -572,28 +572,28 @@ enum mvpp2_tag_type { /* Sram result info bits assignment */ #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 #define MVPP2_PRS_RI_DSA_MASK 0x2 -#define MVPP2_PRS_RI_VLAN_MASK 0xc -#define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3)) +#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) +#define MVPP2_PRS_RI_VLAN_NONE 0x0 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) -#define MVPP2_PRS_RI_L2_CAST_MASK 0x600 -#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) +#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) +#define MVPP2_PRS_RI_L2_UCAST 0x0 #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) #define MVPP2_PRS_RI_PPPOE_MASK 0x800 -#define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000 -#define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14)) +#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) +#define MVPP2_PRS_RI_L3_UN 0x0 #define MVPP2_PRS_RI_L3_IP4 BIT(12) #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) #define MVPP2_PRS_RI_L3_IP6 BIT(14) #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) -#define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000 -#define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16)) +#define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) +#define MVPP2_PRS_RI_L3_UCAST 0x0 #define MVPP2_PRS_RI_L3_MCAST BIT(15) #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 -- cgit v0.10.2 From d1d075a5587bafaa118a53af64c0feaff067fc9b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 12:31:53 +0100 Subject: net: mvpp2: enable building on 64-bit platforms The mvpp2 is going to be extended to support the Marvell Armada 7K/8K platform, which is ARM64. As a preparation to this work, this commit enables building the mvpp2 driver on ARM64, by: - Adjusting the Kconfig dependency - Fixing the types used in the driver so that they are 32/64-bits compliant. We use dma_addr_t for DMA addresses, and unsigned long for virtual addresses. It is worth mentioning that after this commit, the driver is for now still only used on 32-bits platforms, and will only work on 32-bits platforms. Changed by Stefan for U-Boot: Removed the Kconfig change as it does not apply to U-Boot this way. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 769680a..d508590 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2219,7 +2219,8 @@ static int mvpp2_bm_pool_create(struct udevice *dev, if (!bm_pool->virt_addr) return -ENOMEM; - if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) { + if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, + MVPP2_BM_POOL_PTR_ALIGN)) { dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); return -ENOMEM; @@ -2359,14 +2360,15 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool) } /* Get pool number from a BM cookie */ -static inline int mvpp2_bm_cookie_pool_get(u32 cookie) +static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie) { return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF; } /* Release buffer to BM */ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, - u32 buf_phys_addr, u32 buf_virt_addr) + dma_addr_t buf_phys_addr, + unsigned long buf_virt_addr) { mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr); mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr); @@ -2397,8 +2399,8 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port, for (i = 0; i < buf_num; i++) { mvpp2_bm_pool_put(port, bm_pool->id, - (u32)buffer_loc.rx_buffer[i], - (u32)buffer_loc.rx_buffer[i]); + (dma_addr_t)buffer_loc.rx_buffer[i], + (unsigned long)buffer_loc.rx_buffer[i]); } @@ -3333,7 +3335,7 @@ static int mvpp2_rx_refill(struct mvpp2_port *port, struct mvpp2_bm_pool *bm_pool, u32 bm, u32 phys_addr) { - mvpp2_pool_refill(port, bm, phys_addr, phys_addr); + mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)phys_addr); return 0; } -- cgit v0.10.2 From a7c28ff184637fdc1fef1c4ea714193b5e82ad82 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 15 Feb 2017 12:46:18 +0100 Subject: net: mvpp2: enable building on 64-bit platforms (more U-Boot specific) Some more U-Boot specific 64bit support changes, mostly changing u32 to unsigned long. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index d508590..82d3ff9 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -959,7 +959,7 @@ struct mvpp2_bm_pool { int pkt_size; /* BPPE virtual base address */ - u32 *virt_addr; + unsigned long *virt_addr; /* BPPE physical base address */ dma_addr_t phys_addr; @@ -1003,8 +1003,8 @@ struct buffer_location { struct mvpp2_tx_desc *aggr_tx_descs; struct mvpp2_tx_desc *tx_descs; struct mvpp2_rx_desc *rx_descs; - u32 *bm_pool[MVPP2_BM_POOLS_NUM]; - u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM]; + unsigned long *bm_pool[MVPP2_BM_POOLS_NUM]; + unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM]; int first_rxq; }; @@ -3963,8 +3963,8 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length) tx_desc = mvpp2_txq_next_desc_get(aggr_txq); tx_desc->phys_txq = txq->id; tx_desc->data_size = length; - tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN; - tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN; + tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN; + tx_desc->buf_phys_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN; /* First and Last descriptor */ tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; @@ -4088,24 +4088,29 @@ static int mvpp2_base_probe(struct udevice *dev) /* Align buffer area for descs and rx_buffers to 1MiB */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); - mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); + mmu_set_region_dcache_behaviour((unsigned long)bd_space, + BD_SPACE, DCACHE_OFF); buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space; size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE; - buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size); + buffer_loc.tx_descs = + (struct mvpp2_tx_desc *)((unsigned long)bd_space + size); size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE; - buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size); + buffer_loc.rx_descs = + (struct mvpp2_rx_desc *)((unsigned long)bd_space + size); size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE; for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { - buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size); + buffer_loc.bm_pool[i] = + (unsigned long *)((unsigned long)bd_space + size); size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32); } for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { - buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size); + buffer_loc.rx_buffer[i] = + (unsigned long *)((unsigned long)bd_space + size); size += RX_BUFFER_SIZE; } -- cgit v0.10.2 From 4dae32e676e3c125cb04daab3668d7b4591dd74c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 10:27:51 +0100 Subject: net: mvpp2: use "dma" instead of "phys" where appropriate As indicated by Russell King, the mvpp2 driver currently uses a lot "phys" or "phys_addr" to store what really is a DMA address. This commit clarifies this by using "dma" or "dma_addr" where appropriate. This is especially important as we are going to introduce more changes where the distinction between physical address and DMA address will be key. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 82d3ff9..53ddb33 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -799,7 +799,7 @@ struct mvpp2_tx_desc { u8 packet_offset; /* the offset from the buffer beginning */ u8 phys_txq; /* destination queue ID */ u16 data_size; /* data size of transmitted packet in bytes */ - u32 buf_phys_addr; /* physical addr of transmitted buffer */ + u32 buf_dma_addr; /* physical addr of transmitted buffer */ u32 buf_cookie; /* cookie for access to TX buffer in tx path */ u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ u32 reserved2; /* reserved (for future use) */ @@ -809,7 +809,7 @@ struct mvpp2_rx_desc { u32 status; /* info about received packet */ u16 reserved1; /* parser_info (for future use, PnC) */ u16 data_size; /* size of received packet in bytes */ - u32 buf_phys_addr; /* physical address of the buffer */ + u32 buf_dma_addr; /* physical address of the buffer */ u32 buf_cookie; /* cookie for access to RX buffer in rx path */ u16 reserved2; /* gem_port_id (for future use, PON) */ u16 reserved3; /* csum_l4 (for future use, PnC) */ @@ -864,7 +864,7 @@ struct mvpp2_tx_queue { struct mvpp2_tx_desc *descs; /* DMA address of the Tx DMA descriptors array */ - dma_addr_t descs_phys; + dma_addr_t descs_dma; /* Index of the last Tx DMA descriptor */ int last_desc; @@ -887,7 +887,7 @@ struct mvpp2_rx_queue { struct mvpp2_rx_desc *descs; /* DMA address of the RX DMA descriptors array */ - dma_addr_t descs_phys; + dma_addr_t descs_dma; /* Index of the last RX DMA descriptor */ int last_desc; @@ -960,8 +960,8 @@ struct mvpp2_bm_pool { /* BPPE virtual base address */ unsigned long *virt_addr; - /* BPPE physical base address */ - dma_addr_t phys_addr; + /* BPPE DMA base address */ + dma_addr_t dma_addr; /* Ports using BM pool */ u32 port_map; @@ -971,7 +971,7 @@ struct mvpp2_bm_pool { }; struct mvpp2_buff_hdr { - u32 next_buff_phys_addr; + u32 next_buff_dma_addr; u32 next_buff_virt_addr; u16 byte_count; u16 info; @@ -2215,7 +2215,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev, u32 val; bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id]; - bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id]; + bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id]; if (!bm_pool->virt_addr) return -ENOMEM; @@ -2227,7 +2227,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev, } mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), - bm_pool->phys_addr); + bm_pool->dma_addr); mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); @@ -2367,20 +2367,21 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie) /* Release buffer to BM */ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, - dma_addr_t buf_phys_addr, + dma_addr_t buf_dma_addr, unsigned long buf_virt_addr) { mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr); - mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr); + mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); } /* Refill BM pool */ static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, - u32 phys_addr, u32 cookie) + dma_addr_t dma_addr, + u32 cookie) { int pool = mvpp2_bm_cookie_pool_get(bm); - mvpp2_bm_pool_put(port, pool, phys_addr, cookie); + mvpp2_bm_pool_put(port, pool, dma_addr, cookie); } /* Allocate buffers for the pool */ @@ -2944,7 +2945,7 @@ static int mvpp2_aggr_txq_init(struct udevice *dev, { /* Allocate memory for TX descriptors */ aggr_txq->descs = buffer_loc.aggr_tx_descs; - aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs; + aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs; if (!aggr_txq->descs) return -ENOMEM; @@ -2961,7 +2962,7 @@ static int mvpp2_aggr_txq_init(struct udevice *dev, /* Set Tx descriptors queue starting address */ /* indirect access */ mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), - aggr_txq->descs_phys); + aggr_txq->descs_dma); mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num); return 0; @@ -2976,7 +2977,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, /* Allocate memory for RX descriptors */ rxq->descs = buffer_loc.rx_descs; - rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs; + rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs; if (!rxq->descs) return -ENOMEM; @@ -2990,7 +2991,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, /* Set Rx descriptors queue starting address - indirect access */ mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); - mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys); + mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma); mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); @@ -3017,7 +3018,7 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); u32 bm = mvpp2_bm_cookie_build(rx_desc); - mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, + mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr, rx_desc->buf_cookie); } mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); @@ -3032,7 +3033,7 @@ static void mvpp2_rxq_deinit(struct mvpp2_port *port, rxq->descs = NULL; rxq->last_desc = 0; rxq->next_desc_to_proc = 0; - rxq->descs_phys = 0; + rxq->descs_dma = 0; /* Clear Rx descriptors queue starting address and size; * free descriptor number @@ -3055,7 +3056,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port, /* Allocate memory for Tx descriptors */ txq->descs = buffer_loc.tx_descs; - txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs; + txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs; if (!txq->descs) return -ENOMEM; @@ -3067,7 +3068,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port, /* Set Tx descriptors queue starting address - indirect access */ mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); - mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys); + mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma); mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & MVPP2_TXQ_DESC_SIZE_MASK); mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); @@ -3119,7 +3120,7 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port, txq->descs = NULL; txq->last_desc = 0; txq->next_desc_to_proc = 0; - txq->descs_phys = 0; + txq->descs_dma = 0; /* Set minimum bandwidth for disabled TXQs */ mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); @@ -3333,9 +3334,9 @@ static void mvpp2_rx_error(struct mvpp2_port *port, /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ static int mvpp2_rx_refill(struct mvpp2_port *port, struct mvpp2_bm_pool *bm_pool, - u32 bm, u32 phys_addr) + u32 bm, dma_addr_t dma_addr) { - mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)phys_addr); + mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr); return 0; } @@ -3854,7 +3855,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) struct mvpp2_port *port = dev_get_priv(dev); struct mvpp2_rx_desc *rx_desc; struct mvpp2_bm_pool *bm_pool; - dma_addr_t phys_addr; + dma_addr_t dma_addr; u32 bm, rx_status; int pool, rx_bytes, err; int rx_received; @@ -3885,7 +3886,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) rx_desc = mvpp2_rxq_next_desc_get(rxq); rx_status = rx_desc->status; rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE; - phys_addr = rx_desc->buf_phys_addr; + dma_addr = rx_desc->buf_dma_addr; bm = mvpp2_bm_cookie_build(rx_desc); pool = mvpp2_bm_cookie_pool_get(bm); @@ -3903,12 +3904,12 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) if (rx_status & MVPP2_RXD_ERR_SUMMARY) { mvpp2_rx_error(port, rx_desc); /* Return the buffer to the pool */ - mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, + mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr, rx_desc->buf_cookie); return 0; } - err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr); + err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr); if (err) { netdev_err(port->dev, "failed to refill BM pools\n"); return 0; @@ -3919,7 +3920,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) mvpp2_rxq_status_update(port, rxq->id, 1, 1); /* give packet to stack - skip on first n bytes */ - data = (u8 *)phys_addr + 2 + 32; + data = (u8 *)dma_addr + 2 + 32; if (rx_bytes <= 0) return 0; @@ -3964,7 +3965,7 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length) tx_desc->phys_txq = txq->id; tx_desc->data_size = length; tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN; - tx_desc->buf_phys_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN; + tx_desc->buf_dma_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN; /* First and Last descriptor */ tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; -- cgit v0.10.2 From 15f4df3091e20a0cbb8ab23a2d009cc71d9e37f5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 10:29:43 +0100 Subject: net: mvpp2: remove support for buffer header Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 53ddb33..90ab6d7 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -970,22 +970,6 @@ struct mvpp2_bm_pool { int in_use_thresh; }; -struct mvpp2_buff_hdr { - u32 next_buff_dma_addr; - u32 next_buff_virt_addr; - u16 byte_count; - u16 info; - u8 reserved1; /* bm_qset (for future use, BM) */ -}; - -/* Buffer header info bits */ -#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff -#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK) -#define MVPP2_B_HDR_INFO_LAST_OFFS 12 -#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12) -#define MVPP2_B_HDR_INFO_IS_LAST(info) \ - ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS) - /* Static declaractions */ /* Number of RXQs used by single port */ @@ -3892,10 +3876,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) pool = mvpp2_bm_cookie_pool_get(bm); bm_pool = &port->priv->bm_pools[pool]; - /* Check if buffer header is used */ - if (rx_status & MVPP2_RXD_BUF_HDR) - return 0; - /* In case of an error, release the requested buffer pointer * to the Buffer Manager. This request process is controlled * by the hardware, and the information about the buffer is -- cgit v0.10.2 From cd9ee19226a15039127801915803769720071316 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 10:37:59 +0100 Subject: net: mvpp2: store physical address of buffer in rx_desc->buf_cookie Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 90ab6d7..17ce0e9 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2352,20 +2352,25 @@ static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie) /* Release buffer to BM */ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, dma_addr_t buf_dma_addr, - unsigned long buf_virt_addr) + unsigned long buf_phys_addr) { - mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr); + /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply + * returned in the "cookie" field of the RX + * descriptor. Instead of storing the virtual address, we + * store the physical address + */ + mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); } /* Refill BM pool */ static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, dma_addr_t dma_addr, - u32 cookie) + phys_addr_t phys_addr) { int pool = mvpp2_bm_cookie_pool_get(bm); - mvpp2_bm_pool_put(port, pool, dma_addr, cookie); + mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); } /* Allocate buffers for the pool */ -- cgit v0.10.2 From cfa414aefd530bba4dd5105c77615104c96367bf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 15:35:00 +0100 Subject: net: mvpp2: add and use accessors for TX/RX descriptors The PPv2.2 IP has a different TX and RX descriptor layout compared to PPv2.1. In order to prepare for the introduction of PPv2.2 support in mvpp2, this commit adds accessors for the different fields of the TX and RX descriptors, and changes the code to use them. For now, the mvpp2_port argument passed to the accessors is not used, but it will be used in follow-up to update the descriptor according to the version of the IP being used. Apart from the mechanical changes to use the newly introduced accessors, a few other changes, needed to use the accessors, are made: - The mvpp2_txq_inc_put() function now takes a mvpp2_port as first argument, as it is needed to use the accessors. - Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first argument, for the same reason. - In mvpp2_rx_error(), instead of accessing the RX descriptor in each case of the switch, we introduce a local variable to store the packet size. - Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie" variable to store the RX descriptor cookie, rather than accessing it from the descriptor each time. - In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the packet size from the TX descriptor, we use the actual value available in the function, which is used to set the TX descriptor packet size a few lines before. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 17ce0e9..d199eaf 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -1016,6 +1016,65 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) return readl(priv->base + offset); } +static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, + struct mvpp2_tx_desc *tx_desc, + dma_addr_t dma_addr) +{ + tx_desc->buf_dma_addr = dma_addr; +} + +static void mvpp2_txdesc_size_set(struct mvpp2_port *port, + struct mvpp2_tx_desc *tx_desc, + size_t size) +{ + tx_desc->data_size = size; +} + +static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, + struct mvpp2_tx_desc *tx_desc, + unsigned int txq) +{ + tx_desc->phys_txq = txq; +} + +static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, + struct mvpp2_tx_desc *tx_desc, + unsigned int command) +{ + tx_desc->command = command; +} + +static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, + struct mvpp2_tx_desc *tx_desc, + unsigned int offset) +{ + tx_desc->packet_offset = offset; +} + +static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) +{ + return rx_desc->buf_dma_addr; +} + +static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) +{ + return rx_desc->buf_cookie; +} + +static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) +{ + return rx_desc->data_size; +} + +static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) +{ + return rx_desc->status; +} + static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) { txq_pcpu->txq_get_index++; @@ -2779,11 +2838,15 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port *port, } /* Obtain BM cookie information from descriptor */ -static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc) +static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) { - int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >> - MVPP2_RXD_BM_POOL_ID_OFFS; int cpu = smp_processor_id(); + int pool; + + pool = (mvpp2_rxdesc_status_get(port, rx_desc) & + MVPP2_RXD_BM_POOL_ID_MASK) >> + MVPP2_RXD_BM_POOL_ID_OFFS; return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) | ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS); @@ -3005,10 +3068,11 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, for (i = 0; i < rx_received; i++) { struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); - u32 bm = mvpp2_bm_cookie_build(rx_desc); + u32 bm = mvpp2_bm_cookie_build(port, rx_desc); - mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr, - rx_desc->buf_cookie); + mvpp2_pool_refill(port, bm, + mvpp2_rxdesc_dma_addr_get(port, rx_desc), + mvpp2_rxdesc_cookie_get(port, rx_desc)); } mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); } @@ -3302,20 +3366,21 @@ static void mvpp2_link_event(struct mvpp2_port *port) static void mvpp2_rx_error(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - u32 status = rx_desc->status; + u32 status = mvpp2_rxdesc_status_get(port, rx_desc); + size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); switch (status & MVPP2_RXD_ERR_CODE_MASK) { case MVPP2_RXD_ERR_CRC: - netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n", - status, rx_desc->data_size); + netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", + status, sz); break; case MVPP2_RXD_ERR_OVERRUN: - netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n", - status, rx_desc->data_size); + netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", + status, sz); break; case MVPP2_RXD_ERR_RESOURCE: - netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n", - status, rx_desc->data_size); + netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", + status, sz); break; } } @@ -3873,11 +3938,12 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) return 0; rx_desc = mvpp2_rxq_next_desc_get(rxq); - rx_status = rx_desc->status; - rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE; - dma_addr = rx_desc->buf_dma_addr; + rx_status = mvpp2_rxdesc_status_get(port, rx_desc); + rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); + rx_bytes -= MVPP2_MH_SIZE; + dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); - bm = mvpp2_bm_cookie_build(rx_desc); + bm = mvpp2_bm_cookie_build(port, rx_desc); pool = mvpp2_bm_cookie_pool_get(bm); bm_pool = &port->priv->bm_pools[pool]; @@ -3889,8 +3955,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) if (rx_status & MVPP2_RXD_ERR_SUMMARY) { mvpp2_rx_error(port, rx_desc); /* Return the buffer to the pool */ - mvpp2_pool_refill(port, bm, rx_desc->buf_dma_addr, - rx_desc->buf_cookie); + mvpp2_pool_refill(port, bm, dma_addr, dma_addr); return 0; } @@ -3947,13 +4012,16 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length) /* Get a descriptor for the first part of the packet */ tx_desc = mvpp2_txq_next_desc_get(aggr_txq); - tx_desc->phys_txq = txq->id; - tx_desc->data_size = length; - tx_desc->packet_offset = (unsigned long)packet & MVPP2_TX_DESC_ALIGN; - tx_desc->buf_dma_addr = (unsigned long)packet & ~MVPP2_TX_DESC_ALIGN; + mvpp2_txdesc_txq_set(port, tx_desc, txq->id); + mvpp2_txdesc_size_set(port, tx_desc, length); + mvpp2_txdesc_offset_set(port, tx_desc, + (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN); + mvpp2_txdesc_dma_addr_set(port, tx_desc, + (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN); /* First and Last descriptor */ - tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE - | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; + mvpp2_txdesc_cmd_set(port, tx_desc, + MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE + | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC); /* Flush tx data */ flush_dcache_range((unsigned long)packet, -- cgit v0.10.2 From 16a9898d80d3a3975034126aef8b38611a8ddf3b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 14:08:59 +0100 Subject: net: mvpp2: add hw_version field in "struct mvpp2" In preparation to the introduction for the support of PPv2.2 in the mvpp2 driver, this commit adds a hw_version field to the struct mvpp2, and uses the .data field of the DT match table to fill it in. Having the MVPP21 and MVPP22 definitions available will allow to start adding the necessary conditional code to support PPv2.2. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index d199eaf..9683439 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -707,6 +707,9 @@ struct mvpp2 { /* Tclk value */ u32 tclk; + /* HW version */ + enum { MVPP21, MVPP22 } hw_version; + struct mii_dev *bus; }; @@ -4132,6 +4135,9 @@ static int mvpp2_base_probe(struct udevice *dev) u32 size = 0; int i; + /* Save hw-version */ + priv->hw_version = dev_get_driver_data(dev); + /* * U-Boot special buffer handling: * @@ -4234,7 +4240,10 @@ static int mvpp2_base_bind(struct udevice *parent) } static const struct udevice_id mvpp2_ids[] = { - { .compatible = "marvell,armada-375-pp2" }, + { + .compatible = "marvell,armada-375-pp2", + .data = MVPP21, + }, { } }; -- cgit v0.10.2 From 9a6db0bb064cf513a8f523fd0a51265e8bd907bf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 15 Feb 2017 16:25:53 +0100 Subject: net: mvpp2: introduce an intermediate union for the TX/RX descriptors Since the format of the HW descriptors is different between PPv2.1 and PPv2.2, this commit introduces an intermediate union, with for now only the PPv2.1 descriptors. The bulk of the driver code only manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the descriptors can only be accessed and modified through the accessor functions. A follow-up commit will add the descriptor definitions for PPv2.2. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 9683439..f063b04 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -797,7 +797,8 @@ struct mvpp2_port { #define MVPP2_RXD_L3_IP6 BIT(30) #define MVPP2_RXD_BUF_HDR BIT(31) -struct mvpp2_tx_desc { +/* HW TX descriptor for PPv2.1 */ +struct mvpp21_tx_desc { u32 command; /* Options used by HW for packet transmitting.*/ u8 packet_offset; /* the offset from the buffer beginning */ u8 phys_txq; /* destination queue ID */ @@ -808,7 +809,8 @@ struct mvpp2_tx_desc { u32 reserved2; /* reserved (for future use) */ }; -struct mvpp2_rx_desc { +/* HW RX descriptor for PPv2.1 */ +struct mvpp21_rx_desc { u32 status; /* info about received packet */ u16 reserved1; /* parser_info (for future use, PnC) */ u16 data_size; /* size of received packet in bytes */ @@ -823,6 +825,21 @@ struct mvpp2_rx_desc { u32 reserved8; }; +/* Opaque type used by the driver to manipulate the HW TX and RX + * descriptors + */ +struct mvpp2_tx_desc { + union { + struct mvpp21_tx_desc pp21; + }; +}; + +struct mvpp2_rx_desc { + union { + struct mvpp21_rx_desc pp21; + }; +}; + /* Per-CPU Tx queue control */ struct mvpp2_txq_pcpu { int cpu; @@ -1023,59 +1040,59 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, dma_addr_t dma_addr) { - tx_desc->buf_dma_addr = dma_addr; + tx_desc->pp21.buf_dma_addr = dma_addr; } static void mvpp2_txdesc_size_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, size_t size) { - tx_desc->data_size = size; + tx_desc->pp21.data_size = size; } static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, unsigned int txq) { - tx_desc->phys_txq = txq; + tx_desc->pp21.phys_txq = txq; } static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, unsigned int command) { - tx_desc->command = command; + tx_desc->pp21.command = command; } static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, unsigned int offset) { - tx_desc->packet_offset = offset; + tx_desc->pp21.packet_offset = offset; } static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->buf_dma_addr; + return rx_desc->pp21.buf_dma_addr; } static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->buf_cookie; + return rx_desc->pp21.buf_cookie; } static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->data_size; + return rx_desc->pp21.data_size; } static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->status; + return rx_desc->pp21.status; } static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) -- cgit v0.10.2 From f50a0118d12e362f84ec10240c9e00048779adc5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 11:08:46 +0100 Subject: net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors This commit adds the definition of the PPv2.2 HW descriptors, adjusts the mvpp2_tx_desc and mvpp2_rx_desc structures accordingly, and adapts the accessors to work on both PPv2.1 and PPv2.2. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index f063b04..605c8bc 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -825,18 +825,42 @@ struct mvpp21_rx_desc { u32 reserved8; }; +/* HW TX descriptor for PPv2.2 */ +struct mvpp22_tx_desc { + u32 command; + u8 packet_offset; + u8 phys_txq; + u16 data_size; + u64 reserved1; + u64 buf_dma_addr_ptp; + u64 buf_cookie_misc; +}; + +/* HW RX descriptor for PPv2.2 */ +struct mvpp22_rx_desc { + u32 status; + u16 reserved1; + u16 data_size; + u32 reserved2; + u32 reserved3; + u64 buf_dma_addr_key_hash; + u64 buf_cookie_misc; +}; + /* Opaque type used by the driver to manipulate the HW TX and RX * descriptors */ struct mvpp2_tx_desc { union { struct mvpp21_tx_desc pp21; + struct mvpp22_tx_desc pp22; }; }; struct mvpp2_rx_desc { union { struct mvpp21_rx_desc pp21; + struct mvpp22_rx_desc pp22; }; }; @@ -1040,59 +1064,90 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, dma_addr_t dma_addr) { - tx_desc->pp21.buf_dma_addr = dma_addr; + if (port->priv->hw_version == MVPP21) { + tx_desc->pp21.buf_dma_addr = dma_addr; + } else { + u64 val = (u64)dma_addr; + + tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); + tx_desc->pp22.buf_dma_addr_ptp |= val; + } } static void mvpp2_txdesc_size_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, size_t size) { - tx_desc->pp21.data_size = size; + if (port->priv->hw_version == MVPP21) + tx_desc->pp21.data_size = size; + else + tx_desc->pp22.data_size = size; } static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, unsigned int txq) { - tx_desc->pp21.phys_txq = txq; + if (port->priv->hw_version == MVPP21) + tx_desc->pp21.phys_txq = txq; + else + tx_desc->pp22.phys_txq = txq; } static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, unsigned int command) { - tx_desc->pp21.command = command; + if (port->priv->hw_version == MVPP21) + tx_desc->pp21.command = command; + else + tx_desc->pp22.command = command; } static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, unsigned int offset) { - tx_desc->pp21.packet_offset = offset; + if (port->priv->hw_version == MVPP21) + tx_desc->pp21.packet_offset = offset; + else + tx_desc->pp22.packet_offset = offset; } static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->pp21.buf_dma_addr; + if (port->priv->hw_version == MVPP21) + return rx_desc->pp21.buf_dma_addr; + else + return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); } static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->pp21.buf_cookie; + if (port->priv->hw_version == MVPP21) + return rx_desc->pp21.buf_cookie; + else + return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); } static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->pp21.data_size; + if (port->priv->hw_version == MVPP21) + return rx_desc->pp21.data_size; + else + return rx_desc->pp22.data_size; } static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc) { - return rx_desc->pp21.status; + if (port->priv->hw_version == MVPP21) + return rx_desc->pp21.status; + else + return rx_desc->pp22.status; } static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) -- cgit v0.10.2 From c8feeb2b93a2b320d2a533e0443f95c61e157293 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 11:29:16 +0100 Subject: net: mvpp2: adjust the allocation/free of BM pools for PPv2.2 This commit adjusts the allocation and freeing of BM pools to support PPv2.2. This involves: - Checking that the number of buffer pointers is a multiple of 16, as required by the hardware. - Adjusting the size of the DMA coherent area allocated for buffer pointers. Indeed, PPv2.2 needs space for 2 pointers of 64-bits per buffer, as opposed to 2 pointers of 32-bits per buffer in PPv2.1. The size in bytes is now stored in a new field of the mvpp2_bm_pool structure. - On PPv2.2, getting the physical and virtual address of each buffer requires reading the MVPP2_BM_ADDR_HIGH_ALLOC to get the high order bits of those addresses. A new utility function mvpp2_bm_bufs_get_addrs() is introduced to handle this. - On PPv2.2, releasing a buffer requires writing the high order 32 bits of the physical address to MVPP2_BM_PHY_VIRT_HIGH_RLS_REG. We no longer need to write the virtual address to MVPP2_BM_VIRT_RLS_REG. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 605c8bc..4f4e674 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -251,14 +251,23 @@ do { \ #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 +#define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444 +#define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff +#define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00 +#define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) #define MVPP2_BM_VIRT_RLS_REG 0x64c0 -#define MVPP2_BM_MC_RLS_REG 0x64c4 +#define MVPP21_BM_MC_RLS_REG 0x64c4 #define MVPP2_BM_MC_ID_MASK 0xfff #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12) +#define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 +#define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff +#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 +#define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 +#define MVPP22_BM_MC_RLS_REG 0x64d4 /* TX Scheduler registers */ #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 @@ -2332,6 +2341,12 @@ static int mvpp2_bm_pool_create(struct udevice *dev, { u32 val; + /* Number of buffer pointers must be a multiple of 16, as per + * hardware constraints + */ + if (!IS_ALIGNED(size, 16)) + return -EINVAL; + bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id]; bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id]; if (!bm_pool->virt_addr) @@ -2345,7 +2360,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev, } mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), - bm_pool->dma_addr); + lower_32_bits(bm_pool->dma_addr)); mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); @@ -2488,6 +2503,21 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, dma_addr_t buf_dma_addr, unsigned long buf_phys_addr) { + if (port->priv->hw_version == MVPP22) { + u32 val = 0; + + if (sizeof(dma_addr_t) == 8) + val |= upper_32_bits(buf_dma_addr) & + MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; + + if (sizeof(phys_addr_t) == 8) + val |= (upper_32_bits(buf_phys_addr) + << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & + MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; + + mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val); + } + /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply * returned in the "cookie" field of the RX * descriptor. Instead of storing the virtual address, we @@ -4237,7 +4267,10 @@ static int mvpp2_base_probe(struct udevice *dev) for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { buffer_loc.bm_pool[i] = (unsigned long *)((unsigned long)bd_space + size); - size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32); + if (priv->hw_version == MVPP21) + size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32); + else + size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64); } for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { -- cgit v0.10.2 From 8f3e4c38005d88f04b24b27c6eda362d7ef1a6d5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Feb 2017 06:53:51 +0100 Subject: net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2 The MVPP2_RXQ_CONFIG_REG register has a slightly different layout between PPv2.1 and PPv2.2, so this commit adapts the functions modifying this register to accommodate for both the PPv2.1 and PPv2.2 cases. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 4f4e674..e5b42b9 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -91,9 +91,11 @@ do { \ #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) #define MVPP2_RXQ_POOL_SHORT_OFFS 20 -#define MVPP2_RXQ_POOL_SHORT_MASK 0x700000 +#define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 +#define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 #define MVPP2_RXQ_POOL_LONG_OFFS 24 -#define MVPP2_RXQ_POOL_LONG_MASK 0x7000000 +#define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 +#define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 #define MVPP2_RXQ_DISABLE_MASK BIT(31) @@ -2467,17 +2469,20 @@ static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv) static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, int lrxq, int long_pool) { - u32 val; + u32 val, mask; int prxq; /* Get queue physical ID */ prxq = port->rxqs[lrxq]->id; - val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); - val &= ~MVPP2_RXQ_POOL_LONG_MASK; - val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & - MVPP2_RXQ_POOL_LONG_MASK); + if (port->priv->hw_version == MVPP21) + mask = MVPP21_RXQ_POOL_LONG_MASK; + else + mask = MVPP22_RXQ_POOL_LONG_MASK; + val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); + val &= ~mask; + val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); } -- cgit v0.10.2 From b8c8e6ffac5bc5ce01b562b4506650e6629815b6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Feb 2017 06:57:24 +0100 Subject: net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2 This commit modifies the mvpp2_defaults_set() function to not do the loopback and FIFO threshold initialization, which are not needed for PPv2.2. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index e5b42b9..e75979b 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2755,16 +2755,18 @@ static void mvpp2_defaults_set(struct mvpp2_port *port) { int tx_port_num, val, queue, ptxq, lrxq; - /* Configure port to loopback if needed */ - if (port->flags & MVPP2_F_LOOPBACK) - mvpp2_port_loopback_set(port); - - /* Update TX FIFO MIN Threshold */ - val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); - val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; - /* Min. TX threshold must be less than minimal packet length */ - val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); - writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + if (port->priv->hw_version == MVPP21) { + /* Configure port to loopback if needed */ + if (port->flags & MVPP2_F_LOOPBACK) + mvpp2_port_loopback_set(port); + + /* Update TX FIFO MIN Threshold */ + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + /* Min. TX threshold must be less than minimal packet length */ + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + } /* Disable Legacy WRR, Disable EJP, Release from reset */ tx_port_num = mvpp2_egress_port(port); -- cgit v0.10.2 From 80350f55cf3ab7e7d82833219d37380abf78d173 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 11:36:57 +0100 Subject: net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2 In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG registers have a slightly different layout, because they need to contain a 64-bit address for the RX and TX descriptor arrays. This commit adjusts those functions accordingly. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index e75979b..5e888e7 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -143,6 +143,7 @@ do { \ /* Descriptor Manager Top Registers */ #define MVPP2_RXQ_NUM_REG 0x2040 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 +#define MVPP22_DESC_ADDR_OFFS 8 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) @@ -184,6 +185,7 @@ do { \ #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) +#define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) @@ -3107,6 +3109,8 @@ static int mvpp2_aggr_txq_init(struct udevice *dev, int desc_num, int cpu, struct mvpp2 *priv) { + u32 txq_dma; + /* Allocate memory for TX descriptors */ aggr_txq->descs = buffer_loc.aggr_tx_descs; aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs; @@ -3123,10 +3127,16 @@ static int mvpp2_aggr_txq_init(struct udevice *dev, aggr_txq->next_desc_to_proc = mvpp2_read(priv, MVPP2_AGGR_TXQ_INDEX_REG(cpu)); - /* Set Tx descriptors queue starting address */ - /* indirect access */ - mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), - aggr_txq->descs_dma); + /* Set Tx descriptors queue starting address indirect + * access + */ + if (priv->hw_version == MVPP21) + txq_dma = aggr_txq->descs_dma; + else + txq_dma = aggr_txq->descs_dma >> + MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; + + mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num); return 0; @@ -3137,6 +3147,8 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq) { + u32 rxq_dma; + rxq->size = port->rx_ring_size; /* Allocate memory for RX descriptors */ @@ -3155,7 +3167,11 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, /* Set Rx descriptors queue starting address - indirect access */ mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); - mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma); + if (port->priv->hw_version == MVPP21) + rxq_dma = rxq->descs_dma; + else + rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; + mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); -- cgit v0.10.2 From 26a5278c9e6f0aa477f14dc38ccbf8dc30fe9cb3 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Feb 2017 08:03:37 +0100 Subject: net: mvpp2: handle register mapping and access for PPv2.2 This commit adjusts the mvpp2 driver register mapping and access logic to support PPv2.2, to handle a number of differences. Due to how the registers are laid out in memory, the Device Tree binding for the "reg" property is different: - On PPv2.1, we had a first area for the common registers, and then one area per port. - On PPv2.2, we have a first area for the common registers, and a second area for all the per-ports registers. In addition, on PPv2.2, the area for the common registers is split into so-called "address spaces" of 64 KB each. They allow to access the same registers, but from different CPUs. Hence the introduction of cpu_base[] in 'struct mvpp2', and the modification of the mvpp2_write() and mvpp2_read() register accessors. For PPv2.1, the compatibility is preserved by using an "address space" size of 0. Changed by Stefan for U-Boot: Since we don't support multiple CPUs in U-Boot, I've removed all the code, macros and variables introduced in the Linux patch version for this. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 5e888e7..645a818 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -342,6 +342,9 @@ do { \ #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) +#define MVPP22_PORT_BASE 0x30e00 +#define MVPP22_PORT_OFFSET 0x1000 + #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff /* Descriptor ring Macros */ @@ -702,6 +705,7 @@ struct mvpp2 { /* Shared registers' base addresses */ void __iomem *base; void __iomem *lms_base; + void __iomem *iface_base; /* List of pointers to port structures */ struct mvpp2_port **port_list; @@ -736,6 +740,11 @@ struct mvpp2_pcpu_stats { struct mvpp2_port { u8 id; + /* Index of the port from the "group of ports" complex point + * of view + */ + int gop_id; + int irq; struct mvpp2 *priv; @@ -3270,7 +3279,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port, mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | - MVPP2_PREF_BUF_THRESH(desc_per_txq/2)); + MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); /* WRR / EJP configuration - indirect access */ tx_port_num = mvpp2_egress_port(port); @@ -3779,11 +3788,24 @@ static int mvpp2_port_probe(struct udevice *dev, port->phy_interface = phy_mode; port->phyaddr = phyaddr; - port->base = (void __iomem *)dev_get_addr_index(dev->parent, - priv_common_regs_num - + id); - if (IS_ERR(port->base)) - return PTR_ERR(port->base); + if (priv->hw_version == MVPP21) { + port->base = (void __iomem *)dev_get_addr_index( + dev->parent, priv_common_regs_num + id); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + } else { + u32 gop_id; + + gop_id = fdtdec_get_int(gd->fdt_blob, port_node, + "gop-port-id", -1); + if (id == -1) { + dev_err(&pdev->dev, "missing gop-port-id value\n"); + return -EINVAL; + } + + port->base = priv->iface_base + MVPP22_PORT_BASE + + gop_id * MVPP22_PORT_OFFSET; + } port->tx_ring_size = MVPP2_MAX_TXD; port->rx_ring_size = MVPP2_MAX_RXD; @@ -4307,9 +4329,15 @@ static int mvpp2_base_probe(struct udevice *dev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - priv->lms_base = (void *)dev_get_addr_index(dev, 1); - if (IS_ERR(priv->lms_base)) - return PTR_ERR(priv->lms_base); + if (priv->hw_version == MVPP21) { + priv->lms_base = (void *)dev_get_addr_index(dev, 1); + if (IS_ERR(priv->lms_base)) + return PTR_ERR(priv->lms_base); + } else { + priv->iface_base = (void *)dev_get_addr_index(dev, 1); + if (IS_ERR(priv->iface_base)) + return PTR_ERR(priv->iface_base); + } /* Finally create and register the MDIO bus driver */ bus = mdio_alloc(); -- cgit v0.10.2 From 7c7311f1a28ec05caf4b6a5df9d817e502e793dd Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 11:42:51 +0100 Subject: net: mvpp2: handle misc PPv2.1/PPv2.2 differences This commit handles a few miscellaneous differences between PPv2.1 and PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY polling, etc.). Changed by Stefan for U-Boot: Since mvpp2_port_power_up() has multiple callers in U-Boot, the U-Boot version of this patch does not remove this function but simply adds the check for MVPP21 before the mvpp2_port_fc_adv_enable() call. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 645a818..51922c0 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -342,6 +342,9 @@ do { \ #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) +#define MVPP22_SMI_MISC_CFG_REG 0x1204 +#define MVPP22_SMI_POLLING_EN BIT(10) + #define MVPP22_PORT_BASE 0x30e00 #define MVPP22_PORT_OFFSET 0x1000 @@ -3639,9 +3642,12 @@ static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port) static void mvpp2_port_power_up(struct mvpp2_port *port) { + struct mvpp2 *priv = port->priv; + mvpp2_port_mii_set(port); mvpp2_port_periodic_xon_disable(port); - mvpp2_port_fc_adv_enable(port); + if (priv->hw_version == MVPP21) + mvpp2_port_fc_adv_enable(port); mvpp2_port_reset(port); } @@ -3892,9 +3898,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) mvpp2_conf_mbus_windows(dram_target_info, priv); /* Disable HW PHY polling */ - val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); - val |= MVPP2_PHY_AN_STOP_SMI0_MASK; - writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + if (priv->hw_version == MVPP21) { + val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + val |= MVPP2_PHY_AN_STOP_SMI0_MASK; + writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + } else { + val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); + val &= ~MVPP22_SMI_POLLING_EN; + writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); + } /* Allocate and initialize aggregated TXQs */ priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(), @@ -3920,8 +3932,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), CONFIG_MV_ETH_RXQ); - writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, - priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); + if (priv->hw_version == MVPP21) + writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, + priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); /* Allow cache snoop when transmiting packets */ mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); -- cgit v0.10.2 From cdf77799a36ab72d9c04a5073c681cb0e0839086 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Feb 2017 08:41:07 +0100 Subject: net: mvpp2: add AXI bridge initialization for PPv2.2 The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this commit adds the necessary initialization of the AXI bridge. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 51922c0..b56af82 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -198,6 +198,34 @@ do { \ #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) #define MVPP2_BASE_ADDR_ENABLE 0x4060 +/* AXI Bridge Registers */ +#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 +#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 +#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 +#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 +#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 +#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c +#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 +#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 +#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 +#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 +#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 +#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 + +/* Values for AXI Bridge registers */ +#define MVPP22_AXI_ATTR_CACHE_OFFS 0 +#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 + +#define MVPP22_AXI_CODE_CACHE_OFFS 0 +#define MVPP22_AXI_CODE_DOMAIN_OFFS 4 + +#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 +#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 +#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb + +#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 +#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 + /* Interrupt Cause and Mask registers */ #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq)) @@ -3879,6 +3907,60 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv) mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); } +static void mvpp2_axi_init(struct mvpp2 *priv) +{ + u32 val, rdval, wrval; + + mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); + + /* AXI Bridge Configuration */ + + rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE + << MVPP22_AXI_ATTR_CACHE_OFFS; + rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_ATTR_DOMAIN_OFFS; + + wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE + << MVPP22_AXI_ATTR_CACHE_OFFS; + wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_ATTR_DOMAIN_OFFS; + + /* BM */ + mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); + mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); + + /* Descriptors */ + mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); + mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); + + /* Buffer Data */ + mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); + + val = MVPP22_AXI_CODE_CACHE_NON_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); + mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); + + val = MVPP22_AXI_CODE_CACHE_RD_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + + mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); + + val = MVPP22_AXI_CODE_CACHE_WR_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + + mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); +} + /* Initialize network controller common part HW */ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) { @@ -3897,6 +3979,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) if (dram_target_info) mvpp2_conf_mbus_windows(dram_target_info, priv); + if (priv->hw_version == MVPP22) + mvpp2_axi_init(priv); + /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); -- cgit v0.10.2 From bc0bbf41b10bb377b91b89863684bcb1865e8a4c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Feb 2017 08:46:37 +0100 Subject: net: mvpp2: rework RXQ interrupt group initialization for PPv2.2 This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is configured, since it changed between PPv2.1 and PPv2.2. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index b56af82..16a9c75 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -228,7 +228,21 @@ do { \ /* Interrupt Cause and Mask registers */ #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) -#define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq)) +#define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq)) + +#define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 +#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf +#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 +#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 + +#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf +#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 + +#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 +#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f +#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 +#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 + #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) @@ -3747,7 +3761,19 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) } /* Configure Rx queue group interrupt for this port */ - mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ); + if (priv->hw_version == MVPP21) { + mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), + CONFIG_MV_ETH_RXQ); + } else { + u32 val; + + val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET); + mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); + + val = (CONFIG_MV_ETH_RXQ << + MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET); + mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); + } /* Create Rx descriptor rings */ for (queue = 0; queue < rxq_number; queue++) { @@ -4013,9 +4039,23 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) mvpp2_rx_fifo_init(priv); /* Reset Rx queue group interrupt configuration */ - for (i = 0; i < MVPP2_MAX_PORTS; i++) - mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), - CONFIG_MV_ETH_RXQ); + for (i = 0; i < MVPP2_MAX_PORTS; i++) { + if (priv->hw_version == MVPP21) { + mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i), + CONFIG_MV_ETH_RXQ); + continue; + } else { + u32 val; + + val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET); + mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); + + val = (CONFIG_MV_ETH_RXQ << + MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET); + mvpp2_write(priv, + MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); + } + } if (priv->hw_version == MVPP21) writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, -- cgit v0.10.2 From 09b3f948dc5a74c24da62d09e7d469ba4e71c93d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 16 Feb 2017 09:03:16 +0100 Subject: net: mvpp2: adapt rxq distribution to PPv2.2 In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4 RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7 to the second port, 8->11 to the third port, etc. In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate RXQs from the range of 32 RXQs available for each port. So port 0 must use RXQs in the range 0->31, port 1 in the range 32->63, etc. This commit adapts the mvpp2 to this difference between PPv2.1 and PPv2.2: - The constant definition MVPP2_MAX_RXQ is replaced by a new field 'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of RXQs per port. This field is initialized during ->probe() depending on the IP version. - MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total number of RXQs by multiplying the number of ports by the maximum of RXQs per port. This was anyway used in only one place. - In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted to cope with the different allocation strategy between PPv2.1 and PPv2.2. Due to this change, the 'next_first_rxq' argument of this function is no longer needed and is removed. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 16a9c75..c683fff 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -454,9 +454,6 @@ do { \ /* Maximum number of TXQs used by single port */ #define MVPP2_MAX_TXQ 8 -/* Maximum number of RXQs used by single port */ -#define MVPP2_MAX_RXQ 8 - /* Default number of TXQs in use */ #define MVPP2_DEFAULT_TXQ 1 @@ -464,9 +461,6 @@ do { \ #define MVPP2_DEFAULT_RXQ 1 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */ -/* Total number of RXQs available to all ports */ -#define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ) - /* Max number of Rx descriptors */ #define MVPP2_MAX_RXD 16 @@ -772,6 +766,9 @@ struct mvpp2 { /* HW version */ enum { MVPP21, MVPP22 } hw_version; + /* Maximum number of RXQs per port */ + unsigned int max_port_rxqs; + struct mii_dev *bus; }; @@ -3700,7 +3697,8 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) struct mvpp2_txq_pcpu *txq_pcpu; int queue, cpu, err; - if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM) + if (port->first_rxq + rxq_number > + MVPP2_MAX_PORTS * priv->max_port_rxqs) return -EINVAL; /* Disable port */ @@ -3808,8 +3806,7 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) static int mvpp2_port_probe(struct udevice *dev, struct mvpp2_port *port, int port_node, - struct mvpp2 *priv, - int *next_first_rxq) + struct mvpp2 *priv) { int phy_node; u32 id; @@ -3843,7 +3840,10 @@ static int mvpp2_port_probe(struct udevice *dev, port->priv = priv; port->id = id; - port->first_rxq = *next_first_rxq; + if (priv->hw_version == MVPP21) + port->first_rxq = port->id * rxq_number; + else + port->first_rxq = port->id * priv->max_port_rxqs; port->phy_node = phy_node; port->phy_interface = phy_mode; port->phyaddr = phyaddr; @@ -3877,8 +3877,6 @@ static int mvpp2_port_probe(struct udevice *dev, } mvpp2_port_power_up(port); - /* Increment the first Rx queue number to be used by the next port */ - *next_first_rxq += CONFIG_MV_ETH_RXQ; priv->port_list[id] = port; return 0; } @@ -3995,7 +3993,8 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) u32 val; /* Checks for hardware constraints (U-Boot uses only one rxq) */ - if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) { + if ((rxq_number > priv->max_port_rxqs) || + (txq_number > MVPP2_MAX_TXQ)) { dev_err(&pdev->dev, "invalid queue size parameter\n"); return -EINVAL; } @@ -4388,8 +4387,7 @@ static int mvpp2_probe(struct udevice *dev) return err; } - return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv, - &buffer_loc.first_rxq); + return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); } static const struct eth_ops mvpp2_ops = { @@ -4477,6 +4475,11 @@ static int mvpp2_base_probe(struct udevice *dev) return PTR_ERR(priv->iface_base); } + if (priv->hw_version == MVPP21) + priv->max_port_rxqs = 8; + else + priv->max_port_rxqs = 32; + /* Finally create and register the MDIO bus driver */ bus = mdio_alloc(); if (!bus) { -- cgit v0.10.2 From a83a6418a233349c48fec4a203a7d94333dc06d9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 11:54:31 +0100 Subject: net: mvpp2: finally add the PPv2.2 compatible string Now that the mvpp2 driver has been modified to accommodate the support for PPv2.2, we can finally advertise this support by adding the appropriate compatible string. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index c683fff..16da28d 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4541,6 +4541,10 @@ static const struct udevice_id mvpp2_ids[] = { .compatible = "marvell,armada-375-pp2", .data = MVPP21, }, + { + .compatible = "marvell,armada-7k-pp22", + .data = MVPP22, + }, { } }; -- cgit v0.10.2 From 0a61e9ad1c9455a1ed5c31fad3f4a991271db02e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Feb 2017 08:31:32 +0100 Subject: net: mvpp2: Add MDIO support for PPv2.2 In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver, currently only supporting the 32bit platforms (Armada 37x). This patch now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF can be used as well on these platforms. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 16da28d..8751ee8 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -397,7 +397,9 @@ do { \ (((index) < (q)->last_desc) ? ((index) + 1) : 0) /* SMI: 0xc0054 -> offset 0x54 to lms_base */ -#define MVPP2_SMI 0x0054 +#define MVPP21_SMI 0x0054 +/* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */ +#define MVPP22_SMI 0x1200 #define MVPP2_PHY_REG_MASK 0x1f /* SMI register fields */ #define MVPP2_SMI_DATA_OFFS 0 /* Data */ @@ -745,6 +747,7 @@ struct mvpp2 { void __iomem *base; void __iomem *lms_base; void __iomem *iface_base; + void __iomem *mdio_base; /* List of pointers to port structures */ struct mvpp2_port **port_list; @@ -4089,7 +4092,7 @@ static int smi_wait_ready(struct mvpp2 *priv) /* wait till the SMI is not busy */ do { /* read smi register */ - smi_reg = readl(priv->lms_base + MVPP2_SMI); + smi_reg = readl(priv->mdio_base); if (timeout-- == 0) { printf("Error: SMI busy timeout\n"); return -EFAULT; @@ -4131,14 +4134,14 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) | MVPP2_SMI_OPCODE_READ; /* write the smi register */ - writel(smi_reg, priv->lms_base + MVPP2_SMI); + writel(smi_reg, priv->mdio_base); /* wait till read value is ready */ timeout = MVPP2_SMI_TIMEOUT; do { /* read smi register */ - smi_reg = readl(priv->lms_base + MVPP2_SMI); + smi_reg = readl(priv->mdio_base); if (timeout-- == 0) { printf("Err: SMI read ready timeout\n"); return -EFAULT; @@ -4149,7 +4152,7 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++) ; - return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK; + return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK; } /* @@ -4186,7 +4189,7 @@ static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, smi_reg &= ~MVPP2_SMI_OPCODE_READ; /* write the smi register */ - writel(smi_reg, priv->lms_base + MVPP2_SMI); + writel(smi_reg, priv->mdio_base); return 0; } @@ -4469,10 +4472,14 @@ static int mvpp2_base_probe(struct udevice *dev) priv->lms_base = (void *)dev_get_addr_index(dev, 1); if (IS_ERR(priv->lms_base)) return PTR_ERR(priv->lms_base); + + priv->mdio_base = priv->lms_base + MVPP21_SMI; } else { priv->iface_base = (void *)dev_get_addr_index(dev, 1); if (IS_ERR(priv->iface_base)) return PTR_ERR(priv->iface_base); + + priv->mdio_base = priv->iface_base + MVPP22_SMI; } if (priv->hw_version == MVPP21) -- cgit v0.10.2 From 1fabbd074e8fb0315901c2e0ba04ca2519a5bb6f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Feb 2017 15:26:06 +0100 Subject: net: mvpp2: Move probe function from MISC to ETH DM driver This patch moves the base_probe function mvpp2_base_probe() from the MISC driver to the ETH driver. When integrated in the MISC driver, probe is called too early before the U-Boot ethernet infrastructure (especially the MDIO / PHY interface) has been initialized. Resulting in errors in mdio_register(). Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 8751ee8..06909e6 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -773,6 +773,8 @@ struct mvpp2 { unsigned int max_port_rxqs; struct mii_dev *bus; + + int probe_done; }; struct mvpp2_pcpu_stats { @@ -4377,42 +4379,6 @@ static void mvpp2_stop(struct udevice *dev) mvpp2_cleanup_txqs(port); } -static int mvpp2_probe(struct udevice *dev) -{ - struct mvpp2_port *port = dev_get_priv(dev); - struct mvpp2 *priv = dev_get_priv(dev->parent); - int err; - - /* Initialize network controller */ - err = mvpp2_init(dev, priv); - if (err < 0) { - dev_err(&pdev->dev, "failed to initialize controller\n"); - return err; - } - - return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); -} - -static const struct eth_ops mvpp2_ops = { - .start = mvpp2_start, - .send = mvpp2_send, - .recv = mvpp2_recv, - .stop = mvpp2_stop, -}; - -static struct driver mvpp2_driver = { - .name = "mvpp2", - .id = UCLASS_ETH, - .probe = mvpp2_probe, - .ops = &mvpp2_ops, - .priv_auto_alloc_size = sizeof(struct mvpp2_port), - .platdata_auto_alloc_size = sizeof(struct eth_pdata), -}; - -/* - * Use a MISC device to bind the n instances (child nodes) of the - * network base controller in UCLASS_ETH. - */ static int mvpp2_base_probe(struct udevice *dev) { struct mvpp2 *priv = dev_get_priv(dev); @@ -4503,6 +4469,47 @@ static int mvpp2_base_probe(struct udevice *dev) return mdio_register(bus); } +static int mvpp2_probe(struct udevice *dev) +{ + struct mvpp2_port *port = dev_get_priv(dev); + struct mvpp2 *priv = dev_get_priv(dev->parent); + int err; + + /* Only call the probe function for the parent once */ + if (!priv->probe_done) { + err = mvpp2_base_probe(dev->parent); + priv->probe_done = 1; + } + /* Initialize network controller */ + err = mvpp2_init(dev, priv); + if (err < 0) { + dev_err(&pdev->dev, "failed to initialize controller\n"); + return err; + } + + return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); +} + +static const struct eth_ops mvpp2_ops = { + .start = mvpp2_start, + .send = mvpp2_send, + .recv = mvpp2_recv, + .stop = mvpp2_stop, +}; + +static struct driver mvpp2_driver = { + .name = "mvpp2", + .id = UCLASS_ETH, + .probe = mvpp2_probe, + .ops = &mvpp2_ops, + .priv_auto_alloc_size = sizeof(struct mvpp2_port), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +/* + * Use a MISC device to bind the n instances (child nodes) of the + * network base controller in UCLASS_ETH. + */ static int mvpp2_base_bind(struct udevice *parent) { const void *blob = gd->fdt_blob; @@ -4560,6 +4567,5 @@ U_BOOT_DRIVER(mvpp2_base) = { .id = UCLASS_MISC, .of_match = mvpp2_ids, .bind = mvpp2_base_bind, - .probe = mvpp2_base_probe, .priv_auto_alloc_size = sizeof(struct mvpp2), }; -- cgit v0.10.2 From 30edc374ea230d73a92d4dc250bfd0cf60ce81c9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Feb 2017 13:29:08 +0100 Subject: net: mvpp2.c: Clear all buffer / descriptor areas before usage This fixes problems noticed with the PPv2.2 A7k/8k port, when not all elements of the descriptors had been cleared before use. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 06909e6..b9e0fdc 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4429,6 +4429,9 @@ static int mvpp2_base_probe(struct udevice *dev) size += RX_BUFFER_SIZE; } + /* Clear the complete area so that all descriptors are cleared */ + memset(bd_space, 0, size); + /* Save base addresses for later use */ priv->base = (void *)dev_get_addr_index(dev, 0); if (IS_ERR(priv->base)) -- cgit v0.10.2 From e7935c47706755b8bc7b74db30203fbcd49331e5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 15 Feb 2017 11:42:59 +0100 Subject: net: mvpp2: Enable compilation for Armada 7K/8K platforms Since Armada 7K/8K is also equipped with a newer version of the MVPP2 ethernet controller, lets enable compilation of this driver for these platforms. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 70e3661..8aa9279 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -124,12 +124,12 @@ config FEC_MXC NXP i.MX processors. config MVPP2 - bool "Marvell Armada 375 network interface support" - depends on ARMADA_375 + bool "Marvell Armada 375/7K/8K network interface support" + depends on ARMADA_375 || ARMADA_8K select PHYLIB help This driver supports the network interface units in the - Marvell ARMADA 375 SoC. + Marvell ARMADA 375, 7K and 8K SoCs. config MACB bool "Cadence MACB/GEM Ethernet Interface" -- cgit v0.10.2 From a6555ebe1bd8bde87c7baccd83ce127bb1a6f098 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 20 Feb 2017 12:27:25 +0100 Subject: arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K This commit adds the description of the PPv2.2 hardware block for the Marvell Armada 7K and Armada 8K processors, and their corresponding Armada 7040 and 8040 Development boards. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 63442df..776bc78 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -209,3 +209,28 @@ no-1-8-v; non-removable; }; + +&cpm_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpm_ethernet { + status = "okay"; +}; + +&cpm_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; +}; + +&cpm_eth2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; +}; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 40def9d..f1f196f 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -283,3 +283,19 @@ &cps_utmi0 { status = "okay"; }; + +&cpm_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpm_ethernet { + status = "okay"; +}; + +&cpm_eth2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; +}; diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 1f0edde..229046f 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -61,6 +61,43 @@ interrupt-parent = <&gic>; ranges = <0x0 0x0 0xf2000000 0x2000000>; + cpm_ethernet: ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; + clock-names = "pp_clk", "gop_clk", "mg_clk"; + status = "disabled"; + dma-coherent; + + cpm_eth0: eth0 { + interrupts = ; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + cpm_eth1: eth1 { + interrupts = ; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + cpm_eth2: eth2 { + interrupts = ; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; + }; + }; + + cpm_mdio: mdio@12a200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x12a200 0x10>; + }; + cpm_syscon0: system-controller@440000 { compatible = "marvell,cp110-system-controller0", "syscon"; diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index ff3fbed..5876391 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -61,6 +61,43 @@ interrupt-parent = <&gic>; ranges = <0x0 0x0 0xf4000000 0x2000000>; + cps_ethernet: ethernet@0 { + compatible = "marvell,armada-7k-pp22"; + reg = <0x0 0x100000>, <0x129000 0xb000>; + clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; + clock-names = "pp_clk", "gop_clk", "mg_clk"; + status = "disabled"; + dma-coherent; + + cps_eth0: eth0 { + interrupts = ; + port-id = <0>; + gop-port-id = <0>; + status = "disabled"; + }; + + cps_eth1: eth1 { + interrupts = ; + port-id = <1>; + gop-port-id = <2>; + status = "disabled"; + }; + + cps_eth2: eth2 { + interrupts = ; + port-id = <2>; + gop-port-id = <3>; + status = "disabled"; + }; + }; + + cps_mdio: mdio@12a200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x12a200 0x10>; + }; + cps_syscon0: system-controller@440000 { compatible = "marvell,cp110-system-controller0", "syscon"; -- cgit v0.10.2 From def844299cfbe65a625ace8d724e92063f3fce9f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Feb 2017 12:25:26 +0100 Subject: arm64: mvebu: armada-7k/8k: Enable MVPP2 ethernet driver Since we've now integrated the A7k/8k support in the mvpp2 ethernet driver, lets enable the support for both Marvell developments boards. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig index f20158a..fdafeb6 100644 --- a/configs/mvebu_db-88f7040_defconfig +++ b/configs/mvebu_db-88f7040_defconfig @@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y +CONFIG_MVPP2=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_DW_MVEBU=y diff --git a/configs/mvebu_db-88f8040_defconfig b/configs/mvebu_db-88f8040_defconfig index 3611b84..9866e19 100644 --- a/configs/mvebu_db-88f8040_defconfig +++ b/configs/mvebu_db-88f8040_defconfig @@ -47,7 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y +CONFIG_MVPP2=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_DW_MVEBU=y diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index a8a9d15..8ee5f27 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -81,6 +81,14 @@ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ +/* + * Ethernet Driver configuration + */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 + /* USB 2.0 */ #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -- cgit v0.10.2 From c9607c932585e6757ad1c378751030c2a4234227 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 24 Feb 2017 10:12:41 +0100 Subject: net: mvpp2: Handle eth device naming in multi-CP case correctly Currently, the naming of the ethernet ports is not handled correctly in the multi-CP (Communication Processor) case. On Armada 8k, the slave-CP also instantiates an ethernet controller with the same device ID's. This patch now takes this into account and adds the required base-id so that the slave-CP ethernet devices will be named "mvpp2-3 ...". This patch also updates my Copyright notice to include 2017 as well. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index b9e0fdc..2328c25 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -6,7 +6,7 @@ * Marcin Wojtas * * U-Boot version: - * Copyright (C) 2016 Stefan Roese + * Copyright (C) 2016-2017 Stefan Roese * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -1090,6 +1090,8 @@ static int rxq_number = MVPP2_DEFAULT_RXQ; /* Number of TXQs used by single port */ static int txq_number = MVPP2_DEFAULT_TXQ; +static int base_id; + #define MVPP2_DRIVER_NAME "mvpp2" #define MVPP2_DRIVER_VERSION "1.0" @@ -4523,6 +4525,7 @@ static int mvpp2_base_bind(struct udevice *parent) char *name; int subnode; u32 id; + int base_id_add; /* Lookup eth driver */ drv = lists_uclass_lookup(UCLASS_ETH); @@ -4531,7 +4534,12 @@ static int mvpp2_base_bind(struct udevice *parent) return -ENOENT; } + base_id_add = base_id; + fdt_for_each_subnode(subnode, blob, node) { + /* Increment base_id for all subnodes, also the disabled ones */ + base_id++; + /* Skip disabled ports */ if (!fdtdec_get_is_enabled(blob, subnode)) continue; @@ -4541,6 +4549,7 @@ static int mvpp2_base_bind(struct udevice *parent) return -ENOMEM; id = fdtdec_get_int(blob, subnode, "port-id", -1); + id += base_id_add; name = calloc(1, 16); sprintf(name, "mvpp2-%d", id); -- cgit v0.10.2 From ff572c6d530387868ad7c03158a322ecfd9a7768 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 1 Mar 2017 13:09:42 +0100 Subject: net: mvpp2: Add RX and TX FIFO configuration for PPv2.2 This patch adds the PPv2.2 specific FIFO configuration to the mvpp2 driver. The RX FIFO packet data size is changed to the recommended FIFO sizes. The TX FIFO configuration is newly added. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 2328c25..d0f20cc 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -482,9 +482,23 @@ do { \ #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) /* RX FIFO constants */ -#define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000 -#define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80 -#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 +#define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000 +#define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80 +#define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000 +#define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000 +#define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000 +#define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200 +#define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80 +#define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40 +#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 + +/* TX general registers */ +#define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) +#define MVPP22_TX_FIFO_SIZE_MASK 0xf + +/* TX FIFO constants */ +#define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa +#define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ @@ -3927,10 +3941,35 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv) int port; for (port = 0; port < MVPP2_MAX_PORTS; port++) { - mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), - MVPP2_RX_FIFO_PORT_DATA_SIZE); - mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), - MVPP2_RX_FIFO_PORT_ATTR_SIZE); + if (priv->hw_version == MVPP22) { + if (port == 0) { + mvpp2_write(priv, + MVPP2_RX_DATA_FIFO_SIZE_REG(port), + MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE); + mvpp2_write(priv, + MVPP2_RX_ATTR_FIFO_SIZE_REG(port), + MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE); + } else if (port == 1) { + mvpp2_write(priv, + MVPP2_RX_DATA_FIFO_SIZE_REG(port), + MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE); + mvpp2_write(priv, + MVPP2_RX_ATTR_FIFO_SIZE_REG(port), + MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE); + } else { + mvpp2_write(priv, + MVPP2_RX_DATA_FIFO_SIZE_REG(port), + MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE); + mvpp2_write(priv, + MVPP2_RX_ATTR_FIFO_SIZE_REG(port), + MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE); + } + } else { + mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), + MVPP21_RX_FIFO_PORT_DATA_SIZE); + mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), + MVPP21_RX_FIFO_PORT_ATTR_SIZE); + } } mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, @@ -3938,6 +3977,24 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv) mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); } +/* Initialize Tx FIFO's */ +static void mvpp2_tx_fifo_init(struct mvpp2 *priv) +{ + int port, val; + + for (port = 0; port < MVPP2_MAX_PORTS; port++) { + /* Port 0 supports 10KB TX FIFO */ + if (port == 0) { + val = MVPP2_TX_FIFO_DATA_SIZE_10KB & + MVPP22_TX_FIFO_SIZE_MASK; + } else { + val = MVPP2_TX_FIFO_DATA_SIZE_3KB & + MVPP22_TX_FIFO_SIZE_MASK; + } + mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); + } +} + static void mvpp2_axi_init(struct mvpp2 *priv) { u32 val, rdval, wrval; @@ -4044,6 +4101,10 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) /* Rx Fifo Init */ mvpp2_rx_fifo_init(priv); + /* Tx Fifo Init */ + if (priv->hw_version == MVPP22) + mvpp2_tx_fifo_init(priv); + /* Reset Rx queue group interrupt configuration */ for (i = 0; i < MVPP2_MAX_PORTS; i++) { if (priv->hw_version == MVPP21) { -- cgit v0.10.2 From d11e9347461cff9ce89e6e65764f73fad0f19c6f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 23 Feb 2017 11:58:26 +0100 Subject: net: include/phy.h: Add new PHY interface modes This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/include/phy.h b/include/phy.h index 5477496..8e507cd 100644 --- a/include/phy.h +++ b/include/phy.h @@ -61,6 +61,9 @@ typedef enum { PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_XAUI, + PHY_INTERFACE_MODE_RXAUI, + PHY_INTERFACE_MODE_SFI, PHY_INTERFACE_MODE_NONE, /* Must be last */ PHY_INTERFACE_MODE_COUNT, @@ -80,6 +83,9 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", [PHY_INTERFACE_MODE_RTBI] = "rtbi", [PHY_INTERFACE_MODE_XGMII] = "xgmii", + [PHY_INTERFACE_MODE_XAUI] = "xaui", + [PHY_INTERFACE_MODE_RXAUI] = "rxaui", + [PHY_INTERFACE_MODE_SFI] = "sfi", [PHY_INTERFACE_MODE_NONE] = "", }; -- cgit v0.10.2 From 66b11ccbb616910c593a18ba7232e30c3b13ee43 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 22 Mar 2017 14:11:16 +0100 Subject: net: mvpp2: Restructure probe / init functions This patch does a bit of restructuring of the probe / init functions, mainly to allow earlier register access as it is needed for the upcoming GoP (Group of Ports) and NetC (Net Complex) code. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index d0f20cc..1c83884 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3823,19 +3823,14 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) return 0; } -/* Ports initialization */ -static int mvpp2_port_probe(struct udevice *dev, - struct mvpp2_port *port, - int port_node, - struct mvpp2 *priv) +static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) { + int port_node = dev_of_offset(dev); + const char *phy_mode_str; int phy_node; u32 id; u32 phyaddr; - const char *phy_mode_str; int phy_mode = -1; - int priv_common_regs_num = 2; - int err; phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); if (phy_node < 0) { @@ -3859,46 +3854,37 @@ static int mvpp2_port_probe(struct udevice *dev, phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0); - port->priv = priv; port->id = id; - if (priv->hw_version == MVPP21) + if (port->priv->hw_version == MVPP21) port->first_rxq = port->id * rxq_number; else - port->first_rxq = port->id * priv->max_port_rxqs; + port->first_rxq = port->id * port->priv->max_port_rxqs; port->phy_node = phy_node; port->phy_interface = phy_mode; port->phyaddr = phyaddr; - if (priv->hw_version == MVPP21) { - port->base = (void __iomem *)dev_get_addr_index( - dev->parent, priv_common_regs_num + id); - if (IS_ERR(port->base)) - return PTR_ERR(port->base); - } else { - u32 gop_id; - - gop_id = fdtdec_get_int(gd->fdt_blob, port_node, - "gop-port-id", -1); - if (id == -1) { - dev_err(&pdev->dev, "missing gop-port-id value\n"); - return -EINVAL; - } + return 0; +} - port->base = priv->iface_base + MVPP22_PORT_BASE + - gop_id * MVPP22_PORT_OFFSET; - } +/* Ports initialization */ +static int mvpp2_port_probe(struct udevice *dev, + struct mvpp2_port *port, + int port_node, + struct mvpp2 *priv) +{ + int err; port->tx_ring_size = MVPP2_MAX_TXD; port->rx_ring_size = MVPP2_MAX_RXD; err = mvpp2_port_init(dev, port); if (err < 0) { - dev_err(&pdev->dev, "failed to init port %d\n", id); + dev_err(&pdev->dev, "failed to init port %d\n", port->id); return err; } mvpp2_port_power_up(port); - priv->port_list[id] = port; + priv->port_list[port->id] = port; return 0; } @@ -4546,6 +4532,36 @@ static int mvpp2_probe(struct udevice *dev) err = mvpp2_base_probe(dev->parent); priv->probe_done = 1; } + + port->priv = dev_get_priv(dev->parent); + + err = phy_info_parse(dev, port); + if (err) + return err; + + /* + * We need the port specific io base addresses at this stage, since + * gop_port_init() accesses these registers + */ + if (priv->hw_version == MVPP21) { + int priv_common_regs_num = 2; + + port->base = (void __iomem *)dev_get_addr_index( + dev->parent, priv_common_regs_num + port->id); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + } else { + port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "gop-port-id", -1); + if (port->id == -1) { + dev_err(&pdev->dev, "missing gop-port-id value\n"); + return -EINVAL; + } + + port->base = priv->iface_base + MVPP22_PORT_BASE + + port->gop_id * MVPP22_PORT_OFFSET; + } + /* Initialize network controller */ err = mvpp2_init(dev, priv); if (err < 0) { -- cgit v0.10.2 From 9acb7da14ebb55b2a9819c34a24f4ce6e99202c4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 22 Mar 2017 14:15:40 +0100 Subject: net: mvpp2: Read phy-speed from DT to select between 1GB and 2.5GB SGMII Read the "phy-speed" DT property to differentiate between 1 and 2.5GB SGMII operations. Please note that its unclear right now, if this DT property will be accepted in mainline Linux. If not, we need to revisit this code and change it to use the accepted property. Signed-off-by: Stefan Roese Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 1c83884..245a760 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -839,6 +839,8 @@ struct mvpp2_port { unsigned int duplex; unsigned int speed; + unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */ + struct mvpp2_bm_pool *pool_long; struct mvpp2_bm_pool *pool_short; @@ -3852,6 +3854,15 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) return -EINVAL; } + /* + * ToDo: + * Not sure if this DT property "phy-speed" will get accepted, so + * this might change later + */ + /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */ + port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node, + "phy-speed", 1000); + phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0); port->id = id; -- cgit v0.10.2 From 31aa1e38157882834b19a360b4096e848ed5bd2c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 22 Mar 2017 15:07:30 +0100 Subject: net: mvpp2: Add GoP and NetC support for ports 2 & 3 (RGMII & SGMII) This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only RGMII and SGMII support have been added, as these are the only interfaces that this code has been tested with. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 245a760..217afa6 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -355,6 +355,7 @@ do { \ /* Per-port registers */ #define MVPP2_GMAC_CTRL_0_REG 0x0 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) +#define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) @@ -366,29 +367,131 @@ do { \ #define MVPP2_GMAC_SA_LOW_OFFS 7 #define MVPP2_GMAC_CTRL_2_REG 0x8 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) +#define MVPP2_GMAC_SGMII_MODE_MASK BIT(0) #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4) +#define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5) #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) +#define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9) #define MVPP2_GMAC_AUTONEG_CONFIG 0xc #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) +#define MVPP2_GMAC_EN_PCS_AN BIT(2) +#define MVPP2_GMAC_AN_BYPASS_EN BIT(3) #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) #define MVPP2_GMAC_AN_SPEED_EN BIT(7) #define MVPP2_GMAC_FC_ADV_EN BIT(9) +#define MVPP2_GMAC_EN_FC_AN BIT(11) #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) +#define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15) #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) +#define MVPP2_GMAC_CTRL_4_REG 0x90 +#define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0) +#define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5) +#define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6) +#define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7) -#define MVPP22_SMI_MISC_CFG_REG 0x1204 +/* + * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, + * relative to port->base. + */ + +/* Port Mac Control0 */ +#define MVPP22_XLG_CTRL0_REG 0x100 +#define MVPP22_XLG_PORT_EN BIT(0) +#define MVPP22_XLG_MAC_RESETN BIT(1) +#define MVPP22_XLG_RX_FC_EN BIT(7) +#define MVPP22_XLG_MIBCNT_DIS BIT(13) +/* Port Mac Control1 */ +#define MVPP22_XLG_CTRL1_REG 0x104 +#define MVPP22_XLG_MAX_RX_SIZE_OFFS 0 +#define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff +/* Port Interrupt Mask */ +#define MVPP22_XLG_INTERRUPT_MASK_REG 0x118 +#define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1) +/* Port Mac Control3 */ +#define MVPP22_XLG_CTRL3_REG 0x11c +#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) +#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) +#define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13) +/* Port Mac Control4 */ +#define MVPP22_XLG_CTRL4_REG 0x184 +#define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5) +#define MVPP22_XLG_FORWARD_PFC_EN BIT(6) +#define MVPP22_XLG_MODE_DMA_1G BIT(12) +#define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14) + +/* XPCS registers */ + +/* Global Configuration 0 */ +#define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0 +#define MVPP22_XPCS_PCSRESET BIT(0) +#define MVPP22_XPCS_PCSMODE_OFFS 3 +#define MVPP22_XPCS_PCSMODE_MASK (0x3 << \ + MVPP22_XPCS_PCSMODE_OFFS) +#define MVPP22_XPCS_LANEACTIVE_OFFS 5 +#define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \ + MVPP22_XPCS_LANEACTIVE_OFFS) + +/* MPCS registers */ + +#define PCS40G_COMMON_CONTROL 0x14 +#define FORWARD_ERROR_CORRECTION_MASK BIT(1) + +#define PCS_CLOCK_RESET 0x14c +#define TX_SD_CLK_RESET_MASK BIT(0) +#define RX_SD_CLK_RESET_MASK BIT(1) +#define MAC_CLK_RESET_MASK BIT(2) +#define CLK_DIVISION_RATIO_OFFS 4 +#define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS) +#define CLK_DIV_PHASE_SET_MASK BIT(11) + +/* System Soft Reset 1 */ +#define GOP_SOFT_RESET_1_REG 0x108 +#define NETC_GOP_SOFT_RESET_OFFS 6 +#define NETC_GOP_SOFT_RESET_MASK (0x1 << \ + NETC_GOP_SOFT_RESET_OFFS) + +/* Ports Control 0 */ +#define NETCOMP_PORTS_CONTROL_0_REG 0x110 +#define NETC_BUS_WIDTH_SELECT_OFFS 1 +#define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \ + NETC_BUS_WIDTH_SELECT_OFFS) +#define NETC_GIG_RX_DATA_SAMPLE_OFFS 29 +#define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \ + NETC_GIG_RX_DATA_SAMPLE_OFFS) +#define NETC_CLK_DIV_PHASE_OFFS 31 +#define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS) +/* Ports Control 1 */ +#define NETCOMP_PORTS_CONTROL_1_REG 0x114 +#define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p) +#define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \ + NETC_PORTS_ACTIVE_OFFSET(p)) +#define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p) +#define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \ + NETC_PORT_GIG_RF_RESET_OFFS(p)) +#define NETCOMP_CONTROL_0_REG 0x120 +#define NETC_GBE_PORT0_SGMII_MODE_OFFS 0 +#define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \ + NETC_GBE_PORT0_SGMII_MODE_OFFS) +#define NETC_GBE_PORT1_SGMII_MODE_OFFS 1 +#define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \ + NETC_GBE_PORT1_SGMII_MODE_OFFS) +#define NETC_GBE_PORT1_MII_MODE_OFFS 2 +#define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \ + NETC_GBE_PORT1_MII_MODE_OFFS) + +#define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04) #define MVPP22_SMI_POLLING_EN BIT(10) -#define MVPP22_PORT_BASE 0x30e00 -#define MVPP22_PORT_OFFSET 0x1000 +#define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ + (0x4 * (port))) #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff @@ -414,6 +517,48 @@ do { \ #define MVPP2_PHY_ADDR_MASK 0x1f #define MVPP2_PHY_REG_MASK 0x1f +/* Additional PPv2.2 offsets */ +#define MVPP22_MPCS 0x007000 +#define MVPP22_XPCS 0x007400 +#define MVPP22_PORT_BASE 0x007e00 +#define MVPP22_PORT_OFFSET 0x001000 +#define MVPP22_RFU1 0x318000 + +/* Maximum number of ports */ +#define MVPP22_GOP_MAC_NUM 4 + +/* Sets the field located at the specified in data */ +#define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41 +#define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5 +#define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb + +/* Net Complex */ +enum mv_netc_topology { + MV_NETC_GE_MAC2_SGMII = BIT(0), + MV_NETC_GE_MAC3_SGMII = BIT(1), + MV_NETC_GE_MAC3_RGMII = BIT(2), +}; + +enum mv_netc_phase { + MV_NETC_FIRST_PHASE, + MV_NETC_SECOND_PHASE, +}; + +enum mv_netc_sgmii_xmi_mode { + MV_NETC_GBE_SGMII, + MV_NETC_GBE_XMII, +}; + +enum mv_netc_mii_mode { + MV_NETC_GBE_RGMII, + MV_NETC_GBE_MII, +}; + +enum mv_netc_lanes { + MV_NETC_LANE_23, + MV_NETC_LANE_45, +}; + /* Various constants */ /* Coalescing */ @@ -763,6 +908,12 @@ struct mvpp2 { void __iomem *iface_base; void __iomem *mdio_base; + void __iomem *mpcs_base; + void __iomem *xpcs_base; + void __iomem *rfu1_base; + + u32 netc_config; + /* List of pointers to port structures */ struct mvpp2_port **port_list; @@ -2826,6 +2977,570 @@ static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); } +/* PPv2.2 GoP/GMAC config */ + +/* Set the MAC to reset or exit from reset */ +static int gop_gmac_reset(struct mvpp2_port *port, int reset) +{ + u32 val; + + /* read - modify - write */ + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + if (reset) + val |= MVPP2_GMAC_PORT_RESET_MASK; + else + val &= ~MVPP2_GMAC_PORT_RESET_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + return 0; +} + +/* + * gop_gpcs_mode_cfg + * + * Configure port to working with Gig PCS or don't. + */ +static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + if (en) + val |= MVPP2_GMAC_PCS_ENABLE_MASK; + else + val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; + /* enable / disable PCS on this port */ + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + return 0; +} + +static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + if (en) + val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK; + else + val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK; + /* enable / disable PCS on this port */ + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + return 0; +} + +static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) +{ + u32 val, thresh; + + /* + * Configure minimal level of the Tx FIFO before the lower part + * starts to read a packet + */ + thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH; + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + + /* Disable bypass of sync module */ + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK; + /* configure DP clock select according to mode */ + val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK; + /* configure QSGMII bypass according to mode */ + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + val |= MVPP2_GMAC_PORT_DIS_PADING_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + /* + * Configure GIG MAC to 1000Base-X mode connected to a fiber + * transceiver + */ + val |= MVPP2_GMAC_PORT_TYPE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); + + /* configure AN 0x9268 */ + val = MVPP2_GMAC_EN_PCS_AN | + MVPP2_GMAC_AN_BYPASS_EN | + MVPP2_GMAC_CONFIG_MII_SPEED | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_FC_ADV_EN | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + +static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) +{ + u32 val, thresh; + + /* + * Configure minimal level of the Tx FIFO before the lower part + * starts to read a packet + */ + thresh = MVPP2_SGMII_TX_FIFO_MIN_TH; + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + + /* Disable bypass of sync module */ + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK; + /* configure DP clock select according to mode */ + val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK; + /* configure QSGMII bypass according to mode */ + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + val |= MVPP2_GMAC_PORT_DIS_PADING_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + /* configure GIG MAC to SGMII mode */ + val &= ~MVPP2_GMAC_PORT_TYPE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); + + /* configure AN */ + val = MVPP2_GMAC_EN_PCS_AN | + MVPP2_GMAC_AN_BYPASS_EN | + MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_EN_FC_AN | + MVPP2_GMAC_AN_DUPLEX_EN | + MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + +static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) +{ + u32 val, thresh; + + /* + * Configure minimal level of the Tx FIFO before the lower part + * starts to read a packet + */ + thresh = MVPP2_RGMII_TX_FIFO_MIN_TH; + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + + /* Disable bypass of sync module */ + val = readl(port->base + MVPP2_GMAC_CTRL_4_REG); + val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK; + /* configure DP clock select according to mode */ + val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK; + val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; + val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + /* configure GIG MAC to SGMII mode */ + val &= ~MVPP2_GMAC_PORT_TYPE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); + + /* configure AN 0xb8e8 */ + val = MVPP2_GMAC_AN_BYPASS_EN | + MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_EN_FC_AN | + MVPP2_GMAC_AN_DUPLEX_EN | + MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + +/* Set the internal mux's to the required MAC in the GOP */ +static int gop_gmac_mode_cfg(struct mvpp2_port *port) +{ + u32 val; + + /* Set TX FIFO thresholds */ + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + if (port->phy_speed == 2500) + gop_gmac_sgmii2_5_cfg(port); + else + gop_gmac_sgmii_cfg(port); + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + gop_gmac_rgmii_cfg(port); + break; + + default: + return -1; + } + + /* Jumbo frame support - 0x1400*2= 0x2800 bytes */ + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; + val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); + + /* PeriodicXonEn disable */ + val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); + val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); + + return 0; +} + +static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port) +{ + u32 val; + + /* relevant only for MAC0 (XLG0 and GMAC0) */ + if (port->gop_id > 0) + return; + + /* configure 1Gig MAC mode */ + val = readl(port->base + MVPP22_XLG_CTRL3_REG); + val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; + val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; + writel(val, port->base + MVPP22_XLG_CTRL3_REG); +} + +static int gop_gpcs_reset(struct mvpp2_port *port, int reset) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + if (reset) + val &= ~MVPP2_GMAC_SGMII_MODE_MASK; + else + val |= MVPP2_GMAC_SGMII_MODE_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + return 0; +} + +/* + * gop_port_init + * + * Init physical port. Configures the port mode and all it's elements + * accordingly. + * Does not verify that the selected mode/port number is valid at the + * core level. + */ +static int gop_port_init(struct mvpp2_port *port) +{ + int mac_num = port->gop_id; + + if (mac_num >= MVPP22_GOP_MAC_NUM) { + netdev_err(NULL, "%s: illegal port number %d", __func__, + mac_num); + return -1; + } + + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + gop_gmac_reset(port, 1); + + /* configure PCS */ + gop_gpcs_mode_cfg(port, 0); + gop_bypass_clk_cfg(port, 1); + + /* configure MAC */ + gop_gmac_mode_cfg(port); + /* pcs unreset */ + gop_gpcs_reset(port, 0); + + /* mac unreset */ + gop_gmac_reset(port, 0); + break; + + case PHY_INTERFACE_MODE_SGMII: + /* configure PCS */ + gop_gpcs_mode_cfg(port, 1); + + /* configure MAC */ + gop_gmac_mode_cfg(port); + /* select proper Mac mode */ + gop_xlg_2_gig_mac_cfg(port); + + /* pcs unreset */ + gop_gpcs_reset(port, 0); + /* mac unreset */ + gop_gmac_reset(port, 0); + break; + + default: + netdev_err(NULL, "%s: Requested port mode (%d) not supported\n", + __func__, port->phy_interface); + return -1; + } + + return 0; +} + +static void gop_port_enable(struct mvpp2_port *port, int enable) +{ + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_SGMII: + if (enable) + mvpp2_port_enable(port); + else + mvpp2_port_disable(port); + break; + + default: + netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__, + port->phy_interface); + return; + } +} + +/* RFU1 functions */ +static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset) +{ + return readl(priv->rfu1_base + offset); +} + +static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data) +{ + writel(data, priv->rfu1_base + offset); +} + +static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type) +{ + u32 val = 0; + + if (gop_id == 2) { + if (phy_type == PHY_INTERFACE_MODE_SGMII) + val |= MV_NETC_GE_MAC2_SGMII; + } + + if (gop_id == 3) { + if (phy_type == PHY_INTERFACE_MODE_SGMII) + val |= MV_NETC_GE_MAC3_SGMII; + else if (phy_type == PHY_INTERFACE_MODE_RGMII || + phy_type == PHY_INTERFACE_MODE_RGMII_ID) + val |= MV_NETC_GE_MAC3_RGMII; + } + + return val; +} + +static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG); + reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id)); + + val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id); + val &= NETC_PORTS_ACTIVE_MASK(gop_id); + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg); +} + +static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG); + reg &= ~NETC_GBE_PORT1_MII_MODE_MASK; + + val <<= NETC_GBE_PORT1_MII_MODE_OFFS; + val &= NETC_GBE_PORT1_MII_MODE_MASK; + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg); +} + +static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG); + reg &= ~NETC_GOP_SOFT_RESET_MASK; + + val <<= NETC_GOP_SOFT_RESET_OFFS; + val &= NETC_GOP_SOFT_RESET_MASK; + + reg |= val; + + gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg); +} + +static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG); + reg &= ~NETC_CLK_DIV_PHASE_MASK; + + val <<= NETC_CLK_DIV_PHASE_OFFS; + val &= NETC_CLK_DIV_PHASE_MASK; + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg); +} + +static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG); + reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id)); + + val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id); + val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id); + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg); +} + +static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id, + u32 val) +{ + u32 reg, mask, offset; + + if (gop_id == 2) { + mask = NETC_GBE_PORT0_SGMII_MODE_MASK; + offset = NETC_GBE_PORT0_SGMII_MODE_OFFS; + } else { + mask = NETC_GBE_PORT1_SGMII_MODE_MASK; + offset = NETC_GBE_PORT1_SGMII_MODE_OFFS; + } + reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG); + reg &= ~mask; + + val <<= offset; + val &= mask; + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg); +} + +static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG); + reg &= ~NETC_BUS_WIDTH_SELECT_MASK; + + val <<= NETC_BUS_WIDTH_SELECT_OFFS; + val &= NETC_BUS_WIDTH_SELECT_MASK; + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg); +} + +static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val) +{ + u32 reg; + + reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG); + reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK; + + val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS; + val &= NETC_GIG_RX_DATA_SAMPLE_MASK; + + reg |= val; + + gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg); +} + +static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id, + enum mv_netc_phase phase) +{ + switch (phase) { + case MV_NETC_FIRST_PHASE: + /* Set Bus Width to HB mode = 1 */ + gop_netc_bus_width_select(priv, 1); + /* Select RGMII mode */ + gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII); + break; + + case MV_NETC_SECOND_PHASE: + /* De-assert the relevant port HB reset */ + gop_netc_port_rf_reset(priv, gop_id, 1); + break; + } +} + +static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id, + enum mv_netc_phase phase) +{ + switch (phase) { + case MV_NETC_FIRST_PHASE: + /* Set Bus Width to HB mode = 1 */ + gop_netc_bus_width_select(priv, 1); + /* Select SGMII mode */ + if (gop_id >= 1) { + gop_netc_gbe_sgmii_mode_select(priv, gop_id, + MV_NETC_GBE_SGMII); + } + + /* Configure the sample stages */ + gop_netc_sample_stages_timing(priv, 0); + /* Configure the ComPhy Selector */ + /* gop_netc_com_phy_selector_config(netComplex); */ + break; + + case MV_NETC_SECOND_PHASE: + /* De-assert the relevant port HB reset */ + gop_netc_port_rf_reset(priv, gop_id, 1); + break; + } +} + +static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase) +{ + u32 c = priv->netc_config; + + if (c & MV_NETC_GE_MAC2_SGMII) + gop_netc_mac_to_sgmii(priv, 2, phase); + else + gop_netc_mac_to_xgmii(priv, 2, phase); + + if (c & MV_NETC_GE_MAC3_SGMII) { + gop_netc_mac_to_sgmii(priv, 3, phase); + } else { + gop_netc_mac_to_xgmii(priv, 3, phase); + if (c & MV_NETC_GE_MAC3_RGMII) + gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII); + else + gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII); + } + + /* Activate gop ports 0, 2, 3 */ + gop_netc_active_port(priv, 0, 1); + gop_netc_active_port(priv, 2, 1); + gop_netc_active_port(priv, 3, 1); + + if (phase == MV_NETC_SECOND_PHASE) { + /* Enable the GOP internal clock logic */ + gop_netc_gop_clock_logic_set(priv, 1); + /* De-assert GOP unit reset */ + gop_netc_gop_reset(priv, 1); + } + + return 0; +} + /* Set defaults to the MVPP2 port */ static void mvpp2_defaults_set(struct mvpp2_port *port) { @@ -3602,7 +4317,10 @@ static void mvpp2_start_dev(struct mvpp2_port *port) mvpp2_gmac_max_rx_size_set(port); mvpp2_txp_max_tx_size_set(port); - mvpp2_port_enable(port); + if (port->priv->hw_version == MVPP21) + mvpp2_port_enable(port); + else + gop_port_enable(port, 1); } /* Set hw internals when stopping port */ @@ -3612,7 +4330,11 @@ static void mvpp2_stop_dev(struct mvpp2_port *port) mvpp2_ingress_disable(port); mvpp2_egress_disable(port); - mvpp2_port_disable(port); + + if (port->priv->hw_version == MVPP21) + mvpp2_port_disable(port); + else + gop_port_enable(port, 0); } static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) @@ -3706,7 +4428,9 @@ static void mvpp2_port_power_up(struct mvpp2_port *port) { struct mvpp2 *priv = port->priv; - mvpp2_port_mii_set(port); + /* On PPv2.2 the GoP / interface configuration has already been done */ + if (priv->hw_version == MVPP21) + mvpp2_port_mii_set(port); mvpp2_port_periodic_xon_disable(port); if (priv->hw_version == MVPP21) mvpp2_port_fc_adv_enable(port); @@ -3726,7 +4450,10 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) /* Disable port */ mvpp2_egress_disable(port); - mvpp2_port_disable(port); + if (priv->hw_version == MVPP21) + mvpp2_port_disable(port); + else + gop_port_enable(port, 0); port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), GFP_KERNEL); @@ -4509,6 +5236,11 @@ static int mvpp2_base_probe(struct udevice *dev) return PTR_ERR(priv->iface_base); priv->mdio_base = priv->iface_base + MVPP22_SMI; + + /* Store common base addresses for all ports */ + priv->mpcs_base = priv->iface_base + MVPP22_MPCS; + priv->xpcs_base = priv->iface_base + MVPP22_XPCS; + priv->rfu1_base = priv->iface_base + MVPP22_RFU1; } if (priv->hw_version == MVPP21) @@ -4571,6 +5303,9 @@ static int mvpp2_probe(struct udevice *dev) port->base = priv->iface_base + MVPP22_PORT_BASE + port->gop_id * MVPP22_PORT_OFFSET; + + /* GoP Init */ + gop_port_init(port); } /* Initialize network controller */ @@ -4580,7 +5315,20 @@ static int mvpp2_probe(struct udevice *dev) return err; } - return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); + err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); + if (err) + return err; + + if (priv->hw_version == MVPP22) { + priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id, + port->phy_interface); + + /* Netcomplex configurations for all ports */ + gop_netc_init(priv, MV_NETC_FIRST_PHASE); + gop_netc_init(priv, MV_NETC_SECOND_PHASE); + } + + return 0; } static const struct eth_ops mvpp2_ops = { -- cgit v0.10.2 From 2fe23044cd7e8145dfd995d76cd6b991ad3da2a1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 22 Mar 2017 15:09:38 +0100 Subject: net: mvpp2: Add GoP and NetC support for port 0 (SFI) This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to the Marvell mvpp2 ethernet driver for the missing port 0. This code is mostly copied from the Marvell U-Boot version and was written by Stefan Chulski. Please note that only SFI support have been added, as this is the only interface that this code has been tested with. XAUI and RXAUI support might follow at a later stage. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 217afa6..a2de1ae 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3225,6 +3225,130 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int reset) return 0; } +/* Set the internal mux's to the required PCS in the PI */ +static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes) +{ + u32 val; + int lane; + + switch (num_of_lanes) { + case 1: + lane = 0; + break; + case 2: + lane = 1; + break; + case 4: + lane = 2; + break; + default: + return -1; + } + + /* configure XG MAC mode */ + val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); + val &= ~MVPP22_XPCS_PCSMODE_OFFS; + val &= ~MVPP22_XPCS_LANEACTIVE_MASK; + val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS; + writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); + + return 0; +} + +static int gop_mpcs_mode(struct mvpp2_port *port) +{ + u32 val; + + /* configure PCS40G COMMON CONTROL */ + val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL); + val &= ~FORWARD_ERROR_CORRECTION_MASK; + writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL); + + /* configure PCS CLOCK RESET */ + val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET); + val &= ~CLK_DIVISION_RATIO_MASK; + val |= 1 << CLK_DIVISION_RATIO_OFFS; + writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); + + val &= ~CLK_DIV_PHASE_SET_MASK; + val |= MAC_CLK_RESET_MASK; + val |= RX_SD_CLK_RESET_MASK; + val |= TX_SD_CLK_RESET_MASK; + writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET); + + return 0; +} + +/* Set the internal mux's to the required MAC in the GOP */ +static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes) +{ + u32 val; + + /* configure 10G MAC mode */ + val = readl(port->base + MVPP22_XLG_CTRL0_REG); + val |= MVPP22_XLG_RX_FC_EN; + writel(val, port->base + MVPP22_XLG_CTRL0_REG); + + val = readl(port->base + MVPP22_XLG_CTRL3_REG); + val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; + val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC; + writel(val, port->base + MVPP22_XLG_CTRL3_REG); + + /* read - modify - write */ + val = readl(port->base + MVPP22_XLG_CTRL4_REG); + val &= ~MVPP22_XLG_MODE_DMA_1G; + val |= MVPP22_XLG_FORWARD_PFC_EN; + val |= MVPP22_XLG_FORWARD_802_3X_FC_EN; + val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK; + writel(val, port->base + MVPP22_XLG_CTRL4_REG); + + /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */ + val = readl(port->base + MVPP22_XLG_CTRL1_REG); + val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK; + val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS; + writel(val, port->base + MVPP22_XLG_CTRL1_REG); + + /* unmask link change interrupt */ + val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG); + val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE; + val |= 1; /* unmask summary bit */ + writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG); + + return 0; +} + +/* Set PCS to reset or exit from reset */ +static int gop_xpcs_reset(struct mvpp2_port *port, int reset) +{ + u32 val; + + /* read - modify - write */ + val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); + if (reset) + val &= ~MVPP22_XPCS_PCSRESET; + else + val |= MVPP22_XPCS_PCSRESET; + writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG); + + return 0; +} + +/* Set the MAC to reset or exit from reset */ +static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset) +{ + u32 val; + + /* read - modify - write */ + val = readl(port->base + MVPP22_XLG_CTRL0_REG); + if (reset) + val &= ~MVPP22_XLG_MAC_RESETN; + else + val |= MVPP22_XLG_MAC_RESETN; + writel(val, port->base + MVPP22_XLG_CTRL0_REG); + + return 0; +} + /* * gop_port_init * @@ -3236,6 +3360,7 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int reset) static int gop_port_init(struct mvpp2_port *port) { int mac_num = port->gop_id; + int num_of_act_lanes; if (mac_num >= MVPP22_GOP_MAC_NUM) { netdev_err(NULL, "%s: illegal port number %d", __func__, @@ -3276,6 +3401,22 @@ static int gop_port_init(struct mvpp2_port *port) gop_gmac_reset(port, 0); break; + case PHY_INTERFACE_MODE_SFI: + num_of_act_lanes = 2; + mac_num = 0; + /* configure PCS */ + gop_xpcs_mode(port, num_of_act_lanes); + gop_mpcs_mode(port); + /* configure MAC */ + gop_xlg_mac_mode_cfg(port, num_of_act_lanes); + + /* pcs unreset */ + gop_xpcs_reset(port, 0); + + /* mac unreset */ + gop_xlg_mac_reset(port, 0); + break; + default: netdev_err(NULL, "%s: Requested port mode (%d) not supported\n", __func__, port->phy_interface); @@ -3285,6 +3426,22 @@ static int gop_port_init(struct mvpp2_port *port) return 0; } +static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable) +{ + u32 val; + + val = readl(port->base + MVPP22_XLG_CTRL0_REG); + if (enable) { + /* Enable port and MIB counters update */ + val |= MVPP22_XLG_PORT_EN; + val &= ~MVPP22_XLG_MIBCNT_DIS; + } else { + /* Disable port */ + val &= ~MVPP22_XLG_PORT_EN; + } + writel(val, port->base + MVPP22_XLG_CTRL0_REG); +} + static void gop_port_enable(struct mvpp2_port *port, int enable) { switch (port->phy_interface) { @@ -3297,6 +3454,10 @@ static void gop_port_enable(struct mvpp2_port *port, int enable) mvpp2_port_disable(port); break; + case PHY_INTERFACE_MODE_SFI: + gop_xlg_mac_port_enable(port, enable); + + break; default: netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__, port->phy_interface); -- cgit v0.10.2 From 025e5921be8555f38ad4578df07b337fb6d185e0 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 22 Mar 2017 15:11:00 +0100 Subject: net: mvpp2: Add missing PHY_INTERFACE_MODE_RGMII_ID Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should be handled identical to PHY_INTERFACE_MODE_RGMII. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index a2de1ae..79442b8 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -2886,6 +2886,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) val |= MVPP2_GMAC_INBAND_AN_MASK; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: val |= MVPP2_GMAC_PORT_RGMII_MASK; default: val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; -- cgit v0.10.2 From 3e3cbb4967f0bff734aba20ca501bd391d858d77 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 9 Mar 2017 12:01:57 +0100 Subject: net: mvpp2: Enable PHY polling mode on PPv2.2 Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 79442b8..36e209e 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4957,14 +4957,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) if (priv->hw_version == MVPP22) mvpp2_axi_init(priv); - /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { + /* Disable HW PHY polling */ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val |= MVPP2_PHY_AN_STOP_SMI0_MASK; writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); } else { + /* Enable HW PHY polling */ val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); - val &= ~MVPP22_SMI_POLLING_EN; + val |= MVPP22_SMI_POLLING_EN; writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); } -- cgit v0.10.2 From fb64072934a5a4d0e8b89d2e9fd64c5e12d5c2ea Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Mar 2017 06:07:45 +0100 Subject: net: mvpp2: Configure SMI PHY address needed for PHY polling On PPv2.2 we enable PHY polling, so we also need to configure the PHY address in the specific PHY address rgisters. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 36e209e..dc9fbb9 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5329,6 +5329,14 @@ static void mvpp2_stop(struct udevice *dev) mvpp2_cleanup_txqs(port); } +static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) +{ + writel(port->phyaddr, port->priv->iface_base + + MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); + + return 0; +} + static int mvpp2_base_probe(struct udevice *dev) { struct mvpp2 *priv = dev_get_priv(dev); @@ -5467,6 +5475,9 @@ static int mvpp2_probe(struct udevice *dev) port->base = priv->iface_base + MVPP22_PORT_BASE + port->gop_id * MVPP22_PORT_OFFSET; + /* Set phy address of the port */ + mvpp22_smi_phy_addr_cfg(port); + /* GoP Init */ gop_port_init(port); } -- cgit v0.10.2 From fbaa266230872c4ea4ab5dff8f0b0f8b80417092 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 13 Mar 2017 06:50:04 +0100 Subject: net: mvpp2: Remove unreferenced in_use_thresh from struct mvpp2_bm_pool As pointed out by Stefan Chulski, this variable is unused and should be removed. Signed-off-by: Stefan Roese Cc: Stefan Chulski Acked-by: Joe Hershberger diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index dc9fbb9..8ffe6c8 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -1245,9 +1245,6 @@ struct mvpp2_bm_pool { /* Ports using BM pool */ u32 port_map; - - /* Occupied buffers indicator */ - int in_use_thresh; }; /* Static declaractions */ @@ -2792,7 +2789,6 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port, /* Update BM driver with number of buffers added to pool */ bm_pool->buf_num += i; - bm_pool->in_use_thresh = bm_pool->buf_num / 4; return i; } -- cgit v0.10.2 From d74238aeb671f45929086be0a91fb6583d11924a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 9 Mar 2017 14:35:28 +0100 Subject: arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G The default configuration for the COMPHY-0 port should be 1G, as its used as 1G SGMII connection. This change is necessary to get the MAC2 port (SGMII) working on this DB. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 776bc78..84e0dbd 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -159,7 +159,7 @@ &cpm_comphy { phy0 { phy-type = ; - phy-speed = ; + phy-speed = ; }; phy1 { -- cgit v0.10.2 From 941f7a4b2606ef468f4f3b763261b758eadee861 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Mar 2017 11:08:44 +0100 Subject: arm64: mvebu: Enable CONFIG_PHY_MARVELL in Armada7k/8k-DB defconfig The Marvell PHY support is needed espescially for the A7040-DB with the SGMII port (port 2). As without the marvell PHY driver configuration for SGMII, ethernet won't work. Signed-off-by: Stefan Roese Cc: Stefan Chulski Cc: Kostya Porotchkin Cc: Nadav Haklai Acked-by: Joe Hershberger diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig index fdafeb6..797eabb 100644 --- a/configs/mvebu_db-88f7040_defconfig +++ b/configs/mvebu_db-88f7040_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MARVELL=y CONFIG_MVPP2=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/configs/mvebu_db-88f8040_defconfig b/configs/mvebu_db-88f8040_defconfig index 9866e19..046da09 100644 --- a/configs/mvebu_db-88f8040_defconfig +++ b/configs/mvebu_db-88f8040_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MARVELL=y CONFIG_MVPP2=y CONFIG_PCI=y CONFIG_DM_PCI=y -- cgit v0.10.2