From 5f533aeb5117ebe4ef1d10b5cae326334965035d Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 11 Nov 2011 15:55:35 -0600 Subject: gpio: Modify common gpio.h to more closely match Linux Change "int gp" to "unsigned gpio" Add request and free entry-points Signed-off-by: Joe Hershberger Cc: Joe Hershberger Signed-off-by: Kim Phillips diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index a1ebb28..c19e16c 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2011, NVIDIA Corp. All rights reserved. * See file CREDITS for list of people who contributed to this * project. * @@ -19,6 +20,9 @@ * MA 02111-1307 USA */ +#ifndef _ASM_GENERIC_GPIO_H_ +#define _ASM_GENERIC_GPIO_H_ + /* * Generic GPIO API for U-Boot * @@ -38,37 +42,56 @@ */ /** + * Request ownership of a GPIO. + * + * @param gpio GPIO number + * @param label Name given to the GPIO + * @return 0 if ok, -1 on error + */ +int gpio_request(unsigned gpio, const char *label); + +/** + * Stop using the GPIO. This function should not alter pin configuration. + * + * @param gpio GPIO number + * @return 0 if ok, -1 on error + */ +int gpio_free(unsigned gpio); + +/** * Make a GPIO an input. * - * @param gp GPIO number + * @param gpio GPIO number * @return 0 if ok, -1 on error */ -int gpio_direction_input(int gp); +int gpio_direction_input(unsigned gpio); /** * Make a GPIO an output, and set its value. * - * @param gp GPIO number + * @param gpio GPIO number * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_direction_output(int gp, int value); +int gpio_direction_output(unsigned gpio, int value); /** * Get a GPIO's value. This will work whether the GPIO is an input * or an output. * - * @param gp GPIO number + * @param gpio GPIO number * @return 0 if low, 1 if high, -1 on error */ -int gpio_get_value(int gp); +int gpio_get_value(unsigned gpio); /** - * Set an output GPIO's value. The GPIO must already be an output of + * Set an output GPIO's value. The GPIO must already be an output or * this function may have no effect. * - * @param gp GPIO number + * @param gpio GPIO number * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_set_value(int gp, int value); +int gpio_set_value(unsigned gpio, int value); + +#endif /* _ASM_GENERIC_GPIO_H_ */ -- cgit v0.10.2 From 365d607033b8fcb0a8c27aabcb4bb05fb3b64465 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 11 Nov 2011 15:55:36 -0600 Subject: gpio: Replace ARM gpio.h with the common API in include/asm-generic ARM boards should use the generic GPIO API This means changing gpio to unsigned type Remove the unused gpio_toggle() function which is not part of the API Comment that free should not modify pin state Signed-off-by: Joe Hershberger Cc: Joe Hershberger fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and extended to the new mxs_gpio.c. Signed-off-by: Kim Phillips Cc: Albert ARIBAUD diff --git a/arch/arm/cpu/armv7/omap-common/gpio.c b/arch/arm/cpu/armv7/omap-common/gpio.c index 75a02da..fc89f2a 100644 --- a/arch/arm/cpu/armv7/omap-common/gpio.c +++ b/arch/arm/cpu/armv7/omap-common/gpio.c @@ -36,7 +36,7 @@ * published by the Free Software Foundation. */ #include -#include +#include #include #include @@ -56,17 +56,17 @@ static inline int get_gpio_index(int gpio) static inline int gpio_valid(int gpio) { if (gpio < 0) - return -EINVAL; + return -1; if (gpio < 192) return 0; - return -EINVAL; + return -1; } static int check_gpio(int gpio) { if (gpio_valid(gpio) < 0) { printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); - return -EINVAL; + return -1; } return 0; } @@ -106,7 +106,7 @@ static int _get_gpio_direction(const struct gpio_bank *bank, int gpio) reg += OMAP_GPIO_OE; break; default: - return -EINVAL; + return -1; } v = __raw_readl(reg); @@ -142,27 +142,29 @@ static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, /** * Set value of the specified gpio */ -void gpio_set_value(int gpio, int value) +int gpio_set_value(unsigned gpio, int value) { const struct gpio_bank *bank; if (check_gpio(gpio) < 0) - return; + return -1; bank = get_gpio_bank(gpio); _set_gpio_dataout(bank, get_gpio_index(gpio), value); + + return 0; } /** * Get value of the specified gpio */ -int gpio_get_value(int gpio) +int gpio_get_value(unsigned gpio) { const struct gpio_bank *bank; void *reg; int input; if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; bank = get_gpio_bank(gpio); reg = bank->base; switch (bank->method) { @@ -176,11 +178,11 @@ int gpio_get_value(int gpio) reg += OMAP_GPIO_DATAOUT; break; default: - return -EINVAL; + return -1; } break; default: - return -EINVAL; + return -1; } return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; @@ -194,7 +196,7 @@ int gpio_direction_input(unsigned gpio) const struct gpio_bank *bank; if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; bank = get_gpio_bank(gpio); _set_gpio_direction(bank, get_gpio_index(gpio), 1); @@ -210,7 +212,7 @@ int gpio_direction_output(unsigned gpio, int value) const struct gpio_bank *bank; if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; bank = get_gpio_bank(gpio); _set_gpio_dataout(bank, get_gpio_index(gpio), value); @@ -224,10 +226,10 @@ int gpio_direction_output(unsigned gpio, int value) * * NOTE: Argument 'label' is unused. */ -int gpio_request(int gpio, const char *label) +int gpio_request(unsigned gpio, const char *label) { if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; return 0; } @@ -235,6 +237,7 @@ int gpio_request(int gpio, const char *label) /** * Reset and free the gpio after using it. */ -void gpio_free(unsigned gpio) +int gpio_free(unsigned gpio) { + return 0; } diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index eb071d1..d49ad08 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,38 +1,2 @@ -/* - * Copyright (c) 2011, NVIDIA Corp. All rights reserved. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _GPIO_H_ -#define _GPIO_H_ - #include -/* - * Generic GPIO API - */ - -int gpio_request(int gp, const char *label); -void gpio_free(int gp); -void gpio_toggle_value(int gp); -int gpio_direction_input(int gp); -int gpio_direction_output(int gp, int value); -int gpio_get_value(int gp); -void gpio_set_value(int gp, int value); - -#endif /* _GPIO_H_ */ +#include diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index 74b58e8..84d2b77 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -181,87 +180,93 @@ static const struct pinmux_config gpio_pinmux[] = { { pinmux(18), 8, 2 }, }; -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (gp >= MAX_NUM_GPIOS) + if (gpio >= MAX_NUM_GPIOS) return -1; - if (gpio_registry[gp].is_registered) + if (gpio_registry[gpio].is_registered) return -1; - gpio_registry[gp].is_registered = 1; - strncpy(gpio_registry[gp].name, label, GPIO_NAME_SIZE); - gpio_registry[gp].name[GPIO_NAME_SIZE - 1] = 0; + gpio_registry[gpio].is_registered = 1; + strncpy(gpio_registry[gpio].name, label, GPIO_NAME_SIZE); + gpio_registry[gpio].name[GPIO_NAME_SIZE - 1] = 0; - davinci_configure_pin_mux(&gpio_pinmux[gp], 1); + davinci_configure_pin_mux(&gpio_pinmux[gpio], 1); return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { - gpio_registry[gp].is_registered = 0; -} + if (gpio >= MAX_NUM_GPIOS) + return -1; -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); + if (!gpio_registry[gpio].is_registered) + return -1; + + gpio_registry[gpio].is_registered = 0; + gpio_registry[gpio].name[0] = '\0'; + /* Do not configure as input or change pin mux here */ + return 0; } -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { struct davinci_gpio *bank; - bank = GPIO_BANK(gp); - setbits_le32(&bank->dir, 1U << GPIO_BIT(gp)); + bank = GPIO_BANK(gpio); + setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); return 0; } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { struct davinci_gpio *bank; - bank = GPIO_BANK(gp); - clrbits_le32(&bank->dir, 1U << GPIO_BIT(gp)); - gpio_set_value(gp, value); + bank = GPIO_BANK(gpio); + clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); + gpio_set_value(gpio, value); return 0; } -int gpio_get_value(int gp) +int gpio_get_value(unsigned gpio) { struct davinci_gpio *bank; unsigned int ip; - bank = GPIO_BANK(gp); - ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gp)); + bank = GPIO_BANK(gpio); + ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio)); return ip ? 1 : 0; } -void gpio_set_value(int gp, int value) +int gpio_set_value(unsigned gpio, int value) { struct davinci_gpio *bank; - bank = GPIO_BANK(gp); + bank = GPIO_BANK(gpio); if (value) - bank->set_data = 1U << GPIO_BIT(gp); + bank->set_data = 1U << GPIO_BIT(gpio); else - bank->clr_data = 1U << GPIO_BIT(gp); + bank->clr_data = 1U << GPIO_BIT(gpio); + + return 0; } void gpio_info(void) { - int gp, dir, val; + unsigned gpio, dir, val; struct davinci_gpio *bank; - for (gp = 0; gp < MAX_NUM_GPIOS; ++gp) { - bank = GPIO_BANK(gp); - dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gp)); - val = gpio_get_value(gp); + for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) { + bank = GPIO_BANK(gpio); + dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gpio)); + val = gpio_get_value(gpio); printf("% 4d: %s: %d [%c] %s\n", - gp, dir ? " in" : "out", val, - gpio_registry[gp].is_registered ? 'x' : ' ', - gpio_registry[gp].name); + gpio, dir ? " in" : "out", val, + gpio_registry[gpio].is_registered ? 'x' : ' ', + gpio_registry[gpio].name); } } diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c index 276f206..c80891c 100644 --- a/drivers/gpio/mvgpio.c +++ b/drivers/gpio/mvgpio.c @@ -35,81 +35,79 @@ #define MV_MAX_GPIO 128 #endif -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO requested %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO requested %d\n", __func__, gpio); + return -1; } return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { + return 0; } -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); -} - -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { struct gpio_reg *gpio_reg_bank; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gcdr); return 0; } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { struct gpio_reg *gpio_reg_bank; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr); - gpio_set_value(gp, value); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gsdr); + gpio_set_value(gpio, value); return 0; } -int gpio_get_value(int gp) +int gpio_get_value(unsigned gpio) { struct gpio_reg *gpio_reg_bank; - u32 gp_val; + u32 gpio_val; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); - gp_val = readl(&gpio_reg_bank->gplr); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); + gpio_val = readl(&gpio_reg_bank->gplr); - return GPIO_VAL(gp, gp_val); + return GPIO_VAL(gpio, gpio_val); } -void gpio_set_value(int gp, int value) +int gpio_set_value(unsigned gpio, int value) { struct gpio_reg *gpio_reg_bank; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); if (value) - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpsr); else - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpcr); + + return 0; } diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 908808d..df6bbbb 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -58,7 +58,7 @@ static int mxc_gpio_direction(unsigned int gpio, u32 l; if (port >= ARRAY_SIZE(gpio_ports)) - return -EINVAL; + return -1; gpio &= 0x1f; @@ -78,14 +78,14 @@ static int mxc_gpio_direction(unsigned int gpio, return 0; } -void gpio_set_value(int gpio, int value) +int gpio_set_value(unsigned gpio, int value) { unsigned int port = gpio >> 5; struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) - return; + return -1; gpio &= 0x1f; @@ -97,55 +97,53 @@ void gpio_set_value(int gpio, int value) else l &= ~(1 << gpio); writel(l, ®s->gpio_dr); + + return 0; } -int gpio_get_value(int gpio) +int gpio_get_value(unsigned gpio) { unsigned int port = gpio >> 5; struct gpio_regs *regs; - u32 l; + u32 val; if (port >= ARRAY_SIZE(gpio_ports)) - return -EINVAL; + return -1; gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; - l = (readl(®s->gpio_dr) >> gpio) & 0x01; + val = (readl(®s->gpio_dr) >> gpio) & 0x01; - return l; + return val; } -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - unsigned int port = gp >> 5; + unsigned int port = gpio >> 5; if (port >= ARRAY_SIZE(gpio_ports)) - return -EINVAL; + return -1; return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { + return 0; } -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); -} - -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { - return mxc_gpio_direction(gp, MXC_GPIO_DIRECTION_IN); + return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN); } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { - int ret = mxc_gpio_direction(gp, MXC_GPIO_DIRECTION_OUT); + int ret = mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT); if (ret < 0) return ret; - gpio_set_value(gp, value); + gpio_set_value(gpio, value); return 0; } diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 539738b..0365812 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -69,68 +69,64 @@ void mxs_gpio_init(void) } } -int gpio_get_value(int gp) +int gpio_get_value(unsigned gpio) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DIN(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); - return (readl(®->reg) >> PAD_PIN(gp)) & 1; + return (readl(®->reg) >> PAD_PIN(gpio)) & 1; } -void gpio_set_value(int gp, int value) +void gpio_set_value(unsigned gpio, int value) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOUT(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); if (value) - writel(1 << PAD_PIN(gp), ®->reg_set); + writel(1 << PAD_PIN(gpio), ®->reg_set); else - writel(1 << PAD_PIN(gp), ®->reg_clr); + writel(1 << PAD_PIN(gpio), ®->reg_clr); } -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gp), ®->reg_clr); + writel(1 << PAD_PIN(gpio), ®->reg_clr); return 0; } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gp), ®->reg_set); + writel(1 << PAD_PIN(gpio), ®->reg_set); - gpio_set_value(gp, value); + gpio_set_value(gpio, value); return 0; } -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (PAD_BANK(gp) >= PINCTRL_BANKS) - return -EINVAL; + if (PAD_BANK(gpio) >= PINCTRL_BANKS) + return -1; return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { -} - -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); + return 0; } diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 1edf9a2..47f3213 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -20,7 +20,7 @@ #include #include -#include +#include #define CON_MASK(x) (0xf << ((x) << 2)) #define CON_SFR(x, v) ((v) << ((x) << 2)) @@ -142,46 +142,55 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -struct s5p_gpio_bank *s5p_gpio_get_bank(int nr) +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) { - int bank = nr / GPIO_PER_BANK; + int bank = gpio / GPIO_PER_BANK; bank *= sizeof(struct s5p_gpio_bank); - return (struct s5p_gpio_bank *) (s5p_gpio_base(nr) + bank); + return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); } -int s5p_gpio_get_pin(int nr) +int s5p_gpio_get_pin(unsigned gpio) { - return nr % GPIO_PER_BANK; + return gpio % GPIO_PER_BANK; } -int gpio_request(int gpio, const char *label) +/* Common GPIO API */ + +int gpio_request(unsigned gpio, const char *label) { return 0; } -int gpio_direction_input(int nr) +int gpio_free(unsigned gpio) { - s5p_gpio_direction_input(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr)); return 0; } -int gpio_direction_output(int nr, int value) +int gpio_direction_input(unsigned gpio) { - s5p_gpio_direction_output(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr), value); + s5p_gpio_direction_input(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio)); return 0; } -int gpio_get_value(int nr) +int gpio_direction_output(unsigned gpio, int value) { - return (int) s5p_gpio_get_value(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr)); + s5p_gpio_direction_output(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), value); + return 0; } -void gpio_set_value(int nr, int value) +int gpio_get_value(unsigned gpio) { - s5p_gpio_set_value(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr), value); + return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio)); +} + +int gpio_set_value(unsigned gpio, int value) +{ + s5p_gpio_set_value(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), value); + + return 0; } diff --git a/drivers/gpio/tegra2_gpio.c b/drivers/gpio/tegra2_gpio.c index 22669b6..70ca46f 100644 --- a/drivers/gpio/tegra2_gpio.c +++ b/drivers/gpio/tegra2_gpio.c @@ -49,188 +49,192 @@ static char *get_name(int i) return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; } -/* Return config of pin 'gp' as GPIO (1) or SFPIO (0) */ -static int get_config(int gp) +/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ +static int get_config(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; int type; - u = readl(&bank->gpio_config[GPIO_PORT(gp)]); - type = (u >> GPIO_BIT(gp)) & 1; + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); + type = (u >> GPIO_BIT(gpio)) & 1; debug("get_config: port = %d, bit = %d is %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), type ? "GPIO" : "SFPIO"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); return type; } -/* Config pin 'gp' as GPIO or SFPIO, based on 'type' */ -static void set_config(int gp, int type) +/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ +static void set_config(unsigned gpio, int type) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; debug("set_config: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), type ? "GPIO" : "SFPIO"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - u = readl(&bank->gpio_config[GPIO_PORT(gp)]); + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); if (type) /* GPIO */ - u |= 1 << GPIO_BIT(gp); + u |= 1 << GPIO_BIT(gpio); else - u &= ~(1 << GPIO_BIT(gp)); - writel(u, &bank->gpio_config[GPIO_PORT(gp)]); + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); } -/* Return GPIO pin 'gp' direction - 0 = input or 1 = output */ -static int get_direction(int gp) +/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ +static int get_direction(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; int dir; - u = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); - dir = (u >> GPIO_BIT(gp)) & 1; + u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); + dir = (u >> GPIO_BIT(gpio)) & 1; debug("get_direction: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), dir ? "OUT" : "IN"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); return dir; } -/* Config GPIO pin 'gp' as input or output (OE) as per 'output' */ -static void set_direction(int gp, int output) +/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ +static void set_direction(unsigned gpio, int output) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; debug("set_direction: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), output ? "OUT" : "IN"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); - u = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); + u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); if (output) - u |= 1 << GPIO_BIT(gp); + u |= 1 << GPIO_BIT(gpio); else - u &= ~(1 << GPIO_BIT(gp)); - writel(u, &bank->gpio_dir_out[GPIO_PORT(gp)]); + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); } -/* set GPIO pin 'gp' output bit as 0 or 1 as per 'high' */ -static void set_level(int gp, int high) +/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ +static void set_level(unsigned gpio, int high) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; debug("set_level: port = %d, bit %d == %d\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), high); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); - u = readl(&bank->gpio_out[GPIO_PORT(gp)]); + u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); if (high) - u |= 1 << GPIO_BIT(gp); + u |= 1 << GPIO_BIT(gpio); else - u &= ~(1 << GPIO_BIT(gp)); - writel(u, &bank->gpio_out[GPIO_PORT(gp)]); + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } /* * Generic_GPIO primitives. */ -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (gp >= MAX_NUM_GPIOS) + if (gpio >= MAX_NUM_GPIOS) return -1; if (label != NULL) { - strncpy(gpio_names[gp].name, label, GPIO_NAME_SIZE); - gpio_names[gp].name[GPIO_NAME_SIZE - 1] = '\0'; + strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE); + gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0'; } /* Configure as a GPIO */ - set_config(gp, 1); + set_config(gpio, 1); return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { + if (gpio >= MAX_NUM_GPIOS) + return -1; + + gpio_names[gpio].name[0] = '\0'; + /* Do not configure as input or change pin mux here */ + return 0; } -/* read GPIO OUT value of pin 'gp' */ -static int gpio_get_output_value(int gp) +/* read GPIO OUT value of pin 'gpio' */ +static int gpio_get_output_value(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; int val; debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&bank->gpio_out[GPIO_PORT(gp)]); + val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); - return (val >> GPIO_BIT(gp)) & 1; + return (val >> GPIO_BIT(gpio)) & 1; } -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_output_value(gp)); -} - -/* set GPIO pin 'gp' as an input */ -int gpio_direction_input(int gp) +/* set GPIO pin 'gpio' as an input */ +int gpio_direction_input(unsigned gpio) { debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); /* Configure GPIO direction as input. */ - set_direction(gp, 0); + set_direction(gpio, 0); return 0; } -/* set GPIO pin 'gp' as an output, with polarity 'value' */ -int gpio_direction_output(int gp, int value) +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int gpio_direction_output(unsigned gpio, int value) { debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp), value ? "HIGH" : "LOW"); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), + value ? "HIGH" : "LOW"); /* Configure GPIO output value. */ - set_level(gp, value); + set_level(gpio, value); /* Configure GPIO direction as output. */ - set_direction(gp, 1); + set_direction(gpio, 1); return 0; } -/* read GPIO IN value of pin 'gp' */ -int gpio_get_value(int gp) +/* read GPIO IN value of pin 'gpio' */ +int gpio_get_value(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; int val; debug("gpio_get_value: pin = %d (port %d:bit %d)\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&bank->gpio_in[GPIO_PORT(gp)]); + val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); - return (val >> GPIO_BIT(gp)) & 1; + return (val >> GPIO_BIT(gpio)) & 1; } -/* write GPIO OUT value to pin 'gp' */ -void gpio_set_value(int gp, int value) +/* write GPIO OUT value to pin 'gpio' */ +int gpio_set_value(unsigned gpio, int value) { debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp), value); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); /* Configure GPIO output value. */ - set_level(gp, value); + set_level(gpio, value); + + return 0; } /* @@ -238,7 +242,8 @@ void gpio_set_value(int gp, int value) */ void gpio_info(void) { - int c, type; + unsigned c; + int type; for (c = 0; c < MAX_NUM_GPIOS; c++) { type = get_config(c); /* GPIO, not SFPIO */ -- cgit v0.10.2 From 4b5657938853ea3f478d86408e6534cb3a89ec11 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 11 Nov 2011 15:55:37 -0600 Subject: mpc83xx: Add a GPIO driver for the MPC83XX family Signed-off-by: Joe Hershberger Cc: Joe Hershberger Signed-off-by: Kim Phillips diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h new file mode 100644 index 0000000..036f51e --- /dev/null +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -0,0 +1,38 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MPC83XX_GPIO_H_ +#define _MPC83XX_GPIO_H_ + +/* + * The MCP83xx's 1-2 GPIO controllers each with 32 bits. + */ +#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \ + defined(CONFIG_MPC8315) +#define MPC83XX_GPIO_CTRLRS 1 +#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) +#define MPC83XX_GPIO_CTRLRS 2 +#else +#define MPC83XX_GPIO_CTRLRS 0 +#endif + +#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS) + +void mpc83xx_gpio_init_f(void); +void mpc83xx_gpio_init_r(void); + +#endif /* MPC83XX_GPIO_H_ */ diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h new file mode 100644 index 0000000..d49ad08 --- /dev/null +++ b/arch/powerpc/include/asm/gpio.h @@ -0,0 +1,2 @@ +#include +#include diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index e22c096..4375a55 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o +COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c new file mode 100644 index 0000000..a9afcb2 --- /dev/null +++ b/drivers/gpio/mpc83xx_gpio.c @@ -0,0 +1,199 @@ +/* + * Freescale MPC83xx GPIO handling. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifndef CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION +#define CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION +#define CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN +#define CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN +#define CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_0_INIT_VALUE +#define CONFIG_MPC83XX_GPIO_0_INIT_VALUE 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_1_INIT_VALUE +#define CONFIG_MPC83XX_GPIO_1_INIT_VALUE 0 +#endif + +static unsigned int gpio_output_value[MPC83XX_GPIO_CTRLRS]; + +/* + * Generic_GPIO primitives. + */ + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio >= MAX_NUM_GPIOS) + return -1; + + return 0; +} + +int gpio_free(unsigned gpio) +{ + /* Do not set to input */ + return 0; +} + +/* set GPIO pin 'gpio' as an input */ +int gpio_direction_input(unsigned gpio) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + clrbits_be32(&im->gpio[ctrlr].dir, line_mask); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int gpio_direction_output(unsigned gpio, int value) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + if (value != 0 && value != 1) { + printf("Error: Value parameter must be 0 or 1.\n"); + return -1; + } + + gpio_set_value(gpio, value); + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + /* Make the line output */ + setbits_be32(&im->gpio[ctrlr].dir, line_mask); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +int gpio_get_value(unsigned gpio) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + /* Read the value and mask off the bit */ + return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0; +} + +/* write GPIO OUT value to pin 'gpio' */ +int gpio_set_value(unsigned gpio, int value) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + if (value != 0 && value != 1) { + printf("Error: Value parameter must be 0 or 1.\n"); + return -1; + } + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + /* Update the local output buffer soft copy */ + gpio_output_value[ctrlr] = + (gpio_output_value[ctrlr] & ~line_mask) | \ + (value ? line_mask : 0); + + /* Write the output */ + out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]); + + return 0; +} + +/* Configure GPIO registers early */ +void mpc83xx_gpio_init_f() +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + +#if MPC83XX_GPIO_CTRLRS >= 1 + out_be32(&im->gpio[0].dir, CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION); + out_be32(&im->gpio[0].odr, CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN); + out_be32(&im->gpio[0].dat, CONFIG_MPC83XX_GPIO_0_INIT_VALUE); + out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */ + out_be32(&im->gpio[0].imr, 0); + out_be32(&im->gpio[0].icr, 0); +#endif + +#if MPC83XX_GPIO_CTRLRS >= 2 + out_be32(&im->gpio[1].dir, CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION); + out_be32(&im->gpio[1].odr, CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN); + out_be32(&im->gpio[1].dat, CONFIG_MPC83XX_GPIO_1_INIT_VALUE); + out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */ + out_be32(&im->gpio[1].imr, 0); + out_be32(&im->gpio[1].icr, 0); +#endif +} + +/* Initialize GPIO soft-copies */ +void mpc83xx_gpio_init_r() +{ +#if MPC83XX_GPIO_CTRLRS >= 1 + gpio_output_value[0] = CONFIG_MPC83XX_GPIO_0_INIT_VALUE; +#endif + +#if MPC83XX_GPIO_CTRLRS >= 2 + gpio_output_value[1] = CONFIG_MPC83XX_GPIO_1_INIT_VALUE; +#endif +} -- cgit v0.10.2 From 0eaf8f9ea8e17f642f65c058cc6ed70e5e1441e7 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 11 Nov 2011 15:55:38 -0600 Subject: mpc8313erdb: Enable GPIO support on the MPC8313E RDB Signed-off-by: Joe Hershberger Cc: Joe Hershberger Signed-off-by: Kim Phillips diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 08f873d..730ec4e 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -31,6 +31,9 @@ #include #include #include +#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL) +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +45,18 @@ int board_early_init_f(void) if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; #endif +#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL) + mpc83xx_gpio_init_f(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL) + mpc83xx_gpio_init_r(); +#endif return 0; } diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 31503af..39bdcf8 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -82,7 +82,8 @@ #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ #define CONFIG_SYS_IMMR 0xE0000000 @@ -363,6 +364,9 @@ #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CONFIG_MPC83XX_GPIO 1 +#define CONFIG_CMD_GPIO 1 + /* * Serial Port */ @@ -581,7 +585,8 @@ /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ -#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ + /* Enable Internal USB Phy and GPIO on LCD Connector */ +#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) #define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ -- cgit v0.10.2 From 513e396b4fda8fe06d3e336ba74d31c75ef757db Mon Sep 17 00:00:00 2001 From: Marco Schmid Date: Wed, 14 Dec 2011 16:21:42 +0100 Subject: powerpc/83xx/km: update SDRAM parameters for km8321 boards Measurements during HW basic test showed, that the SDRAM timing has to be optimized. This patch adapted these timings accordingly. Signed-off-by: Marco Schmid Signed-off-by: Holger Brunck cc: Valentin Longchamp Acked-by: Heiko Schocher Signed-off-by: Kim Phillips diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 902ae26..580b72f 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -70,7 +70,8 @@ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN) + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -82,7 +83,7 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE 0x47860242 #define CONFIG_SYS_DDR_MODE2 0x8080c000 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ @@ -94,20 +95,20 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (2 << TIMING_CFG1_WRREC_SHIFT) | \ - (6 << TIMING_CFG1_REFREC_SHIFT) | \ - (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (2 << TIMING_CFG1_PRETOACT_SHIFT)) + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT)) @@ -122,7 +123,10 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + #define CONFIG_SYS_LBC_LBCR 0x00000000 /* -- cgit v0.10.2 From d926d186d77e6b2e43a6300bda2f662992ae5115 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Wed, 14 Dec 2011 16:21:43 +0100 Subject: powerpc/83xx/km: remove obsolete defines for tuda1 CONFIG_SYS_LCRR is unused and CONFIG_SYS_LBC_LBCR is already defined in the common header file, so remove them. Signed-off-by: Holger Brunck cc: Valentin Longchamp Acked-by: Heiko Schocher Signed-off-by: Kim Phillips diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h index 577bbd0..2581d8a 100644 --- a/include/configs/tuda1.h +++ b/include/configs/tuda1.h @@ -41,12 +41,6 @@ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * Init Local Bus Memory Controller: * * Bank Bus Machine PortSz Size Device -- cgit v0.10.2 From 5f2a44d5ea2893370b5c443cc659b3ab6b3944e2 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Wed, 14 Dec 2011 16:21:44 +0100 Subject: powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1 These boards are from a u-boot point of view identical. So collect the two headerfiles to one, to decrease maintenance. Signed-off-by: Holger Brunck cc: Valentin Longchamp cc: Heiko Schocher Signed-off-by: Kim Phillips diff --git a/MAINTAINERS b/MAINTAINERS index 4bf12b5..5cb70b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -436,11 +436,12 @@ Heiko Schocher municse MPC5200 sc3 PPC405GP suvd3 MPC8321 - tuda1 MPC8321 - tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 +Holger Brunck + tuxx1 MPC8321 + Peter De Schrijver ML2 PPC4xx diff --git a/boards.cfg b/boards.cfg index 0b32532..0eeb4c7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -593,8 +593,7 @@ MPC837XERDB powerpc mpc83xx mpc837xerdb freesca kmeter1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile suvd3 powerpc mpc83xx km83xx keymile -tuda1 powerpc mpc83xx km83xx keymile -tuxa1 powerpc mpc83xx km83xx keymile +tuxx1 powerpc mpc83xx km83xx keymile MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h deleted file mode 100644 index 2581d8a..0000000 --- a/include/configs/tuda1.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2011 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_TUDA1 /* TUDA1 board specific */ -#define CONFIG_HOSTNAME tuda1 -#define CONFIG_KM_BOARD_NAME "tuda1" - -#define CONFIG_SYS_TEXT_BASE 0xF0000000 - -/* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" - -#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local GPCM 8 bit 256MB PAXG - * 3 Local GPCM 8 bit 256MB PINC3 - * - */ - -/* - * PAXG on the local bus CS2 - */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) -/* - * PINC3 on the local bus CS3 - */ -/* Access window base at PINC3 base */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR) - -#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ - 0x0000c000 | \ - MxMR_WLFx_2X) - -/* - * MMU Setup - */ -/* PAXG: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* PINC3: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_H */ diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h deleted file mode 100644 index 2d9af3f..0000000 --- a/include/configs/tuxa1.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010 - * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_TUXA1 /* TUXA1 board specific */ -#define CONFIG_HOSTNAME tuxa1 -#define CONFIG_KM_BOARD_NAME "tuxa1" - -#define CONFIG_SYS_TEXT_BASE 0xF0000000 - -/* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" - -#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ -#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ -#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local GPCM 8 bit 256MB LPXF - * 3 Local GPCM 8 bit 256MB PINC2 - * - */ - -/* - * LPXF on the local bus CS2 - * Window base at flash base - * Window size: 256 MB - */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) -/* - * PINC2 on the local bus CS3 - * Access window base at PINC2 base - * Window size: 256 MB - */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR) - -#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ - 0x0000c000 | \ - MxMR_WLFx_2X) - -/* - * MMU Setup - */ -/* LPXF: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* PINC2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h new file mode 100644 index 0000000..b07f6b3 --- /dev/null +++ b/include/configs/tuxx1.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2011 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_TUXXX /* TUXX1 board specific */ +#define CONFIG_HOSTNAME tuxx1 +#define CONFIG_KM_BOARD_NAME "tuxx1" + +#define CONFIG_SYS_TEXT_BASE 0xF0000000 + +/* include common defines/options for all 8321 Keymile boards */ +#include "km/km8321-common.h" + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 + * ---- --- ------- ------ ----- --------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 + * + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) +/* + * Configuration for C3 on the local bus + */ +/* Access window base at PINC3 base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From f5a474bd7ac44385ea8e852129ab4f6ae5c6d6d3 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Wed, 14 Dec 2011 16:21:45 +0100 Subject: powerpc/83xx/km: add support for 8321 based tuge1 board This board is similar to our tuxx1 target. But on this board there is only one application specific chip select configured. Signed-off-by: Holger Brunck cc: Valentin Longchamp Acked-by: Heiko Schocher Signed-off-by: Kim Phillips diff --git a/MAINTAINERS b/MAINTAINERS index 5cb70b0..28729d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -440,6 +440,7 @@ Heiko Schocher ve8313 MPC8313 Holger Brunck + tuge1 MPC8321 tuxx1 MPC8321 Peter De Schrijver diff --git a/boards.cfg b/boards.cfg index 0eeb4c7..35bc525 100644 --- a/boards.cfg +++ b/boards.cfg @@ -593,6 +593,7 @@ MPC837XERDB powerpc mpc83xx mpc837xerdb freesca kmeter1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile suvd3 powerpc mpc83xx km83xx keymile +tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2 tuxx1 powerpc mpc83xx km83xx keymile MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index b07f6b3..f6d2b17 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -27,9 +27,13 @@ /* * High Level Configuration Options */ -#define CONFIG_TUXXX /* TUXX1 board specific */ +#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */ #define CONFIG_HOSTNAME tuxx1 +#ifdef CONFIG_KM_DISABLE_APP2 +#define CONFIG_KM_BOARD_NAME "tuge1" +#else #define CONFIG_KM_BOARD_NAME "tuxx1" +#endif #define CONFIG_SYS_TEXT_BASE 0xF0000000 @@ -38,16 +42,18 @@ #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#ifndef CONFIG_KM_DISABLE_APP2 #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ +#endif /* * Init Local Bus Memory Controller: * - * Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 - * ---- --- ------- ------ ----- --------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 + * Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1 + * ---- --- ------- ------ ----- ---------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused * */ @@ -71,6 +77,7 @@ OR_GPCM_TRLX_SET | \ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) +#ifndef CONFIG_KM_DISABLE_APP2 /* * Configuration for C3 on the local bus */ @@ -94,6 +101,7 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) +#endif /* * MMU Setup @@ -113,6 +121,11 @@ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#ifdef CONFIG_KM_DISABLE_APP2 +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#else /* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_RW | \ @@ -125,6 +138,7 @@ BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) +#endif #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U #define CONFIG_SYS_IBAT7L (0) -- cgit v0.10.2 From c947c12e7805e5562b5c803f74eaceba8c66ba56 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 4 Jan 2012 16:48:26 -0600 Subject: mpc8313erdb: fix mtdparts address Fix a copy-and-paste error when adapting mpc8315erdb mtdparts to mpc8313erdb. mtdids was already using the proper address on mpc8313erdb. Signed-off-by: Scott Wood Signed-off-by: Kim Phillips diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 39bdcf8..863c9b9 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -267,7 +267,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e2800000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -- cgit v0.10.2