From 674ef7bd02de948b6d8757f6a43a6f2fa4d88769 Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Mon, 18 Jan 2010 19:03:28 +0800 Subject: Nand boot: Add nand boot support for MPC8569mds board This patch add nand boot support for MPC8569mds board. Signed-off-by: Liu Yu diff --git a/MAKEALL b/MAKEALL index 15e93cf..aac52bb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -404,6 +404,7 @@ LIST_85xx=" \ MPC8568MDS \ MPC8569MDS \ MPC8569MDS_ATM \ + MPC8569MDS_NAND \ MPC8572DS \ MPC8572DS_36BIT \ P2020DS \ diff --git a/Makefile b/Makefile index 69b963f..c4ef585 100644 --- a/Makefile +++ b/Makefile @@ -2490,6 +2490,7 @@ MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale MPC8569MDS_ATM_config \ +MPC8569MDS_NAND_config \ MPC8569MDS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk index 962f79b..7de0f7c 100644 --- a/board/freescale/mpc8569mds/config.mk +++ b/board/freescale/mpc8569mds/config.mk @@ -23,4 +23,13 @@ # # mpc8569mds board # +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +endif +endif + +ifndef TEXT_BASE TEXT_BASE = 0xfff80000 +endif diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index 3b8ee05..73dcc3e 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ae2fc19..6cf807b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* * Only possible on E500 Version 2 or newer cores. */ @@ -74,16 +80,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_END 0x00400000 /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) @@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE /*Chip select 0 - Flash*/ -#define CONFIG_SYS_BR0_PRELIM 0xfe000801 -#define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 +#define CONFIG_FLASH_BR_PRELIM 0xfe000801 +#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 /*Chip select 1 - BCSR*/ #define CONFIG_SYS_BR1_PRELIM 0xf8000801 @@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO /* Chip select 3 - NAND */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xFC000000 +#else +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#endif + +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void); | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR) + +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif /* * SDRAM on the LocalBus @@ -437,10 +487,18 @@ extern unsigned long get_clock_freq(void); /* * Environment */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile new file mode 100644 index 0000000..7ed9d61 --- /dev/null +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -0,0 +1,133 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c new file mode 100644 index 0000000..e030656 --- /dev/null +++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c @@ -0,0 +1,75 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCLK_66 66666666 + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + uint plat_ratio, bus_clk, sys_clk; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + sys_clk = SYSCLK_66; + + plat_ratio = gur->porpllsr & 0x0000003e; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to DDR and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} -- cgit v0.10.2 From 15b86c3d6c9a5a2e917b73d758a556568430021a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 16 Jan 2010 21:50:26 -0700 Subject: env_nand.c: print error message and fail gracefully env_nand.c would crash silently if a malloc() for the environment buffers failed; make it print an error message and fail gracefully, i. e. use the default environment then. Signed-off-by: Wolfgang Denk Acked-by: John Rigby diff --git a/common/env_nand.c b/common/env_nand.c index ca631af..a15a950 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -298,6 +298,13 @@ void env_relocate_spec (void) tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE); tmp_env2 = (env_t *) malloc(CONFIG_ENV_SIZE); + if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) { + puts("Can't allocate buffers for environment\n"); + free (tmp_env1); + free (tmp_env2); + return use_default(); + } + if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1)) puts("No Valid Environment Area Found\n"); if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2)) -- cgit v0.10.2 From ef22b50370f7b6d8deba9e9e64d2cb13c542b647 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Mon, 25 Jan 2010 23:12:52 -0700 Subject: arm926ejs: add nand_spl boot support Add CONFIG_PRELOADER/CONFIG_NAND_SPL support for nand booting to arm926ejs/start.S This is derived from CONFIG_PRELOADER support in arm1136/start.S Signed-off-by: John Rigby CC: Scott Wood diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 4421b6a..3b81151 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -53,6 +53,27 @@ .globl _start _start: b reset +#ifdef CONFIG_PRELOADER +/* No exception handlers in preloader */ + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang +/* pad to 64 byte boundary */ + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 +#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -76,6 +97,7 @@ _irq: _fiq: .word fiq +#endif /* CONFIG_PRELOADER */ .balignl 16,0xdeadbeef @@ -150,7 +172,6 @@ relocate: /* relocate U-Boot to RAM */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ beq stack_setup - ldr r2, _armboot_start ldr r3, _bss_start sub r2, r3, r2 /* r2 <- size of armboot */ @@ -166,11 +187,14 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub sp, r0, #128 /* leave 32 words for abort-stack */ +#ifndef CONFIG_PRELOADER sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif +#endif /* CONFIG_PRELOADER */ sub sp, r0, #12 /* leave 3 words for abort-stack */ bic sp, r0, #7 /* 8-byte align stack for ABI compliance */ @@ -179,6 +203,7 @@ clear_bss: ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ +#ifndef CONFIG_PRELOADER clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 @@ -186,11 +211,16 @@ clbss_l:str r2, [r0] /* clear loop... */ bl coloured_LED_init bl red_LED_on +#endif /* CONFIG_PRELOADER */ ldr pc, _start_armboot _start_armboot: +#ifdef CONFIG_NAND_SPL + .word nand_boot +#else .word start_armboot +#endif /* CONFIG_NAND_SPL */ /* @@ -231,6 +261,7 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#ifndef CONFIG_PRELOADER /* ************************************************************************* * @@ -332,10 +363,18 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm +#endif /* CONFIG_PRELOADER */ /* * exception handlers */ +#ifdef CONFIG_PRELOADER + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ +#else /* !CONFIG_PRELOADER */ .align 5 undefined_instruction: get_bad_stack @@ -398,3 +437,4 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_PRELOADER */ -- cgit v0.10.2 From f3bb63a304c4e76010a2a4e99da61f7b6ffffc77 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Tue, 26 Jan 2010 19:24:17 -0700 Subject: Add MX25 support to nand_spl fsl nfc driver MX25 has a different version of the fsl_nfc flash controller known as version 1.1. Add support to the nand_spl fsl_nfc driver Versioning differs from mainline mxc kernel driver no consensus yet on if the naming here and in Redboot or the kernel is "correct". Signed-off-by: John Rigby Signed-off-by: Wolfgang Denk CC: Scott Wood diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index da5be37..279aaa5 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -1,5 +1,4 @@ /* - * * (c) 2009 Magnus Lilja * * See file CREDITS for list of people who contributed to this @@ -25,21 +24,57 @@ #define __FSL_NFC_H /* + * TODO: Use same register defs for nand_spl mxc nand driver + * and mtd mxc nand driver. + * * Register map and bit definitions for the Freescale NAND Flash - * Controller present in i.MX31 and other devices. + * Controller present in various i.MX devices. + * + * MX31 and MX27 have version 1 which has + * 4 512 byte main buffers and + * 4 16 byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. + * + * MX25 has version 1.1 which has + * 8 512 byte main buffers and + * 8 64 byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. */ +#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#define MXC_NFC_V1 +#elif defined(CONFIG_MX25) +#define MXC_NFC_V1_1 +#else +#warning "MXC NFC version not defined" +#endif + +#if defined(MXC_NFC_V1) +#define NAND_MXC_NR_BUFS 4 +#define NAND_MXC_SPARE_BUF_SIZE 16 +#define NAND_MXC_REG_OFFSET 0xe00 +#define NAND_MXC_2K_MULTI_CYCLE 1 +#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_NR_BUFS 8 +#define NAND_MXC_SPARE_BUF_SIZE 64 +#define NAND_MXC_REG_OFFSET 0x1e00 +#else +#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver" +#endif struct fsl_nfc_regs { - u32 main_area0[128]; /* @0x000 */ - u32 main_area1[128]; - u32 main_area2[128]; - u32 main_area3[128]; - u32 spare_area0[4]; - u32 spare_area1[4]; - u32 spare_area2[4]; - u32 spare_area3[4]; - u32 reserved1[64 - 16 + 64 * 5]; - u16 bufsiz; /* @ 0xe00 */ + u32 main_area[NAND_MXC_NR_BUFS][512/4]; + u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4]; + /* + * reserved size is offset of nfc registers + * minus total main and spare sizes + */ + u8 reserved1[NAND_MXC_REG_OFFSET + - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; +#if defined(MXC_NFC_V1) + u16 bufsiz; u16 reserved2; u16 buffer_address; u16 flash_add; @@ -54,6 +89,30 @@ struct fsl_nfc_regs { u16 nand_flash_wr_pr_st; u16 nand_flash_config1; u16 nand_flash_config2; +#elif defined(MXC_NFC_V1_1) + u16 reserved2[2]; + u16 buffer_address; + u16 flash_add; + u16 flash_cmd; + u16 configuration; + u16 ecc_status_result; + u16 ecc_status_result2; + u16 spare_area_size; + u16 nf_wr_prot; + u16 reserved3[2]; + u16 nand_flash_wr_pr_st; + u16 nand_flash_config1; + u16 nand_flash_config2; + u16 reserved4; + u16 unlock_start_blk_add0; + u16 unlock_end_blk_add0; + u16 unlock_start_blk_add1; + u16 unlock_end_blk_add1; + u16 unlock_start_blk_add2; + u16 unlock_end_blk_add2; + u16 unlock_start_blk_add3; + u16 unlock_end_blk_add3; +#endif }; /* @@ -98,6 +157,9 @@ struct fsl_nfc_regs { */ #define NFC_INT 0x8000 +#ifdef MXC_NFC_V1_1 +#define NFC_4_8N_ECC (1 << 0) +#endif #define NFC_SP_EN (1 << 2) #define NFC_ECC_EN (1 << 3) #define NFC_INT_MSK (1 << 4) diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index a9df2a8..f4040a7 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -26,11 +26,15 @@ #include #include +#ifdef CONFIG_MX31 #include +#else +#include +#endif #include #include -static struct fsl_nfc_regs *nfc; +struct fsl_nfc_regs *nfc; static void nfc_wait_ready(void) { @@ -45,13 +49,35 @@ static void nfc_wait_ready(void) writew(tmp, &nfc->nand_flash_config2); } -static void nfc_nand_init(void) +void nfc_nand_init(void) { +#if defined(MXC_NFC_V1_1) + int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; + int config1; + + writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + + /* unlocking RAM Buff */ + writew(0x2, &nfc->configuration); + + /* hardware ECC checking and correct */ + config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800; + /* + * if spare size is larger that 16 bytes per 512 byte hunk + * then use 8 symbol correction instead of 4 + */ + if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16) + config1 &= ~NFC_4_8N_ECC; + else + config1 |= NFC_4_8N_ECC; + writew(config1, &nfc->nand_flash_config1); +#elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ writew(0x2, &nfc->configuration); /* hardware ECC checking and correct */ writew(NFC_ECC_EN, &nfc->nand_flash_config1); +#endif } static void nfc_nand_command(unsigned short command) @@ -65,12 +91,12 @@ static void nfc_nand_page_address(unsigned int page_address) { unsigned int page_count; - writew(0x00, &nfc->flash_cmd); + writew(0x00, &nfc->flash_add); writew(NFC_ADDR, &nfc->nand_flash_config2); nfc_wait_ready(); - /* code only for 2kb flash */ - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) { + /* code only for large page flash */ + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) { writew(0x00, &nfc->flash_add); writew(NFC_ADDR, &nfc->nand_flash_config2); nfc_wait_ready(); @@ -88,22 +114,38 @@ static void nfc_nand_page_address(unsigned int page_address) page_count = page_count >> 8; } while (page_count); } + + writew(0x00, &nfc->flash_add); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); } static void nfc_nand_data_output(void) { + int config1 = readw(&nfc->nand_flash_config1); +#ifdef NAND_MXC_2K_MULTI_CYCLE int i; +#endif + config1 |= NFC_ECC_EN | NFC_INT_MSK; + writew(config1, &nfc->nand_flash_config1); + writew(0, &nfc->buffer_address); + writew(NFC_OUTPUT, &nfc->nand_flash_config2); + nfc_wait_ready(); +#ifdef NAND_MXC_2K_MULTI_CYCLE /* - * The NAND controller requires four output commands for - * large page devices. + * This NAND controller requires multiple input commands + * for pages larger than 512 bytes. */ - for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { - writew(NFC_ECC_EN, &nfc->nand_flash_config1); - writew(i, &nfc->buffer_address); /* read in i:th buffer */ + for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { + config1 = readw(&nfc->nand_flash_config1); + config1 |= NFC_ECC_EN | NFC_INT_MSK; + writew(config1, &nfc->nand_flash_config1); + writew(i, &nfc->buffer_address); writew(NFC_OUTPUT, &nfc->nand_flash_config2); nfc_wait_ready(); } +#endif } static int nfc_nand_check_ecc(void) @@ -121,7 +163,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf) nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address); - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) nfc_nand_command(NAND_CMD_READSTART); nfc_nand_data_output(); /* fill the main buffer 0 */ @@ -129,7 +171,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf) if (nfc_nand_check_ecc()) return -1; - src = &nfc->main_area0[0]; + src = &nfc->main_area[0][0]; dst = (u32 *)buf; /* main copy loop from NAND-buffer to SDRAM memory */ @@ -154,12 +196,12 @@ static int is_badblock(int pagenumber) nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page); - if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) nfc_nand_command(NAND_CMD_READSTART); nfc_nand_data_output(); /* fill the main buffer 0 */ - src = &nfc->spare_area0[0]; + src = &nfc->spare_area[0][0]; /* * IMPORTANT NOTE: The nand flash controller uses a non- @@ -209,7 +251,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { /* * Yes, new block. See if this block is good. If not, - * loop until we find i good block. + * loop until we find a good block. */ while (is_badblock(page)) { page = page + CONFIG_SYS_NAND_PAGE_COUNT; -- cgit v0.10.2 From b081c2e9b9329d7dadc8d13fc9a2bae5c90a1204 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Tue, 26 Jan 2010 19:24:18 -0700 Subject: Nand mxc_nand add v1.1 controller support Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Signed-off-by: John Rigby CC: Scott Wood diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index b2b612e..9633858 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -22,27 +22,65 @@ #include #include #include -#ifdef CONFIG_MX27 +#if defined(CONFIG_MX27) || defined(CONFIG_MX25) #include #endif #define DRIVER_NAME "mxc_nand" +/* + * TODO: Use same register defs here as nand_spl mxc nand driver. + */ +/* + * Register map and bit definitions for the Freescale NAND Flash Controller + * present in various i.MX devices. + * + * MX31 and MX27 have version 1 which has + * 4 512 byte main buffers and + * 4 16 byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. + * + * MX25 has version 1.1 which has + * 8 512 byte main buffers and + * 8 64 byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. + */ +#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#define MXC_NFC_V1 +#elif defined(CONFIG_MX25) +#define MXC_NFC_V1_1 +#else +#warning "MXC NFC version not defined" +#endif + +#if defined(MXC_NFC_V1) +#define NAND_MXC_NR_BUFS 4 +#define NAND_MXC_SPARE_BUF_SIZE 16 +#define NAND_MXC_REG_OFFSET 0xe00 +#define is_mxc_nfc_11() 0 +#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_NR_BUFS 8 +#define NAND_MXC_SPARE_BUF_SIZE 64 +#define NAND_MXC_REG_OFFSET 0x1e00 +#define is_mxc_nfc_11() 1 +#else +#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver" +#endif struct nfc_regs { -/* NFC RAM BUFFER Main area 0 */ - uint8_t main_area0[0x200]; - uint8_t main_area1[0x200]; - uint8_t main_area2[0x200]; - uint8_t main_area3[0x200]; -/* SPARE BUFFER Spare area 0 */ - uint8_t spare_area0[0x10]; - uint8_t spare_area1[0x10]; - uint8_t spare_area2[0x10]; - uint8_t spare_area3[0x10]; - uint8_t pad[0x5c0]; -/* NFC registers */ + uint8_t main_area[NAND_MXC_NR_BUFS][0x200]; + uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; + /* + * reserved size is offset of nfc registers + * minus total main and spare sizes + */ + uint8_t reserved1[NAND_MXC_REG_OFFSET + - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; +#if defined(MXC_NFC_V1) uint16_t nfc_buf_size; - uint16_t reserved; + uint16_t reserved2; uint16_t nfc_buf_addr; uint16_t nfc_flash_addr; uint16_t nfc_flash_cmd; @@ -56,6 +94,30 @@ struct nfc_regs { uint16_t nfc_nf_wrprst; uint16_t nfc_config1; uint16_t nfc_config2; +#elif defined(MXC_NFC_V1_1) + uint16_t reserved2[2]; + uint16_t nfc_buf_addr; + uint16_t nfc_flash_addr; + uint16_t nfc_flash_cmd; + uint16_t nfc_config; + uint16_t nfc_ecc_status_result; + uint16_t nfc_ecc_status_result2; + uint16_t nfc_spare_area_size; + uint16_t nfc_wrprot; + uint16_t reserved3[2]; + uint16_t nfc_nf_wrprst; + uint16_t nfc_config1; + uint16_t nfc_config2; + uint16_t reserved4; + uint16_t nfc_unlockstart_blkaddr; + uint16_t nfc_unlockend_blkaddr; + uint16_t nfc_unlockstart_blkaddr1; + uint16_t nfc_unlockend_blkaddr1; + uint16_t nfc_unlockstart_blkaddr2; + uint16_t nfc_unlockend_blkaddr2; + uint16_t nfc_unlockstart_blkaddr3; + uint16_t nfc_unlockend_blkaddr3; +#endif }; /* @@ -100,6 +162,11 @@ struct nfc_regs { */ #define NFC_INT 0x8000 +#ifdef MXC_NFC_V1_1 +#define NFC_4_8N_ECC (1 << 0) +#else +#define NFC_4_8N_ECC 0 +#endif #define NFC_SP_EN (1 << 2) #define NFC_ECC_EN (1 << 3) #define NFC_BIG (1 << 5) @@ -119,6 +186,7 @@ struct mxc_nand_host { int pagesize_2k; int clk_act; uint16_t col_addr; + unsigned int page_addr; }; static struct mxc_nand_host mxc_host; @@ -135,26 +203,45 @@ static struct mxc_nand_host *host = &mxc_host; #define SPARE_SINGLEBIT_ERROR 0x1 /* OOB placement block for use with hardware ecc generation */ -#ifdef CONFIG_MXC_NAND_HWECC +#if defined(MXC_NFC_V1) +#ifndef CONFIG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 5, .eccpos = {6, 7, 8, 9, 10}, - .oobfree = {{0, 5}, {11, 5}, } + .oobfree = { {0, 5}, {11, 5}, } }; #else -static struct nand_ecclayout nand_soft_eccoob = { - .eccbytes = 6, - .eccpos = {6, 7, 8, 9, 10, 11}, - .oobfree = {{0, 5}, {12, 4}, } +static struct nand_ecclayout nand_hw_eccoob2k = { + .eccbytes = 20, + .eccpos = { + 6, 7, 8, 9, 10, + 22, 23, 24, 25, 26, + 38, 39, 40, 41, 42, + 54, 55, 56, 57, 58, + }, + .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} }, }; #endif - -static struct nand_ecclayout nand_hw_eccoob_largepage = { - .eccbytes = 20, - .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, - 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, - .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } +#elif defined(MXC_NFC_V1_1) +#ifndef CONFIG_SYS_NAND_LARGEPAGE +static struct nand_ecclayout nand_hw_eccoob = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobfree = { {2, 5} } }; +#else +static struct nand_ecclayout nand_hw_eccoob2k = { + .eccbytes = 36, + .eccpos = { + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} }, +}; +#endif +#endif #ifdef CONFIG_MX27 static int is_16bit_nand(void) @@ -178,6 +265,17 @@ static int is_16bit_nand(void) else return 0; } +#elif defined(CONFIG_MX25) +static int is_16bit_nand(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL) + return 1; + else + return 0; +} #else #warning "8/16 bit NAND autodetection not supported" static int is_16bit_nand(void) @@ -258,7 +356,24 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, int spare_only) { - MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only); + if (spare_only) + MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only); + + if (is_mxc_nfc_11()) { + int i; + /* + * The controller copies the 64 bytes of spare data from + * the first 16 bytes of each of the 4 64 byte spare buffers. + * Copy the contiguous data starting in spare_area[0] to + * the four spare area buffers. + */ + for (i = 1; i < 4; i++) { + void __iomem *src = &host->regs->spare_area[0][i * 16]; + void __iomem *dst = &host->regs->spare_area[i][0]; + + mxc_nand_memcpy32(dst, src, 16); + } + } writew(buf_id, &host->regs->nfc_buf_addr); @@ -303,6 +418,22 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); + + if (is_mxc_nfc_11()) { + int i; + + /* + * The controller copies the 64 bytes of spare data to + * the first 16 bytes of each of the 4 spare buffers. + * Make the data contiguous starting in spare_area[0]. + */ + for (i = 1; i < 4; i++) { + void __iomem *src = &host->regs->spare_area[i][0]; + void __iomem *dst = &host->regs->spare_area[0][i * 16]; + + mxc_nand_memcpy32(dst, src, 16); + } + } } /* Request the NANDFC to perform a read of the NAND device ID. */ @@ -330,7 +461,7 @@ static void send_read_id(struct mxc_nand_host *host) */ static uint16_t get_dev_status(struct mxc_nand_host *host) { - void __iomem *main_buf = host->regs->main_area1; + void __iomem *main_buf = host->regs->main_area[1]; uint32_t store; uint16_t ret, tmp; /* Issue status request to NAND device */ @@ -379,6 +510,330 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) */ } +#ifdef MXC_NFC_V1_1 +static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) +{ + struct nand_chip *nand_chip = mtd->priv; + struct mxc_nand_host *host = nand_chip->priv; + uint16_t tmp = readw(&host->regs->nfc_config1); + + if (on) + tmp |= NFC_ECC_EN; + else + tmp &= ~NFC_ECC_EN; + writew(tmp, &host->regs->nfc_config1); +} + +static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + int page, int sndcmd) +{ + struct mxc_nand_host *host = chip->priv; + uint8_t *buf = chip->oob_poi; + int length = mtd->oobsize; + int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; + uint8_t *bufpoi = buf; + int i, toread; + + MTDDEBUG(MTD_DEBUG_LEVEL0, + "%s: Reading OOB area of page %u to oob %p\n", + __FUNCTION__, host->page_addr, buf); + + chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); + for (i = 0; i < chip->ecc.steps; i++) { + toread = min_t(int, length, chip->ecc.prepad); + if (toread) { + chip->read_buf(mtd, bufpoi, toread); + bufpoi += toread; + length -= toread; + } + bufpoi += chip->ecc.bytes; + host->col_addr += chip->ecc.bytes; + length -= chip->ecc.bytes; + + toread = min_t(int, length, chip->ecc.postpad); + if (toread) { + chip->read_buf(mtd, bufpoi, toread); + bufpoi += toread; + length -= toread; + } + } + if (length > 0) + chip->read_buf(mtd, bufpoi, length); + + _mxc_nand_enable_hwecc(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READOOB, + mtd->writesize + chip->ecc.prepad, page); + bufpoi = buf + chip->ecc.prepad; + length = mtd->oobsize - chip->ecc.prepad; + for (i = 0; i < chip->ecc.steps; i++) { + toread = min_t(int, length, chip->ecc.bytes); + chip->read_buf(mtd, bufpoi, toread); + bufpoi += eccpitch; + length -= eccpitch; + host->col_addr += chip->ecc.postpad + chip->ecc.prepad; + } + _mxc_nand_enable_hwecc(mtd, 1); + return 1; +} + +static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, + int page) +{ + struct mxc_nand_host *host = chip->priv; + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + uint8_t *oob = chip->oob_poi; + int steps, size; + int n; + + _mxc_nand_enable_hwecc(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr); + + for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { + host->col_addr = n * eccsize; + chip->read_buf(mtd, buf, eccsize); + buf += eccsize; + + host->col_addr = mtd->writesize + n * eccpitch; + if (chip->ecc.prepad) { + chip->read_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->read_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->read_buf(mtd, oob, size); + _mxc_nand_enable_hwecc(mtd, 0); + + return 0; +} + +static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, + int page) +{ + struct mxc_nand_host *host = chip->priv; + int n, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n", + host->page_addr, buf, oob); + + /* first read out the data area and the available portion of OOB */ + for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { + int stat; + + host->col_addr = n * eccsize; + + chip->read_buf(mtd, p, eccsize); + + host->col_addr = mtd->writesize + n * eccpitch; + + if (chip->ecc.prepad) { + chip->read_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + stat = chip->ecc.correct(mtd, p, oob, NULL); + + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->read_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + /* Calculate remaining oob bytes */ + n = mtd->oobsize - (oob - chip->oob_poi); + if (n) + chip->read_buf(mtd, oob, n); + + /* Then switch ECC off and read the OOB area to get the ECC code */ + _mxc_nand_enable_hwecc(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr); + eccsteps = chip->ecc.steps; + oob = chip->oob_poi + chip->ecc.prepad; + for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { + host->col_addr = mtd->writesize + + n * eccpitch + + chip->ecc.prepad; + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes + chip->ecc.postpad; + } + _mxc_nand_enable_hwecc(mtd, 1); + return 0; +} + +static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + struct mxc_nand_host *host = chip->priv; + int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; + int length = mtd->oobsize; + int i, len, status, steps = chip->ecc.steps; + const uint8_t *bufpoi = chip->oob_poi; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + for (i = 0; i < steps; i++) { + len = min_t(int, length, eccpitch); + + chip->write_buf(mtd, bufpoi, len); + bufpoi += len; + length -= len; + host->col_addr += chip->ecc.prepad + chip->ecc.postpad; + } + if (length > 0) + chip->write_buf(mtd, bufpoi, length); + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + return status & NAND_STATUS_FAIL ? -EIO : 0; +} + +static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + struct mxc_nand_host *host = chip->priv; + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + uint8_t *oob = chip->oob_poi; + int steps, size; + int n; + + for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { + host->col_addr = n * eccsize; + chip->write_buf(mtd, buf, eccsize); + buf += eccsize; + + host->col_addr = mtd->writesize + n * eccpitch; + + if (chip->ecc.prepad) { + chip->write_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + host->col_addr += eccbytes; + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->write_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->write_buf(mtd, oob, size); +} + +static void mxc_nand_write_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + struct mxc_nand_host *host = chip->priv; + int i, n, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad; + int eccsteps = chip->ecc.steps; + const uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); + + for (i = n = 0; + eccsteps; + n++, eccsteps--, i += eccbytes, p += eccsize) { + host->col_addr = n * eccsize; + + chip->write_buf(mtd, p, eccsize); + + host->col_addr = mtd->writesize + n * eccpitch; + + if (chip->ecc.prepad) { + chip->write_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->write_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->write_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + /* Calculate remaining oob bytes */ + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->write_buf(mtd, oob, i); +} + +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *nand_chip = mtd->priv; + struct mxc_nand_host *host = nand_chip->priv; + uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result); + int subpages = mtd->writesize / nand_chip->subpagesize; + int pg2blk_shift = nand_chip->phys_erase_shift - + nand_chip->page_shift; + + do { + if ((ecc_status & 0xf) > 4) { + static int last_bad = -1; + + if (last_bad != host->page_addr >> pg2blk_shift) { + last_bad = host->page_addr >> pg2blk_shift; + printk(KERN_DEBUG + "MXC_NAND: HWECC uncorrectable ECC error" + " in block %u page %u subpage %d\n", + last_bad, host->page_addr, + mtd->writesize / nand_chip->subpagesize + - subpages); + } + return -1; + } + ecc_status >>= 4; + subpages--; + } while (subpages > 0); + + return 0; +} +#else +#define mxc_nand_read_page_syndrome NULL +#define mxc_nand_read_page_raw_syndrome NULL +#define mxc_nand_read_oob_syndrome NULL +#define mxc_nand_write_page_syndrome NULL +#define mxc_nand_write_page_raw_syndrome NULL +#define mxc_nand_write_oob_syndrome NULL +#define mxc_nfc_11_nand_correct_data NULL + static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { @@ -400,6 +855,9 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, return 0; } +#endif + + static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) @@ -415,9 +873,9 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd) uint8_t ret = 0; uint16_t col; uint16_t __iomem *main_buf = - (uint16_t __iomem *)host->regs->main_area0; + (uint16_t __iomem *)host->regs->main_area[0]; uint16_t __iomem *spare_buf = - (uint16_t __iomem *)host->regs->spare_area0; + (uint16_t __iomem *)host->regs->spare_area[0]; union { uint16_t word; uint8_t bytes[2]; @@ -464,9 +922,10 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd) col += mtd->writesize; if (col < mtd->writesize) { - p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1)); + p = (uint16_t __iomem *)(host->regs->main_area[0] + + (col >> 1)); } else { - p = (uint16_t __iomem *)(host->regs->spare_area0 + + p = (uint16_t __iomem *)(host->regs->spare_area[0] + ((col - mtd->writesize) >> 1)); } @@ -525,9 +984,9 @@ static void mxc_nand_write_buf(struct mtd_info *mtd, void __iomem *p; if (col < mtd->writesize) { - p = host->regs->main_area0 + (col & ~3); + p = host->regs->main_area[0] + (col & ~3); } else { - p = host->regs->spare_area0 - + p = host->regs->spare_area[0] - mtd->writesize + (col & ~3); } @@ -595,9 +1054,9 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) void __iomem *p; if (col < mtd->writesize) { - p = host->regs->main_area0 + (col & ~3); + p = host->regs->main_area[0] + (col & ~3); } else { - p = host->regs->spare_area0 - + p = host->regs->spare_area[0] - mtd->writesize + (col & ~3); } @@ -683,7 +1142,7 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) * Used by the upper layer to write command to NAND Flash for * different operations to be carried out on NAND Flash */ -static void mxc_nand_command(struct mtd_info *mtd, unsigned command, +void mxc_nand_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) { struct nand_chip *nand_chip = mtd->priv; @@ -705,6 +1164,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, break; case NAND_CMD_READ0: + host->page_addr = page_addr; host->col_addr = column; host->spare_only = false; break; @@ -750,7 +1210,7 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_PAGEPROG: send_prog_page(host, 0, host->spare_only); - if (host->pagesize_2k) { + if (host->pagesize_2k && !is_mxc_nfc_11()) { /* data in 4 areas datas */ send_prog_page(host, 1, host->spare_only); send_prog_page(host, 2, host->spare_only); @@ -780,30 +1240,12 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, /* Write out page address, if necessary */ if (page_addr != -1) { - /* paddr_0 - p_addr_7 */ - send_addr(host, (page_addr & 0xff)); - - if (host->pagesize_2k) { - send_addr(host, (page_addr >> 8) & 0xFF); - if (mtd->size >= 0x10000000) { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - send_addr(host, (page_addr >> 16) & 0xff); - } else { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - } - } else { - /* One more address cycle for higher density devices */ - if (mtd->size >= 0x4000000) { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - send_addr(host, (page_addr >> 16) & 0xff); - } else { - /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - } - } + u32 page_mask = nand_chip->pagemask; + do { + send_addr(host, page_addr & 0xFF); + page_addr >>= 8; + page_mask >>= 8; + } while (page_mask); } /* Command post-processing step */ @@ -819,9 +1261,11 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, send_cmd(host, NAND_CMD_READSTART); /* read for each AREA */ send_read_page(host, 0, host->spare_only); - send_read_page(host, 1, host->spare_only); - send_read_page(host, 2, host->spare_only); - send_read_page(host, 3, host->spare_only); + if (!is_mxc_nfc_11()) { + send_read_page(host, 1, host->spare_only); + send_read_page(host, 2, host->spare_only); + send_read_page(host, 3, host->spare_only); + } } else { send_read_page(host, 0, host->spare_only); } @@ -843,6 +1287,24 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command, } } +#ifdef MXC_NFC_V1_1 +static void mxc_setup_config1(void) +{ + uint16_t tmp; + + tmp = readw(&host->regs->nfc_config1); + tmp |= NFC_ONE_CYCLE; + tmp |= NFC_4_8N_ECC; + writew(tmp, &host->regs->nfc_config1); + if (host->pagesize_2k) + writew(64/2, &host->regs->nfc_spare_area_size); + else + writew(16/2, &host->regs->nfc_spare_area_size); +} +#else +#define mxc_setup_config1() +#endif + int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; @@ -874,10 +1336,23 @@ int board_nand_init(struct nand_chip *this) this->ecc.calculate = mxc_nand_calculate_ecc; this->ecc.hwctl = mxc_nand_enable_hwecc; this->ecc.correct = mxc_nand_correct_data; - this->ecc.mode = NAND_ECC_HW; + if (is_mxc_nfc_11()) { + this->ecc.mode = NAND_ECC_HW_SYNDROME; + this->ecc.read_page = mxc_nand_read_page_syndrome; + this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome; + this->ecc.read_oob = mxc_nand_read_oob_syndrome; + this->ecc.write_page = mxc_nand_write_page_syndrome; + this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome; + this->ecc.write_oob = mxc_nand_write_oob_syndrome; + this->ecc.bytes = 9; + this->ecc.prepad = 7; + } else { + this->ecc.mode = NAND_ECC_HW; + } + + host->pagesize_2k = 0; + this->ecc.size = 512; - this->ecc.bytes = 3; - this->ecc.layout = &nand_hw_eccoob; tmp = readw(&host->regs->nfc_config1); tmp |= NFC_ECC_EN; writew(tmp, &host->regs->nfc_config1); @@ -888,7 +1363,6 @@ int board_nand_init(struct nand_chip *this) tmp &= ~NFC_ECC_EN; writew(tmp, &host->regs->nfc_config1); #endif - /* Reset NAND */ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); @@ -911,10 +1385,11 @@ int board_nand_init(struct nand_chip *this) #ifdef CONFIG_SYS_NAND_LARGEPAGE host->pagesize_2k = 1; - this->ecc.layout = &nand_hw_eccoob_largepage; + this->ecc.layout = &nand_hw_eccoob2k; #else host->pagesize_2k = 0; + this->ecc.layout = &nand_hw_eccoob; #endif - + mxc_setup_config1(); return err; } -- cgit v0.10.2