From 9bb272e90acf7182311dc524df69b125eac92a53 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 8 Aug 2017 15:45:13 -0700 Subject: driver: mmc: fsl_esdhc: Fix compiling warning Commit 4483b7eb added variable vqmmc_dev but only uses it under CONFIG_DM_REGULATOR. Add the same macro to variable declaration to get rid of compiling warning. Signed-off-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3abd2d3..2bf25ec 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -968,7 +968,9 @@ static int fsl_esdhc_probe(struct udevice *dev) struct fsl_esdhc_priv *priv = dev_get_priv(dev); const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); +#ifdef CONFIG_DM_REGULATOR struct udevice *vqmmc_dev; +#endif fdt_addr_t addr; unsigned int val; int ret; -- cgit v0.10.2 From 3016084b38db72e6f696355c8359e6c45d7ab080 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Mon, 12 Jun 2017 17:14:52 +0800 Subject: armv8: ls1046ardb: update core frequency to 1800MHZ Update the default core frequency to 1800MHZ for best performance under SD boot and eMMC boot. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg index 6a5076e..ccedf87 100644 --- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg +++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # RCW -0c150010 0e000000 00000000 00000000 +0c150012 0e000000 00000000 00000000 11335559 40000012 60040000 c1000000 00000000 00000000 00000000 00238800 20124000 00003000 00000096 00000001 diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg index d5265b8..d3b1522 100644 --- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg +++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # RCW -0c150010 0e000000 00000000 00000000 +0c150012 0e000000 00000000 00000000 11335559 40005012 60040000 c1000000 00000000 00000000 00000000 00238800 20124000 00003101 00000096 00000001 -- cgit v0.10.2 From 6cc914efd23ae49b682cc92f96061480a7382212 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Fri, 9 Jun 2017 11:48:05 +0530 Subject: board/ls2080ardb: Disable SD-related GPIO programming Smart voltage translator is removed from LS2080ARDB/LS2088ARDB RevF boards. It is only used on LS2081ARDB. Programming GPIO is only required for LS2081ARDB. Signed-off-by: Santan Kumar Signed-off-by: Priyanka Jain [YS: Revise commit message] Reviewed-by: York Sun diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index df2d768..210142c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -257,31 +257,17 @@ int board_early_init_f(void) int misc_init_r(void) { -#ifdef CONFIG_FSL_QIXIS - /* - * LS2081ARDB has smart voltage translator which needs - * to be programmed as below - */ -#ifndef CONFIG_TARGET_LS2081ARDB - u8 sw; - - sw = QIXIS_READ(arch); /* - * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator + * LS2081ARDB RevF board has smart voltage translator * which needs to be programmed to enable high speed SD interface * by setting GPIO4_10 output to zero */ - if ((sw & 0xf) == 0x5) { -#endif +#ifdef CONFIG_TARGET_LS2081ARDB out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | in_le32(GPIO4_GPDIR_ADDR))); out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & in_le32(GPIO4_GPDAT_ADDR))); -#ifndef CONFIG_TARGET_LS2081ARDB - } -#endif #endif - if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); -- cgit v0.10.2 From 263536a693b3c3260f88b5e47a1d3e4962d66ba7 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Thu, 15 Jun 2017 17:07:01 +0530 Subject: board:ls2080ardb: Update execution of config_board_mux Function config_board_mux() reads env variable 'hwconfig' which is only available after relocation for QSPI boot. Move calling config_board_mux() to misc_init_r(). Signed-off-by: Santan Kumar [YS: Revise commit message] Reviewed-by: York Sun diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 210142c..f332b6f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -204,25 +204,12 @@ int config_board_mux(int ctrl_type) int board_init(void) { - char *env_hwconfig; - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; #ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; #endif - u32 val; init_final_memctl_regs(); - val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); - - env_hwconfig = getenv("hwconfig"); - - if (hwconfig_f("dspi", env_hwconfig) && - DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) - config_board_mux(MUX_TYPE_DSPI); - else - config_board_mux(MUX_TYPE_SDHC); - #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif @@ -257,6 +244,20 @@ int board_early_init_f(void) int misc_init_r(void) { + char *env_hwconfig; + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; + + val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); + + env_hwconfig = getenv("hwconfig"); + + if (hwconfig_f("dspi", env_hwconfig) && + DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) + config_board_mux(MUX_TYPE_DSPI); + else + config_board_mux(MUX_TYPE_SDHC); + /* * LS2081ARDB RevF board has smart voltage translator * which needs to be programmed to enable high speed SD interface -- cgit v0.10.2 From bf7aecce04f0b29126b870c6d1e926bd26a681e8 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 3 Jul 2017 18:37:11 +0800 Subject: armv8/fsl-lsch2: correct the config description of DSPI clock divider It is derived from Platform clock instead of Platform PLL frequency. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5825f9b..43b869f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -307,7 +307,7 @@ config SYS_FSL_DSPI_CLK_DIV default 2 help This is the divider that is used to derive DSPI clock from Platform - PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. + clock, in another word DSPI_clk = Platform_clk / this_divider. config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" -- cgit v0.10.2 From e4b5143eb61f90ca3a1502e556be65c36a71b9fc Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 4 Jul 2017 11:35:43 +0800 Subject: fsl-lsch2: csu: remove multiple calling function Function enable_layerscape_ns_access() is alreayd called soc-wide. Remove duplicated calling from individual boards. Signed-off-by: Hou Zhiqiang [YS: Add commit message] Reviewed-by: York Sun diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 3340e4d..5854e2d 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -201,10 +201,6 @@ int board_init(void) ls102xa_smmu_stream_id_init(); -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - return 0; } diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index ff32d5c..2da0677 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -435,7 +435,6 @@ void board_init_f(ulong dummy) /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); - enable_layerscape_ns_access(); #endif /* diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 057a11d..883abf7 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -261,10 +261,6 @@ int board_init(void) config_serdes_mux(); #endif -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 1dd5e69..33f1afd 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -69,10 +69,6 @@ int board_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_SECURE_BOOT /* * In case of Secure Boot, the IBR configures the SMMU -- cgit v0.10.2 From 563ac65a1ad2e0f97d1b7c3a9b91d18dddc1bd3d Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 7 Jul 2017 15:10:17 +0800 Subject: dm: arm: ls1021a: Move to driver model for USB This patch enables driver model for USB in defconfigs for LS1021A platforms. Signed-off-by: Alison Wang Reviewed-by: Bin Meng Reviewed-by: York Sun diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index f5bbd1d..2f349ec 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 794a591..eba8383 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index b776ea0..df19113 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index df3fe93..d63b1e0 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -54,6 +54,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index ae55f00..84ced6e 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index c8cb215..2be0495 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -39,6 +39,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 29d6ea1..191f31d 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -40,6 +40,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index bbc73ad..139e5c0 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -41,6 +41,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 7fcb1e3..59ef358 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 8689fa7..c88cca8 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -54,6 +54,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 8647365..2d34e11 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -52,6 +52,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index b254f3b..c38ac89 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -- cgit v0.10.2 From 89d8e1313f18131a5c451f094bad89ba35ed2120 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 18 Jul 2017 11:29:12 +0800 Subject: PCI: layerscape: Fix assigning wrong address to LS2088A pcie cfg1 space This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add LS2088A series SoC pcie support), which only updated cfg_res.start and did not update the .end field. This causes fdt_resource_size() getting wrong value when calculate the cfg1 space address. Signed-off-by: Hou Zhiqiang [YS: Revise subject and commit message] Reviewed-by: York Sun diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 78cde21..610f85c 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -478,6 +478,7 @@ static int ls_pcie_probe(struct udevice *dev) bool ep_mode; uint svr; int ret; + fdt_size_t cfg_size; pcie->bus = dev; @@ -539,8 +540,10 @@ static int ls_pcie_probe(struct udevice *dev) if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || svr == SVR_LS2081A || svr == SVR_LS2041A) { + cfg_size = fdt_resource_size(&pcie->cfg_res); pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; pcie->ctrl = pcie->lut + 0x40000; } -- cgit v0.10.2 From 590e87d1a67a36c6bc0d9a120fa4feac5be142e4 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Fri, 21 Jul 2017 14:10:38 -0500 Subject: mmc: fsl_esdhc: not always setting esdhc fdt status to okay We shouldn't always change the status to okay. There could be situations that the esdhc is intentionally disabled in the device tree. Signed-off-by: Li Yang Reviewed-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 2bf25ec..b69c9b7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -930,8 +930,6 @@ __weak int esdhc_status_fixup(void *blob, const char *compat) return 1; } #endif - do_fixup_by_compat(blob, compat, "status", "okay", - sizeof("okay"), 1); return 0; } -- cgit v0.10.2 From a8ecb39e9e67ddf86cbf859175873684b8afc1d3 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Thu, 27 Jul 2017 17:49:05 +0800 Subject: config: ls1012aqds: Enable USB EHCI support for ls1012aqds Signed-off-by: Rajat Srivastava Signed-off-by: Rajesh Bhagat Signed-off-by: yinbo.zhu [YS: Revise subject, remove commit message] Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..4afc338 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,6 +35,7 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index bebb0df..7120111 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -115,6 +115,8 @@ #ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 847b698..cd3eb47 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -156,7 +156,7 @@ #elif defined(CONFIG_MPC85xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_ARCH_LS1021A) +#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif -- cgit v0.10.2 From 7794d9ab29be14ec5d298e0bac0560ea50c04c02 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Wed, 5 Jul 2017 18:05:08 +0530 Subject: board: ls2080ardb: Add fsl_fdt_fixup_flash IFC and QSPI are muxed on board. Add fsl_fdt_fixup_flash() to disable IFC node in dts if QSPI is enabled, or disable QSPI node in dts if otherwise. Signed-off-by: Santan Kumar Signed-off-by: Priyanka Jain [YS: Revise commit message] Reviewed-by: York Sun diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index f332b6f..d7122b3 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -328,6 +328,32 @@ void board_quiesce_devices(void) #endif #ifdef CONFIG_OF_BOARD_SETUP +void fsl_fdt_fixup_flash(void *fdt) +{ + int offset; + +/* + * IFC and QSPI are muxed on board. + * So disable IFC node in dts if QSPI is enabled or + * disable QSPI node in dts in case QSPI is not enabled. + */ +#ifdef CONFIG_FSL_QSPI + offset = fdt_path_offset(fdt, "/soc/ifc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/ifc"); +#else + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); +#endif + if (offset < 0) + return; + + fdt_status_disabled(fdt, offset); +} + int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; @@ -355,6 +381,8 @@ int ft_board_setup(void *blob, bd_t *bd) fsl_fdt_fixup_dr_usb(blob, bd); + fsl_fdt_fixup_flash(blob); + #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); #endif -- cgit v0.10.2 From 06651b9456d92847cbf4e93b22b020065820bc99 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Thu, 29 Jun 2017 11:19:34 +0530 Subject: driver: net: fsl-mc: fsl_mc_ldpaa_exit exit earlier if dpl applied In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied, it should return earlier without executing dpbp_exit(). Signed-off-by: Santan Kumar Acked-by: Priyanka Jain Acked-by: Yogesh Narayan Gaur Reviewed-by: York Sun diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 8bf25c7..3a30c03 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1336,14 +1336,18 @@ int fsl_mc_ldpaa_exit(bd_t *bd) { int err = 0; bool is_dpl_apply_status = false; + bool mc_boot_status = false; if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) { mc_apply_dpl(mc_lazy_dpl_addr); mc_lazy_dpl_addr = 0; } + if (!get_mc_boot_status()) + mc_boot_status = true; + /* MC is not loaded intentionally, So return success. */ - if (bd && get_mc_boot_status() != 0) + if (bd && !mc_boot_status) return 0; /* If DPL is deployed, set is_dpl_apply_status as TRUE. */ @@ -1354,11 +1358,14 @@ int fsl_mc_ldpaa_exit(bd_t *bd) * For case MC is loaded but DPL is not deployed, return success and * print message on console. Else FDT fix-up code execution hanged. */ - if (bd && !get_mc_boot_status() && !is_dpl_apply_status) { + if (bd && mc_boot_status && !is_dpl_apply_status) { printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n"); return 0; } + if (bd && mc_boot_status && is_dpl_apply_status) + return 0; + err = dpbp_exit(); if (err < 0) { printf("dpbp_exit() failed: %d\n", err); -- cgit v0.10.2 From acb90e8338734004aed6e0cb47585c96611ce9c9 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 3 Jul 2017 17:51:10 +0800 Subject: fsl-lsch2: csu: correct the workaround A-010315 The implementation of function set_pcie_ns_access() uses a wrong argument. The structure array ns_dev has a member 'ind' which is initialized by CSU_CSLX_*. It should use the 'ind' directly to address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*). Signed-off-by: Hou Zhiqiang [YS: Revise commit message] Reviewed-by: York Sun diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index 1c2287d..0c3a54c 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -10,15 +10,15 @@ #include #include -void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) +void set_devices_ns_access(unsigned long index, u16 val) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; uint32_t tmp; - reg = base + ns_dev->ind / 2; + reg = base + index / 2; tmp = in_be32(reg); - if (ns_dev->ind % 2 == 0) { + if (index % 2 == 0) { tmp &= 0x0000ffff; tmp |= val << 16; } else { @@ -34,7 +34,7 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) int i; for (i = 0; i < num; i++) - set_devices_ns_access(ns_dev + i, ns_dev[i].val); + set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); } void enable_layerscape_ns_access(void) @@ -50,20 +50,20 @@ void set_pcie_ns_access(int pcie, u16 val) switch (pcie) { #ifdef CONFIG_PCIE1 case PCIE1: - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + set_devices_ns_access(CSU_CSLX_PCIE1, val); + set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); return; #endif #ifdef CONFIG_PCIE2 case PCIE2: - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + set_devices_ns_access(CSU_CSLX_PCIE2, val); + set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); return; #endif #ifdef CONFIG_PCIE3 case PCIE3: - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + set_devices_ns_access(CSU_CSLX_PCIE3, val); + set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); return; #endif default: diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 8582ac0..027a811 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -30,7 +30,7 @@ struct csu_ns_dev { }; void enable_layerscape_ns_access(void); -void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val); +void set_devices_ns_access(unsigned long, u16 val); void set_pcie_ns_access(int pcie, u16 val); #endif -- cgit v0.10.2 From 1c83df6f3f95055ed1c8fb40d1d0604863eab78b Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Wed, 9 Aug 2017 10:35:45 +0530 Subject: armv8: ls2080a: Increase env sector size for qspi boot Increase env sector size from 64kb to 256kb for qspi boot. Signed-off-by: Santan Kumar Signed-off-by: Priyanka Jain Reviewed-by: York Sun diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 6ae5586..1ec6cb2 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -33,7 +33,7 @@ #define CONFIG_SYS_TEXT_BASE 0x20100000 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x40000 #endif #define CONFIG_SUPPORT_RAW_INITRD -- cgit v0.10.2