From 76d4ae251e4a2f7724f4462baccc2779074fa937 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Fri, 13 Jan 2012 10:11:44 +0300 Subject: zipitz2: fix boot issue introduced by PXA low level init rework CONFIG_SYS_INIT_SP_ADDR points to RAM, but it's used before DRAM controller init. Fix it by setting CONFIG_SYS_INIT_SP_ADDR to SRAM Signed-off-by: Vasily Khoruzhick diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 26204af..80d78b6 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -162,6 +162,12 @@ unsigned char zipitz2_spi_read(void); #endif /* + * SRAM Map + */ +#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ +#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ + +/* * DRAM Map */ #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ @@ -177,7 +183,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048) +#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) /* * NOR FLASH -- cgit v0.10.2 From 81f731ca7c387d6ae1560a27118a4c6a09b6e722 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Wed, 25 Jan 2012 22:54:33 +0300 Subject: zipitz2: use pxa_mmc_gen as MMC driver Signed-off-by: Vasily Khoruzhick diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index b093c2f..4075fb6 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -79,6 +79,14 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_SPI struct { diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 80d78b6..afe1e89 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -45,7 +45,8 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ + "then " \ "source 0xa0000000; " \ "else " \ "bootm 0x60000; " \ @@ -85,7 +86,8 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -- cgit v0.10.2 From c1ff6d8872401dd421a329440debba8fb91ecf2b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 Feb 2012 09:05:16 +0100 Subject: PXA: Remove PXA PCMCIA support Say good bye to some ancient, very broken and unused code. Signed-off-by: Marek Vasut diff --git a/doc/README.PXA_CF b/doc/README.PXA_CF deleted file mode 100644 index 1d76b32..0000000 --- a/doc/README.PXA_CF +++ /dev/null @@ -1,56 +0,0 @@ - -These are brief instructions on how to add support for CF adapters to -custom designed PXA boards. You need to set the parameters in the -config file. This should work for most implementations especially if you -follow the connections of the standard lubbock. Anyway just the block -marked memory configuration should be touched since the other parameters -are imposed by the PXA architecture. - -EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined -would cause looping on inw()/outw() rather than using insw()/outsw(), -thus making sure IDE / ATA bytes are properly swapped. This behaviour -is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with -PCMCIA should #define CONFIG_IDE_SWAP_IO. - -#define CONFIG_IDE_SWAP_IO - -#define CONFIG_PXA_PCMCIA 1 -#define CONFIG_PXA_IDE 1 - -#define CONFIG_PCMCIA_SLOT_A 1 -/* just to keep build system happy */ - -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x28000000 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00004204 -#define CONFIG_SYS_MCMEM1_VAL 0x00000000 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00000000 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x00000000 -/* memory configuration */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -/* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -/* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x1f0 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x1f0 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x3f0 - - -Another important point is that maybe you have to power the pcmcia -subsystem. This is very board specific, for an example on how to -do it please search for CONFIG_EXADRON1 in cmd_pcmcia.c diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 0349508..aa477d4 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -27,7 +27,6 @@ LIB := $(obj)libpcmcia.o COBJS-$(CONFIG_I82365) += i82365.o COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o -COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o COBJS-y += rpx_pcmcia.o COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o COBJS-y += tqm8xx_pcmcia.o diff --git a/drivers/pcmcia/pxa_pcmcia.c b/drivers/pcmcia/pxa_pcmcia.c deleted file mode 100644 index d06ab74..0000000 --- a/drivers/pcmcia/pxa_pcmcia.c +++ /dev/null @@ -1,93 +0,0 @@ -#include -#include - -#include -#include -#include - -static inline void msWait(unsigned msVal) -{ - udelay(msVal*1000); -} - -int pcmcia_on (void) -{ - unsigned int reg_arr[] = { - 0x48000028, CONFIG_SYS_MCMEM0_VAL, - 0x4800002c, CONFIG_SYS_MCMEM1_VAL, - 0x48000030, CONFIG_SYS_MCATT0_VAL, - 0x48000034, CONFIG_SYS_MCATT1_VAL, - 0x48000038, CONFIG_SYS_MCIO0_VAL, - 0x4800003c, CONFIG_SYS_MCIO1_VAL, - - 0, 0 - }; - int i, rc; - -#ifdef CONFIG_EXADRON1 - int cardDetect; - volatile unsigned int *v_pBCRReg = - (volatile unsigned int *) 0x08000000; -#endif - - debug ("%s\n", __FUNCTION__); - - i = 0; - while (reg_arr[i]) { - (*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1]; - i += 2; - } - udelay (1000); - - debug ("%s: programmed mem controller \n", __FUNCTION__); - -#ifdef CONFIG_EXADRON1 - -/*define useful BCR masks */ -#define BCR_CF_INIT_VAL 0x00007230 -#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231 -#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233 -#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213 -#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211 - - /* we see from the GPIO bit if the card is present */ - cardDetect = !(GPLR0 & GPIO_bit (14)); - - if (cardDetect) { - printf ("No PCMCIA card found!\n"); - } - - /* reset the card via the BCR line */ - *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL; - msWait (1500); - - /* enable address bus */ - GPCR1 = 0x01; - /* and the first CF slot */ - MECR = 0x00000002; - -#endif /* EXADRON 1 */ - - rc = check_ide_device (0); /* use just slot 0 */ - - return rc; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_off (void) -{ - return 0; -} -#endif diff --git a/include/pcmcia.h b/include/pcmcia.h index b60323d..ca0bf22 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -313,8 +313,7 @@ extern u_int *pcmcia_pgcrx[]; #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \ - || defined(CONFIG_PXA_PCMCIA) +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) extern int check_ide_device(int slot); #endif -- cgit v0.10.2 From 7e4f5f0cca990ee9798d9f7e9689914616a45440 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Nov 2011 10:49:38 +0000 Subject: arm: Remove jornada link script This link script seems old and incompatible with relocation and its own sa1000 start.S file. It isn't used because the CPU's link script was picked up in preference to this. Signed-off-by: Simon Glass Acked-by: Kristoffer Ericson diff --git a/board/jornada/u-boot.lds b/board/jornada/u-boot.lds deleted file mode 100644 index c75b21f..0000000 --- a/board/jornada/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - __bss_end__ = .; -} -- cgit v0.10.2 From 60994b99b6203ffd1e28140f4f7fcaa117c88901 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2012 12:56:39 +0100 Subject: PXA: Fix warning in zipitz2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configuring for zipitz2 board... zipitz2.c: In function ‘board_mmc_init’: zipitz2.c:85:2: warning: implicit declaration of function ‘pxa_mmc_register’ [-Wimplicit-function-declaration] Signed-off-by: Marek Vasut diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 4075fb6..82dfa82 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include -- cgit v0.10.2 From 30a14ea2b1a4cf39095385a5a38c5bbc67c6b693 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2012 13:59:47 +0100 Subject: PXA: Fix missing get_tbclk() breaking vpac boards Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index b7b0da9..a8f7462 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -94,3 +94,8 @@ void __udelay(unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +ulong get_tbclk(void) +{ + return TIMER_FREQ_HZ; +} -- cgit v0.10.2 From c67d9c5e58d4eb3a23a3ed435a33102adcec8c15 Mon Sep 17 00:00:00 2001 From: Robert Delien Date: Tue, 7 Feb 2012 04:08:55 +0000 Subject: i.mx28: Added register definitions for DIGCTL registers This patch adds register definitions for the registers of the DIGCTL IP-block. Signed-off-by: Robert Delien diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h index 9561b5e..f9e6c53 100644 --- a/arch/arm/include/asm/arch-mx28/imx-regs.h +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/include/asm/arch-mx28/regs-digctl.h b/arch/arm/include/asm/arch-mx28/regs-digctl.h new file mode 100644 index 0000000..9a63594 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-digctl.h @@ -0,0 +1,155 @@ +/* + * Freescale i.MX28 DIGCTL Register Definitions + * + * Copyright (C) 2012 Robert Delien + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_DIGCTL_H__ +#define __MX28_REGS_DIGCTL_H__ + +#include + +#ifndef __ASSEMBLY__ +struct mx28_digctl_regs { + mx28_reg_32(hw_digctl_ctrl) /* 0x000 */ + mx28_reg_32(hw_digctl_status) /* 0x010 */ + mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */ + mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */ + mx28_reg_32(hw_digctl_emi_status) /* 0x040 */ + mx28_reg_32(hw_digctl_read_margin) /* 0x050 */ + uint32_t hw_digctl_writeonce; /* 0x060 */ + uint32_t reserved_writeonce[3]; + mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */ + mx28_reg_32(hw_digctl_bist_status) /* 0x080 */ + uint32_t hw_digctl_entropy; /* 0x090 */ + uint32_t reserved_entropy[3]; + uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ + uint32_t reserved_entropy_latched[3]; + + uint32_t reserved1[4]; + + mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */ + uint32_t hw_digctl_dbgrd; /* 0x0d0 */ + uint32_t reserved_hw_digctl_dbgrd[3]; + uint32_t hw_digctl_dbg; /* 0x0e0 */ + uint32_t reserved_hw_digctl_dbg[3]; + + uint32_t reserved2[4]; + + mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */ + mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */ + mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */ + mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */ + mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */ + mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */ + mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */ + mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */ + mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */ + mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */ + mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ + mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ + mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ + mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ + mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ + + uint32_t reserved3[36]; + + uint32_t hw_digctl_scratch0; /* 0x280 */ + uint32_t reserved_hw_digctl_scratch0[3]; + uint32_t hw_digctl_scratch1; /* 0x290 */ + uint32_t reserved_hw_digctl_scratch1[3]; + uint32_t hw_digctl_armcache; /* 0x2a0 */ + uint32_t reserved_hw_digctl_armcache[3]; + mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ + uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; + uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ + uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; + uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; + uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ + uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; + uint32_t hw_digctl_fsl; /* 0x300 */ + uint32_t reserved_hw_digctl_fsl[3]; + uint32_t hw_digctl_chipid; /* 0x310 */ + uint32_t reserved_hw_digctl_chipid[3]; + + uint32_t reserved4[4]; + + uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ + uint32_t reserved_hw_digctl_ahb_stats_select[3]; + + uint32_t reserved5[12]; + + uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ + uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; + uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ + uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; + uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ + uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; + uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ + uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; + uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; + uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ + uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; + uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ + uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; + uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; + uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ + uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; + + uint32_t reserved6[64]; + + uint32_t hw_digctl_mpte0_loc; /* 0x500 */ + uint32_t reserved_hw_digctl_mpte0_loc[3]; + uint32_t hw_digctl_mpte1_loc; /* 0x510 */ + uint32_t reserved_hw_digctl_mpte1_loc[3]; + uint32_t hw_digctl_mpte2_loc; /* 0x520 */ + uint32_t reserved_hw_digctl_mpte2_loc[3]; + uint32_t hw_digctl_mpte3_loc; /* 0x530 */ + uint32_t reserved_hw_digctl_mpte3_loc[3]; + uint32_t hw_digctl_mpte4_loc; /* 0x540 */ + uint32_t reserved_hw_digctl_mpte4_loc[3]; + uint32_t hw_digctl_mpte5_loc; /* 0x550 */ + uint32_t reserved_hw_digctl_mpte5_loc[3]; + uint32_t hw_digctl_mpte6_loc; /* 0x560 */ + uint32_t reserved_hw_digctl_mpte6_loc[3]; + uint32_t hw_digctl_mpte7_loc; /* 0x570 */ + uint32_t reserved_hw_digctl_mpte7_loc[3]; + uint32_t hw_digctl_mpte8_loc; /* 0x580 */ + uint32_t reserved_hw_digctl_mpte8_loc[3]; + uint32_t hw_digctl_mpte9_loc; /* 0x590 */ + uint32_t reserved_hw_digctl_mpte9_loc[3]; + uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ + uint32_t reserved_hw_digctl_mpte10_loc[3]; + uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ + uint32_t reserved_hw_digctl_mpte11_loc[3]; + uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ + uint32_t reserved_hw_digctl_mpte12_loc[3]; + uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ + uint32_t reserved_hw_digctl_mpte13_loc[3]; + uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ + uint32_t reserved_hw_digctl_mpte14_loc[3]; + uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ + uint32_t reserved_hw_digctl_mpte15_loc[3]; +}; +#endif + +#endif /* __MX28_REGS_DIGCTL_H__ */ -- cgit v0.10.2 From 1e94d07faf871ebe0fdd06de0b14dc048c742913 Mon Sep 17 00:00:00 2001 From: Robert Delien Date: Tue, 7 Feb 2012 04:08:56 +0000 Subject: i.mx28: Replaced magic numbers for scratch register addresses with register definitions This patch replaces the use of magice numbers for scratch register addresses with earlier defined register definitions. Signed-off-by: Robert Delien diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index 683777f..b235091 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -261,14 +261,14 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -#define HW_DIGCTRL_SCRATCH0 0x8001c280 -#define HW_DIGCTRL_SCRATCH1 0x8001c290 int mx28_dram_init(void) { + struct mx28_digctl_regs *digctl_regs = + (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz[2]; - sz[0] = readl(HW_DIGCTRL_SCRATCH0); - sz[1] = readl(HW_DIGCTRL_SCRATCH1); + sz[0] = readl(&digctl_regs->hw_digctl_scratch0); + sz[1] = readl(&digctl_regs->hw_digctl_scratch1); if (sz[0] != sz[1]) { printf("MX28:\n" diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 00493b8..db67011 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -165,8 +165,6 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } -#define HW_DIGCTRL_SCRATCH0 0x8001c280 -#define HW_DIGCTRL_SCRATCH1 0x8001c290 void data_abort_memdetect_handler(void) __attribute__((naked)); void data_abort_memdetect_handler(void) { @@ -175,6 +173,8 @@ void data_abort_memdetect_handler(void) void mx28_mem_get_size(void) { + struct mx28_digctl_regs *digctl_regs = + (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; @@ -183,8 +183,8 @@ void mx28_mem_get_size(void) vt[4] = (uint32_t)&data_abort_memdetect_handler; sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - writel(sz, HW_DIGCTRL_SCRATCH0); - writel(sz, HW_DIGCTRL_SCRATCH1); + writel(sz, &digctl_regs->hw_digctl_scratch0); + writel(sz, &digctl_regs->hw_digctl_scratch1); /* Restore the old DABT handler. */ vt[4] = da; -- cgit v0.10.2 From 4e187fbcdf602bd6661e5fe7dc3f9c17b796dc39 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Sun, 12 Feb 2012 21:29:47 +0000 Subject: mx6q: mx6qsabrelite: Update the README The SD loader binary is now downloadable at https://wiki.linaro.org/Boards/MX6QSabreLite under a open-source 3-clause BSD license. Update the README for this. The discussion shows that it's hard to change the hardware regarding the default SPI NOR boot of the SabreLite boards. I.e. this will stay the default boot. Therefore remove the 'early version of' statement. Signed-off-by: Dirk Behme CC: Stefano Babic CC: Jason Liu diff --git a/doc/README.mx6qsabrelite b/doc/README.mx6qsabrelite index 4add2bf..0498cba 100644 --- a/doc/README.mx6qsabrelite +++ b/doc/README.mx6qsabrelite @@ -7,20 +7,24 @@ i.MX6q SabreLite board. --------------------------------- The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports -boot from SD card only. However, by default, the early version of SabreLite +boot from SD card only. However, by default, the SabreLite boards boot from the SPI NOR flash. These boards need to be reflashed with a small SD card loader to support boot from SD card. This small SD card loader will be flashed into the SPI NOR. The board will still boot from SPI NOR, but the loader will in turn request the BootROM to load the U-Boot from SD card. -At the moment of writing, please check with Freescale on the availablity of -this small SD loader binary. + +The SD card loader is available from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +under a open-source 3-clause BSD license. To update the SPI-NOR on the SabreLite board without the Freescale manufacturing tool use the following procedure: 1. Write this SD card loader onto a large SD card using: - sudo dd if=MX6_SPI_to_SD_loader.bin of=/dev/sXx + sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx Note: Replace sXx with the device representing the SD card in your system. -- cgit v0.10.2 From 3f467529cad0789b6dcc44f5ebc595c3e47341ce Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 8 Feb 2012 22:33:25 +0000 Subject: usb/ehci: Add USB support for the MX6Q Currently, only USB Host 1 is supported. Cc: Remy Bohmer Signed-off-by: Wolfgang Grandegger diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fa3a124..ef98563 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -36,6 +36,19 @@ enum pll_clocks { struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR; +void enable_usboh3_clk(unsigned char enable) +{ + u32 reg; + + reg = __raw_readl(&imx_ccm->CCGR6); + if (enable) + reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET; + else + reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET); + __raw_writel(reg, &imx_ccm->CCGR6); + +} + static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 636458f..613809b 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -46,5 +46,6 @@ enum mxc_clock { u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +void enable_usboh3_clk(unsigned char enable); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 6b7589b..6a200bb 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -111,6 +111,9 @@ #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 5fdc97b..53ad70a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -44,6 +44,7 @@ endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +COBJS-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c new file mode 100644 index 0000000..b7bf49d --- /dev/null +++ b/drivers/usb/host/ehci-mx6.c @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ehci.h" +#include "ehci-core.h" + +#define USB_OTGREGS_OFFSET 0x000 +#define USB_H1REGS_OFFSET 0x200 +#define USB_H2REGS_OFFSET 0x400 +#define USB_H3REGS_OFFSET 0x600 +#define USB_OTHERREGS_OFFSET 0x800 + +#define USB_H1_CTRL_OFFSET 0x04 + +#define USBPHY_CTRL 0x00000030 +#define USBPHY_CTRL_SET 0x00000034 +#define USBPHY_CTRL_CLR 0x00000038 +#define USBPHY_CTRL_TOG 0x0000003c + +#define USBPHY_PWD 0x00000000 +#define USBPHY_CTRL_SFTRST 0x80000000 +#define USBPHY_CTRL_CLKGATE 0x40000000 +#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 +#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 + +#define ANADIG_USB2_CHRG_DETECT 0x00000210 +#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 +#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 + +#define ANADIG_USB2_PLL_480_CTRL 0x00000020 +#define ANADIG_USB2_PLL_480_CTRL_SET 0x00000024 +#define ANADIG_USB2_PLL_480_CTRL_CLR 0x00000028 +#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 +#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 +#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 +#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 + + +#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ +#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ + +/* USBCMD */ +#define UH1_USBCMD_OFFSET 0x140 +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ + +static void usbh1_internal_phy_clock_gate(int on) +{ + void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR; + + phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; + __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg); +} + +static void usbh1_power_config(void) +{ + void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR; + + /* + * Some phy and power's special controls for host1 + * 1. The external charger detector needs to be disabled + * or the signal at DP will be poor + * 2. The PLL's power and output to usb for host 1 + * is totally controlled by IC, so the Software only needs + * to enable them at initializtion. + */ + __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + anatop_base + ANADIG_USB2_CHRG_DETECT); + + __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, + anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR); + + __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | + ANADIG_USB2_PLL_480_CTRL_POWER | + ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, + anatop_base + ANADIG_USB2_PLL_480_CTRL_SET); +} + +static int usbh1_phy_enable(void) +{ + void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR; + void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR + + USB_H1REGS_OFFSET + + UH1_USBCMD_OFFSET); + u32 val; + + /* Stop then Reset */ + val = __raw_readl(usb_cmd); + val &= ~UCMD_RUN_STOP; + __raw_writel(val, usb_cmd); + while (__raw_readl(usb_cmd) & UCMD_RUN_STOP) + ; + + val = __raw_readl(usb_cmd); + val |= UCMD_RESET; + __raw_writel(val, usb_cmd); + while (__raw_readl(usb_cmd) & UCMD_RESET) + ; + + /* Reset USBPHY module */ + val = __raw_readl(phy_ctrl); + val |= USBPHY_CTRL_SFTRST; + __raw_writel(val, phy_ctrl); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + val = __raw_readl(phy_ctrl); + val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); + __raw_writel(val, phy_ctrl); + udelay(10); + + /* Power up the PHY */ + __raw_writel(0, phy_reg + USBPHY_PWD); + /* enable FS/LS device */ + val = __raw_readl(phy_reg + USBPHY_CTRL); + val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); + __raw_writel(val, phy_reg + USBPHY_CTRL); + + return 0; +} + +static void usbh1_oc_config(void) +{ + void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR; + void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET; + u32 val; + + val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET); +#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 + /* mx6qarm2 seems to required a different setting*/ + val &= ~UCTRL_OVER_CUR_POL; +#else + val |= UCTRL_OVER_CUR_POL; +#endif + __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET); + + val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET); + val |= UCTRL_OVER_CUR_DIS; + __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET); +} + +int ehci_hcd_init(void) +{ + struct usb_ehci *ehci; + + enable_usboh3_clk(1); + mdelay(1); + + /* Do board specific initialization */ + board_ehci_hcd_init(CONFIG_MXC_USB_PORT); + +#if CONFIG_MXC_USB_PORT == 1 + /* USB Host 1 */ + usbh1_power_config(); + usbh1_oc_config(); + usbh1_internal_phy_clock_gate(1); + usbh1_phy_enable(); +#else +#error "MXC USB port not yet supported" +#endif + + ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR + + (0x200 * CONFIG_MXC_USB_PORT)); + hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + setbits_le32(&ehci->usbmode, CM_HOST); + + __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + + mdelay(10); + + return 0; +} + +int ehci_hcd_stop(void) +{ + return 0; +} -- cgit v0.10.2 From 2ea73e9e38befa872d215c919f766d837d7a1312 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 8 Feb 2012 22:33:26 +0000 Subject: mx6qsabrelite: add and enable USB Host 1 support Cc: Stefano Babic Cc: Jason Liu Signed-off-by: Wolfgang Grandegger diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f884bb5..db1bea9 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -140,12 +140,30 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } +iomux_v3_cfg_t usb_pads[] = { + MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(GPIO_NUMBER(7, 12), 0); + mdelay(2); + gpio_set_value(GPIO_NUMBER(7, 12), 1); + + return 0; +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1}, diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 982f03f..93000f0 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -80,6 +80,19 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v0.10.2 From f5861ccc749ba4fc23accff05b9e3f392ff9f8ca Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Feb 2012 12:15:01 +0000 Subject: M28: Fix LCD PINMUX The LCD pins configuration was wrong in U-Boot, configure pins properly. Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Detlev Zundel Cc: Stefano Babic Cc: Fabio Estevam diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index 86d7d87..91316a7 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -31,7 +31,7 @@ #include #define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) #define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) @@ -68,15 +68,8 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, - MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, - MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD, - MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, /* UART1 */ MX28_PAD_PWM0__DUART_RX, -- cgit v0.10.2 From af335c579ff70e1862efb7ab614fce1fd3f96667 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Feb 2012 12:15:02 +0000 Subject: M28: Support for the old M28 SoM v1.0 This prototype version SoM is unused and not available to public. Support this only for internal debugging purposes. Signed-off-by: Marek Vasut diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index 91316a7..a04fe18 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -72,8 +72,13 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, /* UART1 */ +#ifdef CONFIG_DENX_M28_V10 + MX28_PAD_AUART0_CTS__DUART_RX, + MX28_PAD_AUART0_RTS__DUART_TX, +#else MX28_PAD_PWM0__DUART_RX, MX28_PAD_PWM1__DUART_TX, +#endif MX28_PAD_AUART0_TX__DUART_RTS, MX28_PAD_AUART0_RX__DUART_CTS, -- cgit v0.10.2 From 40083c52f7a817e6a5c3624cb5590f582f9110fc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Feb 2012 12:15:03 +0000 Subject: i.MX28: Reformat the DRAM memory configuration data Reformat the data so it's easier to navigate through them. Signed-off-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index db67011..4af9eb7 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -32,44 +32,54 @@ #include "mx28_init.h" uint32_t dram_vals[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, - 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, - 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, - 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202, - 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, - 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, - 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200, - 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27, - 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006, - 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, - 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, - 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, - 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, - 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, + 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000F02, + 0x06120612, 0x00000200, 0x00020007, 0xf5014b27, + 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300, + 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, + 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, + 0x00000004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, + 0x00040004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010001 }; void init_m28_200mhz_ddr2(void) -- cgit v0.10.2 From b228e14e9653fe4ead0f39a7a879d1a50e61321a Mon Sep 17 00:00:00 2001 From: Robert Delien Date: Sun, 26 Feb 2012 12:15:05 +0000 Subject: Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8 This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8. Signed-off-by: Robert Delien Acked-by: Marek Vasut Tested-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c index f698506..9d3a018 100644 --- a/arch/arm/cpu/arm926ejs/mx28/clock.c +++ b/arch/arm/cpu/arm926ejs/mx28/clock.c @@ -223,7 +223,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) return; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register)); + (ssp * sizeof(struct mx28_register_32)); clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) @@ -272,7 +272,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) return XTAL_FREQ_KHZ; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mx28_register)); + (ssp * sizeof(struct mx28_register_32)); tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; diff --git a/arch/arm/cpu/arm926ejs/mx28/iomux.c b/arch/arm/cpu/arm926ejs/mx28/iomux.c index 9ea411f..12916b6 100644 --- a/arch/arm/cpu/arm926ejs/mx28/iomux.c +++ b/arch/arm/cpu/arm926ejs/mx28/iomux.c @@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) { u32 reg, ofs, bp, bm; void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mx28_register *mxs_reg; + struct mx28_register_32 *mxs_reg; /* muxsel */ ofs = 0x100; @@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) /* vol */ if (PAD_VOL_VALID(pad)) { bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); if (PAD_VOL(pad)) writel(1 << bp, &mxs_reg->reg_set); else @@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs = PULL_OFFSET; ofs += PAD_BANK(pad) * 0x10; bp = PAD_PIN(pad); - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs); if (PAD_PULL(pad)) writel(1 << bp, &mxs_reg->reg_set); else diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index b235091..9bfd83b 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -63,7 +63,7 @@ void reset_cpu(ulong ignored) ; } -int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout) +int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == mask) @@ -74,7 +74,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout) +int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { if ((readl(®->reg) & mask) == 0) @@ -85,7 +85,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout) return !timeout; } -int mx28_reset_block(struct mx28_register *reg) +int mx28_reset_block(struct mx28_register_32 *reg) { /* Clear SFTRST */ writel(MX28_BLOCK_SFTRST, ®->reg_clr); diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h index a7fa1ec..91d7bc8 100644 --- a/arch/arm/include/asm/arch-mx28/regs-apbh.h +++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h @@ -30,142 +30,142 @@ #ifndef __ASSEMBLY__ struct mx28_apbh_regs { - mx28_reg(hw_apbh_ctrl0) - mx28_reg(hw_apbh_ctrl1) - mx28_reg(hw_apbh_ctrl2) - mx28_reg(hw_apbh_channel_ctrl) - mx28_reg(hw_apbh_devsel) - mx28_reg(hw_apbh_dma_burst_size) - mx28_reg(hw_apbh_debug) + mx28_reg_32(hw_apbh_ctrl0) + mx28_reg_32(hw_apbh_ctrl1) + mx28_reg_32(hw_apbh_ctrl2) + mx28_reg_32(hw_apbh_channel_ctrl) + mx28_reg_32(hw_apbh_devsel) + mx28_reg_32(hw_apbh_dma_burst_size) + mx28_reg_32(hw_apbh_debug) uint32_t reserved[36]; union { struct { - mx28_reg(hw_apbh_ch_curcmdar) - mx28_reg(hw_apbh_ch_nxtcmdar) - mx28_reg(hw_apbh_ch_cmd) - mx28_reg(hw_apbh_ch_bar) - mx28_reg(hw_apbh_ch_sema) - mx28_reg(hw_apbh_ch_debug1) - mx28_reg(hw_apbh_ch_debug2) + mx28_reg_32(hw_apbh_ch_curcmdar) + mx28_reg_32(hw_apbh_ch_nxtcmdar) + mx28_reg_32(hw_apbh_ch_cmd) + mx28_reg_32(hw_apbh_ch_bar) + mx28_reg_32(hw_apbh_ch_sema) + mx28_reg_32(hw_apbh_ch_debug1) + mx28_reg_32(hw_apbh_ch_debug2) } ch[16]; struct { - mx28_reg(hw_apbh_ch0_curcmdar) - mx28_reg(hw_apbh_ch0_nxtcmdar) - mx28_reg(hw_apbh_ch0_cmd) - mx28_reg(hw_apbh_ch0_bar) - mx28_reg(hw_apbh_ch0_sema) - mx28_reg(hw_apbh_ch0_debug1) - mx28_reg(hw_apbh_ch0_debug2) - mx28_reg(hw_apbh_ch1_curcmdar) - mx28_reg(hw_apbh_ch1_nxtcmdar) - mx28_reg(hw_apbh_ch1_cmd) - mx28_reg(hw_apbh_ch1_bar) - mx28_reg(hw_apbh_ch1_sema) - mx28_reg(hw_apbh_ch1_debug1) - mx28_reg(hw_apbh_ch1_debug2) - mx28_reg(hw_apbh_ch2_curcmdar) - mx28_reg(hw_apbh_ch2_nxtcmdar) - mx28_reg(hw_apbh_ch2_cmd) - mx28_reg(hw_apbh_ch2_bar) - mx28_reg(hw_apbh_ch2_sema) - mx28_reg(hw_apbh_ch2_debug1) - mx28_reg(hw_apbh_ch2_debug2) - mx28_reg(hw_apbh_ch3_curcmdar) - mx28_reg(hw_apbh_ch3_nxtcmdar) - mx28_reg(hw_apbh_ch3_cmd) - mx28_reg(hw_apbh_ch3_bar) - mx28_reg(hw_apbh_ch3_sema) - mx28_reg(hw_apbh_ch3_debug1) - mx28_reg(hw_apbh_ch3_debug2) - mx28_reg(hw_apbh_ch4_curcmdar) - mx28_reg(hw_apbh_ch4_nxtcmdar) - mx28_reg(hw_apbh_ch4_cmd) - mx28_reg(hw_apbh_ch4_bar) - mx28_reg(hw_apbh_ch4_sema) - mx28_reg(hw_apbh_ch4_debug1) - mx28_reg(hw_apbh_ch4_debug2) - mx28_reg(hw_apbh_ch5_curcmdar) - mx28_reg(hw_apbh_ch5_nxtcmdar) - mx28_reg(hw_apbh_ch5_cmd) - mx28_reg(hw_apbh_ch5_bar) - mx28_reg(hw_apbh_ch5_sema) - mx28_reg(hw_apbh_ch5_debug1) - mx28_reg(hw_apbh_ch5_debug2) - mx28_reg(hw_apbh_ch6_curcmdar) - mx28_reg(hw_apbh_ch6_nxtcmdar) - mx28_reg(hw_apbh_ch6_cmd) - mx28_reg(hw_apbh_ch6_bar) - mx28_reg(hw_apbh_ch6_sema) - mx28_reg(hw_apbh_ch6_debug1) - mx28_reg(hw_apbh_ch6_debug2) - mx28_reg(hw_apbh_ch7_curcmdar) - mx28_reg(hw_apbh_ch7_nxtcmdar) - mx28_reg(hw_apbh_ch7_cmd) - mx28_reg(hw_apbh_ch7_bar) - mx28_reg(hw_apbh_ch7_sema) - mx28_reg(hw_apbh_ch7_debug1) - mx28_reg(hw_apbh_ch7_debug2) - mx28_reg(hw_apbh_ch8_curcmdar) - mx28_reg(hw_apbh_ch8_nxtcmdar) - mx28_reg(hw_apbh_ch8_cmd) - mx28_reg(hw_apbh_ch8_bar) - mx28_reg(hw_apbh_ch8_sema) - mx28_reg(hw_apbh_ch8_debug1) - mx28_reg(hw_apbh_ch8_debug2) - mx28_reg(hw_apbh_ch9_curcmdar) - mx28_reg(hw_apbh_ch9_nxtcmdar) - mx28_reg(hw_apbh_ch9_cmd) - mx28_reg(hw_apbh_ch9_bar) - mx28_reg(hw_apbh_ch9_sema) - mx28_reg(hw_apbh_ch9_debug1) - mx28_reg(hw_apbh_ch9_debug2) - mx28_reg(hw_apbh_ch10_curcmdar) - mx28_reg(hw_apbh_ch10_nxtcmdar) - mx28_reg(hw_apbh_ch10_cmd) - mx28_reg(hw_apbh_ch10_bar) - mx28_reg(hw_apbh_ch10_sema) - mx28_reg(hw_apbh_ch10_debug1) - mx28_reg(hw_apbh_ch10_debug2) - mx28_reg(hw_apbh_ch11_curcmdar) - mx28_reg(hw_apbh_ch11_nxtcmdar) - mx28_reg(hw_apbh_ch11_cmd) - mx28_reg(hw_apbh_ch11_bar) - mx28_reg(hw_apbh_ch11_sema) - mx28_reg(hw_apbh_ch11_debug1) - mx28_reg(hw_apbh_ch11_debug2) - mx28_reg(hw_apbh_ch12_curcmdar) - mx28_reg(hw_apbh_ch12_nxtcmdar) - mx28_reg(hw_apbh_ch12_cmd) - mx28_reg(hw_apbh_ch12_bar) - mx28_reg(hw_apbh_ch12_sema) - mx28_reg(hw_apbh_ch12_debug1) - mx28_reg(hw_apbh_ch12_debug2) - mx28_reg(hw_apbh_ch13_curcmdar) - mx28_reg(hw_apbh_ch13_nxtcmdar) - mx28_reg(hw_apbh_ch13_cmd) - mx28_reg(hw_apbh_ch13_bar) - mx28_reg(hw_apbh_ch13_sema) - mx28_reg(hw_apbh_ch13_debug1) - mx28_reg(hw_apbh_ch13_debug2) - mx28_reg(hw_apbh_ch14_curcmdar) - mx28_reg(hw_apbh_ch14_nxtcmdar) - mx28_reg(hw_apbh_ch14_cmd) - mx28_reg(hw_apbh_ch14_bar) - mx28_reg(hw_apbh_ch14_sema) - mx28_reg(hw_apbh_ch14_debug1) - mx28_reg(hw_apbh_ch14_debug2) - mx28_reg(hw_apbh_ch15_curcmdar) - mx28_reg(hw_apbh_ch15_nxtcmdar) - mx28_reg(hw_apbh_ch15_cmd) - mx28_reg(hw_apbh_ch15_bar) - mx28_reg(hw_apbh_ch15_sema) - mx28_reg(hw_apbh_ch15_debug1) - mx28_reg(hw_apbh_ch15_debug2) + mx28_reg_32(hw_apbh_ch0_curcmdar) + mx28_reg_32(hw_apbh_ch0_nxtcmdar) + mx28_reg_32(hw_apbh_ch0_cmd) + mx28_reg_32(hw_apbh_ch0_bar) + mx28_reg_32(hw_apbh_ch0_sema) + mx28_reg_32(hw_apbh_ch0_debug1) + mx28_reg_32(hw_apbh_ch0_debug2) + mx28_reg_32(hw_apbh_ch1_curcmdar) + mx28_reg_32(hw_apbh_ch1_nxtcmdar) + mx28_reg_32(hw_apbh_ch1_cmd) + mx28_reg_32(hw_apbh_ch1_bar) + mx28_reg_32(hw_apbh_ch1_sema) + mx28_reg_32(hw_apbh_ch1_debug1) + mx28_reg_32(hw_apbh_ch1_debug2) + mx28_reg_32(hw_apbh_ch2_curcmdar) + mx28_reg_32(hw_apbh_ch2_nxtcmdar) + mx28_reg_32(hw_apbh_ch2_cmd) + mx28_reg_32(hw_apbh_ch2_bar) + mx28_reg_32(hw_apbh_ch2_sema) + mx28_reg_32(hw_apbh_ch2_debug1) + mx28_reg_32(hw_apbh_ch2_debug2) + mx28_reg_32(hw_apbh_ch3_curcmdar) + mx28_reg_32(hw_apbh_ch3_nxtcmdar) + mx28_reg_32(hw_apbh_ch3_cmd) + mx28_reg_32(hw_apbh_ch3_bar) + mx28_reg_32(hw_apbh_ch3_sema) + mx28_reg_32(hw_apbh_ch3_debug1) + mx28_reg_32(hw_apbh_ch3_debug2) + mx28_reg_32(hw_apbh_ch4_curcmdar) + mx28_reg_32(hw_apbh_ch4_nxtcmdar) + mx28_reg_32(hw_apbh_ch4_cmd) + mx28_reg_32(hw_apbh_ch4_bar) + mx28_reg_32(hw_apbh_ch4_sema) + mx28_reg_32(hw_apbh_ch4_debug1) + mx28_reg_32(hw_apbh_ch4_debug2) + mx28_reg_32(hw_apbh_ch5_curcmdar) + mx28_reg_32(hw_apbh_ch5_nxtcmdar) + mx28_reg_32(hw_apbh_ch5_cmd) + mx28_reg_32(hw_apbh_ch5_bar) + mx28_reg_32(hw_apbh_ch5_sema) + mx28_reg_32(hw_apbh_ch5_debug1) + mx28_reg_32(hw_apbh_ch5_debug2) + mx28_reg_32(hw_apbh_ch6_curcmdar) + mx28_reg_32(hw_apbh_ch6_nxtcmdar) + mx28_reg_32(hw_apbh_ch6_cmd) + mx28_reg_32(hw_apbh_ch6_bar) + mx28_reg_32(hw_apbh_ch6_sema) + mx28_reg_32(hw_apbh_ch6_debug1) + mx28_reg_32(hw_apbh_ch6_debug2) + mx28_reg_32(hw_apbh_ch7_curcmdar) + mx28_reg_32(hw_apbh_ch7_nxtcmdar) + mx28_reg_32(hw_apbh_ch7_cmd) + mx28_reg_32(hw_apbh_ch7_bar) + mx28_reg_32(hw_apbh_ch7_sema) + mx28_reg_32(hw_apbh_ch7_debug1) + mx28_reg_32(hw_apbh_ch7_debug2) + mx28_reg_32(hw_apbh_ch8_curcmdar) + mx28_reg_32(hw_apbh_ch8_nxtcmdar) + mx28_reg_32(hw_apbh_ch8_cmd) + mx28_reg_32(hw_apbh_ch8_bar) + mx28_reg_32(hw_apbh_ch8_sema) + mx28_reg_32(hw_apbh_ch8_debug1) + mx28_reg_32(hw_apbh_ch8_debug2) + mx28_reg_32(hw_apbh_ch9_curcmdar) + mx28_reg_32(hw_apbh_ch9_nxtcmdar) + mx28_reg_32(hw_apbh_ch9_cmd) + mx28_reg_32(hw_apbh_ch9_bar) + mx28_reg_32(hw_apbh_ch9_sema) + mx28_reg_32(hw_apbh_ch9_debug1) + mx28_reg_32(hw_apbh_ch9_debug2) + mx28_reg_32(hw_apbh_ch10_curcmdar) + mx28_reg_32(hw_apbh_ch10_nxtcmdar) + mx28_reg_32(hw_apbh_ch10_cmd) + mx28_reg_32(hw_apbh_ch10_bar) + mx28_reg_32(hw_apbh_ch10_sema) + mx28_reg_32(hw_apbh_ch10_debug1) + mx28_reg_32(hw_apbh_ch10_debug2) + mx28_reg_32(hw_apbh_ch11_curcmdar) + mx28_reg_32(hw_apbh_ch11_nxtcmdar) + mx28_reg_32(hw_apbh_ch11_cmd) + mx28_reg_32(hw_apbh_ch11_bar) + mx28_reg_32(hw_apbh_ch11_sema) + mx28_reg_32(hw_apbh_ch11_debug1) + mx28_reg_32(hw_apbh_ch11_debug2) + mx28_reg_32(hw_apbh_ch12_curcmdar) + mx28_reg_32(hw_apbh_ch12_nxtcmdar) + mx28_reg_32(hw_apbh_ch12_cmd) + mx28_reg_32(hw_apbh_ch12_bar) + mx28_reg_32(hw_apbh_ch12_sema) + mx28_reg_32(hw_apbh_ch12_debug1) + mx28_reg_32(hw_apbh_ch12_debug2) + mx28_reg_32(hw_apbh_ch13_curcmdar) + mx28_reg_32(hw_apbh_ch13_nxtcmdar) + mx28_reg_32(hw_apbh_ch13_cmd) + mx28_reg_32(hw_apbh_ch13_bar) + mx28_reg_32(hw_apbh_ch13_sema) + mx28_reg_32(hw_apbh_ch13_debug1) + mx28_reg_32(hw_apbh_ch13_debug2) + mx28_reg_32(hw_apbh_ch14_curcmdar) + mx28_reg_32(hw_apbh_ch14_nxtcmdar) + mx28_reg_32(hw_apbh_ch14_cmd) + mx28_reg_32(hw_apbh_ch14_bar) + mx28_reg_32(hw_apbh_ch14_sema) + mx28_reg_32(hw_apbh_ch14_debug1) + mx28_reg_32(hw_apbh_ch14_debug2) + mx28_reg_32(hw_apbh_ch15_curcmdar) + mx28_reg_32(hw_apbh_ch15_nxtcmdar) + mx28_reg_32(hw_apbh_ch15_cmd) + mx28_reg_32(hw_apbh_ch15_bar) + mx28_reg_32(hw_apbh_ch15_sema) + mx28_reg_32(hw_apbh_ch15_debug1) + mx28_reg_32(hw_apbh_ch15_debug2) }; }; - mx28_reg(hw_apbh_version) + mx28_reg_32(hw_apbh_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h index cac0470..9243bdd 100644 --- a/arch/arm/include/asm/arch-mx28/regs-bch.h +++ b/arch/arm/include/asm/arch-mx28/regs-bch.h @@ -30,30 +30,30 @@ #ifndef __ASSEMBLY__ struct mx28_bch_regs { - mx28_reg(hw_bch_ctrl) - mx28_reg(hw_bch_status0) - mx28_reg(hw_bch_mode) - mx28_reg(hw_bch_encodeptr) - mx28_reg(hw_bch_dataptr) - mx28_reg(hw_bch_metaptr) + mx28_reg_32(hw_bch_ctrl) + mx28_reg_32(hw_bch_status0) + mx28_reg_32(hw_bch_mode) + mx28_reg_32(hw_bch_encodeptr) + mx28_reg_32(hw_bch_dataptr) + mx28_reg_32(hw_bch_metaptr) uint32_t reserved[4]; - mx28_reg(hw_bch_layoutselect) - mx28_reg(hw_bch_flash0layout0) - mx28_reg(hw_bch_flash0layout1) - mx28_reg(hw_bch_flash1layout0) - mx28_reg(hw_bch_flash1layout1) - mx28_reg(hw_bch_flash2layout0) - mx28_reg(hw_bch_flash2layout1) - mx28_reg(hw_bch_flash3layout0) - mx28_reg(hw_bch_flash3layout1) - mx28_reg(hw_bch_dbgkesread) - mx28_reg(hw_bch_dbgcsferead) - mx28_reg(hw_bch_dbgsyndegread) - mx28_reg(hw_bch_dbgahbmread) - mx28_reg(hw_bch_blockname) - mx28_reg(hw_bch_version) + mx28_reg_32(hw_bch_layoutselect) + mx28_reg_32(hw_bch_flash0layout0) + mx28_reg_32(hw_bch_flash0layout1) + mx28_reg_32(hw_bch_flash1layout0) + mx28_reg_32(hw_bch_flash1layout1) + mx28_reg_32(hw_bch_flash2layout0) + mx28_reg_32(hw_bch_flash2layout1) + mx28_reg_32(hw_bch_flash3layout0) + mx28_reg_32(hw_bch_flash3layout1) + mx28_reg_32(hw_bch_dbgkesread) + mx28_reg_32(hw_bch_dbgcsferead) + mx28_reg_32(hw_bch_dbgsyndegread) + mx28_reg_32(hw_bch_dbgahbmread) + mx28_reg_32(hw_bch_blockname) + mx28_reg_32(hw_bch_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h index 93d0397..8e666ee 100644 --- a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h +++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h @@ -30,38 +30,38 @@ #ifndef __ASSEMBLY__ struct mx28_clkctrl_regs { - mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */ - mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */ - mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */ - mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */ - mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mx28_reg(hw_clkctrl_cpu) /* 0x50 */ - mx28_reg(hw_clkctrl_hbus) /* 0x60 */ - mx28_reg(hw_clkctrl_xbus) /* 0x70 */ - mx28_reg(hw_clkctrl_xtal) /* 0x80 */ - mx28_reg(hw_clkctrl_ssp0) /* 0x90 */ - mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */ - mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */ - mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */ - mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */ - mx28_reg(hw_clkctrl_spdif) /* 0xe0 */ - mx28_reg(hw_clkctrl_emi) /* 0xf0 */ - mx28_reg(hw_clkctrl_saif0) /* 0x100 */ - mx28_reg(hw_clkctrl_saif1) /* 0x110 */ - mx28_reg(hw_clkctrl_lcdif) /* 0x120 */ - mx28_reg(hw_clkctrl_etm) /* 0x130 */ - mx28_reg(hw_clkctrl_enet) /* 0x140 */ - mx28_reg(hw_clkctrl_hsadc) /* 0x150 */ - mx28_reg(hw_clkctrl_flexcan) /* 0x160 */ + mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */ + mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */ + mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */ + mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */ + mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */ + mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ + mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ + mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ + mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ + mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */ + mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */ + mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */ + mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */ + mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */ + mx28_reg_32(hw_clkctrl_etm) /* 0x130 */ + mx28_reg_32(hw_clkctrl_enet) /* 0x140 */ + mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */ + mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */ uint32_t reserved[16]; - mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */ - mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */ - mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */ - mx28_reg(hw_clkctrl_reset) /* 0x1e0 */ - mx28_reg(hw_clkctrl_status) /* 0x1f0 */ - mx28_reg(hw_clkctrl_version) /* 0x200 */ + mx28_reg_32(hw_clkctrl_frac0) /* 0x1b0 */ + mx28_reg_32(hw_clkctrl_frac1) /* 0x1c0 */ + mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ + mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */ + mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */ + mx28_reg_32(hw_clkctrl_version) /* 0x200 */ }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index efe975b..75cc9a6 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -47,20 +47,20 @@ * */ -#define __mx28_reg(name) \ +#define __mx28_reg_32(name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; -struct mx28_register { - __mx28_reg(reg) +struct mx28_register_32 { + __mx28_reg_32(reg) }; -#define mx28_reg(name) \ +#define mx28_reg_32(name) \ union { \ - struct { __mx28_reg(name) }; \ - struct mx28_register name##_reg; \ + struct { __mx28_reg_32(name) }; \ + struct mx28_register_32 name##_reg; \ }; #endif /* __MX28_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h index 0096793..1b487f4 100644 --- a/arch/arm/include/asm/arch-mx28/regs-gpmi.h +++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h @@ -30,22 +30,22 @@ #ifndef __ASSEMBLY__ struct mx28_gpmi_regs { - mx28_reg(hw_gpmi_ctrl0) - mx28_reg(hw_gpmi_compare) - mx28_reg(hw_gpmi_eccctrl) - mx28_reg(hw_gpmi_ecccount) - mx28_reg(hw_gpmi_payload) - mx28_reg(hw_gpmi_auxiliary) - mx28_reg(hw_gpmi_ctrl1) - mx28_reg(hw_gpmi_timing0) - mx28_reg(hw_gpmi_timing1) + mx28_reg_32(hw_gpmi_ctrl0) + mx28_reg_32(hw_gpmi_compare) + mx28_reg_32(hw_gpmi_eccctrl) + mx28_reg_32(hw_gpmi_ecccount) + mx28_reg_32(hw_gpmi_payload) + mx28_reg_32(hw_gpmi_auxiliary) + mx28_reg_32(hw_gpmi_ctrl1) + mx28_reg_32(hw_gpmi_timing0) + mx28_reg_32(hw_gpmi_timing1) uint32_t reserved[4]; - mx28_reg(hw_gpmi_data) - mx28_reg(hw_gpmi_stat) - mx28_reg(hw_gpmi_debug) - mx28_reg(hw_gpmi_version) + mx28_reg_32(hw_gpmi_data) + mx28_reg_32(hw_gpmi_stat) + mx28_reg_32(hw_gpmi_debug) + mx28_reg_32(hw_gpmi_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h index 30e0ed7..2e2e814 100644 --- a/arch/arm/include/asm/arch-mx28/regs-i2c.h +++ b/arch/arm/include/asm/arch-mx28/regs-i2c.h @@ -27,20 +27,20 @@ #ifndef __ASSEMBLY__ struct mx28_i2c_regs { - mx28_reg(hw_i2c_ctrl0) - mx28_reg(hw_i2c_timing0) - mx28_reg(hw_i2c_timing1) - mx28_reg(hw_i2c_timing2) - mx28_reg(hw_i2c_ctrl1) - mx28_reg(hw_i2c_stat) - mx28_reg(hw_i2c_queuectrl) - mx28_reg(hw_i2c_queuestat) - mx28_reg(hw_i2c_queuecmd) - mx28_reg(hw_i2c_queuedata) - mx28_reg(hw_i2c_data) - mx28_reg(hw_i2c_debug0) - mx28_reg(hw_i2c_debug1) - mx28_reg(hw_i2c_version) + mx28_reg_32(hw_i2c_ctrl0) + mx28_reg_32(hw_i2c_timing0) + mx28_reg_32(hw_i2c_timing1) + mx28_reg_32(hw_i2c_timing2) + mx28_reg_32(hw_i2c_ctrl1) + mx28_reg_32(hw_i2c_stat) + mx28_reg_32(hw_i2c_queuectrl) + mx28_reg_32(hw_i2c_queuestat) + mx28_reg_32(hw_i2c_queuecmd) + mx28_reg_32(hw_i2c_queuedata) + mx28_reg_32(hw_i2c_data) + mx28_reg_32(hw_i2c_debug0) + mx28_reg_32(hw_i2c_debug1) + mx28_reg_32(hw_i2c_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h index ea2fd7b..2738035 100644 --- a/arch/arm/include/asm/arch-mx28/regs-ocotp.h +++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h @@ -30,49 +30,49 @@ #ifndef __ASSEMBLY__ struct mx28_ocotp_regs { - mx28_reg(hw_ocotp_ctrl) /* 0x0 */ - mx28_reg(hw_ocotp_data) /* 0x10 */ - mx28_reg(hw_ocotp_cust0) /* 0x20 */ - mx28_reg(hw_ocotp_cust1) /* 0x30 */ - mx28_reg(hw_ocotp_cust2) /* 0x40 */ - mx28_reg(hw_ocotp_cust3) /* 0x50 */ - mx28_reg(hw_ocotp_crypto0) /* 0x60 */ - mx28_reg(hw_ocotp_crypto1) /* 0x70 */ - mx28_reg(hw_ocotp_crypto2) /* 0x80 */ - mx28_reg(hw_ocotp_crypto3) /* 0x90 */ - mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */ - mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */ - mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */ - mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */ - mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */ - mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */ - mx28_reg(hw_ocotp_swcap) /* 0x100 */ - mx28_reg(hw_ocotp_custcap) /* 0x110 */ - mx28_reg(hw_ocotp_lock) /* 0x120 */ - mx28_reg(hw_ocotp_ops0) /* 0x130 */ - mx28_reg(hw_ocotp_ops1) /* 0x140 */ - mx28_reg(hw_ocotp_ops2) /* 0x150 */ - mx28_reg(hw_ocotp_ops3) /* 0x160 */ - mx28_reg(hw_ocotp_un0) /* 0x170 */ - mx28_reg(hw_ocotp_un1) /* 0x180 */ - mx28_reg(hw_ocotp_un2) /* 0x190 */ - mx28_reg(hw_ocotp_rom0) /* 0x1a0 */ - mx28_reg(hw_ocotp_rom1) /* 0x1b0 */ - mx28_reg(hw_ocotp_rom2) /* 0x1c0 */ - mx28_reg(hw_ocotp_rom3) /* 0x1d0 */ - mx28_reg(hw_ocotp_rom4) /* 0x1e0 */ - mx28_reg(hw_ocotp_rom5) /* 0x1f0 */ - mx28_reg(hw_ocotp_rom6) /* 0x200 */ - mx28_reg(hw_ocotp_rom7) /* 0x210 */ - mx28_reg(hw_ocotp_srk0) /* 0x220 */ - mx28_reg(hw_ocotp_srk1) /* 0x230 */ - mx28_reg(hw_ocotp_srk2) /* 0x240 */ - mx28_reg(hw_ocotp_srk3) /* 0x250 */ - mx28_reg(hw_ocotp_srk4) /* 0x260 */ - mx28_reg(hw_ocotp_srk5) /* 0x270 */ - mx28_reg(hw_ocotp_srk6) /* 0x280 */ - mx28_reg(hw_ocotp_srk7) /* 0x290 */ - mx28_reg(hw_ocotp_version) /* 0x2a0 */ + mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */ + mx28_reg_32(hw_ocotp_data) /* 0x10 */ + mx28_reg_32(hw_ocotp_cust0) /* 0x20 */ + mx28_reg_32(hw_ocotp_cust1) /* 0x30 */ + mx28_reg_32(hw_ocotp_cust2) /* 0x40 */ + mx28_reg_32(hw_ocotp_cust3) /* 0x50 */ + mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */ + mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */ + mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */ + mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */ + mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ + mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ + mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ + mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ + mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ + mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ + mx28_reg_32(hw_ocotp_swcap) /* 0x100 */ + mx28_reg_32(hw_ocotp_custcap) /* 0x110 */ + mx28_reg_32(hw_ocotp_lock) /* 0x120 */ + mx28_reg_32(hw_ocotp_ops0) /* 0x130 */ + mx28_reg_32(hw_ocotp_ops1) /* 0x140 */ + mx28_reg_32(hw_ocotp_ops2) /* 0x150 */ + mx28_reg_32(hw_ocotp_ops3) /* 0x160 */ + mx28_reg_32(hw_ocotp_un0) /* 0x170 */ + mx28_reg_32(hw_ocotp_un1) /* 0x180 */ + mx28_reg_32(hw_ocotp_un2) /* 0x190 */ + mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */ + mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */ + mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */ + mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */ + mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */ + mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */ + mx28_reg_32(hw_ocotp_rom6) /* 0x200 */ + mx28_reg_32(hw_ocotp_rom7) /* 0x210 */ + mx28_reg_32(hw_ocotp_srk0) /* 0x220 */ + mx28_reg_32(hw_ocotp_srk1) /* 0x230 */ + mx28_reg_32(hw_ocotp_srk2) /* 0x240 */ + mx28_reg_32(hw_ocotp_srk3) /* 0x250 */ + mx28_reg_32(hw_ocotp_srk4) /* 0x260 */ + mx28_reg_32(hw_ocotp_srk5) /* 0x270 */ + mx28_reg_32(hw_ocotp_srk6) /* 0x280 */ + mx28_reg_32(hw_ocotp_srk7) /* 0x290 */ + mx28_reg_32(hw_ocotp_version) /* 0x2a0 */ }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h index 73739ca..80dcdf6 100644 --- a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h +++ b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h @@ -30,129 +30,129 @@ #ifndef __ASSEMBLY__ struct mx28_pinctrl_regs { - mx28_reg(hw_pinctrl_ctrl) /* 0x0 */ + mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */ uint32_t reserved1[60]; - mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */ - mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */ - mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */ - mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */ - mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */ - mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */ - mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */ - mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */ - mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */ - mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */ - mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */ - mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */ - mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */ - mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */ + mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ + mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ + mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ + mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ + mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ + mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ + mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ + mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ + mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ + mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ + mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ + mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ + mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ + mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ uint32_t reserved2[72]; - mx28_reg(hw_pinctrl_drive0) /* 0x300 */ - mx28_reg(hw_pinctrl_drive1) /* 0x310 */ - mx28_reg(hw_pinctrl_drive2) /* 0x320 */ - mx28_reg(hw_pinctrl_drive3) /* 0x330 */ - mx28_reg(hw_pinctrl_drive4) /* 0x340 */ - mx28_reg(hw_pinctrl_drive5) /* 0x350 */ - mx28_reg(hw_pinctrl_drive6) /* 0x360 */ - mx28_reg(hw_pinctrl_drive7) /* 0x370 */ - mx28_reg(hw_pinctrl_drive8) /* 0x380 */ - mx28_reg(hw_pinctrl_drive9) /* 0x390 */ - mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */ - mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */ - mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */ - mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */ - mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */ - mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */ - mx28_reg(hw_pinctrl_drive16) /* 0x400 */ - mx28_reg(hw_pinctrl_drive17) /* 0x410 */ - mx28_reg(hw_pinctrl_drive18) /* 0x420 */ - mx28_reg(hw_pinctrl_drive19) /* 0x430 */ + mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */ + mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */ + mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */ + mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */ + mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */ + mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */ + mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */ + mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */ + mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */ + mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */ + mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ + mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ + mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ + mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ + mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ + mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ + mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */ + mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */ + mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */ + mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */ uint32_t reserved3[112]; - mx28_reg(hw_pinctrl_pull0) /* 0x600 */ - mx28_reg(hw_pinctrl_pull1) /* 0x610 */ - mx28_reg(hw_pinctrl_pull2) /* 0x620 */ - mx28_reg(hw_pinctrl_pull3) /* 0x630 */ - mx28_reg(hw_pinctrl_pull4) /* 0x640 */ - mx28_reg(hw_pinctrl_pull5) /* 0x650 */ - mx28_reg(hw_pinctrl_pull6) /* 0x660 */ + mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */ + mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */ + mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */ + mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */ + mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */ + mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */ + mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */ uint32_t reserved4[36]; - mx28_reg(hw_pinctrl_dout0) /* 0x700 */ - mx28_reg(hw_pinctrl_dout1) /* 0x710 */ - mx28_reg(hw_pinctrl_dout2) /* 0x720 */ - mx28_reg(hw_pinctrl_dout3) /* 0x730 */ - mx28_reg(hw_pinctrl_dout4) /* 0x740 */ + mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */ + mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */ + mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */ + mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */ + mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */ uint32_t reserved5[108]; - mx28_reg(hw_pinctrl_din0) /* 0x900 */ - mx28_reg(hw_pinctrl_din1) /* 0x910 */ - mx28_reg(hw_pinctrl_din2) /* 0x920 */ - mx28_reg(hw_pinctrl_din3) /* 0x930 */ - mx28_reg(hw_pinctrl_din4) /* 0x940 */ + mx28_reg_32(hw_pinctrl_din0) /* 0x900 */ + mx28_reg_32(hw_pinctrl_din1) /* 0x910 */ + mx28_reg_32(hw_pinctrl_din2) /* 0x920 */ + mx28_reg_32(hw_pinctrl_din3) /* 0x930 */ + mx28_reg_32(hw_pinctrl_din4) /* 0x940 */ uint32_t reserved6[108]; - mx28_reg(hw_pinctrl_doe0) /* 0xb00 */ - mx28_reg(hw_pinctrl_doe1) /* 0xb10 */ - mx28_reg(hw_pinctrl_doe2) /* 0xb20 */ - mx28_reg(hw_pinctrl_doe3) /* 0xb30 */ - mx28_reg(hw_pinctrl_doe4) /* 0xb40 */ + mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */ + mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */ + mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */ + mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */ + mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */ uint32_t reserved7[300]; - mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */ - mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */ - mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */ - mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */ - mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */ + mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ + mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ + mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ + mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ + mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ uint32_t reserved8[44]; - mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */ - mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */ - mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */ - mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */ - mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */ + mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ + mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ + mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ + mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ + mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ uint32_t reserved9[44]; - mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */ - mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */ - mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */ - mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */ - mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */ + mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ + mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ + mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ + mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ + mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ uint32_t reserved10[44]; - mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */ - mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */ - mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */ - mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */ - mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */ + mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ + mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ + mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ + mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ + mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ uint32_t reserved11[44]; - mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */ - mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */ - mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */ - mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */ - mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */ + mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ + mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ + mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ + mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ + mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ uint32_t reserved12[380]; - mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ uint32_t reserved13[76]; - mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ + mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h index 9da63ad..8eadc6d 100644 --- a/arch/arm/include/asm/arch-mx28/regs-power.h +++ b/arch/arm/include/asm/arch-mx28/regs-power.h @@ -26,10 +26,10 @@ #ifndef __ASSEMBLY__ struct mx28_power_regs { - mx28_reg(hw_power_ctrl) - mx28_reg(hw_power_5vctrl) - mx28_reg(hw_power_minpwr) - mx28_reg(hw_power_charge) + mx28_reg_32(hw_power_ctrl) + mx28_reg_32(hw_power_5vctrl) + mx28_reg_32(hw_power_minpwr) + mx28_reg_32(hw_power_charge) uint32_t hw_power_vdddctrl; uint32_t reserved_vddd[3]; uint32_t hw_power_vddactrl; @@ -44,23 +44,23 @@ struct mx28_power_regs { uint32_t reserved_misc[3]; uint32_t hw_power_dclimits; uint32_t reserved_dclimits[3]; - mx28_reg(hw_power_loopctrl) + mx28_reg_32(hw_power_loopctrl) uint32_t hw_power_sts; uint32_t reserved_sts[3]; - mx28_reg(hw_power_speed) + mx28_reg_32(hw_power_speed) uint32_t hw_power_battmonitor; uint32_t reserved_battmonitor[3]; uint32_t reserved[4]; - mx28_reg(hw_power_reset) - mx28_reg(hw_power_debug) - mx28_reg(hw_power_thermal) - mx28_reg(hw_power_usb1ctrl) - mx28_reg(hw_power_special) - mx28_reg(hw_power_version) - mx28_reg(hw_power_anaclkctrl) - mx28_reg(hw_power_refctrl) + mx28_reg_32(hw_power_reset) + mx28_reg_32(hw_power_debug) + mx28_reg_32(hw_power_thermal) + mx28_reg_32(hw_power_usb1ctrl) + mx28_reg_32(hw_power_special) + mx28_reg_32(hw_power_version) + mx28_reg_32(hw_power_anaclkctrl) + mx28_reg_32(hw_power_refctrl) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h index fe2fda9..e605a03 100644 --- a/arch/arm/include/asm/arch-mx28/regs-rtc.h +++ b/arch/arm/include/asm/arch-mx28/regs-rtc.h @@ -27,20 +27,20 @@ #ifndef __ASSEMBLY__ struct mx28_rtc_regs { - mx28_reg(hw_rtc_ctrl) - mx28_reg(hw_rtc_stat) - mx28_reg(hw_rtc_milliseconds) - mx28_reg(hw_rtc_seconds) - mx28_reg(hw_rtc_rtc_alarm) - mx28_reg(hw_rtc_watchdog) - mx28_reg(hw_rtc_persistent0) - mx28_reg(hw_rtc_persistent1) - mx28_reg(hw_rtc_persistent2) - mx28_reg(hw_rtc_persistent3) - mx28_reg(hw_rtc_persistent4) - mx28_reg(hw_rtc_persistent5) - mx28_reg(hw_rtc_debug) - mx28_reg(hw_rtc_version) + mx28_reg_32(hw_rtc_ctrl) + mx28_reg_32(hw_rtc_stat) + mx28_reg_32(hw_rtc_milliseconds) + mx28_reg_32(hw_rtc_seconds) + mx28_reg_32(hw_rtc_rtc_alarm) + mx28_reg_32(hw_rtc_watchdog) + mx28_reg_32(hw_rtc_persistent0) + mx28_reg_32(hw_rtc_persistent1) + mx28_reg_32(hw_rtc_persistent2) + mx28_reg_32(hw_rtc_persistent3) + mx28_reg_32(hw_rtc_persistent4) + mx28_reg_32(hw_rtc_persistent5) + mx28_reg_32(hw_rtc_debug) + mx28_reg_32(hw_rtc_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h index ab3870c..be71d48 100644 --- a/arch/arm/include/asm/arch-mx28/regs-ssp.h +++ b/arch/arm/include/asm/arch-mx28/regs-ssp.h @@ -29,26 +29,26 @@ #ifndef __ASSEMBLY__ struct mx28_ssp_regs { - mx28_reg(hw_ssp_ctrl0) - mx28_reg(hw_ssp_cmd0) - mx28_reg(hw_ssp_cmd1) - mx28_reg(hw_ssp_xfer_size) - mx28_reg(hw_ssp_block_size) - mx28_reg(hw_ssp_compref) - mx28_reg(hw_ssp_compmask) - mx28_reg(hw_ssp_timing) - mx28_reg(hw_ssp_ctrl1) - mx28_reg(hw_ssp_data) - mx28_reg(hw_ssp_sdresp0) - mx28_reg(hw_ssp_sdresp1) - mx28_reg(hw_ssp_sdresp2) - mx28_reg(hw_ssp_sdresp3) - mx28_reg(hw_ssp_ddr_ctrl) - mx28_reg(hw_ssp_dll_ctrl) - mx28_reg(hw_ssp_status) - mx28_reg(hw_ssp_dll_sts) - mx28_reg(hw_ssp_debug) - mx28_reg(hw_ssp_version) + mx28_reg_32(hw_ssp_ctrl0) + mx28_reg_32(hw_ssp_cmd0) + mx28_reg_32(hw_ssp_cmd1) + mx28_reg_32(hw_ssp_xfer_size) + mx28_reg_32(hw_ssp_block_size) + mx28_reg_32(hw_ssp_compref) + mx28_reg_32(hw_ssp_compmask) + mx28_reg_32(hw_ssp_timing) + mx28_reg_32(hw_ssp_ctrl1) + mx28_reg_32(hw_ssp_data) + mx28_reg_32(hw_ssp_sdresp0) + mx28_reg_32(hw_ssp_sdresp1) + mx28_reg_32(hw_ssp_sdresp2) + mx28_reg_32(hw_ssp_sdresp3) + mx28_reg_32(hw_ssp_ddr_ctrl) + mx28_reg_32(hw_ssp_dll_ctrl) + mx28_reg_32(hw_ssp_status) + mx28_reg_32(hw_ssp_dll_sts) + mx28_reg_32(hw_ssp_debug) + mx28_reg_32(hw_ssp_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h index 1b941cf..3e8dfe7 100644 --- a/arch/arm/include/asm/arch-mx28/regs-timrot.h +++ b/arch/arm/include/asm/arch-mx28/regs-timrot.h @@ -29,25 +29,25 @@ #ifndef __ASSEMBLY__ struct mx28_timrot_regs { - mx28_reg(hw_timrot_rotctrl) - mx28_reg(hw_timrot_rotcount) - mx28_reg(hw_timrot_timctrl0) - mx28_reg(hw_timrot_running_count0) - mx28_reg(hw_timrot_fixed_count0) - mx28_reg(hw_timrot_match_count0) - mx28_reg(hw_timrot_timctrl1) - mx28_reg(hw_timrot_running_count1) - mx28_reg(hw_timrot_fixed_count1) - mx28_reg(hw_timrot_match_count1) - mx28_reg(hw_timrot_timctrl2) - mx28_reg(hw_timrot_running_count2) - mx28_reg(hw_timrot_fixed_count2) - mx28_reg(hw_timrot_match_count2) - mx28_reg(hw_timrot_timctrl3) - mx28_reg(hw_timrot_running_count3) - mx28_reg(hw_timrot_fixed_count3) - mx28_reg(hw_timrot_match_count3) - mx28_reg(hw_timrot_version) + mx28_reg_32(hw_timrot_rotctrl) + mx28_reg_32(hw_timrot_rotcount) + mx28_reg_32(hw_timrot_timctrl0) + mx28_reg_32(hw_timrot_running_count0) + mx28_reg_32(hw_timrot_fixed_count0) + mx28_reg_32(hw_timrot_match_count0) + mx28_reg_32(hw_timrot_timctrl1) + mx28_reg_32(hw_timrot_running_count1) + mx28_reg_32(hw_timrot_fixed_count1) + mx28_reg_32(hw_timrot_match_count1) + mx28_reg_32(hw_timrot_timctrl2) + mx28_reg_32(hw_timrot_running_count2) + mx28_reg_32(hw_timrot_fixed_count2) + mx28_reg_32(hw_timrot_match_count2) + mx28_reg_32(hw_timrot_timctrl3) + mx28_reg_32(hw_timrot_running_count3) + mx28_reg_32(hw_timrot_fixed_count3) + mx28_reg_32(hw_timrot_match_count3) + mx28_reg_32(hw_timrot_version) }; #endif diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h index e823e19..0291d81 100644 --- a/arch/arm/include/asm/arch-mx28/regs-usbphy.h +++ b/arch/arm/include/asm/arch-mx28/regs-usbphy.h @@ -24,16 +24,16 @@ #define __REGS_USBPHY_H__ struct mx28_usbphy_regs { - mx28_reg(hw_usbphy_pwd) - mx28_reg(hw_usbphy_tx) - mx28_reg(hw_usbphy_rx) - mx28_reg(hw_usbphy_ctrl) - mx28_reg(hw_usbphy_status) - mx28_reg(hw_usbphy_debug) - mx28_reg(hw_usbphy_debug0_status) - mx28_reg(hw_usbphy_debug1) - mx28_reg(hw_usbphy_version) - mx28_reg(hw_usbphy_ip) + mx28_reg_32(hw_usbphy_pwd) + mx28_reg_32(hw_usbphy_tx) + mx28_reg_32(hw_usbphy_rx) + mx28_reg_32(hw_usbphy_ctrl) + mx28_reg_32(hw_usbphy_status) + mx28_reg_32(hw_usbphy_debug) + mx28_reg_32(hw_usbphy_debug0_status) + mx28_reg_32(hw_usbphy_debug1) + mx28_reg_32(hw_usbphy_version) + mx28_reg_32(hw_usbphy_ip) }; #define USBPHY_PWD_RXPWDRX (1 << 20) diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h index f101494..15d8de3 100644 --- a/arch/arm/include/asm/arch-mx28/sys_proto.h +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -23,9 +23,13 @@ #ifndef __MX28_H__ #define __MX28_H__ -int mx28_reset_block(struct mx28_register *reg); -int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout); -int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout); +int mx28_reset_block(struct mx28_register_32 *reg); +int mx28_wait_mask_set(struct mx28_register_32 *reg, + uint32_t mask, + int timeout); +int mx28_wait_mask_clr(struct mx28_register_32 *reg, + uint32_t mask, + int timeout); int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 0365812..38dbc81 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DIN(bank); - struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); + struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); return (readl(®->reg) >> PAD_PIN(gpio)) & 1; } @@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOUT(bank); - struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); + struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); if (value) writel(1 << PAD_PIN(gpio), ®->reg_set); @@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); - struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); + struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); writel(1 << PAD_PIN(gpio), ®->reg_clr); @@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value) { uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); - struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); + struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset); writel(1 << PAD_PIN(gpio), ®->reg_set); diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index c795f23..e1bd37e 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -75,8 +75,8 @@ int ehci_hcd_init(void) int ret; uint32_t usb_base, cap_base; - struct mx28_register *digctl_ctrl = - (struct mx28_register *)HW_DIGCTL_CTRL; + struct mx28_register_32 *digctl_ctrl = + (struct mx28_register_32 *)HW_DIGCTL_CTRL; struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; @@ -119,8 +119,8 @@ int ehci_hcd_stop(void) { int ret; uint32_t tmp; - struct mx28_register *digctl_ctrl = - (struct mx28_register *)HW_DIGCTL_CTRL; + struct mx28_register_32 *digctl_ctrl = + (struct mx28_register_32 *)HW_DIGCTL_CTRL; struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; -- cgit v0.10.2 From 531bb825fdee7fd1d14417061f07335787514f20 Mon Sep 17 00:00:00 2001 From: Robert Delien Date: Sun, 26 Feb 2012 12:15:06 +0000 Subject: Introducing 8-bit wide register, mx28_register_8 This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien Acked-by: Marek Vasut Tested-by: Marek Vasut diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index 75cc9a6..94b512d 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -47,16 +47,32 @@ * */ +#define __mx28_reg_8(name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ + #define __mx28_reg_32(name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; +struct mx28_register_8 { + __mx28_reg_8(reg) +}; + struct mx28_register_32 { __mx28_reg_32(reg) }; +#define mx28_reg_8(name) \ + union { \ + struct { __mx28_reg_8(name) }; \ + struct mx28_register_32 name##_reg; \ + }; + #define mx28_reg_32(name) \ union { \ struct { __mx28_reg_32(name) }; \ -- cgit v0.10.2 From 56df16f25ab81196669538c648ff466c24a43788 Mon Sep 17 00:00:00 2001 From: Robert Delien Date: Sun, 26 Feb 2012 12:15:07 +0000 Subject: Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien Acked-by: Marek Vasut Tested-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mx28/clock.c b/arch/arm/cpu/arm926ejs/mx28/clock.c index 9d3a018..0439f9c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/clock.c +++ b/arch/arm/cpu/arm926ejs/mx28/clock.c @@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clkctrl, clkseq, clkfrac; - uint32_t frac, div; + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); @@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void) } /* REF Path */ - clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0); - frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK; + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } @@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t frac, div; - uint32_t clkctrl, clkseq, clkfrac; + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); @@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void) return XTAL_FREQ_MHZ / div; } - clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0); - /* REF Path */ - frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >> - CLKCTRL_FRAC0_EMIFRAC_OFFSET; + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } @@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t frac, div; - uint32_t clkctrl, clkseq, clkfrac; + uint32_t clkctrl, clkseq, div; + uint8_t clkfrac, frac; clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi); @@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void) return XTAL_FREQ_MHZ / div; } - clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1); - /* REF Path */ - frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >> - CLKCTRL_FRAC1_GPMIFRAC_OFFSET; + clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]); + frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; div = clkctrl & CLKCTRL_GPMI_DIV_MASK; return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } @@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t div; + int io_reg; if (freq == 0) return; - if (io > MXC_IOCLK1) + if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) return; div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; @@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) if (div > 35) div = 35; - if (io == MXC_IOCLK0) { - writel(CLKCTRL_FRAC0_CLKGATEIO0, - &clkctrl_regs->hw_clkctrl_frac0_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_IO0FRAC_MASK, - div << CLKCTRL_FRAC0_IO0FRAC_OFFSET); - writel(CLKCTRL_FRAC0_CLKGATEIO0, - &clkctrl_regs->hw_clkctrl_frac0_clr); - } else { - writel(CLKCTRL_FRAC0_CLKGATEIO1, - &clkctrl_regs->hw_clkctrl_frac0_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_IO1FRAC_MASK, - div << CLKCTRL_FRAC0_IO1FRAC_OFFSET); - writel(CLKCTRL_FRAC0_CLKGATEIO1, - &clkctrl_regs->hw_clkctrl_frac0_clr); - } + io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); + writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[io_reg]); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); } /* @@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io) { struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t tmp, ret; + uint8_t ret; + int io_reg; - if (io > MXC_IOCLK1) + if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) return 0; - tmp = readl(&clkctrl_regs->hw_clkctrl_frac0); + io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ - if (io == MXC_IOCLK0) - ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >> - CLKCTRL_FRAC0_IO0FRAC_OFFSET; - else - ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >> - CLKCTRL_FRAC0_IO1FRAC_OFFSET; + ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & + CLKCTRL_FRAC_FRAC_MASK; return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret; } diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 4af9eb7..0b1c109 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -96,22 +96,20 @@ void mx28_mem_init_clock(void) (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; /* Gate EMI clock */ - writel(CLKCTRL_FRAC0_CLKGATEEMI, - &clkctrl_regs->hw_clkctrl_frac0_set); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); - /* EMI = 205MHz */ - writel(CLKCTRL_FRAC0_EMIFRAC_MASK, - &clkctrl_regs->hw_clkctrl_frac0_set); - writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) & - CLKCTRL_FRAC0_EMIFRAC_MASK, - &clkctrl_regs->hw_clkctrl_frac0_clr); + /* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ + writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); /* Ungate EMI clock */ - writel(CLKCTRL_FRAC0_CLKGATEEMI, - &clkctrl_regs->hw_clkctrl_frac0_clr); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); early_delay(11000); + /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), &clkctrl_regs->hw_clkctrl_emi); @@ -128,10 +126,10 @@ void mx28_mem_setup_cpu_and_hbus(void) struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - /* CPU = 454MHz and ungate CPU clock */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, - CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU, - 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET); + /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz + * and ungate CPU clock */ + writeb(19 & CLKCTRL_FRAC_FRAC_MASK, + (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); /* Set CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h index 8e666ee..3c4947d 100644 --- a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h +++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h @@ -56,8 +56,8 @@ struct mx28_clkctrl_regs { uint32_t reserved[16]; - mx28_reg_32(hw_clkctrl_frac0) /* 0x1b0 */ - mx28_reg_32(hw_clkctrl_frac1) /* 0x1c0 */ + mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ + mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */ mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */ @@ -248,35 +248,17 @@ struct mx28_clkctrl_regs { #define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) #define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) -#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31) -#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30) -#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24) -#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24 -#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23) -#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22) -#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16) -#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16 -#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15) -#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14) -#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8) -#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8 -#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7) -#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6) -#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f -#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0 - -#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23) -#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22) -#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16) -#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16 -#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15) -#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14) -#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8) -#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8 -#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7) -#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6) -#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f -#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0 +#define CLKCTRL_FRAC_CLKGATE (1 << 7) +#define CLKCTRL_FRAC_STABLE (1 << 6) +#define CLKCTRL_FRAC_FRAC_MASK 0x3f +#define CLKCTRL_FRAC_FRAC_OFFSET 0 +#define CLKCTRL_FRAC0_CPU 0 +#define CLKCTRL_FRAC0_EMI 1 +#define CLKCTRL_FRAC0_IO1 2 +#define CLKCTRL_FRAC0_IO0 3 +#define CLKCTRL_FRAC1_PIX 0 +#define CLKCTRL_FRAC1_HSADC 1 +#define CLKCTRL_FRAC1_GPMI 2 #define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) #define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) -- cgit v0.10.2 From 667c9a80082d30281978e8159958f38e8c7ef10a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 14 Feb 2012 07:29:36 +0000 Subject: .gitignore: Add .su files The '-fstack-usage' option to gcc will generate .su files, ignore them. Acked-by: Mike Frysinger Signed-off-by: Tom Rini diff --git a/.gitignore b/.gitignore index e4e95e2..0f32fd8 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ *.orig *.a *.o +*.su *~ *.swp *.patch -- cgit v0.10.2 From 6f4acc179cd73203ed9927751af083dd666c3636 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 14 Feb 2012 07:29:37 +0000 Subject: config.mk: Make cc-option create a file under include/generated Testing for -fstack-usage requires the creation of an output file, which isn't possible with /dev/null. Signed-off-by: Tom Rini diff --git a/config.mk b/config.mk index ddaa477..596ba93 100644 --- a/config.mk +++ b/config.mk @@ -108,13 +108,12 @@ HOSTCFLAGS += -pedantic # only supported compiler options are used # CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk - -$(if $(wildcard $(CC_OPTIONS_CACHE_FILE)),,\ - $(shell mkdir -p $(dir $(CC_OPTIONS_CACHE_FILE)))) +CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o -include $(CC_OPTIONS_CACHE_FILE) -cc-option-sys = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ +cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \ + if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \ > /dev/null 2>&1; then \ echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \ echo "$(1)"; fi) -- cgit v0.10.2 From 4a30f1e874a269696b983bd66673809c431edbc0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 20 Feb 2012 13:50:10 +0000 Subject: config.mk: Check for -fstack-usage support Acked-by: Mike Frysinger Signed-off-by: Tom Rini diff --git a/Makefile b/Makefile index 1446131..08921a5 100644 --- a/Makefile +++ b/Makefile @@ -747,7 +747,7 @@ clean: @rm -f $(obj)MLO @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) @find $(OBJTREE) -type f \ - \( -name 'core' -o -name '*.bak' -o -name '*~' \ + \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \ -o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \ | xargs rm -f diff --git a/config.mk b/config.mk index 596ba93..fa33e62 100644 --- a/config.mk +++ b/config.mk @@ -232,6 +232,10 @@ CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \ $(call cc-option,-Wno-format-security) CFLAGS += $(CFLAGS_WARN) +# Report stack usage if supported +CFLAGS_STACK := $(call cc-option,-fstack-usage) +CFLAGS += $(CFLAGS_STACK) + # $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g # option to the assembler. AFLAGS_DEBUG := -- cgit v0.10.2 From ad1820a3c6b16ada7a73db5720b28a804d321cb9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 14 Feb 2012 07:29:39 +0000 Subject: spl.c: Use __noreturn decorator Acked-by: Mike Frysinger Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 9c1f7e3..3a2d957 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -92,9 +92,9 @@ void spl_parse_image_header(const struct image_header *header) } } -static void jump_to_image_no_args(void) +static void __noreturn jump_to_image_no_args(void) { - typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn)); + typedef void __noreturn (*image_entry_noargs_t)(u32 *); image_entry_noargs_t image_entry = (image_entry_noargs_t) spl_image.entry_point; @@ -107,7 +107,6 @@ static void jump_to_image_no_args(void) image_entry((u32 *)boot_params_ptr_addr); } -void jump_to_image_no_args(void) __attribute__ ((noreturn)); void board_init_r(gd_t *id, ulong dummy) { u32 boot_device; -- cgit v0.10.2 From 95579793b1bd8266d55285cedc3003cbe4def7f9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 14 Feb 2012 07:29:40 +0000 Subject: README: document more SPL config options Signed-off-by: Tom Rini diff --git a/README b/README index b69a3b6..5452813 100644 --- a/README +++ b/README @@ -2464,11 +2464,29 @@ FIT uImage format: CONFIG_SPL Enable building of SPL globally. + CONFIG_SPL_LDSCRIPT + LDSCRIPT for linking the SPL binary. + + CONFIG_SPL_MAX_SIZE + Maximum binary size (text, data and rodata) of the SPL binary. + CONFIG_SPL_TEXT_BASE TEXT_BASE for linking the SPL binary. - CONFIG_SPL_LDSCRIPT - LDSCRIPT for linking the SPL binary. + CONFIG_SPL_BSS_START_ADDR + Link address for the BSS within the SPL binary. + + CONFIG_SPL_BSS_MAX_SIZE + Maximum binary size of the BSS section of the SPL binary. + + CONFIG_SPL_STACK + Adress of the start of the stack SPL will use + + CONFIG_SYS_SPL_MALLOC_START + Starting address of the malloc pool used in SPL. + + CONFIG_SYS_SPL_MALLOC_SIZE + The size of the malloc pool used in SPL. CONFIG_SPL_LIBCOMMON_SUPPORT Support for common/libcommon.o in SPL binary @@ -2485,6 +2503,45 @@ FIT uImage format: CONFIG_SPL_MMC_SUPPORT Support for drivers/mmc/libmmc.o in SPL binary + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, + CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS, + CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION + Address, size and partition on the MMC to load U-Boot from + when the MMC is being used in raw mode. + + CONFIG_SPL_FAT_SUPPORT + Support for fs/fat/libfat.o in SPL binary + + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME + Filename to read to load U-Boot when reading from FAT + + CONFIG_SPL_NAND_SIMPLE + Support for drivers/mtd/nand/libnand.o in SPL binary + + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, + CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, + CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE, + CONFIG_SYS_NAND_ECCBYTES + Defines the size and behavior of the NAND that SPL uses + to read U-Boot with CONFIG_SPL_NAND_SIMPLE + + CONFIG_SYS_NAND_U_BOOT_OFFS + Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot + from. + + CONFIG_SYS_NAND_U_BOOT_START + Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot + to. + + CONFIG_SYS_NAND_HW_ECC_OOBFIRST + Define this if you need to first read the OOB and then the + data. This is used for example on davinci plattforms. + + CONFIG_SPL_OMAP3_ID_NAND + Support for an OMAP3-specific set of functions to return the + ID and MFR of the first attached NAND chip, if present. + CONFIG_SPL_SERIAL_SUPPORT Support for drivers/serial/libserial.o in SPL binary @@ -2494,9 +2551,6 @@ FIT uImage format: CONFIG_SPL_SPI_SUPPORT Support for drivers/spi/libspi.o in SPL binary - CONFIG_SPL_FAT_SUPPORT - Support for fs/fat/libfat.o in SPL binary - CONFIG_SPL_LIBGENERIC_SUPPORT Support for lib/libgeneric.o in SPL binary @@ -3344,11 +3398,6 @@ Low Level (hardware related) configuration options: that is executed before the actual U-Boot. E.g. when compiling a NAND SPL. -- CONFIG_SYS_NAND_HW_ECC_OOBFIRST - define this, if you want to read first the oob data - and then the data. This is used for example on - davinci plattforms. - - CONFIG_USE_ARCH_MEMCPY CONFIG_USE_ARCH_MEMSET If these options are used a optimized version of memcpy/memset will -- cgit v0.10.2 From 71e6840279e3da7f5c0c1f8002bb9943bd90aec6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 20 Feb 2012 13:27:43 +0000 Subject: SPL: Add README.omap3 This document describes the SPL process for OMAP3 (and related) boards as well as a partial memory map and how to verify certain aspects outside of running on the target. Signed-off-by: Tom Rini diff --git a/doc/SPL/README.omap3 b/doc/SPL/README.omap3 new file mode 100644 index 0000000..cc5d5c0 --- /dev/null +++ b/doc/SPL/README.omap3 @@ -0,0 +1,74 @@ +Overview of SPL on OMAP3 devices +================================ + +Introduction +------------ + +This document provides an overview of how SPL functions on OMAP3 (and related +such as am35x and am37x) processors. + +Methodology +----------- + +On these platforms the ROM supports trying a sequence of boot devices. Once +one has been used successfully to load SPL this information is stored in memory +and the location stored in a register. We will read this to determine where to +read U-Boot from in turn. + +Memory Map +---------- + +This is an example of a typical setup. See top-level README for documentation +of which CONFIG variables control these values. For a given board and the +amount of DRAM available to it different values may need to be used. +Note that the size of the SPL text rodata and data is enforced with a CONFIG +option and growing over that size results in a link error. The SPL stack +starts at the top of SRAM (which is configurable) and grows downward. The +space between the top of SRAM and the enforced upper bound on the size of the +SPL text, data and rodata is considered the safe stack area. Details on +confirming this behavior are shown below. + +A portion of the system memory map looks as follows: +SRAM: 0x40200000 - 0x4020FFFF +DDR1: 0x80000000 - 0xBFFFFFFF + +Option 1 (SPL only): +0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata +0x4020BC00 - 0x4020FFFC: Area for the SPL stack. +0x80000000 - 0x8007FFFF: Area for the SPL BSS. +0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot +0x80208000 - 0x80307FFF: malloc() pool available to SPL. + +Option 2 (SPL or X-Loader): +0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata +0x4020BC00 - 0x4020FFFC: Area for the SPL stack. +0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot +0x87000000 - 0x8707FFFF: Area for the SPL BSS. +0x87080000 - 0x870FFFFF: malloc() pool available to SPL. + +For the areas that reside within DDR1 they must not be used prior to s_init() +completing. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL +uses while running. This is why we have two versions of the memory map that +only vary in where the BSS and malloc pool reside. + +Estimating stack usage +---------------------- + +With gcc 4.6 (and later) and the use of GNU cflow it is possible to estimate +stack usage at various points in run sequence of SPL. The -fstack-usage option +to gcc will produce '.su' files (such as arch/arm/cpu/armv7/syslib.su) that +will give stack usage information and cflow can construct program flow. + +Must have gcc 4.6 or later, which supports -fstack-usage + +1) Build normally +2) Perform the following shell command to generate a list of C files used in +SPL: +$ find spl -name '*.su' | sed -e 's:^spl/::' -e 's:[.]su$:.c:' > used-spl.list +3) Execute cflow: +$ cflow --main=board_init_r `cat used-spl.list` 2>&1 | $PAGER + +cflow will spit out a number of warnings as it does not parse +the config files and picks functions based on #ifdef. Parsing the '.i' +files instead introduces another set of headaches. These warnings are +not usually important to understanding the flow, however. -- cgit v0.10.2 From 24de357a30dbabf8e0eb5acb43397851b0bc53fb Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Tue, 31 Jan 2012 12:03:57 +0000 Subject: SPL: Add YMODEM over UART load support Adds support for loading U-Boot from UART using YMODEM protocol. If YMODEM support is enabled in SPL and the romcode indicates that SPL loaded via UART then SPL will wait for start of a YMODEM transfer via the console port. Signed-off-by: Matt Porter Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 3f7a0b2..447fcd5 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -52,6 +52,9 @@ endif ifdef CONFIG_SPL_MMC_SUPPORT COBJS += spl_mmc.o endif +ifdef CONFIG_SPL_YMODEM_SUPPORT +COBJS += spl_ymodem.o +endif endif ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 3a2d957..99bb382 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -133,6 +133,11 @@ void board_init_r(gd_t *id, ulong dummy) spl_nand_load_image(); break; #endif +#ifdef CONFIG_SPL_YMODEM_SUPPORT + case BOOT_DEVICE_UART: + spl_ymodem_load_image(); + break; +#endif default: printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); hang(); diff --git a/arch/arm/cpu/armv7/omap-common/spl_ymodem.c b/arch/arm/cpu/armv7/omap-common/spl_ymodem.c new file mode 100644 index 0000000..47663f7 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/spl_ymodem.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2011 + * Texas Instruments, + * + * Matt Porter + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#define BUF_SIZE 1024 + +static int getcymodem(void) { + if (tstc()) + return (getc()); + return -1; +} + +void spl_ymodem_load_image(void) +{ + int size = 0; + int err; + int res; + int ret; + connection_info_t info; + char buf[BUF_SIZE]; + ulong store_addr = ~0; + ulong addr = 0; + + info.mode = xyzModem_ymodem; + ret = xyzModem_stream_open(&info, &err); + + if (!ret) { + while ((res = + xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) { + if (addr == 0) + spl_parse_image_header((struct image_header *)buf); + store_addr = addr + spl_image.load_addr; + size += res; + addr += res; + memcpy((char *)(store_addr), buf, res); + } + } else { + printf("spl: ymodem err - %s\n", xyzModem_error(err)); + hang(); + } + + xyzModem_stream_close(&err); + xyzModem_stream_terminate(false, &getcymodem); + + printf("Loaded %d bytes\n", size); +} diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 34bec45..25f95b4 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -99,6 +99,9 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +/* YMODEM SPL functions */ +void spl_ymodem_load_image(void); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/common/Makefile b/common/Makefile index fd9b3b0..04faa0b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -185,6 +185,9 @@ COBJS-$(CONFIG_UPDATE_TFTP) += update.o COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o endif +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o +endif COBJS-y += console.o COBJS-y += dlmalloc.o COBJS-y += memsize.o diff --git a/lib/Makefile b/lib/Makefile index e6e6ec6..4b5734a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -55,6 +55,9 @@ else COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o endif +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +endif COBJS-y += ctype.o COBJS-y += div64.o COBJS-y += string.o -- cgit v0.10.2 From 763cf0a3d24124916824e31793fbafbbb4311597 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Tue, 31 Jan 2012 12:03:58 +0000 Subject: SPL: Enable YMODEM support on BeagleBone and AM335x EVM Cc: Chandan Nath Tested-by: Tom Rini Signed-off-by: Matt Porter diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 6683b3e..d0fbc88 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -145,6 +145,7 @@ #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* -- cgit v0.10.2 From e0e7f3b210ce553c6caab05b71891a1279eb551e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 00:44:22 +0100 Subject: Examples: Properly append LDFLAGS to LD command The LD command in examples/standalone/Makefile ignored platform specific LDFLAGS setup. Pass these LDFLAGS to the command. Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index e23865b..baaa2fb 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -96,7 +96,7 @@ $(LIB): $(obj).depend $(LIBOBJS) $(ELF): $(obj)%: $(obj)%.o $(LIB) - $(LD) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ + $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc -- cgit v0.10.2 From 696df71b5f564916db6762b8f21605676abc6baf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 00:00:12 +0100 Subject: IXP: Make IXP buildable with arm-linux- toolchains Add -EB flag to LD to switch endianness of the linker. This should make armeb targets buildable again. Also, make use of U-Boot's internal libgcc instead of toolchain's one, this works around the use of libraries from GCC, which might be little endian. Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk index 9149665..b02e8af 100644 --- a/arch/arm/cpu/ixp/config.mk +++ b/arch/arm/cpu/ixp/config.mk @@ -28,6 +28,9 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 +PLATFORM_LDFLAGS += -EB +USE_PRIVATE_LIBGCC = yes + # -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error PLATFORM_RELFLAGS += -ffunction-sections LDFLAGS_u-boot += --gc-sections -- cgit v0.10.2 From 8e807ec3aa977fd50bea18ce0b51b15877a6bde5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 00:45:35 +0100 Subject: IXP: Fix missing MACH_TYPE_{ACTUX?,PNB3,DVLHOST} These symbols are no longer defined in Linux-ARM's mach-types files. Replace these with CONFIG_MACH_TYPE instead. Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index 2f631b7..bc68eb3 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -59,8 +59,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c index 9040a09..9e9e600 100644 --- a/board/actux2/actux2.c +++ b/board/actux2/actux2.c @@ -59,8 +59,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX2; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c index 64e5215..7559c1d 100644 --- a/board/actux3/actux3.c +++ b/board/actux3/actux3.c @@ -57,8 +57,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX3; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c index d20d881..6303c1e 100644 --- a/board/actux4/actux4.c +++ b/board/actux4/actux4.c @@ -54,8 +54,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX4; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c index 561e47f..c2c67cc 100644 --- a/board/dvlhost/dvlhost.c +++ b/board/dvlhost/dvlhost.c @@ -46,8 +46,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_DVLHOST; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c index 3aaebf2..d3ee133 100644 --- a/board/prodrive/pdnb3/pdnb3.c +++ b/board/prodrive/pdnb3/pdnb3.c @@ -46,9 +46,6 @@ static unsigned long old_val = 0; */ int board_init(void) { - /* arch number of PDNB3 */ - gd->bd->bi_arch_number = MACH_TYPE_PDNB3; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/include/configs/actux1.h b/include/configs/actux1.h index 00780d0..bdd2239 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX1 1 +#define CONFIG_MACH_TYPE 1479 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/actux2.h b/include/configs/actux2.h index cb97434..c55571c 100644 --- a/include/configs/actux2.h +++ b/include/configs/actux2.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX2 1 +#define CONFIG_MACH_TYPE 1480 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 816d982..78ee2b5 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX3 1 +#define CONFIG_MACH_TYPE 1481 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/actux4.h b/include/configs/actux4.h index 90badd3..c1105df 100644 --- a/include/configs/actux4.h +++ b/include/configs/actux4.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX4 1 +#define CONFIG_MACH_TYPE 1532 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h index 86fecd1..4eda91e 100644 --- a/include/configs/dvlhost.h +++ b/include/configs/dvlhost.h @@ -30,6 +30,8 @@ #define CONFIG_IXP425 1 #define CONFIG_DVLHOST 1 +#define CONFIG_MACH_TYPE 1343 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 56bb464..43ec38f 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -33,6 +33,8 @@ #define CONFIG_IXP425 1 /* This is an IXP425 CPU */ #define CONFIG_PDNB3 1 /* on an PDNB3 board */ +#define CONFIG_MACH_TYPE 1002 + #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ -- cgit v0.10.2 From 0c7857f253771d7fdc3fefa1e9c8cb7cb7a369d7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 01:00:52 +0100 Subject: IXP: Squash warnings in IXP NPE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IxEthAcc.c: In function ‘ixEthAccInit’: IxEthAcc.c:105:21: warning: comparison between ‘IxEthDBStatus’ and ‘enum ’ [-Wenum-compare] IxEthDBAPISupport.c: In function ‘ixEthDBPortAddressSet’: IxEthDBAPISupport.c:633:18: warning: variable ‘ackPortAddressLock’ set but not used [-Wunused-but-set-variable] IxQMgrDispatcher.c: In function ‘ixQMgrLLPShow’: IxQMgrDispatcher.c:1194:18: warning: variable ‘q’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/arch/arm/cpu/ixp/npe/IxEthAcc.c b/arch/arm/cpu/ixp/npe/IxEthAcc.c index 061b24b..20d3d9e 100644 --- a/arch/arm/cpu/ixp/npe/IxEthAcc.c +++ b/arch/arm/cpu/ixp/npe/IxEthAcc.c @@ -102,7 +102,7 @@ PUBLIC IxEthAccStatus ixEthAccInit() /* * Initialize Control plane */ - if (ixEthDBInit() != IX_ETH_ACC_SUCCESS) + if (ixEthDBInit() != IX_ETH_DB_SUCCESS) { IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0); diff --git a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c b/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c index 25633a3..36bc200 100644 --- a/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c +++ b/arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c @@ -630,7 +630,6 @@ IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) { IxNpeMhMessage message; - IxOsalMutex *ackPortAddressLock; IX_STATUS result; /* use this macro instead CHECK_PORT @@ -644,8 +643,6 @@ IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAdd return IX_ETH_DB_PORT_UNINITIALIZED; } - ackPortAddressLock = &ixEthDBPortInfo[portID].npeAckLock; - /* Operation stops here when Ethernet Learning is not enabled */ if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c index 642e67a..9cb1439 100644 --- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c +++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c @@ -1191,7 +1191,6 @@ ixQMgrLLPShow (int resetStats) { #ifndef NDEBUG UINT8 i = 0; - IxQMgrQInfo *q; UINT32 intEnableRegVal = 0; printf ("Livelock statistics are printed on the fly.\n"); @@ -1200,8 +1199,6 @@ ixQMgrLLPShow (int resetStats) for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) { - q = &dispatchQInfo[i]; - if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER) { printf (" %2d ", i); -- cgit v0.10.2 From 2152df67c351f167641e0000177c0de746be8665 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 01:02:14 +0100 Subject: IXP: Move PDNB3 and SCPU from Makefile to boards.cfg Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/Makefile b/Makefile index 08921a5..01bf2b0 100644 --- a/Makefile +++ b/Makefile @@ -677,18 +677,6 @@ SX1_config: unconfig @$(MKCONFIG) -n $@ SX1 arm arm925t sx1 ######################################################################### -## XScale Systems -######################################################################### - -pdnb3_config \ -scpu_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring scpu_,$@)" ] ; then \ - echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \ - fi - @$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive - -######################################################################### ## ARM1176 Systems ######################################################################### smdk6400_noUSB_config \ diff --git a/boards.cfg b/boards.cfg index 28cc345..ade2034 100644 --- a/boards.cfg +++ b/boards.cfg @@ -244,6 +244,8 @@ actux2 arm ixp actux3 arm ixp actux4 arm ixp dvlhost arm ixp +pdnb3 arm ixp pdnb3 prodrive +scpu arm ixp pdnb3 prodrive - pdnb3:SCPU balloon3 arm pxa lubbock arm pxa palmld arm pxa -- cgit v0.10.2 From 44e63c228ea8730af5782d1c29c5bef2e57c9b0e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 01:10:00 +0100 Subject: IXP: Fix NAND build warning on PDNB3 and SCPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nand.c: In function ‘pdnb3_nand_read_buf’: nand.c:107:4: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] nand.c: In function ‘pdnb3_nand_dev_ready’: nand.c:124:18: warning: variable ‘val’ set but not used [-Wunused-but-set-variable] Remove the 4-byte-at-time read mode altogether, the most is bogus and will likely cause unaligned accesses. Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c index 2efe027..6d1f203 100644 --- a/board/prodrive/pdnb3/nand.c +++ b/board/prodrive/pdnb3/nand.c @@ -96,16 +96,8 @@ static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; - if (len % 4) { - for (i = 0; i < len; i++) - buf[i] = readb(&(pdnb3_ndfc->data)); - } else { - ulong *ptr = (ulong *)buf; - int count = len >> 2; - - for (i = 0; i < count; i++) - *ptr++ = readl(&(pdnb3_ndfc->data)); - } + for (i = 0; i < len; i++) + buf[i] = readb(&(pdnb3_ndfc->data)); } static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) @@ -121,12 +113,10 @@ static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int le static int pdnb3_nand_dev_ready(struct mtd_info *mtd) { - volatile u_char val; - /* * Blocking read to wait for NAND to be ready */ - val = readb(&(pdnb3_ndfc->wait)); + readb(&(pdnb3_ndfc->wait)); /* * Return always true -- cgit v0.10.2 From cd207cde948ecf9ff50a0fa1ae2650f65579c9c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 11:57:43 +0100 Subject: IXP: Fix GPIO_INT_ACT_LOW_SET() The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7. This is due to the fact that there are two registers for total of 16 lines. Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h index 5132607..c2e9c82 100644 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ b/arch/arm/include/asm/arch-ixp/ixp425.h @@ -358,6 +358,9 @@ #define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) #define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) +#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \ + IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R) + /* * Macros to make it easy to access the GPIO registers */ @@ -365,8 +368,11 @@ #define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) #define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) #define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) -#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \ - (*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3)) +#define GPIO_INT_ACT_LOW_SET(line) \ + *IXP425_GPIO_GPITR(line) = \ + (*IXP425_GPIO_GPITR(line) & \ + ~(0x7 << (((line) & 0x7) * 3))) | \ + (0x1 << (((line) & 0x7) * 3)) \ /* * Constants to make it easy to access Timer Control/Status registers -- cgit v0.10.2 From 49d3e2721164eaef5df702a26cfca6efd430be30 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Wed, 22 Feb 2012 22:50:19 +0000 Subject: imximage: Remove overwriting of flash_offset The flash header supports different flash offsets for different boot devices. E.g. parallel NOR or OneNAND use a different offset than FLASH_OFFSET_STANDARD (== 0x400). The flash offset is correctly read from the configuration in parse_cfg_cmd(). But is then overwritten wrongly in set_imx_hdr_v1/2(). Fix this by removing this overwriting. Use the flash offset correctly read from the configuration, instead. If there is no flash_offset read from the configuration file, i.e. the BOOT_FROM tag is missing, exit with an error message. Signed-off-by: Dirk Behme CC: Jason Liu CC: Stefano Babic Tested-by: Stefano Babic diff --git a/tools/imximage.c b/tools/imximage.c index 1e0f5d4..03a7716 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -216,8 +216,12 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len, dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table; uint32_t base_offset; - /* Set default offset */ - imxhdr->flash_offset = FLASH_OFFSET_STANDARD; + /* Exit if there is no BOOT_FROM field specifying the flash_offset */ + if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) { + fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n", + params->imagename); + exit(EXIT_FAILURE); + } /* Set magic number */ fhdr_v1->app_code_barker = APP_CODE_BARKER; @@ -253,8 +257,12 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len, imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2; flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr; - /* Set default offset */ - imxhdr->flash_offset = FLASH_OFFSET_STANDARD; + /* Exit if there is no BOOT_FROM field specifying the flash_offset */ + if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) { + fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n", + params->imagename); + exit(EXIT_FAILURE); + } /* Set magic number */ fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ @@ -525,6 +533,8 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * set up function ptr group to V1 by default. */ imximage_version = IMXIMAGE_V1; + /* Be able to detect if the cfg file has no BOOT_FROM tag */ + imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED; set_hdr_func(imxhdr); /* Parse dcd configuration file */ diff --git a/tools/imximage.h b/tools/imximage.h index d784a8d..34f293d 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -32,6 +32,7 @@ #define HEADER_OFFSET 0x400 #define CMD_DATA_STR "DATA" +#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF #define FLASH_OFFSET_STANDARD 0x400 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD -- cgit v0.10.2 From 9ff323df76b677fb64ae8490e5fafd3a2e51e8da Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 2 Mar 2012 12:55:09 +0000 Subject: i.MX6: mx6qsabrelite: add ext2 support Current Ubuntu releases from Freescale contain a boot script in ext3 filesystem. Signed-off-by: Eric Nelson diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 93000f0..bb3a46b 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -64,6 +64,7 @@ #define CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -- cgit v0.10.2 From 0bd14dea635e95eb7c16bb93fac38a76095fb586 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:08 +0000 Subject: mx51evk: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3b18a18..1477b21 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -199,7 +199,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x90010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From bc9d5ef107b3feca44eacd18b321e8b4547462f9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:09 +0000 Subject: mx53evk: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Cc: Jason Liu Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 11fe6ef..a77e5b2 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -161,7 +161,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From 869aed7bcea04e449521fdf5f494207b13afed6b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:10 +0000 Subject: mx53smd: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 032f722..a04db3f 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -149,7 +149,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From f361a5c0753f910f1bc3db51970120df77499b2e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:11 +0000 Subject: efikamx: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Cc: Marek Vasut Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Tested-by: Marek Vasut diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index e2f0f74..af542fa 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -240,7 +240,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x90010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From 304e49e6cbec7ce8577a528e5be36930d098243b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:07 +0000 Subject: mx31pdk: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 4da6020..49d440b 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -141,7 +141,7 @@ /* memtest works on */ #define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x80010000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 -- cgit v0.10.2 From 82081406a2acd15fb4b4beed7f91f57f56c9365f Mon Sep 17 00:00:00 2001 From: Helmut Raiger Date: Wed, 15 Feb 2012 22:44:34 +0000 Subject: mx31: add "ARM11P power gating" to get_reset_cause Add missing reset reason 7 to get_reset_cause(). Signed-off-by: Helmut Raiger diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index d60afc9..8873fb7 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -210,6 +210,8 @@ static char *get_reset_cause(void) return "WDOG"; case 0x0006: return "JTAG"; + case 0x0007: + return "ARM11P power gating"; default: return "unknown reset"; } -- cgit v0.10.2 From d928a8f3f395040a2d204543eb96b8796aa425fc Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 26 Feb 2012 12:03:15 +0000 Subject: mx6q: mx6qsabrelite: setup_spi() should be called in board_init to allow use for environment Signed-off-by: Eric Nelson diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index db1bea9..7fe2dc9 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -259,10 +259,6 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - return 0; } @@ -278,6 +274,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; } -- cgit v0.10.2 From 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Feb 2012 12:15:04 +0000 Subject: i.MX28: Enable additional DRAM address bits Enables all fourteen address lines for DRAM Signed-off-by: Marek Vasut Acked-by: Marek Vasut Tested-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 0b1c109..43a90ff 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -39,7 +39,7 @@ uint32_t dram_vals[] = { 0x00000000, 0x00000100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010101, 0x01010101, - 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, -- cgit v0.10.2 From 1c9ceff8ca896bd04cc2c85f762662dceecd7927 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 12 Mar 2012 15:04:12 +0000 Subject: i.MX6: mx6q_sabrelite: add CONFIG_REVISION_TAG This is needed to support Freescale-supplied userspaces. At the moment, both the IPU and VPU libraries provided by Freescale in the "imx-lib" package contain routines which scrape the system revision from /proc/cpuinfo. In the VPU library, this information is used to load the proper firmware, allowing a single binary to be used across various i.MX processors. Signed-off-by: Eric Nelson Acked-by: Marek Vasut Acked-by: Stefano Babic diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 7fe2dc9..1d09a72 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -215,6 +215,11 @@ int board_mmc_init(bd_t *bis) } #endif +u32 get_board_rev(void) +{ + return 0x63000 ; +} + #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t ecspi1_pads[] = { /* SS1 */ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index bb3a46b..a1a2267 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -33,6 +33,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -- cgit v0.10.2 From c338f0b5c60d3b133139539fdfc39d2f2cb29b06 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 4 Mar 2012 10:51:36 +0000 Subject: i.MX6: mx6qsabrelite: add MACH_TYPE_MX6Q_SABRELITE Allow non-dt kernels to boot Signed-off-by: Troy Kisky diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index a1a2267..8bc8a83 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -28,6 +28,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MACH_TYPE 3769 + #include #define CONFIG_CMDLINE_TAG -- cgit v0.10.2 From cece262209aaacf6f842c8d15832f882eb2467d8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 13 Mar 2012 07:26:48 +0000 Subject: mx6: Fix reset cause for Power On Reset case After booting mx6qsabrelite from POR the following is reported: CPU: Freescale i.MX61 family rev1.0 at 792 MHz Reset cause: unknown reset This is because both the POR and WDOG bits are set after reset. Fix this by also checking both bits in the POR case. Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 1e30ae5..6d7486b 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -44,6 +44,7 @@ static char *get_reset_cause(void) switch (cause) { case 0x00001: + case 0x00011: return "POR"; case 0x00004: return "CSU"; -- cgit v0.10.2 From 334bd0e225ade19f3a3ac91e4f89fe8a2c6ea0b5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 13 Mar 2012 07:26:49 +0000 Subject: mx6: Remove duplicate definition of ANATOP_BASE_ADDR Remove duplicate definition of ANATOP_BASE_ADDR. Signed-off-by: Fabio Estevam diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 6a200bb..5ba5f39 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -115,7 +115,6 @@ #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) -- cgit v0.10.2 From a22429d2bfaa16588635a02958ebcd06114dd697 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Mar 2012 11:32:09 +0000 Subject: pmic_i2c: Return error in case of invalid pmic_i2c_tx_num Return error in case of invalid pmic_i2c_tx_num. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Acked-by: Lukasz Majewski Acked-by: Stefano Babic diff --git a/drivers/misc/pmic_i2c.c b/drivers/misc/pmic_i2c.c index ad55d64..95a3365 100644 --- a/drivers/misc/pmic_i2c.c +++ b/drivers/misc/pmic_i2c.c @@ -47,6 +47,9 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) case 1: buf[0] = val & 0xff; break; + default: + printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num); + return -1; } if (i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num)) @@ -73,6 +76,9 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) case 1: ret_val = buf[0]; break; + default: + printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num); + return -1; } memcpy(val, &ret_val, sizeof(ret_val)); -- cgit v0.10.2 From a89300338a0d0c43ff21c50d793782c310c882ee Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Jan 2012 14:05:39 +0000 Subject: i.MX28: Make the stabilization delays shorter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be enough according to the datasheet and bootlets. Signed-off-by: Marek Vasut Cc: Wolfgang Denk Cc: Detlev Zundel Cc: Stefano Babic Cc: Robert Deliën Cc: Fabio Estevam Cc: Matthias Fuchs diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 271da8d..aa4117d 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -729,7 +729,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) @@ -766,7 +766,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) @@ -826,7 +826,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) @@ -863,7 +863,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) - early_delay(1500); + early_delay(500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) -- cgit v0.10.2 From d9fb6a4c7e61d735eec2936a8dc3877f83e61d24 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 18 Mar 2012 17:23:35 +0000 Subject: mxs_spi: Return proper timeout error Instead of returning -1, it is preferred to return -ETIMEDOUT in case of timeouts. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index adb9ca8..4e6f14e 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -162,7 +162,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg, SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { printf("MXS SPI: Timeout waiting for start\n"); - return -1; + return -ETIMEDOUT; } if (tx) @@ -174,7 +174,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { printf("MXS SPI: Timeout waiting for data\n"); - return -1; + return -ETIMEDOUT; } *rx = readl(&ssp_regs->hw_ssp_data); @@ -184,7 +184,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { printf("MXS SPI: Timeout waiting for finish\n"); - return -1; + return -ETIMEDOUT; } } -- cgit v0.10.2 From 494931a67465a95b66da346ec7bd002fdf40adee Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 16 Mar 2012 11:32:43 +0000 Subject: i.MX28: Drop __naked function from spl_mem_init Instead of compiling the function and using the result as a constant, simply use the constant. NOTE: This patch works around bug: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546 Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Tom Rini diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 43a90ff..911bbef 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -173,22 +173,18 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } -void data_abort_memdetect_handler(void) __attribute__((naked)); -void data_abort_memdetect_handler(void) -{ - asm volatile("subs pc, r14, #4"); -} - void mx28_mem_get_size(void) { struct mx28_digctl_regs *digctl_regs = (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; + /* The following is "subs pc, r14, #4", used as return from DABT. */ + const uint32_t data_abort_memdetect_handler = 0xe25ef004; /* Replace the DABT handler. */ da = vt[4]; - vt[4] = (uint32_t)&data_abort_memdetect_handler; + vt[4] = data_abort_memdetect_handler; sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); writel(sz, &digctl_regs->hw_digctl_scratch0); -- cgit v0.10.2 From a7683867463481bfea84af4d60af832ddfb3da7f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Mar 2012 04:21:45 +0000 Subject: mx6: Read silicon revision from register Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam Acked-by: Stefano Babic Acked-by: Jason Liu diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 6d7486b..3d58d8a 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -64,13 +64,33 @@ static char *get_reset_cause(void) } #if defined(CONFIG_DISPLAY_CPUINFO) + +static char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case 0x63: + return "6Q"; /* Quad-core version of the mx6 */ + case 0x61: + return "6DS"; /* Dual/Solo version of the mx6 */ + case 0x60: + return "6SL"; /* Solo-Lite version of the mx6 */ + case 0x51: + return "51"; + case 0x53: + return "53"; + default: + return "unknown"; + } +} + int print_cpuinfo(void) { u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", - (cpurev & 0xFF000) >> 12, + + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2ac74b5..a81e2bc 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -32,7 +32,13 @@ u32 get_cpu_rev(void) { - int system_rev = 0x61000 | CHIP_REV_1_0; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg = readl(&anatop->digprog); + + /* Read mx6 variant: quad, dual or solo */ + int system_rev = (reg >> 4) & 0xFF000; + /* Read mx6 silicon revision */ + system_rev |= (reg & 0xFF) + 0x10; return system_rev; } diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5ba5f39..cad957a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -294,5 +294,147 @@ struct aipstz_regs { u32 opacr4; }; +struct anatop_regs { + u32 pll_sys; /* 0x000 */ + u32 pll_sys_set; /* 0x004 */ + u32 pll_sys_clr; /* 0x008 */ + u32 pll_sys_tog; /* 0x00c */ + u32 usb1_pll_480_ctrl; /* 0x010 */ + u32 usb1_pll_480_ctrl_set; /* 0x014 */ + u32 usb1_pll_480_ctrl_clr; /* 0x018 */ + u32 usb1_pll_480_ctrl_tog; /* 0x01c */ + u32 usb2_pll_480_ctrl; /* 0x020 */ + u32 usb2_pll_480_ctrl_set; /* 0x024 */ + u32 usb2_pll_480_ctrl_clr; /* 0x028 */ + u32 usb2_pll_480_ctrl_tog; /* 0x02c */ + u32 pll_528; /* 0x030 */ + u32 pll_528_set; /* 0x034 */ + u32 pll_528_clr; /* 0x038 */ + u32 pll_528_tog; /* 0x03c */ + u32 pll_528_ss; /* 0x040 */ + u32 rsvd0[3]; + u32 pll_528_num; /* 0x050 */ + u32 rsvd1[3]; + u32 pll_528_denom; /* 0x060 */ + u32 rsvd2[3]; + u32 pll_audio; /* 0x070 */ + u32 pll_audio_set; /* 0x074 */ + u32 pll_audio_clr; /* 0x078 */ + u32 pll_audio_tog; /* 0x07c */ + u32 pll_audio_num; /* 0x080 */ + u32 rsvd3[3]; + u32 pll_audio_denom; /* 0x090 */ + u32 rsvd4[3]; + u32 pll_video; /* 0x0a0 */ + u32 pll_video_set; /* 0x0a4 */ + u32 pll_video_clr; /* 0x0a8 */ + u32 pll_video_tog; /* 0x0ac */ + u32 pll_video_num; /* 0x0b0 */ + u32 rsvd5[3]; + u32 pll_video_denom; /* 0x0c0 */ + u32 rsvd6[3]; + u32 pll_mlb; /* 0x0d0 */ + u32 pll_mlb_set; /* 0x0d4 */ + u32 pll_mlb_clr; /* 0x0d8 */ + u32 pll_mlb_tog; /* 0x0dc */ + u32 pll_enet; /* 0x0e0 */ + u32 pll_enet_set; /* 0x0e4 */ + u32 pll_enet_clr; /* 0x0e8 */ + u32 pll_enet_tog; /* 0x0ec */ + u32 pfd_480; /* 0x0f0 */ + u32 pfd_480_set; /* 0x0f4 */ + u32 pfd_480_clr; /* 0x0f8 */ + u32 pfd_480_tog; /* 0x0fc */ + u32 pfd_528; /* 0x100 */ + u32 pfd_528_set; /* 0x104 */ + u32 pfd_528_clr; /* 0x108 */ + u32 pfd_528_tog; /* 0x10c */ + u32 reg_1p1; /* 0x110 */ + u32 reg_1p1_set; /* 0x114 */ + u32 reg_1p1_clr; /* 0x118 */ + u32 reg_1p1_tog; /* 0x11c */ + u32 reg_3p0; /* 0x120 */ + u32 reg_3p0_set; /* 0x124 */ + u32 reg_3p0_clr; /* 0x128 */ + u32 reg_3p0_tog; /* 0x12c */ + u32 reg_2p5; /* 0x130 */ + u32 reg_2p5_set; /* 0x134 */ + u32 reg_2p5_clr; /* 0x138 */ + u32 reg_2p5_tog; /* 0x13c */ + u32 reg_core; /* 0x140 */ + u32 reg_core_set; /* 0x144 */ + u32 reg_core_clr; /* 0x148 */ + u32 reg_core_tog; /* 0x14c */ + u32 ana_misc0; /* 0x150 */ + u32 ana_misc0_set; /* 0x154 */ + u32 ana_misc0_clr; /* 0x158 */ + u32 ana_misc0_tog; /* 0x15c */ + u32 ana_misc1; /* 0x160 */ + u32 ana_misc1_set; /* 0x164 */ + u32 ana_misc1_clr; /* 0x168 */ + u32 ana_misc1_tog; /* 0x16c */ + u32 ana_misc2; /* 0x170 */ + u32 ana_misc2_set; /* 0x174 */ + u32 ana_misc2_clr; /* 0x178 */ + u32 ana_misc2_tog; /* 0x17c */ + u32 tempsense0; /* 0x180 */ + u32 tempsense0_set; /* 0x184 */ + u32 tempsense0_clr; /* 0x188 */ + u32 tempsense0_tog; /* 0x18c */ + u32 tempsense1; /* 0x190 */ + u32 tempsense1_set; /* 0x194 */ + u32 tempsense1_clr; /* 0x198 */ + u32 tempsense1_tog; /* 0x19c */ + u32 usb1_vbus_detect; /* 0x1a0 */ + u32 usb1_vbus_detect_set; /* 0x1a4 */ + u32 usb1_vbus_detect_clr; /* 0x1a8 */ + u32 usb1_vbus_detect_tog; /* 0x1ac */ + u32 usb1_chrg_detect; /* 0x1b0 */ + u32 usb1_chrg_detect_set; /* 0x1b4 */ + u32 usb1_chrg_detect_clr; /* 0x1b8 */ + u32 usb1_chrg_detect_tog; /* 0x1bc */ + u32 usb1_vbus_det_stat; /* 0x1c0 */ + u32 usb1_vbus_det_stat_set; /* 0x1c4 */ + u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ + u32 usb1_vbus_det_stat_tog; /* 0x1cc */ + u32 usb1_chrg_det_stat; /* 0x1d0 */ + u32 usb1_chrg_det_stat_set; /* 0x1d4 */ + u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ + u32 usb1_chrg_det_stat_tog; /* 0x1dc */ + u32 usb1_loopback; /* 0x1e0 */ + u32 usb1_loopback_set; /* 0x1e4 */ + u32 usb1_loopback_clr; /* 0x1e8 */ + u32 usb1_loopback_tog; /* 0x1ec */ + u32 usb1_misc; /* 0x1f0 */ + u32 usb1_misc_set; /* 0x1f4 */ + u32 usb1_misc_clr; /* 0x1f8 */ + u32 usb1_misc_tog; /* 0x1fc */ + u32 usb2_vbus_detect; /* 0x200 */ + u32 usb2_vbus_detect_set; /* 0x204 */ + u32 usb2_vbus_detect_clr; /* 0x208 */ + u32 usb2_vbus_detect_tog; /* 0x20c */ + u32 usb2_chrg_detect; /* 0x210 */ + u32 usb2_chrg_detect_set; /* 0x214 */ + u32 usb2_chrg_detect_clr; /* 0x218 */ + u32 usb2_chrg_detect_tog; /* 0x21c */ + u32 usb2_vbus_det_stat; /* 0x220 */ + u32 usb2_vbus_det_stat_set; /* 0x224 */ + u32 usb2_vbus_det_stat_clr; /* 0x228 */ + u32 usb2_vbus_det_stat_tog; /* 0x22c */ + u32 usb2_chrg_det_stat; /* 0x230 */ + u32 usb2_chrg_det_stat_set; /* 0x234 */ + u32 usb2_chrg_det_stat_clr; /* 0x238 */ + u32 usb2_chrg_det_stat_tog; /* 0x23c */ + u32 usb2_loopback; /* 0x240 */ + u32 usb2_loopback_set; /* 0x244 */ + u32 usb2_loopback_clr; /* 0x248 */ + u32 usb2_loopback_tog; /* 0x24c */ + u32 usb2_misc; /* 0x250 */ + u32 usb2_misc_set; /* 0x254 */ + u32 usb2_misc_clr; /* 0x258 */ + u32 usb2_misc_tog; /* 0x25c */ + u32 digprog; /* 0x260 */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ -- cgit v0.10.2 From 522b2a02e6569970e18f539577f4fd6ce81bbc42 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 19 Mar 2012 12:36:10 +0000 Subject: USB: ehci-mx6: Add proper IO accessors Add proper IO accessors for mx6 usb registers. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic Acked-by: Marek Vasut Acked-by: Jason Liu diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index b7bf49d..5dec673 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -46,13 +46,9 @@ #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 -#define ANADIG_USB2_CHRG_DETECT 0x00000210 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 -#define ANADIG_USB2_PLL_480_CTRL 0x00000020 -#define ANADIG_USB2_PLL_480_CTRL_SET 0x00000024 -#define ANADIG_USB2_PLL_480_CTRL_CLR 0x00000028 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 @@ -77,8 +73,7 @@ static void usbh1_internal_phy_clock_gate(int on) static void usbh1_power_config(void) { - void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR; - + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; /* * Some phy and power's special controls for host1 * 1. The external charger detector needs to be disabled @@ -89,15 +84,15 @@ static void usbh1_power_config(void) */ __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B | ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, - anatop_base + ANADIG_USB2_CHRG_DETECT); + &anatop->usb2_chrg_detect); __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, - anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR); + &anatop->usb2_pll_480_ctrl); __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, - anatop_base + ANADIG_USB2_PLL_480_CTRL_SET); + &anatop->usb2_pll_480_ctrl_set); } static int usbh1_phy_enable(void) -- cgit v0.10.2 From 1fc3bbd17a9812998a7d7c2a3990b0fe2e605a2c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 22 Mar 2012 14:29:03 +0000 Subject: mx28evk: Provide default values for SPI bus and chip select Provide default values for SPI bus and chip select. This allows the command "sf probe" to work without passing SPI bus and chip select numbers as arguments. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 04967d7..30814c6 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -186,6 +186,8 @@ /* SPI Flash */ #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 /* this may vary and depends on the installed chip */ #define CONFIG_SPI_FLASH_SST #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -- cgit v0.10.2 From 94f0003f654fb490ee4be2e2aef1811835f1fb8d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 22 Mar 2012 14:29:04 +0000 Subject: configs: imx: Use CONFIG_SF_DEFAULT_CS CONFIG_SPI_FLASH_CS is not used anywhere. Use CONFIG_SF_DEFAULT_CS instead. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Acked-by: Stefano Babic diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index af542fa..120055f 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -113,7 +113,7 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_CS (1 | 121 << 8) +#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #define CONFIG_SF_DEFAULT_SPEED 25000000 diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4d59153..4b97c71 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -252,7 +252,7 @@ #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_CS 2 +#define CONFIG_SF_DEFAULT_CS 2 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 35b71f7..f6904f3 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -72,7 +72,7 @@ * Use gpio 4 pin 25 as chip select for SPI flash * This corresponds to gpio 121 */ -#define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8)) #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 25000000 -- cgit v0.10.2 From 67ee3dd35e20953e9e271d01a4ba4c4b417ec961 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 21 Mar 2012 05:42:45 +0000 Subject: mx53: Make PLL2 to be the parent of UART clock Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53. FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock. On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem. Tested on a mx53loco board booting a FSL kernel and also a mainline kernel. Reported-by: Otavio Salvador Signed-off-by: Fabio Estevam Acked-by: Otavio Salvador diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 01f6d75..74ab753 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -284,10 +284,24 @@ ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] #elif defined(CONFIG_MX53) + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00808145 + orr r1, r1, #(2 << 10) + orr r1, r1, #(0 << 16) + orr r1, r1, #(1 << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, =0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + /* Change uart clk parent to pll2*/ + ldr r1, [r0, #CLKCTL_CSCMR1] + and r1, r1, #0xfcffffff + orr r1, r1, #0x01000000 + str r1, [r0, #CLKCTL_CSCMR1] ldr r1, [r0, #CLKCTL_CSCDR1] - orr r1, r1, #0x3f - eor r1, r1, #0x3f - orr r1, r1, #0x21 + and r1, r1, #0xffffffc0 + orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] #endif /* make sure divider effective */ -- cgit v0.10.2 From 19db9be4aa39e9112356c09c511f1c4726b64c74 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 19 Mar 2012 13:41:25 +0000 Subject: mx53ard: Initialize return code with error The variable "rc" is the return of board_eth_init() function. Initialize it with an error code, so that this function can return an error when CONFIG_SMC911X is not set. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index e90e39e..2d21584 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -287,7 +287,7 @@ int board_init(void) int board_eth_init(bd_t *bis) { - int rc = 0; + int rc = -ENODEV; weim_smc911x_iomux(); weim_cs1_settings(); -- cgit v0.10.2 From 1648a37505e84fc4e5268b026c3f1db862107e00 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:34 +0000 Subject: Add cmd_spl command This adds a spl command to the u-boot. Related config: CONFIG_CMD_SPL activate/deactivate the command CONFIG_CMD_SPL_NAND_OFS Offset in NAND to use Signed-off-by: Simon Schwarz Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk diff --git a/common/Makefile b/common/Makefile index 04faa0b..ed2fb45 100644 --- a/common/Makefile +++ b/common/Makefile @@ -162,6 +162,7 @@ COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o endif COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o +COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o # others ifdef CONFIG_DDR_SPD diff --git a/common/cmd_spl.c b/common/cmd_spl.c new file mode 100644 index 0000000..9ec054a --- /dev/null +++ b/common/cmd_spl.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const char **subcmd_list[] = { + + [SPL_EXPORT_FDT] = (const char * []) { +#ifdef CONFIG_OF_LIBFDT + "start", + "loados", + #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + "ramdisk", + #endif + "fdt", + "cmdline", + "bdt", + "prep", +#endif + NULL, + }, + [SPL_EXPORT_ATAGS] = (const char * []) { +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) + "start", + "loados", +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + "ramdisk", +#endif + "cmdline", + "bdt", + "prep", +#endif + NULL, + }, + NULL +}; + +/* Calls bootm with the parameters given */ +static int call_bootm(int argc, char * const argv[], const char *subcommand[]) +{ + char *bootm_argv[5]; + + int i = 0; + int ret = 0; + int j; + + /* create paramter array */ + bootm_argv[0] = "do_bootm"; + switch (argc) { + case 3: + bootm_argv[4] = argv[2]; /* fdt addr */ + case 2: + bootm_argv[3] = argv[1]; /* initrd addr */ + case 1: + bootm_argv[2] = argv[0]; /* kernel addr */ + } + + + /* + * - do the work - + * exec subcommands of do_bootm to init the images + * data structure + */ + while (subcommand[i] != NULL) { + bootm_argv[1] = (char *)subcommand[i]; + debug("args %d: %s %s ", argc, bootm_argv[0], bootm_argv[1]); + for (j = 0; j < argc; j++) + debug("%s ", bootm_argv[j + 2]); + debug("\n"); + + ret = do_bootm(find_cmd("do_bootm"), 0, argc+2, + bootm_argv); + debug("Subcommand retcode: %d\n", ret); + i++; + } + + if (ret) { + printf("ERROR prep subcommand failed!\n"); + return -1; + } + + return 0; +} + +static cmd_tbl_t cmd_spl_export_sub[] = { + U_BOOT_CMD_MKENT(fdt, 0, 1, (void *)SPL_EXPORT_FDT, "", ""), + U_BOOT_CMD_MKENT(atags, 0, 1, (void *)SPL_EXPORT_ATAGS, "", ""), +}; + +static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const cmd_tbl_t *c; + + if (argc < 2) /* no subcommand */ + return cmd_usage(cmdtp); + + c = find_cmd_tbl(argv[1], &cmd_spl_export_sub[0], + ARRAY_SIZE(cmd_spl_export_sub)); + if ((c) && ((int)c->cmd <= SPL_EXPORT_LAST)) { + argc -= 2; + argv += 2; + if (call_bootm(argc, argv, subcmd_list[(int)c->cmd])) + return -1; + switch ((int)c->cmd) { + case SPL_EXPORT_FDT: + printf("Argument image is now in RAM: 0x%p\n", + (void *)images.ft_addr); + break; + case SPL_EXPORT_ATAGS: + printf("Argument image is now in RAM at: 0x%p\n", + (void *)gd->bd->bi_boot_params); + break; + } + } else { + /* Unrecognized command */ + return cmd_usage(cmdtp); + } + + return 0; +} + +static cmd_tbl_t cmd_spl_sub[] = { + U_BOOT_CMD_MKENT(export, 0, 1, (void *)SPL_EXPORT, "", ""), +}; + +static int do_spl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const cmd_tbl_t *c; + int cmd; + + if (argc < 2) /* no subcommand */ + return cmd_usage(cmdtp); + + c = find_cmd_tbl(argv[1], &cmd_spl_sub[0], ARRAY_SIZE(cmd_spl_sub)); + if (c) { + cmd = (int)c->cmd; + switch (cmd) { + case SPL_EXPORT: + argc--; + argv++; + if (spl_export(cmdtp, flag, argc, argv)) + printf("Subcommand failed\n"); + break; + default: + /* unrecognized command */ + return cmd_usage(cmdtp); + } + } else { + /* Unrecognized command */ + return cmd_usage(cmdtp); + } + return 0; +} + +U_BOOT_CMD( + spl, 6 , 1, do_spl, "SPL configuration", + "export [kernel_addr] [initrd_addr] " + "[fdt_addr if = fdt] - export a kernel parameter image\n" + "\t initrd_img can be set to \"-\" if fdt_addr without initrd img is" + "used"); diff --git a/doc/README.commands.spl b/doc/README.commands.spl new file mode 100644 index 0000000..ac33273 --- /dev/null +++ b/doc/README.commands.spl @@ -0,0 +1,31 @@ +The spl command is used to export a boot parameter image to RAM. Later +it may implement more functions connected to the SPL. + +SUBCOMMAND EXPORT +To execute the command everything has to be in place as if bootm should be +used. (kernel image, initrd-image, fdt-image etc.) + +export has two subcommands: + atags: exports the ATAGS + fdt: exports the FDT + +Call is: +spl export [kernel_addr] [initrd_addr] [fdt_addr if fdt] + + +TYPICAL CALL + +on OMAP3: +nandecc hw +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +spl export atags /* export ATAGS */ +nand erase 0x680000 0x20000 /* erase - one page */ +nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ + +call with FDT: +nandecc hw +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ +spl export fdt 0x82000000 - 0x80000100 /* export FDT */ +nand erase 0x680000 0x20000 /* erase - one page */ +nand write 0x680000 0x20000 diff --git a/include/cmd_spl.h b/include/cmd_spl.h new file mode 100644 index 0000000..6d6206d --- /dev/null +++ b/include/cmd_spl.h @@ -0,0 +1,31 @@ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_SPL_H_ +#define _NAND_SPL_H_ + +#define SPL_EXPORT (0x00000001) + +#define SPL_EXPORT_FDT (0x00000001) +#define SPL_EXPORT_ATAGS (0x00000002) +#define SPL_EXPORT_LAST SPL_EXPORT_ATAGS + +#endif /* _NAND_SPL_H_ */ diff --git a/include/image.h b/include/image.h index bbf80f0..a1c6e4e 100644 --- a/include/image.h +++ b/include/image.h @@ -268,6 +268,8 @@ typedef struct bootm_headers { #endif } bootm_headers_t; +extern bootm_headers_t images; + /* * Some systems (for example LWMON) have very short watchdog periods; * we must make sure to split long operations like memmove() or -- cgit v0.10.2 From d38bc97dafe1f98650a674f2d62bcf2a3584a2bb Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:35 +0000 Subject: devkit8000: add config for spl command This adds some configs for devkit8000 to use the new spl command Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 2b6a6ee..e323877 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -351,4 +351,12 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +/* SPL OS boot options */ +#define CONFIG_CMD_SPL +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ +#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ + 0x400000) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) + #endif /* __CONFIG_H */ -- cgit v0.10.2 From df163a59807b21fad5369f7d9771bb97f00e9425 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:36 +0000 Subject: omap-common: Add NAND SPL linux booting This implements booting of Linux from NAND in SPL Related config parameters: CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normally RAM-start + 0x100 (on ARM) Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c index 38d06b1..2a66214 100644 --- a/arch/arm/cpu/armv7/omap-common/spl_nand.c +++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,9 @@ void spl_nand_load_image(void) { struct image_header *header; + int *src __attribute__((unused)); + int *dst __attribute__((unused)); + switch (omap_boot_mode()) { case NAND_MODE_HW_ECC: debug("spl: nand - using hw ecc\n"); @@ -45,26 +49,56 @@ void spl_nand_load_image(void) /*use CONFIG_SYS_TEXT_BASE as temporary storage area */ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); +#ifdef CONFIG_SPL_OS_BOOT + if (!spl_uboot_key()) { + /* + * load parameter image + * load to temp position since nand_spl_load_image reads + * a whole block which is typically larger than + * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite + * following sections like BSS + */ + nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS, + CONFIG_CMD_SPL_WRITE_SIZE, + (void *)CONFIG_SYS_TEXT_BASE); + /* copy to destintion */ + for (dst = (int *)CONFIG_SYS_SPL_ARGS_ADDR, + src = (int *)CONFIG_SYS_TEXT_BASE; + src < (int *)(CONFIG_SYS_TEXT_BASE + + CONFIG_CMD_SPL_WRITE_SIZE); + src++, dst++) { + writel(readl(src), dst); + } + /* load linux */ + nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, + spl_image.size, (void *)spl_image.load_addr); + } else +#endif + { #ifdef CONFIG_NAND_ENV_DST - nand_spl_load_image(CONFIG_ENV_OFFSET, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size, - (void *)image_load_addr); + nand_spl_load_image(CONFIG_ENV_OFFSET, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size, + (void *)spl_image.load_addr); #ifdef CONFIG_ENV_OFFSET_REDUND - nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size, - (void *)image_load_addr); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size, + (void *)spl_image.load_addr); #endif #endif - /* Load u-boot */ - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); + /* Load u-boot */ + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + spl_image.size, (void *)spl_image.load_addr); + } nand_deselect(); } -- cgit v0.10.2 From 9e70c08b6fb7632385d59827e005569e5ddfd31d Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:37 +0000 Subject: devkit8000/spl: init GPMC for dm9000 in SPL Linux crashes if the GPMC isn't configured for the dm9000. Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 25f95b4..85eac7d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -92,6 +92,7 @@ u32 omap_boot_mode(void); /* SPL common function s*/ void spl_parse_image_header(const struct image_header *header); void omap_rev_string(void); +void spl_board_prepare_for_linux(void); /* NAND SPL functions */ void spl_nand_load_image(void); diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 10f189e..dded697 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -73,6 +73,13 @@ int board_init(void) return 0; } +/* Configure GPMC registers for DM9000 */ +static void gpmc_dm9000_config(void) +{ + enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], + CONFIG_DM9000_BASE, GPMC_SIZE_16M); +} + /* * Routine: misc_init_r * Description: Configure board specific parts @@ -144,6 +151,18 @@ int board_eth_init(bd_t *bis) } #endif +#ifdef CONFIG_SPL_OS_BOOT +/* + * Do board specific preperation before SPL + * Linux boot + */ +void spl_board_prepare_for_linux(void) +{ + gpmc_dm9000_config(); +} + +#endif + /* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header -- cgit v0.10.2 From 379c19ab701dba85072f3d238a32c77611bc1284 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:38 +0000 Subject: omap-common/spl: Add linux boot to SPL This adds Linux booting to the SPL This depends on CONFIG_MACH_TYPE patch by Igor Grinberg (http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809) Related CONFIGs: CONFIG_SPL_OS_BOOT Activates/Deactivates the OS booting feature CONFIG_SPL_OS_BOOT_KEY defines the IO-pin number u-boot switch - if pressed u-boot is booted CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normaly RAM-begin + 0x100 Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 99bb382..6b54ac7 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -65,6 +65,25 @@ void board_init_f(ulong dummy) relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); } +/* + * Default function to determine if u-boot or the OS should + * be started. This implementation always returns 1. + * + * Please implement your own board specific funcion to do this. + * + * RETURN + * 0 to not start u-boot + * positive if u-boot should start + */ +#ifdef CONFIG_SPL_OS_BOOT +__weak int spl_start_uboot(void) +{ + printf("SPL: Please implement spl_start_uboot() for your board\n"); + printf("SPL: Direct Linux boot not active!\n"); + return 1; +} +#endif + void spl_parse_image_header(const struct image_header *header) { u32 header_size = sizeof(struct image_header); @@ -92,6 +111,24 @@ void spl_parse_image_header(const struct image_header *header) } } +/* + * This function jumps to an image with argument. Normally an FDT or ATAGS + * image. + * arg: Pointer to paramter image in RAM + */ +#ifdef CONFIG_SPL_OS_BOOT +static void __noreturn jump_to_image_linux(void *arg) +{ + debug("Entering kernel arg pointer: 0x%p\n", arg); + typedef void (*image_entry_arg_t)(int, int, void *) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t) spl_image.entry_point; + /* cleanup_before_linux(); */ /*write SPL function for that*/ + image_entry(0, CONFIG_MACH_TYPE, arg); +} +#endif + static void __noreturn jump_to_image_no_args(void) { typedef void __noreturn (*image_entry_noargs_t)(u32 *); @@ -149,6 +186,13 @@ void board_init_r(gd_t *id, ulong dummy) debug("Jumping to U-Boot\n"); jump_to_image_no_args(); break; +#ifdef CONFIG_SPL_OS_BOOT + case IH_OS_LINUX: + debug("Jumping to Linux\n"); + spl_board_prepare_for_linux(); + jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR); + break; +#endif default: puts("Unsupported OS image.. Jumping nevertheless..\n"); jump_to_image_no_args(); diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c index 2a66214..1295e88 100644 --- a/arch/arm/cpu/armv7/omap-common/spl_nand.c +++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c @@ -29,7 +29,6 @@ #include #include - void spl_nand_load_image(void) { struct image_header *header; @@ -50,7 +49,7 @@ void spl_nand_load_image(void) /*use CONFIG_SYS_TEXT_BASE as temporary storage area */ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); #ifdef CONFIG_SPL_OS_BOOT - if (!spl_uboot_key()) { + if (!spl_start_uboot()) { /* * load parameter image * load to temp position since nand_spl_load_image reads @@ -74,31 +73,39 @@ void spl_nand_load_image(void) nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); spl_parse_image_header(header); - nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, - spl_image.size, (void *)spl_image.load_addr); - } else + if (header->ih_os == IH_OS_LINUX) { + /* happy - was a linux */ + nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, + spl_image.size, (void *)spl_image.load_addr); + nand_deselect(); + return; + } else { + printf("The Expected Linux image was not" + "found. Please check your NAND" + "configuration.\n"); + printf("Trying to start u-boot now...\n"); + } + } #endif - { #ifdef CONFIG_NAND_ENV_DST - nand_spl_load_image(CONFIG_ENV_OFFSET, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size, - (void *)spl_image.load_addr); + nand_spl_load_image(CONFIG_ENV_OFFSET, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size, + (void *)spl_image.load_addr); #ifdef CONFIG_ENV_OFFSET_REDUND - nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size, - (void *)spl_image.load_addr); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size, + (void *)spl_image.load_addr); #endif #endif - /* Load u-boot */ - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); - } + /* Load u-boot */ + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + spl_image.size, (void *)spl_image.load_addr); nand_deselect(); } diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 85eac7d..6f25948 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -93,6 +93,7 @@ u32 omap_boot_mode(void); void spl_parse_image_header(const struct image_header *header); void omap_rev_string(void); void spl_board_prepare_for_linux(void); +int spl_start_uboot(void); /* NAND SPL functions */ void spl_nand_load_image(void); -- cgit v0.10.2 From ace73189a5245bc0b20930d83bbe8054911cb253 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:39 +0000 Subject: omap/spl: change output of spl_parse_image_header This only outputs "Assuming u-boot.bin..." if debug is active. Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 6b54ac7..963acb0 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -101,7 +101,7 @@ void spl_parse_image_header(const struct image_header *header) /* Signature not found - assume u-boot.bin */ printf("mkimage signature not found - ih_magic = %x\n", header->ih_magic); - puts("Assuming u-boot.bin ..\n"); + debug("Assuming u-boot.bin ..\n"); /* Let's assume U-Boot will not be more than 200 KB */ spl_image.size = 200 * 1024; spl_image.entry_point = CONFIG_SYS_TEXT_BASE; -- cgit v0.10.2 From 2d52a9a38c20697b4aeecac0541c7496809e8238 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:40 +0000 Subject: devkit8000: Implement and activate direct OS boot - Implements spl_start_uboot() for devkit8000 - Add configs to activate direct OS boot from SPL Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index dded697..d75e86b 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -41,6 +41,7 @@ #include #include #include "devkit8000.h" +#include #ifdef CONFIG_DRIVER_DM9000 #include #include @@ -161,6 +162,23 @@ void spl_board_prepare_for_linux(void) gpmc_dm9000_config(); } +/* + * devkit8000 specific implementation of spl_start_uboot() + * + * RETURN + * 0 if the button is not pressed + * 1 if the button is pressed + */ +int spl_start_uboot(void) +{ + int val = 0; + if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) { + gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY); + val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY); + gpio_free(CONFIG_SPL_OS_BOOT_KEY); + } + return !val; +} #endif /* diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e323877..eb7c376 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -35,7 +35,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ - +#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's @@ -327,7 +327,7 @@ #define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ +#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ @@ -352,6 +352,9 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ /* SPL OS boot options */ +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_OS_BOOT_KEY 26 + #define CONFIG_CMD_SPL #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ -- cgit v0.10.2 From d460587a44de06e331041f55c30b7d1c432bff8b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 15 Mar 2012 04:01:41 +0000 Subject: Add cache functions to SPL for armv7 Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk CC: Simon Schwarz diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index f97fa3d..6b2addc 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,9 +27,7 @@ LIB = $(obj)lib$(CPU).o START := start.o -ifndef CONFIG_SPL_BUILD COBJS += cache_v7.o -endif COBJS += cpu.o COBJS += syslib.o diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 662c496..c6fa8ef 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -52,7 +52,9 @@ int cleanup_before_linux(void) * * we turn off caches etc ... */ +#ifndef CONFIG_SPL_BUILD disable_interrupts(); +#endif /* * Turn off I-cache and invalidate it diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 300c8fa..39a9550 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -39,8 +39,6 @@ GLCOBJS += div0.o COBJS-y += board.o COBJS-y += bootm.o -COBJS-y += cache.o -COBJS-y += cache-cp15.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o COBJS-y += interrupts.o COBJS-y += reset.o @@ -48,6 +46,9 @@ SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o endif +COBJS-y += cache.o +COBJS-y += cache-cp15.o + SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -- cgit v0.10.2 From da521387a4bde11f83b1f5b79bba0b0c30c7e5d9 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 15 Mar 2012 04:01:42 +0000 Subject: OMAP3: SPL: do not call I2C init if no I2C is set. Call i2c initialization in spl_board_init only if I2C is configured for the board. Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk CC: Simon Schwarz diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index aabc651..1fee574 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -92,7 +92,9 @@ u32 omap_boot_device(void) void spl_board_init(void) { +#ifdef CONFIG_SPL_I2C_SUPPORT i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif } #endif /* CONFIG_SPL_BUILD */ -- cgit v0.10.2 From 53c4492c0b036d73aaa99f2496bf3fcb36448e6c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 15 Mar 2012 04:01:43 +0000 Subject: SPL: call cleanup_before_linux() before booting Linux Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk CC: Simon Schwarz diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 963acb0..0f2e0a2d2 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -124,7 +124,7 @@ static void __noreturn jump_to_image_linux(void *arg) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t) spl_image.entry_point; - /* cleanup_before_linux(); */ /*write SPL function for that*/ + cleanup_before_linux(); image_entry(0, CONFIG_MACH_TYPE, arg); } #endif -- cgit v0.10.2 From 84c21fb16fe474f72109bf665a7cd841e17a2409 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 15 Mar 2012 04:01:44 +0000 Subject: OMAP3: twister: add support to boot Linux from SPL Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk CC: Simon Schwarz diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 50c70ab..b927586 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -136,3 +136,26 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0); } #endif + +#ifdef CONFIG_SPL_OS_BOOT +/* + * Do board specific preperation before SPL + * Linux boot + */ +void spl_board_prepare_for_linux(void) +{ + /* init cs for extern lan */ + enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); +} +int spl_start_uboot(void) +{ + int val = 0; + if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) { + gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY); + val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY); + gpio_free(CONFIG_SPL_OS_BOOT_KEY); + } + return val; +} +#endif diff --git a/include/configs/twister.h b/include/configs/twister.h index 64a886d..a852481 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -51,4 +51,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ "bootcmd=run nandboot\0" +/* SPL OS boot options */ +#define CONFIG_CMD_SPL +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 +#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ + 0x600000) +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_OS_BOOT_KEY 55 + +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_SPL_BOARD_INIT + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 0a672d494d3e5d6265aefc4f450584875e2319ea Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:45 +0000 Subject: arm: Add Prep subcommand support to bootm Adds prep subcommand to bootm implementation of ARM. When bootm is called with the subcommand prep the function stops right after ATAGS creation and before announce_and_cleanup. This is used in command "cmd_spl export" Signed-off-by: Simon Schwarz Acked-by: Stefano Babic Tested-by: Stefano Babic Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h new file mode 100644 index 0000000..db2ff94 --- /dev/null +++ b/arch/arm/include/asm/bootm.h @@ -0,0 +1,26 @@ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef ARM_BOOTM_H +#define ARM_BOOTM_H + +#ifdef CONFIG_USB_DEVICE +extern void udc_disconnect(void); +#endif + +#endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 2961ab2..160ba55 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -1,4 +1,8 @@ -/* +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * - Added prep subcommand support + * - Reorganized source - modeled after powerpc version + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH * Marius Groeger @@ -29,35 +33,26 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) || \ - defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) -static void setup_start_tag (bd_t *bd); - -# ifdef CONFIG_SETUP_MEMORY_TAGS -static void setup_memory_tags (bd_t *bd); -# endif -static void setup_commandline_tag (bd_t *bd, char *commandline); - -# ifdef CONFIG_INITRD_TAG -static void setup_initrd_tag (bd_t *bd, ulong initrd_start, - ulong initrd_end); -# endif -static void setup_end_tag (bd_t *bd); - +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) static struct tag *params; -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ - -static ulong get_sp(void); -#if defined(CONFIG_OF_LIBFDT) -static int bootm_linux_fdt(int machid, bootm_headers_t *images); #endif +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + void arch_lmb_reserve(struct lmb *lmb) { ulong sp; @@ -80,89 +75,7 @@ void arch_lmb_reserve(struct lmb *lmb) gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp); } -static void announce_and_cleanup(void) -{ - printf("\nStarting kernel ...\n\n"); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif - -#ifdef CONFIG_USB_DEVICE - { - extern void udc_disconnect(void); - udc_disconnect(); - } -#endif - cleanup_before_linux(); -} - -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) -{ - bd_t *bd = gd->bd; - char *s; - int machid = bd->bi_arch_number; - void (*kernel_entry)(int zero, int arch, uint params); - -#ifdef CONFIG_CMDLINE_TAG - char *commandline = getenv ("bootargs"); -#endif - - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - s = getenv ("machid"); - if (s) { - machid = simple_strtoul (s, NULL, 16); - printf ("Using machid 0x%x from environment\n", machid); - } - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - #ifdef CONFIG_OF_LIBFDT - if (images->ft_len) - return bootm_linux_fdt(machid, images); -#endif - - kernel_entry = (void (*)(int, int, uint))images->ep; - - debug ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) kernel_entry); - -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) || \ - defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) - setup_start_tag (bd); -#ifdef CONFIG_SERIAL_TAG - setup_serial_tag (¶ms); -#endif -#ifdef CONFIG_REVISION_TAG - setup_revision_tag (¶ms); -#endif -#ifdef CONFIG_SETUP_MEMORY_TAGS - setup_memory_tags (bd); -#endif -#ifdef CONFIG_CMDLINE_TAG - setup_commandline_tag (bd, commandline); -#endif -#ifdef CONFIG_INITRD_TAG - if (images->rd_start && images->rd_end) - setup_initrd_tag (bd, images->rd_start, images->rd_end); -#endif - setup_end_tag(bd); -#endif - - announce_and_cleanup(); - - kernel_entry(0, machid, bd->bi_boot_params); - /* does not return */ - - return 1; -} - -#if defined(CONFIG_OF_LIBFDT) static int fixup_memory_node(void *blob) { bd_t *bd = gd->bd; @@ -177,60 +90,30 @@ static int fixup_memory_node(void *blob) return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); } +#endif -static int bootm_linux_fdt(int machid, bootm_headers_t *images) +static void announce_and_cleanup(void) { - ulong rd_len; - void (*kernel_entry)(int zero, int dt_machid, void *dtblob); - ulong of_size = images->ft_len; - char **of_flat_tree = &images->ft_addr; - ulong *initrd_start = &images->initrd_start; - ulong *initrd_end = &images->initrd_end; - struct lmb *lmb = &images->lmb; - int ret; - - kernel_entry = (void (*)(int, int, void *))images->ep; - - boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); - - rd_len = images->rd_end - images->rd_start; - ret = boot_ramdisk_high(lmb, images->rd_start, rd_len, - initrd_start, initrd_end); - if (ret) - return ret; - - ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); - if (ret) - return ret; - - debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) kernel_entry); - - fdt_chosen(*of_flat_tree, 1); - - fixup_memory_node(*of_flat_tree); - - fdt_fixup_ethernet(*of_flat_tree); - - fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); - - announce_and_cleanup(); - - kernel_entry(0, machid, *of_flat_tree); - /* does not return */ + printf("\nStarting kernel ...\n\n"); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif - return 1; -} +#ifdef CONFIG_USB_DEVICE + udc_disconnect(); #endif + cleanup_before_linux(); +} -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) || \ - defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) static void setup_start_tag (bd_t *bd) { - params = (struct tag *) bd->bi_boot_params; + params = (struct tag *)bd->bi_boot_params; params->hdr.tag = ATAG_CORE; params->hdr.size = tag_size (tag_core); @@ -241,10 +124,10 @@ static void setup_start_tag (bd_t *bd) params = tag_next (params); } - +#endif #ifdef CONFIG_SETUP_MEMORY_TAGS -static void setup_memory_tags (bd_t *bd) +static void setup_memory_tags(bd_t *bd) { int i; @@ -258,10 +141,10 @@ static void setup_memory_tags (bd_t *bd) params = tag_next (params); } } -#endif /* CONFIG_SETUP_MEMORY_TAGS */ - +#endif -static void setup_commandline_tag (bd_t *bd, char *commandline) +#ifdef CONFIG_CMDLINE_TAG +static void setup_commandline_tag(bd_t *bd, char *commandline) { char *p; @@ -285,10 +168,10 @@ static void setup_commandline_tag (bd_t *bd, char *commandline) params = tag_next (params); } - +#endif #ifdef CONFIG_INITRD_TAG -static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) +static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end) { /* an ATAG_INITRD node tells the kernel where the compressed * ramdisk can be found. ATAG_RDIMG is a better name, actually. @@ -301,10 +184,10 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) params = tag_next (params); } -#endif /* CONFIG_INITRD_TAG */ +#endif #ifdef CONFIG_SERIAL_TAG -void setup_serial_tag (struct tag **tmp) +void setup_serial_tag(struct tag **tmp) { struct tag *params = *tmp; struct tag_serialnr serialnr; @@ -332,19 +215,147 @@ void setup_revision_tag(struct tag **in_params) params->u.revision.rev = rev; params = tag_next (params); } -#endif /* CONFIG_REVISION_TAG */ +#endif -static void setup_end_tag (bd_t *bd) +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +static void setup_end_tag(bd_t *bd) { params->hdr.tag = ATAG_NONE; params->hdr.size = 0; } -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +#endif -static ulong get_sp(void) +#ifdef CONFIG_OF_LIBFDT +static int create_fdt(bootm_headers_t *images) { - ulong ret; + ulong of_size = images->ft_len; + char **of_flat_tree = &images->ft_addr; + ulong *initrd_start = &images->initrd_start; + ulong *initrd_end = &images->initrd_end; + struct lmb *lmb = &images->lmb; + ulong rd_len; + int ret; - asm("mov %0, sp" : "=r"(ret) : ); - return ret; + debug("using: FDT\n"); + + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + + rd_len = images->rd_end - images->rd_start; + ret = boot_ramdisk_high(lmb, images->rd_start, rd_len, + initrd_start, initrd_end); + if (ret) + return ret; + + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + if (ret) + return ret; + + fdt_chosen(*of_flat_tree, 1); + fixup_memory_node(*of_flat_tree); + fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); + + return 0; +} +#endif + +/* Subcommand: PREP */ +static void boot_prep_linux(bootm_headers_t *images) +{ +#ifdef CONFIG_CMDLINE_TAG + char *commandline = getenv("bootargs"); +#endif + +#ifdef CONFIG_OF_LIBFDT + if (images->ft_len) { + debug("using: FDT\n"); + if (create_fdt(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } + } else +#endif + { +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) + debug("using: ATAGS\n"); + setup_start_tag(gd->bd); +#ifdef CONFIG_SERIAL_TAG + setup_serial_tag(¶ms); +#endif +#ifdef CONFIG_CMDLINE_TAG + setup_commandline_tag(gd->bd, commandline); +#endif +#ifdef CONFIG_REVISION_TAG + setup_revision_tag(¶ms); +#endif +#ifdef CONFIG_SETUP_MEMORY_TAGS + setup_memory_tags(gd->bd); +#endif +#ifdef CONFIG_INITRD_TAG + if (images->rd_start && images->rd_end) + setup_initrd_tag(gd->bd, images->rd_start, + images->rd_end); +#endif + setup_end_tag(gd->bd); +#else /* all tags */ + printf("FDT and ATAGS support not compiled in - hanging\n"); + hang(); +#endif /* all tags */ + } +} + +/* Subcommand: GO */ +static void boot_jump_linux(bootm_headers_t *images) +{ + unsigned long machid = gd->bd->bi_arch_number; + char *s; + void (*kernel_entry)(int zero, int arch, uint params); + + kernel_entry = (void (*)(int, int, uint))images->ep; + + s = getenv("machid"); + if (s) { + strict_strtoul(s, 16, &machid); + printf("Using machid 0x%lx from environment\n", machid); + } + + debug("## Transferring control to Linux (at address %08lx)" \ + "...\n", (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + announce_and_cleanup(); + kernel_entry(0, machid, gd->bd->bi_boot_params); +} + +/* Main Entry point for arm bootm implementation + * + * Modeled after the powerpc implementation + * DIFFERENCE: Instead of calling prep and go at the end + * they are called if subcommand is equal 0. + */ +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + /* No need for those on ARM */ + if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; + } + + if (flag & BOOTM_STATE_OS_GO) { + boot_jump_linux(images); + return 0; + } + + boot_prep_linux(images); + boot_jump_linux(images); + return 0; } -- cgit v0.10.2 From 0d63b33506a6d40a022a789085f5cb4e636ecaf8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 15 Mar 2012 04:01:46 +0000 Subject: cam_enc_4xx: Rename 'images' to 'imgs' To avoid a conflict with common/cmd_bootm.c's 'images' (which is exposed as part of the Linux SPL series), rename the board-specific 'images' to 'imgs'. Cc: Heiko Schocher Signed-off-by: Tom Rini Acked-by: Heiko Schocher Tested-by: Heiko Schocher diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 5586576..bb29cf3 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -503,7 +503,7 @@ struct fit_images_info { size_t size; }; -static struct fit_images_info images[10]; +static struct fit_images_info imgs[10]; struct menu_display { char title[50]; @@ -688,14 +688,14 @@ static int ait_menu_install_images(void) * img_writeramdisk: write ramdisk to ubi volume */ - while (images[count].type != IH_TYPE_INVALID) { + while (imgs[count].type != IH_TYPE_INVALID) { printf("Installing %s\n", - genimg_get_type_name(images[count].type)); - sprintf(s, "%p", images[count].data); + genimg_get_type_name(imgs[count].type)); + sprintf(s, "%p", imgs[count].data); setenv("img_addr_r", s); - sprintf(s, "%lx", (unsigned long)images[count].size); + sprintf(s, "%lx", (unsigned long)imgs[count].size); setenv("filesize", s); - switch (images[count].subtype) { + switch (imgs[count].subtype) { case FIT_SUBTYPE_DF_ENV_IMAGE: ret = run_command2("run img_writedfenv", 0); break; @@ -865,7 +865,7 @@ static int ait_menu_check_image(void) int found_uboot = -1; int found_ramdisk = -1; - memset(images, 0, sizeof(images)); + memset(imgs, 0, sizeof(imgs)); s = getenv("fit_addr_r"); fit_addr = s ? (unsigned long)simple_strtol(s, NULL, 16) : \ CONFIG_BOARD_IMG_ADDR_R; @@ -911,7 +911,7 @@ static int ait_menu_check_image(void) fit_image_print(addr, noffset, ""); fit_image_get_type(addr, noffset, - &images[count].type); + &imgs[count].type); /* Mandatory properties */ ret = fit_get_desc(addr, noffset, &desc); printf("Description: "); @@ -925,33 +925,33 @@ static int ait_menu_check_image(void) if (ret) { printf("unavailable\n"); } else { - images[count].subtype = ait_subtype_nr(subtype); + imgs[count].subtype = ait_subtype_nr(subtype); printf("%s %d\n", subtype, - images[count].subtype); + imgs[count].subtype); } - sprintf(images[count].desc, "%s", desc); + sprintf(imgs[count].desc, "%s", desc); ret = fit_image_get_data(addr, noffset, - &images[count].data, - &images[count].size); + &imgs[count].data, + &imgs[count].size); printf("Data Size: "); if (ret) printf("unavailable\n"); else - genimg_print_size(images[count].size); - printf("Data @ %p\n", images[count].data); + genimg_print_size(imgs[count].size); + printf("Data @ %p\n", imgs[count].data); count++; } } for (i = 0; i < count; i++) { - if (images[i].subtype == FIT_SUBTYPE_UBOOT_IMAGE) + if (imgs[i].subtype == FIT_SUBTYPE_UBOOT_IMAGE) found_uboot = i; - if (images[i].type == IH_TYPE_RAMDISK) { + if (imgs[i].type == IH_TYPE_RAMDISK) { found_ramdisk = i; - images[i].subtype = FIT_SUBTYPE_RAMDISK_IMAGE; + imgs[i].subtype = FIT_SUBTYPE_RAMDISK_IMAGE; } } @@ -959,31 +959,31 @@ static int ait_menu_check_image(void) if (found_uboot >= 0) { s = getenv("dvn_boot_vers"); if (s) { - ret = strcmp(s, images[found_uboot].desc); + ret = strcmp(s, imgs[found_uboot].desc); if (ret != 0) { setenv("dvn_boot_vers", - images[found_uboot].desc); + imgs[found_uboot].desc); } else { found_uboot = -1; printf("no new uboot version\n"); } } else { - setenv("dvn_boot_vers", images[found_uboot].desc); + setenv("dvn_boot_vers", imgs[found_uboot].desc); } } if (found_ramdisk >= 0) { s = getenv("dvn_app_vers"); if (s) { - ret = strcmp(s, images[found_ramdisk].desc); + ret = strcmp(s, imgs[found_ramdisk].desc); if (ret != 0) { setenv("dvn_app_vers", - images[found_ramdisk].desc); + imgs[found_ramdisk].desc); } else { found_ramdisk = -1; printf("no new ramdisk version\n"); } } else { - setenv("dvn_app_vers", images[found_ramdisk].desc); + setenv("dvn_app_vers", imgs[found_ramdisk].desc); } } if ((found_uboot == -1) && (found_ramdisk == -1)) -- cgit v0.10.2 From f7dad8f12164d08577b42492ae8d350a002e9d99 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 21 Mar 2012 23:56:17 +0000 Subject: NAND: TI: fix warnings in omap_gpmc.c The following warnings are reported for boards using SOFT ECC. omap_gpmc.c:33:30: warning: 'hw_nand_oob' defined but not used omap_gpmc.c:78:13: warning: 'omap_hwecc_init' defined but not used omap_gpmc.c:116:12: warning: 'omap_correct_data' defined but not used omap_gpmc.c:182:12: warning: 'omap_calculate_ecc' defined but not used omap_gpmc.c:208:13: warning: 'omap_enable_hwecc' defined but not used Signed-off-by: Stefano Babic Cc: Tom Rini Cc: Scott Wood diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 1dfe074..ca868ef 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -27,10 +27,12 @@ #include #include #include +#include #include static uint8_t cs; -static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT; +static __maybe_unused struct nand_ecclayout hw_nand_oob = + GPMC_NAND_HW_ECC_LAYOUT; /* * omap_nand_hwcontrol - Set the address pointers corretly for the @@ -75,7 +77,7 @@ int omap_spl_dev_ready(struct mtd_info *mtd) * @mtd: MTD device structure * */ -static void omap_hwecc_init(struct nand_chip *chip) +static void __maybe_unused omap_hwecc_init(struct nand_chip *chip) { /* * Init ECC Control Register @@ -113,7 +115,7 @@ static uint32_t gen_true_ecc(uint8_t *ecc_buf) * * @return 0 if data is OK or corrected, else returns -1 */ -static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat, +static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { uint32_t orig_ecc, new_ecc, res, hm; @@ -179,8 +181,8 @@ static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat, * @dat: unused * @ecc_code: ecc_code buffer */ -static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) +static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd, + const uint8_t *dat, uint8_t *ecc_code) { u_int32_t val; @@ -205,7 +207,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, * @mtd: MTD device structure * @mode: Read/Write mode */ -static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) +static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { struct nand_chip *chip = mtd->priv; uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; -- cgit v0.10.2 From 61712bcad48d2874fbd9e2dc90255f0885b716b0 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Mon, 19 Mar 2012 03:37:40 +0000 Subject: twl4030: fix potential power supply handling issues twl4030_pmrecv_vsel_cfg currently first sets up device group (effectively enabling the supply), and only then sets vsel (selects voltage). This could lead to wrong voltage for a short time, or even long time if second i2c write fails. Fix this by writing vsel first and device group after that. Also introduce error checking to not enable the supply if we failed to set the voltage, and start logging errors as power supply problems are usually important. Signed-off-by: Grazvydas Ignotas diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index 4a4ddeb..36b2144 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -65,13 +65,23 @@ void twl4030_power_reset_init(void) void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp, u8 dev_grp_sel) { - /* Select the Device Group */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel, - dev_grp); + int ret; /* Select the Voltage */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val, + ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val, vsel_reg); + if (ret != 0) { + printf("Could could not write vsel to reg %02x (%d)\n", + vsel_reg, ret); + return; + } + + /* Select the Device Group (enable the supply if dev_grp_sel != 0) */ + ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel, + dev_grp); + if (ret != 0) + printf("Could could not write grp_sel to reg %02x (%d)\n", + dev_grp, ret); } void twl4030_power_init(void) -- cgit v0.10.2 From c2afbb501c4897c7007711645d300a7156812ad1 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 21 Mar 2012 00:14:24 +0000 Subject: OMAP3: mt_ventoux: updated timing for FPGA Fix chipselect timing for FPGA Signed-off-by: Stefano Babic Cc: Tom Rini diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h index 34c1ec5..9b2e43e 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ b/board/teejet/mt_ventoux/mt_ventoux.h @@ -31,12 +31,11 @@ const omap3_sysinfo sysinfo = { /* FPGA CS1 configuration */ #define FPGA_GPMC_CONFIG1 0x00001200 -#define FPGA_GPMC_CONFIG2 0x00111a00 -#define FPGA_GPMC_CONFIG3 0x00010100 -#define FPGA_GPMC_CONFIG4 0x06041a04 -#define FPGA_GPMC_CONFIG5 0x0019101a -#define FPGA_GPMC_CONFIG6 0x890503c0 -#define FPGA_GPMC_CONFIG7 0x00000860 +#define FPGA_GPMC_CONFIG2 0x00161f00 +#define FPGA_GPMC_CONFIG3 0x00040400 +#define FPGA_GPMC_CONFIG4 0x120c1f08 +#define FPGA_GPMC_CONFIG5 0x001e161f +#define FPGA_GPMC_CONFIG6 0x96080fcf #define FPGA_BASE_ADDR 0x20000000 -- cgit v0.10.2 From 88b821bbef64f0b69710ff7d857fc490f72a6d3c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 21 Mar 2012 00:14:25 +0000 Subject: OMAP3: mt_ventoux: sets its own mtdparts Signed-off-by: Stefano Babic Cc: Tom Rini diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 2034b59..5db6d57 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -40,6 +40,16 @@ #define CONFIG_SYS_PROMPT V_PROMPT /* + * Set its own mtdparts, different from common + */ +#undef MTDIDS_DEFAULT +#undef MTDPARTS_DEFAULT +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ + "1m(u-boot),256k(env1)," \ + "256k(env2),8m(ubisystem),-(rootfs)" + +/* * FPGA */ #define CONFIG_CMD_FPGA -- cgit v0.10.2 From 1441aa6ae8a77ada40407cdfbec783f5559f1646 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 5 Oct 2011 03:08:24 +0000 Subject: Davinci: ea20: use gpio framework to access gpios Drop direct access to SOC's registers and use the function of the GPIO driver for da8xx. [Tom: Remove gpio[68]_base as it's now unused] Signed-off-by: Stefano Babic CC: Bastian Ruppert CC: dzu@denx.de CC: Sandeep Paulraj Signed-off-by: Tom Rini diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 9b6c4c0..43632c2 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -172,37 +172,24 @@ static const struct lpsc_resource lpsc[] = { int board_early_init_f(void) { - struct davinci_gpio *gpio6_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK67; - /* PinMux for GPIO */ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) return 1; /* Set the RESETOUTn low */ - writel((readl(&gpio6_base->set_data) & ~(1 << 15)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir); + gpio_direction_output(111, 0); /* Set U0_SW0 low for UART0 as console*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 10)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir); + gpio_direction_output(106, 0); /* Set U0_SW1 low for UART0 as console*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 12)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir); + gpio_direction_output(108, 0); /* Set LCD_B_PWR low to power down LCD Backlight*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 6)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir); + gpio_direction_output(102, 0); /* Set DISP_ON low to disable LCD output*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 1)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir); + gpio_direction_output(97, 0); #ifndef CONFIG_USE_IRQ irq_init(); @@ -264,12 +251,10 @@ int board_early_init_f(void) &davinci_syscfg_regs->mstpri[2]); /* Set LCD_B_PWR low to power up LCD Backlight*/ - writel((readl(&gpio6_base->set_data) | (1 << 6)), - &gpio6_base->set_data); + gpio_set_value(102, 1); /* Set DISP_ON low to disable LCD output*/ - writel((readl(&gpio6_base->set_data) | (1 << 1)), - &gpio6_base->set_data); + gpio_set_value(97, 1); return 0; } @@ -291,17 +276,12 @@ int board_init(void) int board_late_init(void) { - struct davinci_gpio *gpio8_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK8; - /* PinMux for HALTEN */ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) return 1; /* Set HALTEN to high */ - writel((readl(&gpio8_base->set_data) | (1 << 6)), - &gpio8_base->set_data); - writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir); + gpio_direction_output(134, 1); setenv("stdout", "serial"); diff --git a/include/configs/ea20.h b/include/configs/ea20.h index b4610d9..e059b30 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -48,6 +48,7 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 +#define CONFIG_DA8XX_GPIO /* * Memory Info @@ -167,6 +168,7 @@ #define CONFIG_CMD_SAVES #define CONFIG_CMD_MEMORY #define CONFIG_CMD_I2C +#define CONFIG_CMD_GPIO #ifdef CONFIG_CMD_BDI #define CONFIG_CLOCKS -- cgit v0.10.2 From f8d6c50ead35574f69b58da1932b1a366940d5fc Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sun, 25 Mar 2012 22:01:49 +0000 Subject: calimain, enbw_cmc: Fix typo in comments Signed-off-by: Christian Riesch Cc: Heiko Schocher Cc: Tom Rini diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 16d1b08..6c0d931 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -525,7 +525,7 @@ void bootcount_store(ulong a) /* * write RTC kick register to enable write - * for RTC Scratch registers. Cratch0 and 1 are + * for RTC Scratch registers. Scratch0 and 1 are * used for bootcount values. */ writel(RTC_KICK0R_WE, ®->kick0r); diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index 97ba74a..54415ce 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -166,7 +166,7 @@ void bootcount_store(ulong a) /* * write RTC kick register to enable write - * for RTC Scratch registers. Cratch0 and 1 are + * for RTC Scratch registers. Scratch0 and 1 are * used for bootcount values. */ writel(RTC_KICK0R_WE, ®->kick0r); -- cgit v0.10.2 From 08b5ab073d4eb389ffd622f71094cf1c70253c00 Mon Sep 17 00:00:00 2001 From: jacopo mondi Date: Wed, 2 Mar 2011 05:13:22 +0000 Subject: omap3_spi: receive transmit mode Implementation of receive-transmit mode for omap3 MCSPI. Introduces full duplex communication, needed by some spi devices (such as enc28j60). Signed-off-by: jacopo mondi diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index af12c0e..9346c0b 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -297,6 +297,65 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, return 0; } +/*McSPI Transmit Receive Mode*/ +int omap3_spi_txrx(struct spi_slave *slave, + unsigned int len, const u8 *txp, u8 *rxp, unsigned long flags) +{ + struct omap3_spi_slave *ds = to_omap3_spi(slave); + int timeout = SPI_WAIT_TIMEOUT; + int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); + int irqstatus = readl(&ds->regs->irqstatus); + int i=0; + + /*Enable SPI channel*/ + if (flags & SPI_XFER_BEGIN) + writel(OMAP3_MCSPI_CHCTRL_EN, + &ds->regs->channel[ds->slave.cs].chctrl); + + /*set TRANSMIT-RECEIVE Mode*/ + chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf |= OMAP3_MCSPI_CHCONF_FORCE; + writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); + + /*Shift in and out 1 byte at time*/ + for (i=0; i < len; i++){ + /* Write: wait for TX empty (TXS == 1)*/ + irqstatus |= (1<< (4*(ds->slave.bus))); + while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & + OMAP3_MCSPI_CHSTAT_TXS)) { + if (--timeout <= 0) { + printf("SPI TXS timed out, status=0x%08x\n", + readl(&ds->regs->channel[ds->slave.cs].chstat)); + return -1; + } + } + /* Write the data */ + writel(txp[i], &ds->regs->channel[ds->slave.cs].tx); + + /*Read: wait for RX containing data (RXS == 1)*/ + while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & + OMAP3_MCSPI_CHSTAT_RXS)) { + if (--timeout <= 0) { + printf("SPI RXS timed out, status=0x%08x\n", + readl(&ds->regs->channel[ds->slave.cs].chstat)); + return -1; + } + } + /* Read the data */ + rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); + } + + /*if transfer must be terminated disable the channel*/ + if (flags & SPI_XFER_END) { + chconf &= ~OMAP3_MCSPI_CHCONF_FORCE; + writel(chconf, &ds->regs->channel[ds->slave.cs].chconf); + + writel(0, &ds->regs->channel[ds->slave.cs].chctrl); + } + + return 0; +} + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -329,10 +388,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, } ret = 0; } else { - if (dout != NULL) + if (dout != NULL && din != NULL) + ret = omap3_spi_txrx(slave, len, txp, rxp, flags); + else if (dout != NULL) ret = omap3_spi_write(slave, len, txp, flags); - - if (din != NULL) + else if (din != NULL) ret = omap3_spi_read(slave, len, rxp, flags); } return ret; diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index b8e3a4c..0ac801c 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -109,6 +109,8 @@ static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave) return container_of(slave, struct omap3_spi_slave, slave); } +int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp, + u8 *rxp, unsigned long flags); int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, unsigned long flags); int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, -- cgit v0.10.2 From 24efef90c4c9ddc65ae3bd982b09b99b2d0cd4e0 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 7 Mar 2012 04:10:00 +0000 Subject: ARM: davinci: fixes for cam_enc_4xx board - change CONFIG_ENV_RANGE to contain 2 nand erase blocks, one for bad block reserve. - remove from the envvariable "img_writeramdisk" the ubifsmount command, as it is not needed. - erase the hole mtd partition containing u-boot - save environment variable "dvn_app_vers" and "dvn_boot_vers" only after installing the new image. changes requested from Marek Vasut: - arm, davinci: fix eldk-4.2 warnings for cam_enc_4xx board - get rid of run_command2 usage needed since patch: commit 009dde1955583e306cf904c864068f3acb0db499 Author: Simon Glass Date: Tue Feb 14 19:59:20 2012 +0000 Rename run_command2() to run_command() is now in mainline. - add CONFIG_SPL_LIBGENERIC_SUPPORT support - remove CONFIG_CMD_PXE support - fix warning: cam_enc_4xx.c: In function 'menu_handle': cam_enc_4xx.c:609: warning: dereferencing type-punned pointer will break strict-aliasing rules - fix error: arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking with -N Signed-off-by: Heiko Schocher Cc: Marek Vasut Cc: Tom Rini Cc: Fletzer Martin Cc: Wolfgang Denk diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index bb29cf3..32b28f9 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -554,7 +555,7 @@ static char *menu_handle(struct menu_display *display) { struct menu *m; int i; - char *choice = NULL; + void *choice = NULL; char key[2]; int ret; char *s; @@ -606,7 +607,7 @@ static char *menu_handle(struct menu_display *display) sprintf(key, "%d", 1); menu_default_set(m, key); - if (menu_get_choice(m, (void **)&choice) != 1) + if (menu_get_choice(m, &choice) != 1) debug("Problem picking a choice!\n"); menu_destroy(m); @@ -653,7 +654,7 @@ static int ait_writeublheader(void) sprintf(s, "%lx", i); ret = setenv("header_addr", s); if (ret == 0) - ret = run_command2("run img_writeheader", 0); + ret = run_command("run img_writeheader", 0); if (ret != 0) break; } @@ -697,7 +698,7 @@ static int ait_menu_install_images(void) setenv("filesize", s); switch (imgs[count].subtype) { case FIT_SUBTYPE_DF_ENV_IMAGE: - ret = run_command2("run img_writedfenv", 0); + ret = run_command("run img_writedfenv", 0); break; case FIT_SUBTYPE_RAMDISK_IMAGE: t = getenv("img_volume"); @@ -713,16 +714,16 @@ static int ait_menu_install_images(void) if (ret != 0) break; - ret = run_command2("run img_writeramdisk", 0); + ret = run_command("run img_writeramdisk", 0); break; case FIT_SUBTYPE_SPL_IMAGE: - ret = run_command2("run img_writespl", 0); + ret = run_command("run img_writespl", 0); break; case FIT_SUBTYPE_UBL_HEADER: ret = ait_writeublheader(); break; case FIT_SUBTYPE_UBOOT_IMAGE: - ret = run_command2("run img_writeuboot", 0); + ret = run_command("run img_writeuboot", 0); break; default: /* not supported type */ @@ -731,8 +732,19 @@ static int ait_menu_install_images(void) count++; } /* now save dvn_* and img_volume env vars to new values */ - if (ret == 0) - ret = run_command2("run savenewvers", 0); + if (ret == 0) { + t = getenv("x_dvn_boot_vers"); + if (t) + setenv("dvn_boot_vers", t); + + t = getenv("x_dvn_app_vers"); + if (t) + setenv("dvn_boot_vers", t); + + setenv("x_dvn_boot_vers", NULL); + setenv("x_dvn_app_vers", NULL); + ret = run_command("run savenewvers", 0); + } return ret; } @@ -749,6 +761,8 @@ static int ait_menu_evaluate_load(char *choice) break; case '2': /* cancel, back to main */ + setenv("x_dvn_boot_vers", NULL); + setenv("x_dvn_app_vers", NULL); break; } @@ -961,7 +975,7 @@ static int ait_menu_check_image(void) if (s) { ret = strcmp(s, imgs[found_uboot].desc); if (ret != 0) { - setenv("dvn_boot_vers", + setenv("x_dvn_boot_vers", imgs[found_uboot].desc); } else { found_uboot = -1; @@ -976,7 +990,7 @@ static int ait_menu_check_image(void) if (s) { ret = strcmp(s, imgs[found_ramdisk].desc); if (ret != 0) { - setenv("dvn_app_vers", + setenv("x_dvn_app_vers", imgs[found_ramdisk].desc); } else { found_ramdisk = -1; @@ -1005,7 +1019,7 @@ static int ait_menu_evaluate_update(char *choice) break; case '2': /* load image */ - ret = run_command2("run load_img", 0); + ret = run_command("run load_img", 0); printf("ret: %d\n", ret); if (ret) return MENU_UPDATE; @@ -1073,9 +1087,9 @@ int menu_show(int bootdelay) { int ret; - run_command2("run saveparms", 0); + run_command("run saveparms", 0); ret = ait_menu_show(&ait_main, bootdelay); - run_command2("run restoreparms", 0); + run_command("run restoreparms", 0); if (ret == MENU_EXIT_BOOTCMD) return 0; @@ -1085,8 +1099,17 @@ int menu_show(int bootdelay) void menu_display_statusline(struct menu *m) { - printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", - getenv("dvn_boot_vers"), getenv("dvn_app_vers")); + char *s1, *s2; + + s1 = getenv("x_dvn_boot_vers"); + if (!s1) + s1 = getenv("dvn_boot_vers"); + + s2 = getenv("x_dvn_app_vers"); + if (!s2) + s2 = getenv("dvn_app_vers"); + + printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", s1, s2); return; } #endif diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk index b1f9b6c..744b927 100644 --- a/board/ait/cam_enc_4xx/config.mk +++ b/board/ait/cam_enc_4xx/config.mk @@ -12,4 +12,11 @@ PAD_TO := 12320 UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg ifndef CONFIG_SPL_BUILD ALL-y += $(obj)u-boot.ubl +else +# as SPL_TEXT_BASE is not page-aligned, we need for some +# linkers the -n flag (Do not page align data), to prevent +# the following error message: +# arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking +# with -N +LDFLAGS_u-boot-spl += -n endif diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index 6f6e065..52c986e 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -32,7 +32,7 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = CONFIG_SPL_TEXT_BASE; . = ALIGN(4); .text : diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 0fee53f..99856eb 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -161,15 +161,14 @@ #define CONFIG_MENU #define CONFIG_MENU_SHOW #define CONFIG_FIT -#define CONFIG_CMD_PXE #define CONFIG_BOARD_IMG_ADDR_R 0x80000000 #ifdef CONFIG_NAND_DAVINCI #define CONFIG_ENV_SIZE (16 << 10) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x180000 +#define CONFIG_ENV_RANGE 0x040000 #define CONFIG_ENV_OFFSET_REDUND 0x1c0000 -#define CONFIG_ENV_RANGE 0x020000 #undef CONFIG_ENV_IS_IN_FLASH #endif @@ -220,6 +219,7 @@ /* Defines for SPL */ #define CONFIG_SPL +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_LOAD @@ -229,7 +229,7 @@ #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds" #define CONFIG_SPL_STACK (0x00010000 + 0x7f00) -#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE 12320 #ifndef CONFIG_SPL_BUILD @@ -274,6 +274,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000 /* for UBL header */ #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE) @@ -429,7 +430,7 @@ " 0 3000;nandrbl uboot\0" \ "writeuboot=nandrbl uboot;" \ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ - xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ + xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \ ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ @@ -466,14 +467,14 @@ "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \ "img_writeuboot=nandrbl uboot;" \ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ - xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ + xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \ ";nand write ${img_addr_r} " \ xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ "img_writedfenv=ubi part ubi 2048;" \ "ubi write ${img_addr_r} default ${filesize}\0" \ "img_volume=rootfs1\0" \ - "img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "img_writeramdisk=ubi part ubi 2048;" \ "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \ "load_img=tftp ${fit_addr_r} ${img_file}\0" \ "net_nfs=run load_kernel; " \ -- cgit v0.10.2 From d0b3b49615e23d0681a6e883cda7d4bc4f728646 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Thu, 22 Dec 2011 01:16:37 +0000 Subject: ARM: fix s3c2410 timer code This patch fixes the s3c24x0 timer code to work with the ARM relocation feature. Signed-off-by: David Mueller Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index 9571870..d8668be 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -35,19 +35,7 @@ #include #include -int timer_load_val = 0; -static ulong timer_clk; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - - return readl(&timers->tcnto4) & 0xffff; -} - -static ulong timestamp; -static ulong lastdec; +DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { @@ -57,27 +45,27 @@ int timer_init(void) /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ writel(0x0f00, &timers->tcfg0); - if (timer_load_val == 0) { + if (gd->tbu == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 * (default) and prescaler = 16. Should be 10390 * @33.25MHz and 15625 @ 50 MHz */ - timer_load_val = get_PCLK() / (2 * 16 * 100); - timer_clk = get_PCLK() / (2 * 16); + gd->tbu = get_PCLK() / (2 * 16 * 100); + gd->timer_rate_hz = get_PCLK() / (2 * 16); } /* load value for 10 ms timeout */ - lastdec = timer_load_val; - writel(timer_load_val, &timers->tcntb4); + writel(gd->tbu, &timers->tcntb4); /* auto load, manual update of timer 4 */ tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; writel(tmr, &timers->tcon); /* auto load, start timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; writel(tmr, &timers->tcon); - timestamp = 0; + gd->lastinc = 0; + gd->tbl = 0; - return (0); + return 0; } /* @@ -94,7 +82,7 @@ void __udelay (unsigned long usec) ulong start = get_ticks(); tmo = usec / 1000; - tmo *= (timer_load_val * 100); + tmo *= (gd->tbu * 100); tmo /= 1000; while ((ulong) (get_ticks() - start) < tmo) @@ -105,7 +93,7 @@ ulong get_timer_masked(void) { ulong tmr = get_ticks(); - return tmr / (timer_clk / CONFIG_SYS_HZ); + return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ); } void udelay_masked(unsigned long usec) @@ -116,10 +104,10 @@ void udelay_masked(unsigned long usec) if (usec >= 1000) { tmo = usec / 1000; - tmo *= (timer_load_val * 100); + tmo *= (gd->tbu * 100); tmo /= 1000; } else { - tmo = usec * (timer_load_val * 100); + tmo = usec * (gd->tbu * 100); tmo /= (1000 * 1000); } @@ -137,18 +125,19 @@ void udelay_masked(unsigned long usec) */ unsigned long long get_ticks(void) { - ulong now = READ_TIMER(); + struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); + ulong now = readl(&timers->tcnto4) & 0xffff; - if (lastdec >= now) { + if (gd->lastinc >= now) { /* normal mode */ - timestamp += lastdec - now; + gd->tbl += gd->lastinc - now; } else { /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; + gd->tbl += gd->lastinc + gd->tbu - now; } - lastdec = now; + gd->lastinc = now; - return timestamp; + return gd->tbl; } /* @@ -157,20 +146,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - -#if defined(CONFIG_SMDK2400) - tbclk = timer_load_val * 100; -#elif defined(CONFIG_SBC2410X) || \ - defined(CONFIG_SMDK2410) || \ - defined(CONFIG_S3C2440) || \ - defined(CONFIG_VCMA9) - tbclk = CONFIG_SYS_HZ; -#else -# error "tbclk not configured" -#endif - - return tbclk; + return CONFIG_SYS_HZ; } /* -- cgit v0.10.2 From 813fcb8a7ed53933613b38ed6db93f6319c01927 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Mon, 13 Feb 2012 07:38:05 +0000 Subject: EXYNOS: SMDK5250: Support all 4 UARTs This properly configures the mux to enable all UARTs. This also fixes things so that we don't configure balls XUCTSN_1 and XURTSN_1 as UART1 configuration (RTS/CTS), since they aren't connected. Signed-off-by: Doug Anderson Acked-by: Chander kashyap Signed-off-by: Minkyu Kang diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 928c08f..32786e2 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -224,11 +224,51 @@ static void board_uart_init(void) (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; - /* UART1 GPIOs (part1) : GPA0CON[7:4] 0x2222 */ - for (i = 4; i < 8; i++) { + /* + * UART0 GPIOs : GPA0CON[3:0] 0x2222 + * Must set CFG17 switches to select UART0 to use. + */ + for (i = 0; i <= 3; i++) { s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); } + + /* + * UART1 GPIOs : GPA0CON[5:4] 0x22 + * Must set CFG17 switches to select UART1 to use. + * + * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down + * in order to use them (so that those pins can be used for I2C). + */ + for (i = 4; i <= 5; i++) { + s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + } + + /* + * UART2 GPIOs : GPA1CON[1:0] 0x22 + * Must set CFG17 switches to select UART2 to use. + * + * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down + * in order to use them (so that those pins can be used for I2C). + */ + for (i = 0; i <= 1; i++) { + s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + } + + /* + * UART3 GPIOs : GPA1CON[5:4] 0x22 + * Must set CFG16 switches to select UART3 to use. + */ + for (i = 4; i <= 5; i++) { + s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + } + + /* + * There's no mux for UART4--it's internal only + */ } #ifdef CONFIG_BOARD_EARLY_INIT_F -- cgit v0.10.2 From 95c2fb371a2155925005d76dfc09c1c067aa912b Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Fri, 2 Mar 2012 03:25:34 +0000 Subject: EXYNOS: Add structure for Exynos4 DMC Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC). Signed-off-by: Chander Kashyap Signed-off-by: Minkyu Kang diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index debbe50..bd52d16 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -2,6 +2,115 @@ #define __DMC_H__ #ifndef __ASSEMBLY__ +struct exynos4_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int memconfig0; + unsigned int memconfig1; + unsigned int directcmd; + unsigned int prechconfig; + unsigned int phycontrol0; + unsigned int phycontrol1; + unsigned int phycontrol2; + unsigned int phycontrol3; + unsigned int pwrdnconfig; + unsigned char res1[0x4]; + unsigned int timingref; + unsigned int timingrow; + unsigned int timingdata; + unsigned int timingpower; + unsigned int phystatus; + unsigned int phyzqcontrol; + unsigned int chip0status; + unsigned int chip1status; + unsigned int arefstatus; + unsigned int mrstatus; + unsigned int phytest0; + unsigned int phytest1; + unsigned int qoscontrol0; + unsigned int qosconfig0; + unsigned int qoscontrol1; + unsigned int qosconfig1; + unsigned int qoscontrol2; + unsigned int qosconfig2; + unsigned int qoscontrol3; + unsigned int qosconfig3; + unsigned int qoscontrol4; + unsigned int qosconfig4; + unsigned int qoscontrol5; + unsigned int qosconfig5; + unsigned int qoscontrol6; + unsigned int qosconfig6; + unsigned int qoscontrol7; + unsigned int qosconfig7; + unsigned int qoscontrol8; + unsigned int qosconfig8; + unsigned int qoscontrol9; + unsigned int qosconfig9; + unsigned int qoscontrol10; + unsigned int qosconfig10; + unsigned int qoscontrol11; + unsigned int qosconfig11; + unsigned int qoscontrol12; + unsigned int qosconfig12; + unsigned int qoscontrol13; + unsigned int qosconfig13; + unsigned int qoscontrol14; + unsigned int qosconfig14; + unsigned int qoscontrol15; + unsigned int qosconfig15; + unsigned int qostimeout0; + unsigned int qostimeout1; + unsigned char res2[0x8]; + unsigned int ivcontrol; + unsigned char res3[0x8]; + unsigned int perevconfig; + unsigned char res4[0xDF00]; + unsigned int pmnc_ppc_a; + unsigned char res5[0xC]; + unsigned int cntens_ppc_a; + unsigned char res6[0xC]; + unsigned int cntenc_ppc_a; + unsigned char res7[0xC]; + unsigned int intens_ppc_a; + unsigned char res8[0xC]; + unsigned int intenc_ppc_a; + unsigned char res9[0xC]; + unsigned int flag_ppc_a; + unsigned char res10[0xAC]; + unsigned int ccnt_ppc_a; + unsigned char res11[0xC]; + unsigned int pmcnt0_ppc_a; + unsigned char res12[0xC]; + unsigned int pmcnt1_ppc_a; + unsigned char res13[0xC]; + unsigned int pmcnt2_ppc_a; + unsigned char res14[0xC]; + unsigned int pmcnt3_ppc_a; + unsigned char res15[0xEBC]; + unsigned int pmnc_ppc_m; + unsigned char res16[0xC]; + unsigned int cntens_ppc_m; + unsigned char res17[0xC]; + unsigned int cntenc_ppc_m; + unsigned char res18[0xC]; + unsigned int intens_ppc_m; + unsigned char res19[0xC]; + unsigned int intenc_ppc_m; + unsigned char res20[0xC]; + unsigned int flag_ppc_m; + unsigned char res21[0xAC]; + unsigned int ccnt_ppc_m; + unsigned char res22[0xC]; + unsigned int pmcnt0_ppc_m; + unsigned char res23[0xC]; + unsigned int pmcnt1_ppc_m; + unsigned char res24[0xC]; + unsigned int pmcnt2_ppc_m; + unsigned char res25[0xC]; + unsigned int pmcnt3_ppc_m; +}; + struct exynos5_dmc { unsigned int concontrol; unsigned int memcontrol; -- cgit v0.10.2 From d821ad4a618fe2a1a23aa66b8be3559de6e484fa Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 12:58:49 +0000 Subject: net: calxedaxgmac: fix build due to missing __aligned definition Include linux/compiler.h to fix build error due to missing __aligned definition. Signed-off-by: Rob Herring diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index 01b2eee..00e26c2 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -16,6 +16,7 @@ */ #include #include +#include #include #include -- cgit v0.10.2 From bd0d90efcc348d38dedfe74c67bc6923f62bd200 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 21 Feb 2012 12:52:26 +0000 Subject: ARM: highbank: fix warning for calxedaxgmac_initialize Add include of netdev.h to pick-up declaration of calxedaxgmac_initialize. Signed-off-by: Rob Herring diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index b0aa182..5f34fec 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -17,6 +17,7 @@ #include #include +#include #include #include -- cgit v0.10.2 From f1e2d1762dd727e43e22a474f0935475f77c19a5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 21 Feb 2012 12:52:27 +0000 Subject: ARM: highbank: add missing get_tbclk The get_tbclk function was missing and the recent commit "common: add possibility for readline_into_buffer timeout" makes it required. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index d8a0288..d92503f 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -121,3 +121,8 @@ ulong get_timer_masked(void) { return tick_to_time(get_ticks()); } + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} -- cgit v0.10.2 From ceb2071c6bdb9b0f6cfe9b0adecbe8d657be496e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:52 +0000 Subject: ARM: highbank: fix us_to_tick calculation udelay calls were off due to failing to convert us to ns. Fix this and drop the unnecessary shifts since NS_PER_TICK is only 7ns. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index d92503f..0f985e2 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -66,10 +66,10 @@ static inline unsigned long long time_to_tick(unsigned long long time) static inline unsigned long long us_to_tick(unsigned long long us) { - unsigned long long tick = us << 16; + unsigned long long tick = us * 1000; tick += NS_PER_TICK - 1; do_div(tick, NS_PER_TICK); - return tick >> 16; + return tick; } unsigned long long get_ticks(void) -- cgit v0.10.2 From 7b81649a053826dc31804d3260a44ff599a9542a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:53 +0000 Subject: ARM: highbank: change TEXT_BASE to 0x8000 Make some space at the beginning of RAM so the FDT can be loaded to a known fixed address at 0x1000. Signed-off-by: Rob Herring diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5604733..e717273 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -120,7 +120,7 @@ #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_TEXT_BASE 0x00001000 +#define CONFIG_SYS_TEXT_BASE 0x00008000 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 #define CONFIG_SKIP_LOWLEVEL_INIT -- cgit v0.10.2 From 877012df309329a9264e6e9558d4f71bfa0cddbe Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:54 +0000 Subject: ARM: highbank: Add boot counter support Add boot counter support using an sysreg which is persistent across reset. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile index 76faeb0..917c3a3 100644 --- a/arch/arm/cpu/armv7/highbank/Makefile +++ b/arch/arm/cpu/armv7/highbank/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := timer.o +COBJS := timer.o bootcount.o SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/highbank/bootcount.c b/arch/arm/cpu/armv7/highbank/bootcount.c new file mode 100644 index 0000000..9ca0656 --- /dev/null +++ b/arch/arm/cpu/armv7/highbank/bootcount.c @@ -0,0 +1,36 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include + +#ifdef CONFIG_BOOTCOUNT_LIMIT +void bootcount_store(ulong a) +{ + writel((BOOTCOUNT_MAGIC & 0xffff0000) | a, CONFIG_SYS_BOOTCOUNT_ADDR); +} + +ulong bootcount_load(void) +{ + u32 tmp = readl(CONFIG_SYS_BOOTCOUNT_ADDR); + + if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return tmp & 0x0000ffff; +} +#endif diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 5f34fec..096e2f6 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -21,6 +21,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/include/configs/highbank.h b/include/configs/highbank.h index e717273..801f4ae 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -41,6 +41,9 @@ #define CONFIG_BAUDRATE 38400 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c + #define CONFIG_MISC_INIT_R #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -- cgit v0.10.2 From 0c34e69f57ad94e0ba66ace657eda2fb80bc5847 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:55 +0000 Subject: ARM: highbank: add reset support Implement reset for highbank platform. Reset is triggered via a wfi instruction, so enabling armv7 for the compiler is necessary. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/config.mk b/arch/arm/cpu/armv7/highbank/config.mk new file mode 100644 index 0000000..935a147 --- /dev/null +++ b/arch/arm/cpu/armv7/highbank/config.mk @@ -0,0 +1 @@ +PLATFORM_CPPFLAGS += -march=armv7-a diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 096e2f6..1e2da78 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -23,6 +23,12 @@ #include #include +#define HB_SREG_A9_PWR_REQ 0xfff3cf00 +#define HB_PWR_SUSPEND 0 +#define HB_PWR_SOFT_RESET 1 +#define HB_PWR_HARD_RESET 2 +#define HB_PWR_SHUTDOWN 3 + DECLARE_GLOBAL_DATA_PTR; /* @@ -68,4 +74,6 @@ void dram_init_banksize(void) void reset_cpu(ulong addr) { + writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); + asm(" wfi"); } -- cgit v0.10.2 From a34e8549480c41057aa47cea50c0785fd9ce4f4a Mon Sep 17 00:00:00 2001 From: Jason Hobbs Date: Wed, 1 Feb 2012 16:57:56 +0000 Subject: ARM: highbank: change env config to use nvram Update the highbank config to use env from NVRAM. Also remove extra env settings as they are not used unless the default env is used. Signed-off-by: Jason Hobbs Signed-off-by: Rob Herring diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 801f4ae..520fa4c 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -93,12 +93,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtaddr_r=0x600000\0" \ - "pxefile_addr_r=0x700000\0" \ - "kernel_addr_r=0x800000\0" \ - "ramdisk_addr_r=0x01000000\0" \ - /*----------------------------------------------------------------------- * Stack sizes * @@ -118,9 +112,13 @@ #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000) -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_IS_NOWHERE +/* Environment data setup +*/ +#define CONFIG_ENV_IS_IN_NVRAM +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ +#define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */ +#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_TEXT_BASE 0x00008000 -- cgit v0.10.2 From 4a3ea216414ad762b3718775a65437c13f0accbc Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:57 +0000 Subject: ARM: highbank: setup env from boot source register Add support to read the boot src register and set bootcmd env from the selected bootcmdX env setting. Based on Linkstation boot choice selection. Signed-off-by: Rob Herring diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 1e2da78..f41bf05 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -24,6 +24,7 @@ #include #define HB_SREG_A9_PWR_REQ 0xfff3cf00 +#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 #define HB_PWR_HARD_RESET 2 @@ -55,8 +56,20 @@ int board_eth_init(bd_t *bis) int misc_init_r(void) { + char envbuffer[16]; + u32 boot_choice; + ahci_init(0xffe08000); scsi_scan(1); + + boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; + sprintf(envbuffer, "bootcmd%d", boot_choice); + if (getenv(envbuffer)) { + sprintf(envbuffer, "run bootcmd%d", boot_choice); + setenv("bootcmd", envbuffer); + } else + setenv("bootcmd", ""); + return 0; } -- cgit v0.10.2 From 77c3d844b0e2617dace78b39433aebe5d219187d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Tue, 13 Mar 2012 05:01:51 +0000 Subject: atmel-boards: add missing atmel_mci.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 72fa467988e7944407a634ddc4bc6a2df685c04c moved atmel_mci_init() into include/atmel_mci.h. Some AT91 boards are also using this interface and need to include atmel_mci.h now. This patch fixes MAKEALL complaints like this: ---8<--- Configuring for ethernut5 - Board: ethernut5, Options: AT91SAM9XE ethernut5.c: In function 'board_mmc_init': ethernut5.c:235:2: warning: implicit declaration of function 'atmel_mci_init' [-Wimplicit-function-declaration] --->8--- Signed-off-by: Andreas Bießmann CC: Albert Aribaud CC: Reinhard Meyer CC: egnite GmbH diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index fd021a3..e99f437 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -77,6 +77,7 @@ #include #include #include +#include #include #include diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c index e0b4cf2..86a8d0b 100644 --- a/board/emk/top9000/top9000.c +++ b/board/emk/top9000/top9000.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include -- cgit v0.10.2 From b39643b72c89489896b1fc2fd9e230b319f2c0c3 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 28 Mar 2012 02:56:30 +0000 Subject: nhk8815: fix build errors Fix: common/libcommon.o: In function `cread_line': /home/ag/git/u-boot/common/main.c:695: undefined reference to `get_ticks' /home/ag/git/u-boot/common/main.c:695: undefined reference to `get_tbclk' /home/ag/git/u-boot/common/main.c:698: undefined reference to `get_ticks' Signed-off-by: Anatolij Gustschin Cc: Alessandro Rubini Acked-by: Marek Vasut Acked-by: Alessandro Rubini diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c index 1cd0e1f..bc2e4d5 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/timer.c +++ b/arch/arm/cpu/arm926ejs/nomadik/timer.c @@ -75,3 +75,13 @@ void __udelay(unsigned long usec) while ((signed)(end - READ_TIMER()) > 0) ; } + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} -- cgit v0.10.2 From 4af7692026ed23fc0424af7eb54595f05acedfce Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 28 Mar 2012 05:38:42 +0000 Subject: board/vpac270/onenand.c: Fix build errors Building for vpac270_ond_256 configuration fails: arch/arm/lib/libarm.o: In function `icache_disable': /home/ag/git/u-boot/arch/arm/lib/cache-cp15.c:156: multiple definition of `icache_disable' board/vpac270/libvpac270.o:/home/ag/git/u-boot/board/vpac270/onenand.c:65: first defined here arch/arm/lib/libarm.o: In function `dcache_disable': /home/ag/git/u-boot/arch/arm/lib/cache-cp15.c:188: multiple definition of `dcache_disable' board/vpac270/libvpac270.o:/home/ag/git/u-boot/board/vpac270/onenand.c:66: first defined here make[1]: *** [/home/ag/git/u-boot/spl/u-boot-spl] Error 1 Signed-off-by: Anatolij Gustschin Cc: Marek Vasut Acked-by: Marek Vasut diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c index c2ae9a7..47f44c3 100644 --- a/board/vpac270/onenand.c +++ b/board/vpac270/onenand.c @@ -60,6 +60,3 @@ void __attribute__((noreturn)) hang(void) for (;;) ; } - -void icache_disable(void) {} -void dcache_disable(void) {} -- cgit v0.10.2 From a4aaad704827616a94c76f0a8efe06555c363545 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:17 +0000 Subject: ARM926EJS: Implement cache operations Signed-off-by: Marek Vasut Cc: Stefano Babic Acked-by: Stefano Babic diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 504f604..5b23e3a 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -23,29 +23,71 @@ #include #ifndef CONFIG_SYS_DCACHE_OFF -static inline void dcache_noop(void) + +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 +#endif + +void invalidate_dcache_all(void) { - if (dcache_status()) { - puts("WARNING: cache operations are not implemented!\n" - "WARNING: disabling D-Cache now, you can re-enable it" - "later with 'dcache on' command\n"); - dcache_disable(); - } + asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0)); } -void invalidate_dcache_all(void) +void flush_dcache_all(void) { - dcache_noop(); + asm volatile( + "0:" + "mrc p15, 0, r15, c7, c14, 3\n" + "bne 0b\n" + "mcr p15, 0, %0, c7, c10, 4\n" + ::"r"(0):"memory" + ); +} + +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; } void invalidate_dcache_range(unsigned long start, unsigned long stop) { - dcache_noop(); + if (!check_cache_range(start, stop)) + return; + + while (start < stop) { + asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } } void flush_dcache_range(unsigned long start, unsigned long stop) { - dcache_noop(); + if (!check_cache_range(start, stop)) + return; + + while (start < stop) { + asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } + + asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); } #else /* #ifndef CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) @@ -64,7 +106,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { } -void flush_cache(unsigned long start, unsigned long size) +void flush_cache(unsigned long start, unsigned long size) { } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ -- cgit v0.10.2 From c3dfe7077630aa5f81d499c08964005d204c2b3b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:18 +0000 Subject: i.MX28: Add cache support into the APBH DMA driver The desc_append() now flushes descriptors into RAM. Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index e85f5fe..c086629 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -93,6 +93,21 @@ static int mxs_dma_read_semaphore(int channel) return tmp; } +#ifndef CONFIG_SYS_DCACHE_OFF +void mxs_dma_flush_desc(struct mxs_dma_desc *desc) +{ + uint32_t addr; + uint32_t size; + + addr = (uint32_t)desc; + size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); + + flush_dcache_range(addr, addr + size); +} +#else +inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {} +#endif + /* * Enable a DMA channel. * @@ -329,8 +344,10 @@ static int mxs_dma_release(int channel) struct mxs_dma_desc *mxs_dma_desc_alloc(void) { struct mxs_dma_desc *pdesc; + uint32_t size; - pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc)); + size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); + pdesc = memalign(MXS_DMA_ALIGNMENT, size); if (pdesc == NULL) return NULL; @@ -415,12 +432,16 @@ int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) last->cmd.next = mxs_dma_cmd_address(pdesc); last->cmd.data |= MXS_DMA_DESC_CHAIN; + + mxs_dma_flush_desc(last); } pdesc->flags |= MXS_DMA_DESC_READY; if (pdesc->flags & MXS_DMA_DESC_FIRST) pchan->pending_num++; list_add_tail(&pdesc->node, &pchan->active); + mxs_dma_flush_desc(pdesc); + return ret; } -- cgit v0.10.2 From 6b9408edd3f6af6e91bcc0eebd4aedc0aca28934 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:19 +0000 Subject: i.MX28: Add cache support to MXS NAND driver Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index ce2a326..4b1297a 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -50,6 +50,7 @@ struct mxs_nand_info { int cur_chip; uint32_t cmd_queue_len; + uint32_t data_buf_size; uint8_t *cmd_buf; uint8_t *data_buf; @@ -73,6 +74,36 @@ struct mxs_nand_info { struct nand_ecclayout fake_ecc_layout; +/* + * Cache management functions + */ +#ifndef CONFIG_SYS_DCACHE_OFF +static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) +{ + uint32_t addr = (uint32_t)info->data_buf; + + flush_dcache_range(addr, addr + info->data_buf_size); +} + +static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) +{ + uint32_t addr = (uint32_t)info->data_buf; + + invalidate_dcache_range(addr, addr + info->data_buf_size); +} + +static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) +{ + uint32_t addr = (uint32_t)info->cmd_buf; + + flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); +} +#else +static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {} +static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {} +static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {} +#endif + static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info) { struct mxs_dma_desc *desc; @@ -286,6 +317,9 @@ static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) mxs_dma_desc_append(channel, d); + /* Flush caches */ + mxs_nand_flush_cmd_buf(nand_info); + /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) @@ -435,6 +469,9 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) goto rtn; } + /* Invalidate caches */ + mxs_nand_inval_data_buf(nand_info); + memcpy(buf, nand_info->data_buf, length); rtn: @@ -484,6 +521,9 @@ static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, mxs_dma_desc_append(channel, d); + /* Flush caches */ + mxs_nand_flush_data_buf(nand_info); + /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) @@ -600,6 +640,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, goto rtn; } + /* Invalidate caches */ + mxs_nand_inval_data_buf(nand_info); + /* Read DMA completed, now do the mark swapping. */ mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); @@ -687,6 +730,9 @@ static void mxs_nand_ecc_write_page(struct mtd_info *mtd, mxs_dma_desc_append(channel, d); + /* Flush caches */ + mxs_nand_flush_data_buf(nand_info); + /* Execute the DMA chain. */ ret = mxs_dma_go(channel); if (ret) { @@ -978,18 +1024,19 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) uint8_t *buf; const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE; + nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT); + /* DMA buffers */ - buf = memalign(MXS_DMA_ALIGNMENT, size); + buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size); if (!buf) { printf("MXS NAND: Error allocating DMA buffers\n"); return -ENOMEM; } - memset(buf, 0, size); + memset(buf, 0, nand_info->data_buf_size); nand_info->data_buf = buf; nand_info->oob_buf = buf + NAND_MAX_PAGESIZE; - /* Command buffers */ nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT, MXS_NAND_COMMAND_BUFFER_SIZE); -- cgit v0.10.2 From 8635ff9e999071cbfaef50ec4d631e60e8de23d3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:41:35 +0000 Subject: MMC: Implement generic bounce buffer This implements generic bounce buffer at the end of MMC command submission chain. Therefore if unaligned data are passed, they are copied. This stuff should be pushed down into the MMC subsystem to squash all places generating these unaligned data. Signed-off-by: Marek Vasut Cc: Andy Fleming diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 49c3349..74e5fea 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -47,10 +47,105 @@ int __board_mmc_getcd(struct mmc *mmc) { int board_mmc_getcd(struct mmc *mmc)__attribute__((weak, alias("__board_mmc_getcd"))); +#ifdef CONFIG_MMC_BOUNCE_BUFFER +static int mmc_bounce_need_bounce(struct mmc_data *orig) +{ + ulong addr, len; + + if (orig->flags & MMC_DATA_READ) + addr = (ulong)orig->dest; + else + addr = (ulong)orig->src; + + if (addr % ARCH_DMA_MINALIGN) { + debug("MMC: Unaligned data destination address %08lx!\n", addr); + return 1; + } + + len = (ulong)(orig->blocksize * orig->blocks); + if (len % ARCH_DMA_MINALIGN) { + debug("MMC: Unaligned data destination length %08lx!\n", len); + return 1; + } + + return 0; +} + +static int mmc_bounce_buffer_start(struct mmc_data *backup, + struct mmc_data *orig) +{ + ulong origlen, len; + void *buffer; + + if (!orig) + return 0; + + if (!mmc_bounce_need_bounce(orig)) + return 0; + + memcpy(backup, orig, sizeof(struct mmc_data)); + + origlen = orig->blocksize * orig->blocks; + len = roundup(origlen, ARCH_DMA_MINALIGN); + buffer = memalign(ARCH_DMA_MINALIGN, len); + if (!buffer) { + puts("MMC: Error allocating MMC bounce buffer!\n"); + return 1; + } + + if (orig->flags & MMC_DATA_READ) { + orig->dest = buffer; + } else { + memcpy(buffer, orig->src, origlen); + orig->src = buffer; + } + + return 0; +} + +static void mmc_bounce_buffer_stop(struct mmc_data *backup, + struct mmc_data *orig) +{ + ulong len; + + if (!orig) + return; + + if (!mmc_bounce_need_bounce(backup)) + return; + + if (backup->flags & MMC_DATA_READ) { + len = backup->blocksize * backup->blocks; + memcpy(backup->dest, orig->dest, len); + free(orig->dest); + orig->dest = backup->dest; + } else { + free((void *)orig->src); + orig->src = backup->src; + } + + return; + +} +#else +static inline int mmc_bounce_buffer_start(struct mmc_data *backup, + struct mmc_data *orig) { } +static inline void mmc_bounce_buffer_stop(struct mmc_data *backup, + struct mmc_data *orig) { } +#endif + int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { -#ifdef CONFIG_MMC_TRACE + struct mmc_data backup; int ret; + + memset(&backup, 0, sizeof(backup)); + + ret = mmc_bounce_buffer_start(&backup, data); + if (ret) + return ret; + +#ifdef CONFIG_MMC_TRACE int i; u8 *ptr; @@ -99,10 +194,11 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) printf("\t\tERROR MMC rsp not supported\n"); break; } - return ret; #else - return mmc->send_cmd(mmc, cmd, data); + ret = mmc->send_cmd(mmc, cmd, data); #endif + mmc_bounce_buffer_stop(&backup, data); + return ret; } int mmc_send_status(struct mmc *mmc, int timeout) -- cgit v0.10.2 From 3687c4155af6ad502ca216a123cff852917dd364 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:21 +0000 Subject: i.MX28: Do data transfers via DMA in MMC driver This utilizes the newly introduced bounce buffers in the MMC layer. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Andy Fleming Cc: Fabio Estevam diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 5f87a1e..e8bad9d 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -41,6 +41,7 @@ #include #include #include +#include struct mxsmmc_priv { int id; @@ -49,6 +50,7 @@ struct mxsmmc_priv { uint32_t *clkctrl_ssp; uint32_t buswidth; int (*mmc_is_wp)(int); + struct mxs_dma_desc *desc; }; #define MXSMMC_MAX_TIMEOUT 10000 @@ -64,8 +66,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) struct mx28_ssp_regs *ssp_regs = priv->regs; uint32_t reg; int timeout; - uint32_t data_count; - uint32_t *data_ptr; + uint32_t data_count, cache_data_count; uint32_t ctrl0; debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); @@ -183,40 +184,41 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!data) return 0; - /* Process the data */ data_count = data->blocksize * data->blocks; - timeout = MXSMMC_MAX_TIMEOUT; + + if (data_count % ARCH_DMA_MINALIGN) + cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); + else + cache_data_count = data_count; + if (data->flags & MMC_DATA_READ) { - data_ptr = (uint32_t *)data->dest; - while (data_count && --timeout) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_EMPTY)) { - *data_ptr++ = readl(&ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = MXSMMC_MAX_TIMEOUT; - } else - udelay(1000); - } + priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; + priv->desc->cmd.address = (dma_addr_t)data->dest; } else { - data_ptr = (uint32_t *)data->src; - timeout *= 100; - while (data_count && --timeout) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_FULL)) { - writel(*data_ptr++, &ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = MXSMMC_MAX_TIMEOUT; - } else - udelay(1000); - } + priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; + priv->desc->cmd.address = (dma_addr_t)data->src; + + /* Flush data to DRAM so DMA can pick them up */ + flush_dcache_range((uint32_t)priv->desc->cmd.address, + (uint32_t)(priv->desc->cmd.address + cache_data_count)); } - if (!timeout) { - printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", - mmc->block_dev.dev, cmd->cmdidx, reg); + priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | + (data_count << MXS_DMA_DESC_BYTES_OFFSET); + + + mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc); + if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) { + printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); return COMM_ERR; } + /* The data arrived into DRAM, invalidate cache over them */ + if (data->flags & MMC_DATA_READ) { + invalidate_dcache_range((uint32_t)priv->desc->cmd.address, + (uint32_t)(priv->desc->cmd.address + cache_data_count)); + } + /* Check data errors */ reg = readl(&ssp_regs->hw_ssp_status); if (reg & @@ -270,7 +272,8 @@ static int mxsmmc_init(struct mmc *mmc) /* 8 bits word length in MMC mode */ clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, - SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); + SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | + SSP_CTRL1_DMA_ENABLE); /* Set initial bit clock 400 KHz */ mx28_set_ssp_busclock(priv->id, 400); @@ -300,6 +303,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) return -ENOMEM; } + priv->desc = mxs_dma_desc_alloc(); + if (!priv->desc) { + free(priv); + free(mmc); + return -ENOMEM; + } + priv->mmc_is_wp = wp; priv->id = id; switch (id) { @@ -345,7 +355,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) */ mmc->f_min = 400000; mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; - mmc->b_max = 0; + mmc->b_max = 0x40; mmc_register(mmc); return 0; -- cgit v0.10.2 From b3541c1ac93d4e4b786d28ef2f6dc5976a580af5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:22 +0000 Subject: i.MX28: Make use of the bounce buffer This allows i.MX28 MMC host to fully utilize DMA transfers and caches, greatly improving speed. Signed-off-by: Marek Vasut Cc: Fabio Estevam diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4b97c71..8b83180 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -140,6 +140,7 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC +#define CONFIG_MMC_BOUNCE_BUFFER #define CONFIG_GENERIC_MMC #define CONFIG_MXS_MMC #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 30814c6..cdcc6e0 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -138,6 +138,7 @@ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_MMC_BOUNCE_BUFFER #define CONFIG_MXS_MMC #endif -- cgit v0.10.2 From 345cd3584cd90288abd4256678fbfa7d2443bd00 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:23 +0000 Subject: i.MX28: Enable caches by default Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index 9bfd83b..cf6d4e9 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -63,6 +63,16 @@ void reset_cpu(ulong ignored) ; } +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout) { while (--timeout) { -- cgit v0.10.2 From 2c4b3c19a1fe1c4e9ef1ec457cf34821368288d7 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 15 Mar 2012 18:33:24 +0000 Subject: net: force PKTALIGN to ARCH_DMA_MINALIGN This will prevent the need for architectures whose DMA alignment is greater than 32 to have bounce buffers. Signed-off-by: Eric Nelson diff --git a/include/net.h b/include/net.h index 5560785..ee11f82 100644 --- a/include/net.h +++ b/include/net.h @@ -16,6 +16,7 @@ #include #endif /* CONFIG_8xx */ +#include #include /* for nton* / ntoh* stuff */ @@ -31,7 +32,7 @@ # define PKTBUFSRX 4 #endif -#define PKTALIGN 32 +#define PKTALIGN ARCH_DMA_MINALIGN /* IPv4 addresses are always 32 bits in size */ typedef u32 IPaddr_t; -- cgit v0.10.2 From 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 15 Mar 2012 18:33:25 +0000 Subject: net: fec_mxc: allow use with cache enabled Ensure that transmit and receive buffers are cache-line aligned. Invalidate cache for each packet as received, update receive buffer descriptors one cache line at a time, flush cache before transmitting. Original patch by Marek: http://lists.denx.de/pipermail/u-boot/2012-February/117695.html Signed-off-by: Eric Nelson Acked-by: Marek Vasut Tested-by: Marek Vasut diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1fdd071..d8db9f0 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -38,16 +38,28 @@ DECLARE_GLOBAL_DATA_PTR; #error "CONFIG_MII has to be defined!" #endif -#ifndef CONFIG_FEC_XCV_TYPE -#define CONFIG_FEC_XCV_TYPE MII100 +#ifndef CONFIG_FEC_XCV_TYPE +#define CONFIG_FEC_XCV_TYPE MII100 #endif /* * The i.MX28 operates with packets in big endian. We need to swap them before * sending and after receiving. */ -#ifdef CONFIG_MX28 -#define CONFIG_FEC_MXC_SWAP_PACKET +#ifdef CONFIG_MX28 +#define CONFIG_FEC_MXC_SWAP_PACKET +#endif + +#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) + +/* Check various alignment issues at compile time */ +#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) +#error "ARCH_DMA_MINALIGN must be multiple of 16!" +#endif + +#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ + (PKTALIGN % ARCH_DMA_MINALIGN != 0)) +#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" #endif #undef DEBUG @@ -59,7 +71,7 @@ struct nbuf { uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ }; -#ifdef CONFIG_FEC_MXC_SWAP_PACKET +#ifdef CONFIG_FEC_MXC_SWAP_PACKET static void swap_packet(uint32_t *packet, int length) { int i; @@ -259,43 +271,52 @@ static int fec_tx_task_disable(struct fec_priv *fec) * Initialize receive task's buffer descriptors * @param[in] fec all we know about the device yet * @param[in] count receive buffer count to be allocated - * @param[in] size size of each receive buffer + * @param[in] dsize desired size of each receive buffer * @return 0 on success * * For this task we need additional memory for the data buffers. And each * data buffer requires some alignment. Thy must be aligned to a specific - * boundary each (DB_DATA_ALIGNMENT). + * boundary each. */ -static int fec_rbd_init(struct fec_priv *fec, int count, int size) +static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) { - int ix; - uint32_t p = 0; - - /* reserve data memory and consider alignment */ - if (fec->rdb_ptr == NULL) - fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); - p = (uint32_t)fec->rdb_ptr; - if (!p) { - puts("fec_mxc: not enough malloc memory\n"); - return -ENOMEM; - } - memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); - p += DB_DATA_ALIGNMENT-1; - p &= ~(DB_DATA_ALIGNMENT-1); - - for (ix = 0; ix < count; ix++) { - writel(p, &fec->rbd_base[ix].data_pointer); - p += size; - writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); - writew(0, &fec->rbd_base[ix].data_length); - } + uint32_t size; + int i; + /* - * mark the last RBD to close the ring + * Allocate memory for the buffers. This allocation respects the + * alignment */ - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); + size = roundup(dsize, ARCH_DMA_MINALIGN); + for (i = 0; i < count; i++) { + uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); + if (data_ptr == 0) { + uint8_t *data = memalign(ARCH_DMA_MINALIGN, + size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", + __func__, i); + goto err; + } + writel((uint32_t)data, &fec->rbd_base[i].data_pointer); + } /* needs allocation */ + writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); + writew(0, &fec->rbd_base[i].data_length); + } + + /* Mark the last RBD to close the ring. */ + writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); fec->rbd_index = 0; return 0; + +err: + for (; i >= 0; i--) { + uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); + free((void *)data_ptr); + } + + return -ENOMEM; } /** @@ -312,9 +333,13 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int size) */ static void fec_tbd_init(struct fec_priv *fec) { + unsigned addr = (unsigned)fec->tbd_base; + unsigned size = roundup(2 * sizeof(struct fec_bd), + ARCH_DMA_MINALIGN); writew(0x0000, &fec->tbd_base[0].status); writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); fec->tbd_index = 0; + flush_dcache_range(addr, addr+size); } /** @@ -324,16 +349,10 @@ static void fec_tbd_init(struct fec_priv *fec) */ static void fec_rbd_clean(int last, struct fec_bd *pRbd) { - /* - * Reset buffer descriptor as empty - */ + unsigned short flags = FEC_RBD_EMPTY; if (last) - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); - else - writew(FEC_RBD_EMPTY, &pRbd->status); - /* - * no data in it - */ + flags |= FEC_RBD_WRAP; + writew(flags, &pRbd->status); writew(0, &pRbd->data_length); } @@ -387,12 +406,25 @@ static int fec_open(struct eth_device *edev) { struct fec_priv *fec = (struct fec_priv *)edev->priv; int speed; + uint32_t addr, size; + int i; debug("fec_open: fec_open(dev)\n"); /* full-duplex, heartbeat disabled */ writel(1 << 2, &fec->eth->x_cntrl); fec->rbd_index = 0; + /* Invalidate all descriptors */ + for (i = 0; i < FEC_RBD_NUM - 1; i++) + fec_rbd_clean(0, &fec->rbd_base[i]); + fec_rbd_clean(1, &fec->rbd_base[i]); + + /* Flush the descriptors into RAM */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), + ARCH_DMA_MINALIGN); + addr = (uint32_t)fec->rbd_base; + flush_dcache_range(addr, addr + size); + #ifdef FEC_QUIRK_ENET_MAC /* Enable ENET HW endian SWAP */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, @@ -478,38 +510,55 @@ static int fec_open(struct eth_device *edev) static int fec_init(struct eth_device *dev, bd_t* bd) { - uint32_t base; struct fec_priv *fec = (struct fec_priv *)dev->priv; uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; uint32_t rcntrl; - int i; + uint32_t size; + int i, ret; /* Initialize MAC address */ fec_set_hwaddr(dev); /* - * reserve memory for both buffer descriptor chains at once - * Datasheet forces the startaddress of each chain is 16 byte - * aligned + * Allocate transmit descriptors, there are two in total. This + * allocation respects cache alignment. */ - if (fec->base_ptr == NULL) - fec->base_ptr = malloc((2 + FEC_RBD_NUM) * - sizeof(struct fec_bd) + DB_ALIGNMENT); - base = (uint32_t)fec->base_ptr; - if (!base) { - puts("fec_mxc: not enough malloc memory\n"); - return -ENOMEM; + if (!fec->tbd_base) { + size = roundup(2 * sizeof(struct fec_bd), + ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) { + ret = -ENOMEM; + goto err1; + } + memset(fec->tbd_base, 0, size); + fec_tbd_init(fec); + flush_dcache_range((unsigned)fec->tbd_base, size); } - memset((void *)base, 0, (2 + FEC_RBD_NUM) * - sizeof(struct fec_bd) + DB_ALIGNMENT); - base += (DB_ALIGNMENT-1); - base &= ~(DB_ALIGNMENT-1); - - fec->rbd_base = (struct fec_bd *)base; - base += FEC_RBD_NUM * sizeof(struct fec_bd); - - fec->tbd_base = (struct fec_bd *)base; + /* + * Allocate receive descriptors. This allocation respects cache + * alignment. + */ + if (!fec->rbd_base) { + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), + ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) { + ret = -ENOMEM; + goto err2; + } + memset(fec->rbd_base, 0, size); + /* + * Initialize RxBD ring + */ + if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { + ret = -ENOMEM; + goto err3; + } + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); + } /* * Set interrupt mask register @@ -566,23 +615,19 @@ static int fec_init(struct eth_device *dev, bd_t* bd) writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); - /* - * Initialize RxBD/TxBD rings - */ - if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { - free(fec->base_ptr); - fec->base_ptr = NULL; - return -ENOMEM; - } - fec_tbd_init(fec); - - #ifndef CONFIG_PHYLIB if (fec->xcv_type != SEVENWIRE) miiphy_restart_aneg(dev); #endif fec_open(dev); return 0; + +err3: + free(fec->rbd_base); +err2: + free(fec->tbd_base); +err1: + return ret; } /** @@ -631,9 +676,11 @@ static void fec_halt(struct eth_device *dev) * @param[in] length Data count in bytes * @return 0 on success */ -static int fec_send(struct eth_device *dev, volatile void* packet, int length) +static int fec_send(struct eth_device *dev, volatile void *packet, int length) { unsigned int status; + uint32_t size; + uint32_t addr; /* * This routine transmits one frame. This routine only accepts @@ -650,15 +697,21 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length) } /* - * Setup the transmit buffer - * Note: We are always using the first buffer for transmission, - * the second will be empty and only used to stop the DMA engine + * Setup the transmit buffer. We are always using the first buffer for + * transmission, the second will be empty and only used to stop the DMA + * engine. We also flush the packet to RAM here to avoid cache trouble. */ -#ifdef CONFIG_FEC_MXC_SWAP_PACKET +#ifdef CONFIG_FEC_MXC_SWAP_PACKET swap_packet((uint32_t *)packet, length); #endif + + addr = (uint32_t)packet; + size = roundup(length, ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + writew(length, &fec->tbd_base[fec->tbd_index].data_length); - writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); + writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); + /* * update BD's status now * This block: @@ -672,16 +725,30 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length) writew(status, &fec->tbd_base[fec->tbd_index].status); /* + * Flush data cache. This code flushes both TX descriptors to RAM. + * After this code, the descriptors will be safely in RAM and we + * can start DMA. + */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + addr = (uint32_t)fec->tbd_base; + flush_dcache_range(addr, addr + size); + + /* * Enable SmartDMA transmit task */ fec_tx_task_enable(fec); /* - * wait until frame is sent . + * Wait until frame is sent. On each turn of the wait cycle, we must + * invalidate data cache to see what's really in RAM. Also, we need + * barrier here. */ + invalidate_dcache_range(addr, addr + size); while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { udelay(1); + invalidate_dcache_range(addr, addr + size); } + debug("fec_send: status 0x%x index %d\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index); @@ -707,6 +774,8 @@ static int fec_recv(struct eth_device *dev) int frame_length, len = 0; struct nbuf *frame; uint16_t bd_status; + uint32_t addr, size; + int i; uchar buff[FEC_MAX_PKT_SIZE]; /* @@ -737,8 +806,23 @@ static int fec_recv(struct eth_device *dev) } /* - * ensure reading the right buffer status + * Read the buffer status. Before the status can be read, the data cache + * must be invalidated, because the data in RAM might have been changed + * by DMA. The descriptors are properly aligned to cachelines so there's + * no need to worry they'd overlap. + * + * WARNING: By invalidating the descriptor here, we also invalidate + * the descriptors surrounding this one. Therefore we can NOT change the + * contents of this descriptor nor the surrounding ones. The problem is + * that in order to mark the descriptor as processed, we need to change + * the descriptor. The solution is to mark the whole cache line when all + * descriptors in the cache line are processed. */ + addr = (uint32_t)rbd; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + invalidate_dcache_range(addr, addr + size); + bd_status = readw(&rbd->status); debug("fec_recv: status 0x%x\n", bd_status); @@ -751,9 +835,16 @@ static int fec_recv(struct eth_device *dev) frame = (struct nbuf *)readl(&rbd->data_pointer); frame_length = readw(&rbd->data_length) - 4; /* + * Invalidate data cache over the buffer + */ + addr = (uint32_t)frame; + size = roundup(frame_length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(addr, addr + size); + + /* * Fill the buffer and pass it to upper layers */ -#ifdef CONFIG_FEC_MXC_SWAP_PACKET +#ifdef CONFIG_FEC_MXC_SWAP_PACKET swap_packet((uint32_t *)frame->data, frame_length); #endif memcpy(buff, frame->data, frame_length); @@ -765,11 +856,25 @@ static int fec_recv(struct eth_device *dev) (ulong)rbd->data_pointer, bd_status); } + /* - * free the current buffer, restart the engine - * and move forward to the next buffer + * Free the current buffer, restart the engine and move forward + * to the next buffer. Here we check if the whole cacheline of + * descriptors was already processed and if so, we mark it free + * as whole. */ - fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); + size = RXDESC_PER_CACHELINE - 1; + if ((fec->rbd_index & size) == size) { + i = fec->rbd_index - size; + addr = (uint32_t)&fec->rbd_base[i]; + for (; i <= fec->rbd_index ; i++) { + fec_rbd_clean(i == (FEC_RBD_NUM - 1), + &fec->rbd_base[i]); + } + flush_dcache_range(addr, + addr + ARCH_DMA_MINALIGN); + } + fec_rx_task_enable(fec); fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; } @@ -866,7 +971,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) bus->read = fec_phy_read; bus->write = fec_phy_write; sprintf(bus->name, edev->name); -#ifdef CONFIG_MX28 +#ifdef CONFIG_MX28 /* * The i.MX28 has two ethernet interfaces, but they are not equal. * Only the first one can access the MDIO bus. @@ -901,7 +1006,7 @@ err1: return ret; } -#ifndef CONFIG_FEC_MXC_MULTI +#ifndef CONFIG_FEC_MXC_MULTI int fecmxc_initialize(bd_t *bd) { int lout = 1; diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 2eb7803..852b2e0 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -234,22 +234,6 @@ struct ethernet_regs { #endif /** - * @brief Descriptor buffer alignment - * - * i.MX27 requires a 16 byte alignment (but for the first element only) - */ -#define DB_ALIGNMENT 16 - -/** - * @brief Data buffer alignment - * - * i.MX27 requires a four byte alignment for transmit and 16 bits - * alignment for receive so take 16 - * Note: Valid for member data_pointer in struct buffer_descriptor - */ -#define DB_DATA_ALIGNMENT 16 - -/** * @brief Receive & Transmit Buffer Descriptor definitions * * Note: The first BD must be aligned (see DB_ALIGNMENT) @@ -282,8 +266,7 @@ struct fec_priv { struct fec_bd *tbd_base; /* TBD ring */ int tbd_index; /* next transmit BD to write */ bd_t *bd; - void *rdb_ptr; - void *base_ptr; + uint8_t *tdb_ptr; int dev_id; int phy_id; struct mii_dev *bus; -- cgit v0.10.2 From d8bd820935bb9b8bf2717a259eeab4376e9ccc9a Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 17 Feb 2012 06:01:21 +0000 Subject: arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer load The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP load using a constant in tegra2_start. Change it to use a load thru another reg using mov sp, %0 : : "r"(CONST). Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK. Signed-off-by: Tom Warren Acked-by: Simon Glass Tested-by: Simon Glass diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 4c44bb3..f0450f4 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -298,11 +298,11 @@ void tegra2_start(void) writel(0xC0, &pmt->pmt_cfg_ctl); /* - * If we are ARM7 - give it a different stack. We are about to - * start up the A9 which will want to use this one. - */ - asm volatile("ldr sp, =%c0\n" - : : "i"(AVP_EARLY_BOOT_STACK_LIMIT)); + * If we are ARM7 - give it a different stack. We are about to + * start up the A9 which will want to use this one. + */ + asm volatile("mov sp, %0\n" + : : "r"(AVP_EARLY_BOOT_STACK_LIMIT)); start_cpu((u32)_start); halt_avp(); -- cgit v0.10.2 From a53f4a29ac62a2e83d35a4a7b6d6969cf95a5902 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Jan 2012 08:20:50 +0000 Subject: fdt: Add fdtdec_find_aliases() to deal with alias nodes Stephen Warren pointed out that we should use nodes whether or not they have an alias in the /aliases section. The aliases section specifies the order so far as it can, but is not essential. Operating without alisses is useful when the enumerated order of nodes does not matter (admittedly rare in U-Boot). This is considerably more complex, and it is important to keep this complexity out of driver code. This patch creates a function fdtdec_find_aliases() which returns an ordered list of node offsets for a particular compatible ID, taking account of alias nodes. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index d871cdd..492431c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -126,3 +126,50 @@ int fdtdec_get_is_enabled(const void *blob, int node, int default_val); * if not. */ int fdtdec_check_fdt(void); + +/** + * Find the nodes for a peripheral and return a list of them in the correct + * order. This is used to enumerate all the peripherals of a certain type. + * + * To use this, optionally set up a /aliases node with alias properties for + * a peripheral. For example, for usb you could have: + * + * aliases { + * usb0 = "/ehci@c5008000"; + * usb1 = "/ehci@c5000000"; + * }; + * + * Pass "usb" as the name to this function and will return a list of two + * nodes offsets: /ehci@c5008000 and ehci@c5000000. + * + * All nodes returned will match the compatible ID, as it is assumed that + * all peripherals use the same driver. + * + * If no alias node is found, then the node list will be returned in the + * order found in the fdt. If the aliases mention a node which doesn't + * exist, then this will be ignored. If nodes are found with no aliases, + * they will be added in any order. + * + * If there is a gap in the aliases, then this function return a 0 node at + * that position. The return value will also count these gaps. + * + * This function checks node properties and will not return nodes which are + * marked disabled (status = "disabled"). + * + * @param blob FDT blob to use + * @param name Root name of alias to search for + * @param id Compatible ID to look for + * @param node_list Place to put list of found nodes + * @param maxcount Maximum number of nodes to find + * @return number of nodes found on success, FTD_ERR_... on error + */ +int fdtdec_find_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount); + +/* + * Get the name for a compatible ID + * + * @param id Compatible ID to look for + * @return compatible string for that id + */ +const char *fdtdec_get_compatible(enum fdt_compat_id id); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 0f87163..55d5bdf 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -35,6 +35,13 @@ DECLARE_GLOBAL_DATA_PTR; static const char * const compat_names[COMPAT_COUNT] = { }; +const char *fdtdec_get_compatible(enum fdt_compat_id id) +{ + /* We allow reading of the 'unknown' ID for testing purposes */ + assert(id >= 0 && id < COMPAT_COUNT); + return compat_names[id]; +} + /** * Look in the FDT for an alias with the given name and return its node. * @@ -132,6 +139,115 @@ int fdtdec_next_alias(const void *blob, const char *name, return err ? -FDT_ERR_NOTFOUND : node; } +/* TODO: Can we tighten this code up a little? */ +int fdtdec_find_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount) +{ + int name_len = strlen(name); + int nodes[maxcount]; + int num_found = 0; + int offset, node; + int alias_node; + int count; + int i, j; + + /* find the alias node if present */ + alias_node = fdt_path_offset(blob, "/aliases"); + + /* + * start with nothing, and we can assume that the root node can't + * match + */ + memset(nodes, '\0', sizeof(nodes)); + + /* First find all the compatible nodes */ + for (node = count = 0; node >= 0 && count < maxcount;) { + node = fdtdec_next_compatible(blob, node, id); + if (node >= 0) + nodes[count++] = node; + } + if (node >= 0) + debug("%s: warning: maxcount exceeded with alias '%s'\n", + __func__, name); + + /* Now find all the aliases */ + memset(node_list, '\0', sizeof(*node_list) * maxcount); + + for (offset = fdt_first_property_offset(blob, alias_node); + offset > 0; + offset = fdt_next_property_offset(blob, offset)) { + const struct fdt_property *prop; + const char *path; + int number; + int found; + + node = 0; + prop = fdt_get_property_by_offset(blob, offset, NULL); + path = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + if (prop->len && 0 == strncmp(path, name, name_len)) + node = fdt_path_offset(blob, prop->data); + if (node <= 0) + continue; + + /* Get the alias number */ + number = simple_strtoul(path + name_len, NULL, 10); + if (number < 0 || number >= maxcount) { + debug("%s: warning: alias '%s' is out of range\n", + __func__, path); + continue; + } + + /* Make sure the node we found is actually in our list! */ + found = -1; + for (j = 0; j < count; j++) + if (nodes[j] == node) { + found = j; + break; + } + + if (found == -1) { + debug("%s: warning: alias '%s' points to a node " + "'%s' that is missing or is not compatible " + " with '%s'\n", __func__, path, + fdt_get_name(blob, node, NULL), + compat_names[id]); + continue; + } + + /* + * Add this node to our list in the right place, and mark + * it as done. + */ + if (fdtdec_get_is_enabled(blob, node)) { + node_list[number] = node; + if (number >= num_found) + num_found = number + 1; + } + nodes[j] = 0; + } + + /* Add any nodes not mentioned by an alias */ + for (i = j = 0; i < maxcount; i++) { + if (!node_list[i]) { + for (; j < maxcount; j++) + if (nodes[j] && + fdtdec_get_is_enabled(blob, nodes[j])) + break; + + /* Have we run out of nodes to add? */ + if (j == maxcount) + break; + + assert(!node_list[i]); + node_list[i] = nodes[j++]; + if (i >= num_found) + num_found = i + 1; + } + } + + return num_found; +} + /* * This function is a little odd in that it accesses global data. At some * point if the architecture board.c files merge this will make more sense. -- cgit v0.10.2 From dc254f382350f3d193b07d3ad8c7f49b42022ab2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Jan 2012 08:20:51 +0000 Subject: fdt: Add tests for fdtdec The fdtdec_find_aliases_for_id() function is complicated enough that it really should have some tests. This does not necessarily need to be committed to U-Boot, but it might be useful. (note there are a few minor inconsistencies with this patch which will be cleaned up when the USB series is applied) Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/lib/Makefile b/lib/Makefile index 4b5734a..a0fec60 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -40,6 +40,7 @@ COBJS-y += crc32.o COBJS-y += display_options.o COBJS-y += errno.o COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o +COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o COBJS-$(CONFIG_GZIP) += gunzip.o COBJS-y += hashtable.o COBJS-$(CONFIG_LMB) += lmb.o diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c new file mode 100644 index 0000000..497be8e --- /dev/null +++ b/lib/fdtdec_test.c @@ -0,0 +1,226 @@ +/* + * Some very basic tests for fdtdec, accessed through test_fdtdec command. + * They are easiest to use with sandbox. + * + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* The size of our test fdt blob */ +#define FDT_SIZE (16 * 1024) + +/** + * Check if an operation failed, and if so, print an error + * + * @param oper_name Name of operation + * @param err Error code to check + * + * @return 0 if ok, -1 if there was an error + */ +static int fdt_checkerr(const char *oper_name, int err) +{ + if (err) { + printf("%s: %s: %s\n", __func__, oper_name, fdt_strerror(err)); + return -1; + } + + return 0; +} + +/** + * Check the result of an operation and if incorrect, print an error + * + * @param oper_name Name of operation + * @param expected Expected value + * @param value Actual value + * + * @return 0 if ok, -1 if there was an error + */ +static int checkval(const char *oper_name, int expected, int value) +{ + if (expected != value) { + printf("%s: %s: expected %d, but returned %d\n", __func__, + oper_name, expected, value); + return -1; + } + + return 0; +} + +#define CHECK(op) if (fdt_checkerr(#op, op)) return -1 +#define CHECKVAL(op, expected) \ + if (checkval(#op, expected, op)) \ + return -1 +#define CHECKOK(op) CHECKVAL(op, 0) + +/* maximum number of nodes / aliases to generate */ +#define MAX_NODES 20 + +/* + * Make a test fdt + * + * @param fdt Device tree pointer + * @param size Size of device tree blob + * @param aliases Specifies alias assignments. Format is a list of items + * separated by space. Items are #a where + * # is the alias number + * a is the node to point to + * @param nodes Specifies nodes to generate (a=0, b=1), upper case + * means to create a disabled node + */ +static int make_fdt(void *fdt, int size, const char *aliases, + const char *nodes) +{ + char name[20], value[20]; + const char *s; + int fd; + + CHECK(fdt_create(fdt, size)); + CHECK(fdt_finish_reservemap(fdt)); + CHECK(fdt_begin_node(fdt, "")); + + CHECK(fdt_begin_node(fdt, "aliases")); + for (s = aliases; *s;) { + sprintf(name, "i2c%c", *s); + sprintf(value, "/i2c%d@0", s[1] - 'a'); + CHECK(fdt_property_string(fdt, name, value)); + s += 2 + (s[2] != '\0'); + } + CHECK(fdt_end_node(fdt)); + + for (s = nodes; *s; s++) { + sprintf(value, "i2c%d@0", (*s & 0xdf) - 'A'); + CHECK(fdt_begin_node(fdt, value)); + CHECK(fdt_property_string(fdt, "compatible", + fdtdec_get_compatible(COMPAT_UNKNOWN))); + if (*s <= 'Z') + CHECK(fdt_property_string(fdt, "status", "disabled")); + CHECK(fdt_end_node(fdt)); + } + + CHECK(fdt_end_node(fdt)); + CHECK(fdt_finish(fdt)); + CHECK(fdt_pack(fdt)); +#if defined(DEBUG) && defined(CONFIG_SANDBOX) + fd = os_open("/tmp/fdtdec-text.dtb", OS_O_CREAT | OS_O_WRONLY); + if (fd == -1) { + printf("Could not open .dtb file to write\n"); + return -1; + } + os_write(fd, fdt, size); + os_close(fd); +#endif + return 0; +} + +static int run_test(const char *aliases, const char *nodes, const char *expect) +{ + int list[MAX_NODES]; + const char *s; + void *blob; + int i; + + blob = malloc(FDT_SIZE); + if (!blob) { + printf("%s: out of memory\n", __func__); + return 1; + } + + printf("aliases=%s, nodes=%s, expect=%s: ", aliases, nodes, expect); + CHECKVAL(make_fdt(blob, FDT_SIZE, aliases, nodes), 0); + CHECKVAL(fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_UNKNOWN, + list, ARRAY_SIZE(list)), strlen(expect)); + + /* Check we got the right ones */ + for (i = 0, s = expect; *s; s++, i++) { + int want = *s; + const char *name; + int got = ' '; + + name = list[i] ? fdt_get_name(blob, list[i], NULL) : NULL; + if (name) + got = name[3] + 'a' - '0'; + + if (got != want) { + printf("Position %d: Expected '%c', got '%c' ('%s')\n", + i, want, got, name); + return 1; + } + } + + printf("pass\n"); + return 0; +} + +static int do_test_fdtdec(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + /* basic tests */ + CHECKOK(run_test("", "", "")); + CHECKOK(run_test("1e 3d", "", "")); + + /* + * 'a' represents 0, 'b' represents 1, etc. + * The first character is the alias number, the second is the node + * number. So the params mean: + * 0a 1b : point alias 0 to node 0 (a), alias 1 to node 1(b) + * ab : to create nodes 0 and 1 (a and b) + * ab : we expect the function to return two nodes, in + * the order 0, 1 + */ + CHECKOK(run_test("0a 1b", "ab", "ab")); + + CHECKOK(run_test("0a 1c", "ab", "ab")); + CHECKOK(run_test("1c", "ab", "ab")); + CHECKOK(run_test("1b", "ab", "ab")); + CHECKOK(run_test("0b", "ab", "ba")); + CHECKOK(run_test("0b 2d", "dbc", "bcd")); + CHECKOK(run_test("0d 3a 1c 2b", "dbac", "dcba")); + + /* things with holes */ + CHECKOK(run_test("1b 3d", "dbc", "cb d")); + CHECKOK(run_test("1e 3d", "dbc", "bc d")); + + /* no aliases */ + CHECKOK(run_test("", "dbac", "dbac")); + + /* disabled nodes */ + CHECKOK(run_test("0d 3a 1c 2b", "dBac", "dc a")); + CHECKOK(run_test("0b 2d", "DBc", "c")); + CHECKOK(run_test("0b 4d 2c", "DBc", " c")); + + /* conflicting aliases - first one gets it */ + CHECKOK(run_test("2a 1a 0a", "a", " a")); + CHECKOK(run_test("0a 1a 2a", "a", "a")); + + printf("Test passed\n"); + return 0; +} + +U_BOOT_CMD( + test_fdtdec, 3, 1, do_test_fdtdec, + "test_fdtdec", + "Run tests for fdtdec library"); -- cgit v0.10.2 From f88fe2ded4acd035826018f33c6a67033a8f5d07 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:34 +0000 Subject: fdt: Tidy up a few fdtdec problems This fixes five trivial issues in fdtdec.c: 1. fdtdec_get_is_enabled() doesn't really need a default value 2. The fdt must be word-aligned, since otherwise it will fail on ARM 3. The compat_names[] array is missing its first element. This is needed only because the first fdt_compat_id is defined to be invalid. 4. Added a header prototype for fdtdec_next_compatible() 5. Change fdtdec_next_alias() to only increment its 'upto' parameter on success, to make the display error messages in the caller easier. Signed-off-by: Simon Glass Acked-by: Gerald Van Baren Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index 492431c..5469c16 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -82,6 +82,21 @@ int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id, int *upto); /** + * Find the next compatible node for a peripheral. + * + * Do the first call with node = 0. This function will return a pointer to + * the next compatible node. Next time you call this function, pass the + * value returned, and the next node will be provided. + * + * @param blob FDT blob to use + * @param node Start node for search + * @param id Compatible ID to look for (enum fdt_compat_id) + * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more + */ +int fdtdec_next_compatible(const void *blob, int node, + enum fdt_compat_id id); + +/** * Look up an address property in a node and return it as an address. * The property must hold either one address with no trailing data or * one address with a length. This is only tested on 32-bit machines. @@ -112,14 +127,14 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, * Checks whether a node is enabled. * This looks for a 'status' property. If this exists, then returns 1 if * the status is 'ok' and 0 otherwise. If there is no status property, - * it returns the default value. + * it returns 1 on the assumption that anything mentioned should be enabled + * by default. * * @param blob FDT blob * @param node node to examine - * @param default_val default value to return if no 'status' property exists - * @return integer value 0/1, if found, or default_val if not + * @return integer value 0 (not enabled) or 1 (enabled) */ -int fdtdec_get_is_enabled(const void *blob, int node, int default_val); +int fdtdec_get_is_enabled(const void *blob, int node); /** * Checks whether we have a valid fdt available to control U-Boot, and panic diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 55d5bdf..bf31717 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define COMPAT(id, name) name static const char * const compat_names[COMPAT_COUNT] = { + COMPAT(UNKNOWN, ""), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -91,14 +92,21 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, return default_val; } -int fdtdec_get_is_enabled(const void *blob, int node, int default_val) +int fdtdec_get_is_enabled(const void *blob, int node) { const char *cell; + /* + * It should say "okay", so only allow that. Some fdts use "ok" but + * this is a bug. Please fix your device tree source file. See here + * for discussion: + * + * http://www.mail-archive.com/u-boot@lists.denx.de/msg71598.html + */ cell = fdt_getprop(blob, node, "status", NULL); if (cell) - return 0 == strcmp(cell, "ok"); - return default_val; + return 0 == strcmp(cell, "okay"); + return 1; } enum fdt_compat_id fd_dec_lookup(const void *blob, int node) @@ -129,14 +137,16 @@ int fdtdec_next_alias(const void *blob, const char *name, /* snprintf() is not available */ assert(strlen(name) < MAX_STR_LEN); sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto); - (*upto)++; node = find_alias_node(blob, str); if (node < 0) return node; err = fdt_node_check_compatible(blob, node, compat_names[id]); if (err < 0) return err; - return err ? -FDT_ERR_NOTFOUND : node; + if (err) + return -FDT_ERR_NOTFOUND; + (*upto)++; + return node; } /* TODO: Can we tighten this code up a little? */ @@ -256,7 +266,7 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, int fdtdec_check_fdt(void) { /* We must have an fdt */ - if (fdt_check_header(gd->fdt_blob)) + if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) panic("No valid fdt found - please append one to U-Boot\n" "binary or define CONFIG_OF_EMBED\n"); return 0; -- cgit v0.10.2 From d17da65560f15f74f8efe321044b9cdf45e24c9b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:35 +0000 Subject: fdt: Add functions to access phandles, arrays and bools Add a function to look up a property which is a phandle in a node, and another to read a fixed-length integer array from an fdt property. Also add a function to read boolean properties, although there is no actual boolean type in U-Boot. Signed-off-by: Simon Glass Acked-by: Gerald Van Baren Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index 5469c16..a446700 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -188,3 +188,42 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, * @return compatible string for that id */ const char *fdtdec_get_compatible(enum fdt_compat_id id); + +/* Look up a phandle and follow it to its node. Then return the offset + * of that node. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return node offset if found, -ve error code on error + */ +int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name); + +/** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must have at least enough data for + * the array (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found, + * or -FDT_ERR_BADLAYOUT if not enough data + */ +int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, + u32 *array, int count); + +/** + * Look up a boolean property in a node and return it. + * + * A boolean properly is true if present in the device tree and false if not + * present, regardless of its value. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return 1 if the properly is present; 0 if it isn't present + */ +int fdtdec_get_bool(const void *blob, int node, const char *prop_name); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index bf31717..13bb470 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -271,3 +271,70 @@ int fdtdec_check_fdt(void) "binary or define CONFIG_OF_EMBED\n"); return 0; } + +int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name) +{ + const u32 *phandle; + int lookup; + + phandle = fdt_getprop(blob, node, prop_name, NULL); + if (!phandle) + return -FDT_ERR_NOTFOUND; + + lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle)); + return lookup; +} + +/** + * Look up a property in a node and check that it has a minimum length. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param min_len minimum property length in bytes + * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not + found, or -FDT_ERR_BADLAYOUT if not enough data + * @return pointer to cell, which is only valid if err == 0 + */ +static const void *get_prop_check_min_len(const void *blob, int node, + const char *prop_name, int min_len, int *err) +{ + const void *cell; + int len; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (!cell) + *err = -FDT_ERR_NOTFOUND; + else if (len < min_len) + *err = -FDT_ERR_BADLAYOUT; + else + *err = 0; + return cell; +} + +int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, + u32 *array, int count) +{ + const u32 *cell; + int i, err = 0; + + debug("%s: %s\n", __func__, prop_name); + cell = get_prop_check_min_len(blob, node, prop_name, + sizeof(u32) * count, &err); + if (!err) { + for (i = 0; i < count; i++) + array[i] = fdt32_to_cpu(cell[i]); + } + return err; +} + +int fdtdec_get_bool(const void *blob, int node, const char *prop_name) +{ + const s32 *cell; + int len; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + return cell != NULL; +} -- cgit v0.10.2 From ed3ee5cd0640979a200710b9eefa210a617b19ff Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:36 +0000 Subject: fdt: Add basic support for decoding GPIO definitions This adds some support into fdtdec for reading GPIO definitions from the fdt. We permit up to FDT_GPIO_MAX GPIOs in the system. Each GPIO is of the form: gpio-function-name = ; where: phandle is a pointer to the GPIO node gpio_num is the number of the GPIO (0 to 223) flags is a flag, as follows: bit meaning 0 0=polarity normal, 1=active low (inverted) An example is: enable-propounder-gpios = <&gpio 43 0>; which means that GPIO 43 is used to enable the propounder (setting the GPIO high), or that you can detect that the propounder is enabled by checking if the GPIO is high (the fdt does not indicate input/output). Two main functions are provided: fdtdec_decode_gpio() reads a GPIO property from an fdt node and decodes it into a structure. fdtdec_setup_gpio() sets up the GPIO by calling gpio_request for you. Both functions can cope with the property being missing, which is taken to mean that that GPIO function is not available or is not needed. [For reference, from Stephen Warren . It may be that we add this extra complexity later if needed: The correct way to parse such a GPIO property in general is: * Read the first cell. * Find the node referenced by the phandle (the controller). * Ensure property gpio-controller is present in the controller node. * Read property #gpio-cells from the controller node. * Extract #gpio-cells from the original property. * Keep processing more cells from the original property; there may be multiple GPIOs listed. According to the binding documentation in the Linux kernel, Samsung Exynos4 doesn't use this format, and while all other chips do have a flags cell, about 50% of the controllers indicate the cell is unused. ] Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index a446700..2f3842d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -61,6 +61,23 @@ enum fdt_compat_id { COMPAT_COUNT, }; +/* GPIOs are numbered from 0 */ +enum { + FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */ + + FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */ +}; + +/* This is the state of a GPIO pin as defined by the fdt */ +struct fdt_gpio_state { + const char *name; /* name of the fdt property defining this */ + uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */ + u8 flags; /* FDT_GPIO_... flags */ +}; + +/* This tells us whether a fdt_gpio_state record is valid or not */ +#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE) + /** * Find the next numbered alias for a peripheral. This is used to enumerate * all the peripherals of a certain type. @@ -227,3 +244,31 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, * @return 1 if the properly is present; 0 if it isn't present */ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); + +/** + * Decode a single GPIOs from an FDT. + * + * If the property is not found, then the GPIO structure will still be + * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to + * provide optional GPIOs. + * + * @param blob FDT blob to use + * @param node Node to look at + * @param prop_name Node property name + * @param gpio gpio elements to fill from FDT + * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing. + */ +int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, + struct fdt_gpio_state *gpio); + +/** + * Set up a GPIO pin according to the provided gpio information. At present this + * just requests the GPIO. + * + * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to + * deal with optional GPIOs. + * + * @param gpio GPIO info to use for set up + * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error + */ +int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 13bb470..de83226 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -24,6 +24,9 @@ #include #include +/* we need the generic GPIO interface here */ +#include + DECLARE_GLOBAL_DATA_PTR; /* @@ -338,3 +341,79 @@ int fdtdec_get_bool(const void *blob, int node, const char *prop_name) cell = fdt_getprop(blob, node, prop_name, &len); return cell != NULL; } + +/** + * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no + * terminating item. + * + * @param blob FDT blob to use + * @param node Node to look at + * @param prop_name Node property name + * @param gpio Array of gpio elements to fill from FDT. This will be + * untouched if either 0 or an error is returned + * @param max_count Maximum number of elements allowed + * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would + * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing. + */ +static int fdtdec_decode_gpios(const void *blob, int node, + const char *prop_name, struct fdt_gpio_state *gpio, + int max_count) +{ + const struct fdt_property *prop; + const u32 *cell; + const char *name; + int len, i; + + debug("%s: %s\n", __func__, prop_name); + assert(max_count > 0); + prop = fdt_get_property(blob, node, prop_name, &len); + if (!prop) { + debug("FDT: %s: property '%s' missing\n", __func__, prop_name); + return -FDT_ERR_NOTFOUND; + } + + /* We will use the name to tag the GPIO */ + name = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + cell = (u32 *)prop->data; + len /= sizeof(u32) * 3; /* 3 cells per GPIO record */ + if (len > max_count) { + debug("FDT: %s: too many GPIOs / cells for " + "property '%s'\n", __func__, prop_name); + return -FDT_ERR_BADLAYOUT; + } + + /* Read out the GPIO data from the cells */ + for (i = 0; i < len; i++, cell += 3) { + gpio[i].gpio = fdt32_to_cpu(cell[1]); + gpio[i].flags = fdt32_to_cpu(cell[2]); + gpio[i].name = name; + } + + return len; +} + +int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, + struct fdt_gpio_state *gpio) +{ + int err; + + debug("%s: %s\n", __func__, prop_name); + gpio->gpio = FDT_GPIO_NONE; + gpio->name = NULL; + err = fdtdec_decode_gpios(blob, node, prop_name, gpio, 1); + return err == 1 ? 0 : err; +} + +int fdtdec_setup_gpio(struct fdt_gpio_state *gpio) +{ + /* + * Return success if there is no GPIO defined. This is used for + * optional GPIOs) + */ + if (!fdt_gpio_isvalid(gpio)) + return 0; + + if (gpio_request(gpio->gpio, gpio->name)) + return -1; + return 0; +} -- cgit v0.10.2 From 92665df21d71400205feddd8ecc4f4fe2f344c11 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:37 +0000 Subject: arm: fdt: Add skeleton device tree file from kernel This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/dts/skeleton.dtsi b/arch/arm/dts/skeleton.dtsi new file mode 100644 index 0000000..b41d241 --- /dev/null +++ b/arch/arm/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; -- cgit v0.10.2 From c3474ef32db6161c2b51eefa5df2e38a6d3c2e8c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:38 +0000 Subject: tegra: fdt: Add Tegra2x device tree file from kernel This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git config.mk is updated to provide this file to boards through the built-in mechanism: /include/ ARCH_CPU_DTS Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index 2303dba..fe9ef5b 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t endif USE_PRIVATE_LIBGCC = yes + +CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi new file mode 100644 index 0000000..a9a98ea --- /dev/null +++ b/arch/arm/dts/tegra20.dtsi @@ -0,0 +1,168 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra20"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "nvidia,tegra20-gic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 70 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 124 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x200>; + interrupts = < 85 >; + }; + + i2s@70002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002800 0x200>; + interrupts = < 45 >; + dma-channel = < 2 >; + }; + + i2s@70002a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; + reg = <0x70002a00 0x200>; + interrupts = < 35 >; + dma-channel = < 1 >; + }; + + das@70000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 64 65 66 67 87 119 121 >; + #gpio-cells = <2>; + gpio-controller; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000014 0x10 /* Tri-state registers */ + 0x70000080 0x20 /* Mux registers */ + 0x700000a0 0x14 /* Pull-up/down registers */ + 0x70000868 0xa8 >; /* Pad control registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 68 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 69 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 78 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 122 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 123 >; + }; + + sdhci@c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 46 >; + }; + + sdhci@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 47 >; + }; + + sdhci@c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 51 >; + }; + + sdhci@c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 63 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 53 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + }; + +}; -- cgit v0.10.2 From 6710b5b5fd22deb85c9705d757560d7e21a95757 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:39 +0000 Subject: tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts new file mode 100644 index 0000000..dde5d03 --- /dev/null +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Seaboard"; + compatible = "nvidia,seaboard", "nvidia,tegra20"; + + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; + }; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x40000000 >; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + sdhci@c8000400 { + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + }; + + sdhci@c8000600 { + support-8bit; + }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + }; +}; -- cgit v0.10.2 From 849df712a061df4b589b95e2a9646c3458feb995 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:40 +0000 Subject: fdt: Add staging area for device tree binding documentation Add a directory to hold device tree binding files, to permit easy review of this material in U-Boot patches. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/doc/device-tree-bindings/README b/doc/device-tree-bindings/README new file mode 100644 index 0000000..2ea3439 --- /dev/null +++ b/doc/device-tree-bindings/README @@ -0,0 +1,17 @@ +Device Tree Bindings Staging Area +================================= + +This directory contains device tree bindings for U-Boot. + +These follow along with Linux kernel bindings, with a few additions. By +adding the files here, U-Boot patches can clearly show thees additions. +This makes it easier for device tree people to review these additions in +patches sent to the U-Boot mailing list. + +The intent IS to commit these files to U-Boot. Hopefully at some point +the files will be stored in another repo (shared with Linux) which is +brought in as needed. Changes here are intended to mirror changes in the +Linux Documentation/devicetree/bindings/ directory. + +sjg@chromium.org +17-Jan-12 -- cgit v0.10.2 From b257464b1c7522d04650d8e2ab52ee7c1cafa7e4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:41 +0000 Subject: fdt: Add tegra-usb bindings file from linux This file is taken from the Linux mailing list. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt new file mode 100644 index 0000000..035d63d --- /dev/null +++ b/doc/device-tree-bindings/usb/tegra-usb.txt @@ -0,0 +1,13 @@ +Tegra SOC USB controllers + +The device node for a USB controller that is part of a Tegra +SOC is as described in the document "Open Firmware Recommended +Practice : Universal Serial Bus" with the following modifications +and additions : + +Required properties : + - compatible : Should be "nvidia,tegra20-ehci" for USB controllers + used in host mode. + - phy_type : Should be one of "ulpi" or "utmi". + - nvidia,vbus-gpio : If present, specifies a gpio that needs to be + activated for the bus to be powered. -- cgit v0.10.2 From 8b7a47d73d26e562918021bf4027adcb660a1146 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 28 Feb 2012 08:07:47 +0000 Subject: tegra: fdt: Add additional USB binding This adds a property to indicate a port which can switch between host and device mode. Signed-off-by: Simon Glass Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt index 035d63d..5282d44 100644 --- a/doc/device-tree-bindings/usb/tegra-usb.txt +++ b/doc/device-tree-bindings/usb/tegra-usb.txt @@ -11,3 +11,15 @@ Required properties : - phy_type : Should be one of "ulpi" or "utmi". - nvidia,vbus-gpio : If present, specifies a gpio that needs to be activated for the bus to be powered. + +Optional properties: + - dr_mode : dual role mode. Indicates the working mode for + nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", + or "otg". Default to "host" if not defined for backward compatibility. + host means this is a host controller + peripheral means it is device controller + otg means it can operate as either ("on the go") + - nvidia,has-legacy-mode : boolean indicates whether this controller can + operate in legacy mode (as APX 2500 / 2600). In legacy mode some + registers are accessed through the APB_MISC base address instead of + the USB controller. -- cgit v0.10.2 From 1f1a02123cc1643517498e93497a67dfe8824bd7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:43 +0000 Subject: tegra: fdt: Add clock bindings This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock. This uses the RFC clock bindings from Grant Likely so may change later: https://lkml.org/lkml/2011/12/12/498 It is taken from Stephen Warren's patch here: http://patchwork.ozlabs.org/patch/141359/ Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index a9a98ea..2c46e11 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -4,6 +4,22 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + tegra_car: clock@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + intc: interrupt-controller@50041000 { compatible = "nvidia,tegra20-gic"; interrupt-controller; diff --git a/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt b/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt new file mode 100644 index 0000000..5c07fca --- /dev/null +++ b/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt @@ -0,0 +1,207 @@ +NVIDIA Tegra20 Clock And Reset Controller + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The CAR (Clock And Reset) Controller on Tegra is the HW module responsible +for muxing and gating Tegra's clocks, and setting their rates. + +Required properties : +- compatible : Should be "nvidia,tegra20-car" +- reg : Should contain CAR registers location and length +- clocks : Should contain phandle and clock specifiers for two clocks: + the 32 KHz "32k_in", and the board-specific oscillator "osc". +- #clock-cells : Should be 1. + In clock consumers, this cell represents the clock ID exposed by the CAR. + + The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + registers. These IDs often match those in the CAR's RST_DEVICES registers, + but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + this case, those clocks are assigned IDs above 95 in order to highlight + this issue. Implementations that interpret these clock IDs as bit values + within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + explicitly handle these special cases. + + The balance of the clocks controlled by the CAR are assigned IDs of 96 and + above. + + 0 cpu + 1 unassigned + 2 unassigned + 3 ac97 + 4 rtc + 5 tmr + 6 uart1 + 7 unassigned (register bit affects uart2 and vfir) + 8 gpio + 9 sdmmc2 + 10 unassigned (register bit affects spdif_in and spdif_out) + 11 i2s1 + 12 i2c1 + 13 ndflash + 14 sdmmc1 + 15 sdmmc4 + 16 twc + 17 pwm + 18 i2s2 + 19 epp + 20 unassigned (register bit affects vi and vi_sensor) + 21 2d + 22 usbd + 23 isp + 24 3d + 25 ide + 26 disp2 + 27 disp1 + 28 host1x + 29 vcp + 30 unassigned + 31 cache2 + + 32 mem + 33 ahbdma + 34 apbdma + 35 unassigned + 36 kbc + 37 stat_mon + 38 pmc + 39 fuse + 40 kfuse + 41 sbc1 + 42 snor + 43 spi1 + 44 sbc2 + 45 xio + 46 sbc3 + 47 dvc + 48 dsi + 49 unassigned (register bit affects tvo and cve) + 50 mipi + 51 hdmi + 52 csi + 53 tvdac + 54 i2c2 + 55 uart3 + 56 unassigned + 57 emc + 58 usb2 + 59 usb3 + 60 mpe + 61 vde + 62 bsea + 63 bsev + + 64 speedo + 65 uart4 + 66 uart5 + 67 i2c3 + 68 sbc4 + 69 sdmmc3 + 70 pcie + 71 owr + 72 afi + 73 csite + 74 unassigned + 75 avpucq + 76 la + 77 unassigned + 78 unassigned + 79 unassigned + 80 unassigned + 81 unassigned + 82 unassigned + 83 unassigned + 84 irama + 85 iramb + 86 iramc + 87 iramd + 88 cram2 + 89 audio_2x a/k/a audio_2x_sync_clk + 90 clk_d + 91 unassigned + 92 sus + 93 cdev1 + 94 cdev2 + 95 unassigned + + 96 uart2 + 97 vfir + 98 spdif_in + 99 spdif_out + 100 vi + 101 vi_sensor + 102 tvo + 103 cve + 104 osc + 105 clk_32k a/k/a clk_s + 106 clk_m + 107 sclk + 108 cclk + 109 hclk + 110 pclk + 111 blink + 112 pll_a + 113 pll_a_out0 + 114 pll_c + 115 pll_c_out1 + 116 pll_d + 117 pll_d_out0 + 118 pll_e + 119 pll_m + 120 pll_m_out1 + 121 pll_p + 122 pll_p_out1 + 123 pll_p_out2 + 124 pll_p_out3 + 125 pll_p_out4 + 126 pll_s + 127 pll_u + 128 pll_x + 129 cop a/k/a avp + 130 audio a/k/a audio_sync_clk + +Example SoC include file: + +/ { + tegra_car: clock@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + usb@c5004000 { + clocks = <&tegra_car 58>; /* usb2 */ + }; +}; + +Example board file: + +/ { + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + }; + + i2c@7000d000 { + pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + + clk_32k: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; + + &tegra_car { + clocks = <&clk_32k> <&osc>; + }; +}; -- cgit v0.10.2 From cd474cbae676d63f3bfe6c7f080e61262c2d74a7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 28 Feb 2012 08:07:49 +0000 Subject: tegra: fdt: Add clock bindings for Tegra2 Seaboard Add the definition of the oscillator clock frequency and the 32KHz clock. The latter is provided by a PMIC on I2C which we don't actually use at present, but we expect this definition to be used in the kernel and want to keep our .dts the same. Signed-off-by: Simon Glass Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts index dde5d03..452679f 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -16,6 +16,33 @@ reg = < 0x00000000 0x40000000 >; }; + /* This is not used in U-Boot, but is expected to be in kernel .dts */ + i2c@7000d000 { + pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + + clk_32k: clock { + compatible = "fixed-clock"; + /* + * leave out for now due to CPP: + * #clock-cells = <0>; + */ + clock-frequency = <32768>; + }; + }; + }; + + clocks { + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; -- cgit v0.10.2 From 1c1cce99d43e8a39b7cbd8d1440b7a458f7abd3a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:45 +0000 Subject: tegra: usb: fdt: Add additional device tree definitions for USB ports This adds clock references to the USB part of the device tree for U-Boot, and marks USB1 as supporting legacy mode (which we disable in the driver). The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 2c46e11..d6bc9f1 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -165,6 +165,8 @@ reg = <0xc5000000 0x4000>; interrupts = < 52 >; phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + nvidia,has-legacy-mode; }; usb@c5004000 { @@ -172,6 +174,7 @@ reg = <0xc5004000 0x4000>; interrupts = < 53 >; phy_type = "ulpi"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ }; usb@c5008000 { @@ -179,6 +182,7 @@ reg = <0xc5008000 0x4000>; interrupts = < 129 >; phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ }; }; -- cgit v0.10.2 From 1920172ec80b709d017608b6a1d40b766e84c731 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:46 +0000 Subject: tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard We set up two USB ports, one of which can be host or device. For some reason the kernel version does enable both ports. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts index 452679f..ad8169a 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -11,6 +11,12 @@ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; }; + aliases { + /* This defines the order of our USB ports */ + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + }; + memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; @@ -59,5 +65,10 @@ usb@c5000000 { nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + dr_mode = "otg"; + }; + + usb@c5004000 { + status = "disabled"; }; }; -- cgit v0.10.2 From 9ab4ce223c1d991e92e15c9aa0f522d61072155d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:47 +0000 Subject: usb: Add support for txfifo threshold CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset. Signed-off-by: Simon Glass Acked-by: Remy Bohmer Signed-off-by: Tom Warren diff --git a/README b/README index 5452813..d4799e2 100644 --- a/README +++ b/README @@ -1125,6 +1125,9 @@ The following options need to be configured: May be defined to allow interrupt polling instead of using asynchronous interrupts + CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the + txfilltuning field in the EHCI controller on reset. + - USB Device: Define the below if you wish to use the USB console. Once firmware is rebuilt from a serial console issue the diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index ef5afc2..b6422d7 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -255,6 +255,13 @@ static int ehci_reset(void) #endif ehci_writel(reg_ptr, tmp); } + +#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH + cmd = ehci_readl(&hcor->or_txfilltuning); + cmd &= ~TXFIFO_THRESH(0x3f); + cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH); + ehci_writel(&hcor->or_txfilltuning, cmd); +#endif out: return ret; } diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 3d0ad0c..cc00ce4 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -80,7 +80,11 @@ struct ehci_hcor { uint32_t or_ctrldssegment; uint32_t or_periodiclistbase; uint32_t or_asynclistaddr; - uint32_t _reserved_[9]; + uint32_t _reserved_0_; + uint32_t or_burstsize; + uint32_t or_txfilltuning; +#define TXFIFO_THRESH(p) ((p & 0x3f) << 16) + uint32_t _reserved_1_[6]; uint32_t or_configflag; #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; -- cgit v0.10.2 From ed2974493e838399eacd4bf88f38b215955688a8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 6 Mar 2012 17:10:27 +0000 Subject: tegra: fdt: Add function to return peripheral/clock ID A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself). Signed-off-by: Simon Glass Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 11d2346..a94cf81 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -28,6 +28,7 @@ #include #include #include +#include /* * This is our record of the current clock rate of each clock. We don't @@ -918,6 +919,63 @@ void clock_ll_start_uart(enum periph_id periph_id) reset_set_enable(periph_id, 0); } +#ifdef CONFIG_OF_CONTROL +/* + * Convert a device tree clock ID to our peripheral ID. They are mostly + * the same but we are very cautious so we check that a valid clock ID is + * provided. + * + * @param clk_id Clock ID according to tegra2 device tree binding + * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + */ +static enum periph_id clk_id_to_periph_id(int clk_id) +{ + if (clk_id > 95) + return PERIPH_ID_NONE; + + switch (clk_id) { + case 1: + case 2: + case 7: + case 10: + case 20: + case 30: + case 35: + case 49: + case 56: + case 74: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 91: + case 95: + return PERIPH_ID_NONE; + default: + return clk_id; + } +} + +int clock_decode_periph_id(const void *blob, int node) +{ + enum periph_id id; + u32 cell[2]; + int err; + + err = fdtdec_get_int_array(blob, node, "clocks", cell, + ARRAY_SIZE(cell)); + if (err) + return -1; + id = clk_id_to_periph_id(cell[1]); + assert(clock_periph_id_isvalid(id)); + return id; +} +#endif /* CONFIG_OF_CONTROL */ + int clock_verify(void) { struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 080ef18..6b12c76 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -177,6 +177,7 @@ enum periph_id { PERIPH_ID_CRAM2, PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, }; /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ @@ -355,6 +356,18 @@ unsigned clock_get_rate(enum clock_id clkid); */ void clock_ll_start_uart(enum periph_id periph_id); +/** + * Decode a peripheral ID from a device tree node. + * + * This works by looking up the peripheral's 'clocks' node and reading out + * the second cell, which is the clock number / peripheral ID. + * + * @param blob FDT blob to use + * @param node Node to look at + * @return peripheral ID, or PERIPH_ID_NONE if none + */ +enum periph_id clock_decode_periph_id(const void *blob, int node); + /* * Checks that clocks are valid and prints a warning if not * -- cgit v0.10.2 From 87f938c9f7372f587a43fe7babcb171ee0a0672f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:49 +0000 Subject: tegra: usb: Add support for Tegra USB peripheral This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up. Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment: aliases { /* This defines the order of our USB ports */ usb0 = "/usb@0xc5008000"; usb1 = "/usb@0xc5000000"; }; drivers/usb/host files ONLY: Acked-by: Remy Bohmer Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f668a81..e9ac6c9 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c new file mode 100644 index 0000000..c80de7f --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + USB_PORTS_MAX = 4, /* Maximum ports we allow */ +}; + +/* Parameters we need for USB */ +enum { + PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ + PARAM_DIVM, /* PLL INPUT DIVIDER */ + PARAM_DIVP, /* POST DIVIDER (2^N) */ + PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ + PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ + PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ + PARAM_STABLE_COUNT, /* PLL-U STABLE count */ + PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ + PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ + PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ + PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ + + PARAM_COUNT +}; + +/* Possible port types (dual role mode) */ +enum dr_mode { + DR_MODE_NONE = 0, + DR_MODE_HOST, /* supports host operation */ + DR_MODE_DEVICE, /* supports device operation */ + DR_MODE_OTG, /* supports both */ +}; + +/* Information about a USB port */ +struct fdt_usb { + struct usb_ctlr *reg; /* address of registers in physical memory */ + unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ + unsigned enabled:1; /* 1 to enable, 0 to disable */ + unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ + enum dr_mode dr_mode; /* dual role mode */ + enum periph_id periph_id;/* peripheral id */ + struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ +}; + +static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ +static unsigned port_count; /* Number of available ports */ +static int port_current; /* Current port (-1 = none) */ + +/* + * This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * ---------------------------------------------------------------------- + * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) + * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) + * Filter frequency (MHz) 1 4.8 6 2 + * CPCON 1100b 0011b 1100b 1100b + * LFCON0 0 0 0 0 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * --------------------------------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) + * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) + * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) + * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * ms = *1000 / (1/19.2MHz) / 4 + * + * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + */ +static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, + { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } +}; + +/* UTMIP Idle Wait Delay */ +static const u8 utmip_idle_wait_delay = 17; + +/* UTMIP Elastic limit */ +static const u8 utmip_elastic_limit = 16; + +/* UTMIP High Speed Sync Start Delay */ +static const u8 utmip_hs_sync_start_delay = 9; + +/* Put the port into host mode (this only works for OTG ports) */ +static void set_host_mode(struct fdt_usb *config) +{ + if (config->dr_mode == DR_MODE_OTG) { + /* Check whether remote host from USB1 is driving VBus */ + if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, 1); + debug("set_host_mode: GPIO %d high\n", + config->vbus_gpio.gpio); + } + } +} + +void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +{ + /* Reset the USB controller with 2us delay */ + reset_periph(config->periph_id, 2); + + /* + * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under + * base address + */ + if (config->has_legacy_mode) + setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); + + /* Put UTMIP1/3 in reset */ + setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Enable the UTMIP PHY */ + if (config->utmi) + setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); + + /* + * TODO: where do we take the USB1 out of reset? The old code would + * take USB3 out of reset, but not USB1. This code doesn't do either. + */ +} + +/* set up the USB controller with the parameters provided */ +static int init_usb_controller(struct fdt_usb *config, + struct usb_ctlr *usbctlr, const u32 timing[]) +{ + u32 val; + int loop_count; + + clock_enable(config->periph_id); + + /* Reset the usb controller */ + usbf_reset_controller(config, usbctlr); + + /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ + clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Follow the crystal clock disable by >100ns delay */ + udelay(1); + + /* + * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP + * mux must be switched to actually use a_sess_vld threshold. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, + VBUS_SENSE_CTL_MASK, + VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); + } + + /* + * PLL Delay CONFIGURATION settings. The following parameters control + * the bring up of the plls. + */ + val = readl(&usbctlr->utmip_misc_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &usbctlr->utmip_misc_cfg1); + + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&usbctlr->utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &usbctlr->utmip_pll_cfg1); + + /* Setting the tracking length time */ + clrsetbits_le32(&usbctlr->utmip_bias_cfg1, + UTMIP_BIAS_PDTRK_COUNT_MASK, + timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); + + /* Program debounce time for VBUS to become valid */ + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, + UTMIP_DEBOUNCE_CFG0_MASK, + timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); + + setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); + + /* Disable battery charge enabling bit */ + setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); + + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + /* + * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT + * Setting these fields, together with default values of the + * other fields, results in programming the registers below as + * follows: + * UTMIP_HSRX_CFG0 = 0x9168c000 + * UTMIP_HSRX_CFG1 = 0x13 + */ + + /* Set PLL enable delay count and Crystal frequency count */ + val = readl(&usbctlr->utmip_hsrx_cfg0); + clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, + utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, + utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + writel(val, &usbctlr->utmip_hsrx_cfg0); + + /* Configure the UTMIP_HS_SYNC_START_DLY */ + clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, + UTMIP_HS_SYNC_START_DLY_MASK, + utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + + /* Preceed the crystal clock disable by >100ns delay. */ + udelay(1); + + /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ + setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Finished the per-controller init. */ + + /* De-assert UTMIP_RESET to bring out of reset. */ + clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Wait for the phy clock to become valid in 100 ms */ + for (loop_count = 100000; loop_count != 0; loop_count--) { + if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) + break; + udelay(1); + } + if (loop_count == 100000) + return -1; + + return 0; +} + +static void power_up_port(struct usb_ctlr *usbctlr) +{ + /* Deassert power down state */ + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | + UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); + clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | + UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); +} + +static void config_clock(const u32 timing[]) +{ + clock_start_pll(CLOCK_ID_USB, + timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], + timing[PARAM_CPCON], timing[PARAM_LFCON]); +} + +/** + * Add a new USB port to the list of available ports. + * + * @param config USB port configuration + * @return 0 if ok, -1 if error (too many ports) + */ +static int add_port(struct fdt_usb *config, const u32 timing[]) +{ + struct usb_ctlr *usbctlr = config->reg; + + if (port_count == USB_PORTS_MAX) { + debug("tegrausb: Cannot register more than %d ports\n", + USB_PORTS_MAX); + return -1; + } + if (init_usb_controller(config, usbctlr, timing)) { + debug("tegrausb: Cannot init port\n"); + return -1; + } + if (config->utmi) { + /* Disable ICUSB FS/LS transceiver */ + clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); + + /* Select UTMI parallel interface */ + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + power_up_port(usbctlr); + } + port[port_count++] = *config; + + return 0; +} + +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) +{ + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) + return -1; + tegrausb_stop_port(); + set_host_mode(&port[portnum]); + + usbctlr = port[portnum].reg; + *hccr = (u32)&usbctlr->cap_length; + *hcor = (u32)&usbctlr->usb_cmd; + port_current = portnum; + return 0; +} + +int tegrausb_stop_port(void) +{ + struct usb_ctlr *usbctlr; + + if (port_current == -1) + return -1; + + usbctlr = port[port_current].reg; + + /* Stop controller */ + writel(0, &usbctlr->usb_cmd); + udelay(1000); + + /* Initiate controller reset */ + writel(2, &usbctlr->usb_cmd); + udelay(1000); + port_current = -1; + return 0; +} + +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, + struct fdt_usb *config) +{ + const char *phy, *mode; + + config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode) { + if (0 == strcmp(mode, "host")) + config->dr_mode = DR_MODE_HOST; + else if (0 == strcmp(mode, "peripheral")) + config->dr_mode = DR_MODE_DEVICE; + else if (0 == strcmp(mode, "otg")) + config->dr_mode = DR_MODE_OTG; + else { + debug("%s: Cannot decode dr_mode '%s'\n", __func__, + mode); + return -FDT_ERR_NOTFOUND; + } + } else { + config->dr_mode = DR_MODE_HOST; + } + + phy = fdt_getprop(blob, node, "phy_type", NULL); + config->utmi = phy && 0 == strcmp("utmi", phy); + config->enabled = fdtdec_get_is_enabled(blob, node); + config->has_legacy_mode = fdtdec_get_bool(blob, node, + "nvidia,has-legacy-mode"); + config->periph_id = clock_decode_periph_id(blob, node); + if (config->periph_id == PERIPH_ID_NONE) { + debug("%s: Missing/invalid peripheral ID\n", __func__); + return -FDT_ERR_NOTFOUND; + } + fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); + debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, " + "dr_mode=%d\n", config->enabled, config->has_legacy_mode, + config->utmi, config->periph_id, config->vbus_gpio.gpio, + config->dr_mode); + + return 0; +} + +int board_usb_init(const void *blob) +{ + struct fdt_usb config; + unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC); + enum clock_osc_freq freq; + int node_list[USB_PORTS_MAX]; + int node, count, i; + + /* Set up the USB clocks correctly based on our oscillator frequency */ + freq = clock_get_osc_freq(); + config_clock(usb_pll[freq]); + + /* count may return <0 on error */ + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + for (i = 0; i < count; i++) { + debug("USB %d: ", i); + node = node_list[i]; + if (!node) + continue; + if (fdt_decode_usb(blob, node, osc_freq, &config)) { + debug("Cannot decode USB node %s\n", + fdt_get_name(blob, node, NULL)); + return -1; + } + + if (add_port(&config, usb_pll[freq])) + return -1; + set_host_mode(&config); + } + port_current = -1; + + return 0; +} diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 8941443..baae2eb 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -41,6 +41,8 @@ #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) #define NV_PA_PMC_BASE 0x7000E400 #define NV_PA_CSITE_BASE 0x70040000 +#define TEGRA_USB1_BASE 0xC5000000 +#define TEGRA_USB3_BASE 0xC5008000 #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h new file mode 100644 index 0000000..638033b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/usb.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[6]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* USBx_UTMIP_PLL_CFG1_0 */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULP 2 +#define PTS_ICUSB_SER 3 + +#define STS (1 << 29) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + + +/* Change the USB host port into host mode */ +void usb_set_host_mode(void); + +/* Setup USB on the board */ +int board_usb_init(const void *blob); + +/** + * Start up the given port number (ports are numbered from 0 on each board). + * This returns values for the appropriate hccr and hcor addresses to use for + * USB EHCI operations. + * + * @param portnum port number to start + * @param hccr returns start address of EHCI HCCR registers + * @param hcor returns start address of EHCI HCOR registers + * @return 0 if ok, -1 on error (generally invalid port number) + */ +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); + +/** + * Stop the current port + * + * @return 0 if ok, -1 if no port was active + */ +int tegrausb_stop_port(void); + +#endif /* _TEGRA_USB_H_ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 53ad70a..0d4657e 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o COBJS := $(COBJS-y) diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c new file mode 100644 index 0000000..a7e105b --- /dev/null +++ b/drivers/usb/host/ehci-tegra.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include "ehci.h" +#include "ehci-core.h" + +#include +#include + + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + u32 our_hccr, our_hcor; + + /* + * Select the first port, as we don't have a way of selecting others + * yet + */ + if (tegrausb_start_port(0, &our_hccr, &our_hcor)) + return -1; + + hccr = (struct ehci_hccr *)our_hccr; + hcor = (struct ehci_hcor *)our_hcor; + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + tegrausb_stop_port(); + return 0; +} diff --git a/include/fdtdec.h b/include/fdtdec.h index 2f3842d..bde9873 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { */ enum fdt_compat_id { COMPAT_UNKNOWN, + COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index de83226..4ca442a 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #define COMPAT(id, name) name static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, ""), + COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v0.10.2 From 9a263e55dc00f3277d8e82c906ee5c7a1dca0ba5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 28 Mar 2012 10:08:24 +0000 Subject: fdt: Avoid early panic() when there is no FDT present CONFIG_OF_CONTROL requires a valid device tree. However, we cannot call panic() before the console is set up since the message does not appear, and we get a silent failure. Remove the panic from fdtdec_check_fdt() and provide a new function to prepare the fdt for use. This will be called after the console is ready. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index bde9873..6249f22 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,8 +155,21 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, int fdtdec_get_is_enabled(const void *blob, int node); /** - * Checks whether we have a valid fdt available to control U-Boot, and panic - * if not. + * Make sure we have a valid fdt available to control U-Boot. + * + * If not, a message is printed to the console if the console is ready. + * + * @return 0 if all ok, -1 if not + */ +int fdtdec_prepare_fdt(void); + +/** + * Checks that we have a valid fdt available to control U-Boot. + + * However, if not then for the moment nothing is done, since this function + * is called too early to panic(). + * + * @returns 0 */ int fdtdec_check_fdt(void); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4ca442a..5239e79 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -262,17 +262,31 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, return num_found; } +int fdtdec_check_fdt(void) +{ + /* + * We must have an FDT, but we cannot panic() yet since the console + * is not ready. So for now, just assert(). Boards which need an early + * FDT (prior to console ready) will need to make their own + * arrangements and do their own checks. + */ + assert(!fdtdec_prepare_fdt()); + return 0; +} + /* * This function is a little odd in that it accesses global data. At some * point if the architecture board.c files merge this will make more sense. * Even now, it is common code. */ -int fdtdec_check_fdt(void) +int fdtdec_prepare_fdt(void) { - /* We must have an fdt */ - if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) - panic("No valid fdt found - please append one to U-Boot\n" - "binary or define CONFIG_OF_EMBED\n"); + if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) { + printf("No valid FDT found - please append one to U-Boot " + "binary, use u-boot-dtb.bin or define " + "CONFIG_OF_EMBED\n"); + return -1; + } return 0; } -- cgit v0.10.2 From 2866903b3e32909085ffe486baca1bcb44e2caeb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 28 Mar 2012 10:08:25 +0000 Subject: arm: Check for valid FDT after console is up When using CONFIG_OF_CONTROL, add a check that we have a valid FDT and panic() if not. This must be done after the console is ready. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index b9b35de..5270c11 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -293,6 +293,14 @@ void board_init_f(ulong bootflag) } } +#ifdef CONFIG_OF_CONTROL + /* For now, put this check after the console is ready */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } +#endif + debug("monitor len: %08lX\n", gd->mon_len); /* * Ram is setup, size stored in gd !! -- cgit v0.10.2 From f10393e501ede54d2d19a2ad1d533dbe7c926f26 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:50 +0000 Subject: tegra: usb: Add USB support to nvidia boards This adds basic USB support for port 0. The other port is not supported yet. Tegra2 (SeaBoard) # usb start (Re)start USB... USB: Register 10011 NbrPorts 1 USB EHCI 1.00 scanning bus for devices... 5 USB Device(s) found scanning bus for storage devices... 1 Storage Device(s) found Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A) 2932976 bytes read Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index e8253a0..72d8630 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,12 @@ int timer_init(void) return 0; } +void __pin_mux_usb(void) +{ +} + +void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); + /* * Routine: board_init * Description: Early hardware init. @@ -69,6 +76,11 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); +#ifdef CONFIG_USB_EHCI_TEGRA + pin_mux_usb(); + board_usb_init(gd->fdt_blob); +#endif + return 0; } diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index a638af2..09fb158 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -27,4 +27,10 @@ void gpio_config_uart(void); void gpio_early_init_uart(void); +/* + * Set up any pin muxing needed for USB (for now, since fdt doesn't support + * it). Boards can overwrite the default fucction which does nothing. + */ +void pin_mux_usb(void); + #endif /* BOARD_H */ diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 9ab6825..94efb1e 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -90,3 +90,9 @@ int board_mmc_init(bd_t *bd) return 0; } #endif + +void pin_mux_usb(void) +{ + /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ + pinmux_tristate_disable(PINGRP_SLXK); +} -- cgit v0.10.2 From 0291091c9e4dffce1f278d6b87ac123f389595df Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:51 +0000 Subject: tegra: usb: Add common USB defines for tegra2 boards All Tegra2 boards should include tegra2-common. This adds the required USB config to that file. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index e6f385f..266d0e5 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -84,6 +84,16 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} +/* + * This parameter affects a TXFILLTUNING field that controls how much data is + * sent to the latency fifo before it is sent to the wire. Without this + * parameter, the default (2) causes occasional Data Buffer Errors in OUT + * packets depending on the buffer address and size. + */ +#define CONFIG_USB_EHCI_TXFIFO_THRESH 10 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_EHCI_DCACHE + /* include default commands */ #include -- cgit v0.10.2 From db44ebdb5cf7a82ce19d639cad27d9eac13c3a2f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:52 +0000 Subject: tegra: usb: Enable USB on Seaboard Seaboard has a top port which is USB host or device, and a side port which is host only. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 261f952..b6d9f7a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -72,4 +72,11 @@ #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE #define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + #endif /* __CONFIG_H */ -- cgit v0.10.2 From d9fdfe0aa598978054f108ba42ca928aceb8c090 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:53 +0000 Subject: tegra: fdt: Enable FDT support for Seaboard This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index b6d9f7a..1dc775a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,6 +27,11 @@ #include #include "tegra2-common.h" +/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (SeaBoard) # " -- cgit v0.10.2 From 66d6a91dc2aa6554c0ad0cdf8b13b18abead8155 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 6 Mar 2012 17:10:33 +0000 Subject: tegra: fdt: Enable FDT support for Ventana This switches Ventana over to use FDT for run-time config instead of CONFIG options. At present Ventana does not have its own device tree file - it just uses the Seaboard one. Signed-off-by: Tom Warren Signed-off-by: Simon Glass Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/ventana.h b/include/configs/ventana.h index acc9b43..3e55fe5 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -27,6 +27,11 @@ #include #include "tegra2-common.h" +/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (Ventana) # " -- cgit v0.10.2 From f4589a7d6f477876c18eb8087e3ee7fa0a8655ca Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:52 +0000 Subject: tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE Change this name to fit with the current convention in the Tegra header file. Signed-off-by: Simon Glass Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index f0450f4..b749821 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; /* Remove the clamps on the CPU I/O signals */ @@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void) static void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; @@ -157,7 +157,7 @@ static void powerup_cpu(void) static void enable_cpu_power_rail(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_cntrl); @@ -277,7 +277,7 @@ void enable_scu(void) void init_pmc_scratch(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; int i; /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 349d50e..a797e6f 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -47,7 +47,7 @@ enum { unsigned int query_sdram_size(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_scratch20); diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index baae2eb..ca1881e 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -39,7 +39,7 @@ #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_PMC_BASE 0x7000E400 +#define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) #define NV_PA_CSITE_BASE 0x70040000 #define TEGRA_USB1_BASE 0xC5000000 #define TEGRA_USB3_BASE 0xC5008000 @@ -55,7 +55,7 @@ struct timerus { unsigned int cntr_1us; }; #else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL NV_PA_PMC_BASE +#define PRM_RSTCTRL TEGRA2_PMC_BASE #endif #endif /* TEGRA2_H */ -- cgit v0.10.2 From c67822704b73dcfb86debf4c25151e43309af844 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:53 +0000 Subject: fdt: Add function to allow aliases to refer to multiple nodes Some devices can deal with multiple compatible properties. The devices need to know which nodes to bind to which features. For example an I2C driver which supports two different controller types will want to know which type it is dealing with in each case. The new fdtdec_add_aliases_for_id() function deals with this by allowing the driver to search for additional compatible nodes for a different ID. It can then detect the new ones and perform appropriate processing. Another option considered was to return a tuple (node offset, compat id) and have the function be passed a list of compatible IDs. This is more overhead for the common case though. We may add such a function later if more drivers in U-Boot require it. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index 6249f22..1e198f8 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -213,6 +213,29 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount); /* + * This function is similar to fdtdec_find_aliases_for_id() except that it + * adds to the node_list that is passed in. Any 0 elements are considered + * available for allocation - others are considered already used and are + * skipped. + * + * You can use this by calling fdtdec_find_aliases_for_id() with an + * uninitialised array, then setting the elements that are returned to -1, + * say, then calling this function, perhaps with a different compat id. + * Any elements you get back that are >0 are new nodes added by the call + * to this function. + * + * Note that if you have some nodes with aliases and some without, you are + * sailing close to the wind. The call to fdtdec_find_aliases_for_id() with + * one compat_id may fill in positions for which you have aliases defined + * for another compat_id. When you later call *this* function with the second + * compat_id, the alias positions may already be used. A debug warning may + * be generated in this case, but it is safest to define aliases for all + * nodes when you care about the ordering. + */ +int fdtdec_add_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount); + +/* * Get the name for a compatible ID * * @param id Compatible ID to look for diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5239e79..2149bd7 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -153,10 +153,18 @@ int fdtdec_next_alias(const void *blob, const char *name, return node; } -/* TODO: Can we tighten this code up a little? */ int fdtdec_find_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount) { + memset(node_list, '\0', sizeof(*node_list) * maxcount); + + return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount); +} + +/* TODO: Can we tighten this code up a little? */ +int fdtdec_add_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount) +{ int name_len = strlen(name); int nodes[maxcount]; int num_found = 0; @@ -185,8 +193,6 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, __func__, name); /* Now find all the aliases */ - memset(node_list, '\0', sizeof(*node_list) * maxcount); - for (offset = fdt_first_property_offset(blob, alias_node); offset > 0; offset = fdt_next_property_offset(blob, offset)) { @@ -233,11 +239,19 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, * it as done. */ if (fdtdec_get_is_enabled(blob, node)) { + if (node_list[number]) { + debug("%s: warning: alias '%s' requires that " + "a node be placed in the list in a " + "position which is already filled by " + "node '%s'\n", __func__, path, + fdt_get_name(blob, node, NULL)); + continue; + } node_list[number] = node; if (number >= num_found) num_found = number + 1; } - nodes[j] = 0; + nodes[found] = 0; } /* Add any nodes not mentioned by an alias */ -- cgit v0.10.2 From 2e33559f3d4f111f969a7e0da29a264f41bae86a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:54 +0000 Subject: tegra: Enhance clock support to handle 16-bit clock divisors I2C ports have a 16-bit clock divisor. Add code to handle this special case so that I2C speeds below 150KHz are supported. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index a94cf81..39376ab 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -68,6 +68,7 @@ enum clock_type_id { CLOCK_TYPE_MCPT, CLOCK_TYPE_PCM, CLOCK_TYPE_PCMT, + CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */ CLOCK_TYPE_PCXTS, CLOCK_TYPE_PDCT, @@ -99,6 +100,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = { { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) }, { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) }, { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, + { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) }, { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) }, { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) }, }; @@ -212,8 +214,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { /* 0x08 */ TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), + TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16), TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT), TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT), @@ -247,7 +249,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT), TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), /* 0x28 */ @@ -257,7 +259,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), /* 0x30 */ @@ -519,14 +521,16 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source) * Given the parent's rate and the required rate for the children, this works * out the peripheral clock divider to use, in 7.1 binary format. * + * @param divider_bits number of divider bits (8 or 16) * @param parent_rate clock rate of parent clock in Hz * @param rate required clock rate for this clock * @return divider which should be used */ -static int clk_div7_1_get_divider(unsigned long parent_rate, - unsigned long rate) +static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, + unsigned long rate) { u64 divider = parent_rate * 2; + unsigned max_divider = 1 << divider_bits; divider += rate - 1; do_div(divider, rate); @@ -534,7 +538,7 @@ static int clk_div7_1_get_divider(unsigned long parent_rate, if ((s64)divider - 2 < 0) return 0; - if ((s64)divider - 2 > 255) + if ((s64)divider - 2 >= max_divider) return -1; return divider - 2; @@ -572,6 +576,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * required child clock rate. This function assumes that a second-stage * divisor is available which can divide by powers of 2 from 1 to 256. * + * @param divider_bits number of divider bits (8 or 16) * @param parent_rate clock rate of parent clock in Hz * @param rate required clock rate for this clock * @param extra_div value for the second-stage divisor (not set if this @@ -579,8 +584,8 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * @return divider which should be used, or -1 if nothing is valid * */ -static int find_best_divider(unsigned long parent_rate, unsigned long rate, - int *extra_div) +static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, + unsigned long rate, int *extra_div) { int shift; int best_divider = -1; @@ -589,7 +594,8 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate, /* try dividers from 1 to 256 and find closest match */ for (shift = 0; shift <= 8 && best_error > 0; shift++) { unsigned divided_parent = parent_rate >> shift; - int divider = clk_div7_1_get_divider(divided_parent, rate); + int divider = clk_get_divider(divider_bits, divided_parent, + rate); unsigned effective_rate = get_rate_from_divider(divided_parent, divider); int error = rate - effective_rate; @@ -615,10 +621,11 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate, * @param periph_id peripheral to start * @param source PLL id of required parent clock * @param mux_bits Set to number of bits in mux register: 2 or 4 + * @param divider_bits Set to number of divider bits (8 or 16) * @return mux value (0-4, or -1 if not found) */ static int get_periph_clock_source(enum periph_id periph_id, - enum clock_id parent, int *mux_bits) + enum clock_id parent, int *mux_bits, int *divider_bits) { enum clock_type_id type; enum periphc_internal_id internal_id; @@ -632,11 +639,18 @@ static int get_periph_clock_source(enum periph_id periph_id, type = clock_periph_type[internal_id]; assert(clock_type_id_isvalid(type)); - /* Special case here for the clock with a 4-bit source mux */ + /* + * Special cases here for the clock with a 4-bit source mux and I2C + * with its 16-bit divisor + */ if (type == CLOCK_TYPE_PCXTS) *mux_bits = 4; else *mux_bits = 2; + if (type == CLOCK_TYPE_PCMT16) + *divider_bits = 16; + else + *divider_bits = 8; for (mux = 0; mux < CLOCK_MAX_MUX; mux++) if (clock_source[type][mux] == parent) @@ -662,24 +676,22 @@ static int get_periph_clock_source(enum periph_id periph_id, * Adjust peripheral PLL to use the given divider and source. * * @param periph_id peripheral to adjust - * @param parent Required parent clock (for source mux) - * @param divider Required divider in 7.1 format + * @param source Source number (0-3 or 0-7) + * @param mux_bits Number of mux bits (2 or 4) + * @param divider Required divider in 7.1 or 15.1 format * @return 0 if ok, -1 on error (requesting a parent clock which is not valid * for this peripheral) */ -static int adjust_periph_pll(enum periph_id periph_id, - enum clock_id parent, unsigned divider) +static int adjust_periph_pll(enum periph_id periph_id, int source, + int mux_bits, unsigned divider) { u32 *reg = get_periph_source_reg(periph_id); - unsigned source; - int mux_bits; clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK, divider << OUT_CLK_DIVISOR_SHIFT); udelay(1); /* work out the source clock and set it */ - source = get_periph_clock_source(periph_id, parent, &mux_bits); if (source < 0) return -1; if (mux_bits == 4) { @@ -697,14 +709,21 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, enum clock_id parent, unsigned rate, int *extra_div) { unsigned effective_rate; + int mux_bits, divider_bits, source; int divider; + /* work out the source clock and set it */ + source = get_periph_clock_source(periph_id, parent, &mux_bits, + ÷r_bits); + if (extra_div) - divider = find_best_divider(pll_rate[parent], rate, extra_div); + divider = find_best_divider(divider_bits, pll_rate[parent], + rate, extra_div); else - divider = clk_div7_1_get_divider(pll_rate[parent], rate); + divider = clk_get_divider(divider_bits, pll_rate[parent], + rate); assert(divider >= 0); - if (adjust_periph_pll(periph_id, parent, divider)) + if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U; debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, get_periph_source_reg(periph_id), diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index 0b6e004..415e420 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -125,9 +125,15 @@ struct clk_rst_ctlr { #define OSC_FREQ_SHIFT 30 #define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) -/* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 */ +/* + * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits + * but can be 16. We could use knowledge we have to restrict the mask in + * the 8-bit cases (the divider_bits value returned by + * get_periph_clock_source()) but it does not seem worth it since the code + * already checks the ranges of values it is writing, in clk_get_divider(). + */ #define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (255 << OUT_CLK_DIVISOR_SHIFT) +#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) #define OUT_CLK_SOURCE_SHIFT 30 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) -- cgit v0.10.2 From cb445fb4ccd5f1b3e0bf416ca0bafd90a5b2a2b0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:57 +0000 Subject: tegra: i2c: Initialise I2C on Nvidia boards This enables I2C on all Nvidia boards including Seaboard and Harmony. Signed-off-by: Simon Glass Acked-by: Heiko Schocher Signed-off-by: Tom Warren diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 72d8630..85dd359 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -75,6 +76,12 @@ int board_init(void) #endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); +#ifdef CONFIG_TEGRA_I2C +#ifndef CONFIG_SYS_I2C_INIT_BOARD +#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards" +#endif + i2c_init_board(); +#endif #ifdef CONFIG_USB_EHCI_TEGRA pin_mux_usb(); -- cgit v0.10.2 From c360033ffb3b15d64405c9a3aa5216fbf188ff0a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:59 +0000 Subject: tegra: i2c: Select number of controllers for Tegra2 boards The Tegra 2x SOC has four ports, so define TEGRA_I2C_NUM_CONTROLLERS in the shared config file. Signed-off-by: Simon Glass Acked-by: Heiko Schocher Signed-off-by: Tom Warren diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 266d0e5..837f859 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -94,6 +94,9 @@ #define CONFIG_EHCI_IS_TDI #define CONFIG_EHCI_DCACHE +/* Total I2C ports on Tegra2 */ +#define TEGRA_I2C_NUM_CONTROLLERS 4 + /* include default commands */ #include -- cgit v0.10.2 From 905fe99b9f7f63f33cb4e669708d29f83ba9676f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:14:00 +0000 Subject: tegra: i2c: Enable I2C on Seaboard This enables I2C on Seaboard. Signed-off-by: Simon Glass Acked-by: Heiko Schocher Signed-off-by: Tom Warren diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 1dc775a..ae075e7 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -59,6 +59,14 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -- cgit v0.10.2 From 3682cc3d2c3af73dd8e343dd41c5b860a658ac46 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 29 Feb 2012 07:31:27 +0000 Subject: tegra: i2c: Select I2C ordering for Seaboard Select the port ordering for I2C on Seaboard. Signed-off-by: Simon Glass Signed-off-by: Tom Warren diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts index ad8169a..6ba3ec4 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -15,6 +15,11 @@ /* This defines the order of our USB ports */ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; + + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; }; memory { @@ -24,6 +29,7 @@ /* This is not used in U-Boot, but is expected to be in kernel .dts */ i2c@7000d000 { + clock-frequency = <100000>; pmic@34 { compatible = "ti,tps6586x"; reg = <0x34>; @@ -71,4 +77,16 @@ usb@c5004000 { status = "disabled"; }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; }; -- cgit v0.10.2 From 34fa833aeeea498033f2c68b33ed8d57bf951e22 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 6 Mar 2012 19:00:22 +0000 Subject: tegra: fdt: i2c: Add extra I2C bindings for U-Boot Add U-Boot's peripheral clock information to the Tegra20 device tree file. Signed-off-by: Simon Glass Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index d6bc9f1..d5ca02c 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -34,6 +34,8 @@ compatible = "nvidia,tegra20-i2c"; reg = <0x7000C000 0x100>; interrupts = < 70 >; + /* PERIPH_ID_I2C1, PLL_P_OUT3 */ + clocks = <&tegra_car 12>, <&tegra_car 124>; }; i2c@7000c400 { @@ -42,6 +44,8 @@ compatible = "nvidia,tegra20-i2c"; reg = <0x7000C400 0x100>; interrupts = < 116 >; + /* PERIPH_ID_I2C2, PLL_P_OUT3 */ + clocks = <&tegra_car 54>, <&tegra_car 124>; }; i2c@7000c500 { @@ -50,14 +54,18 @@ compatible = "nvidia,tegra20-i2c"; reg = <0x7000C500 0x100>; interrupts = < 124 >; + /* PERIPH_ID_I2C3, PLL_P_OUT3 */ + clocks = <&tegra_car 67>, <&tegra_car 124>; }; i2c@7000d000 { #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; + compatible = "nvidia,tegra20-i2c-dvc"; reg = <0x7000D000 0x200>; interrupts = < 85 >; + /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ + clocks = <&tegra_car 47>, <&tegra_car 124>; }; i2s@70002800 { diff --git a/doc/device-tree-bindings/i2c/tegra20-i2c.txt b/doc/device-tree-bindings/i2c/tegra20-i2c.txt new file mode 100644 index 0000000..d601c17 --- /dev/null +++ b/doc/device-tree-bindings/i2c/tegra20-i2c.txt @@ -0,0 +1,23 @@ +(Placeholder note while we locate the kernel Tegra20 bindings) + +Added in U-Boot: + +Required properties: + - clocks : Two clocks must be given, each as a phandle to the Tegra's + CAR node and the clock number as a parameter: + - the I2C clock to use for the peripheral + - the pll_p_out3 clock, which can be used for fast operation. This + does not change and is the same for all I2C nodes. + +Example: +(TODO: merge with existing example): + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + /* PERIPH_ID_I2C2, PLL_P_OUT3 */ + clocks = <&tegra_car 54>, <&tegra_car 124>; + }; -- cgit v0.10.2 From 96a78ac0c445999ce21fb42ecab061479b4d7056 Mon Sep 17 00:00:00 2001 From: Yen Lin Date: Tue, 6 Mar 2012 19:00:23 +0000 Subject: tegra: i2c: Add I2C driver Add basic i2c driver for Tegra2 with 8- and 16-bit address support. The driver requires CONFIG_OF_CONTROL to obtain its configuration from the device tree. (Simon Glass: sjg@chromium.org modified for upstream) Signed-off-by: Simon Glass Acked-by: Heiko Schocher Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h new file mode 100644 index 0000000..0a7d99c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h @@ -0,0 +1,157 @@ +/* + * NVIDIA Tegra2 I2C controller + * + * Copyright 2010-2011 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_I2C_H_ +#define _TEGRA_I2C_H_ + +#include + +enum { + I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ + I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ +}; + +enum i2c_transaction_flags { + I2C_IS_WRITE = 0x1, /* for I2C write operation */ + I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ + I2C_USE_REPEATED_START = 0x4, /* for repeat start */ + I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ + I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ + I2C_NO_STOP = 0x20, +}; + +/* Contians the I2C transaction details */ +struct i2c_trans_info { + /* flags to indicate the transaction details */ + enum i2c_transaction_flags flags; + u32 address; /* I2C slave device address */ + u32 num_bytes; /* number of bytes to be transferred */ + /* + * Send/receive buffer. For the I2C send operation this buffer should + * be filled with the data to be sent to the slave device. For the I2C + * receive operation this buffer is filled with the data received from + * the slave device. + */ + u8 *buf; + int is_10bit_address; +}; + +struct i2c_control { + u32 tx_fifo; + u32 rx_fifo; + u32 packet_status; + u32 fifo_control; + u32 fifo_status; + u32 int_mask; + u32 int_status; +}; + +struct dvc_ctlr { + u32 ctrl1; /* 00: DVC_CTRL_REG1 */ + u32 ctrl2; /* 04: DVC_CTRL_REG2 */ + u32 ctrl3; /* 08: DVC_CTRL_REG3 */ + u32 status; /* 0C: DVC_STATUS_REG */ + u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ + u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ + u32 reserved_0[2]; /* 18: */ + u32 req; /* 20: DVC_REQ_REGISTER */ + u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ + u32 reserved_1[6]; /* 28: */ + u32 cnfg; /* 40: DVC_I2C_CNFG */ + u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ + u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ + u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ + u32 reserved_2[2]; /* 54: */ + u32 i2c_status; /* 5C: DVC_I2C_STATUS */ + struct i2c_control control; /* 60 ~ 78 */ +}; + +struct i2c_ctlr { + u32 cnfg; /* 00: I2C_I2C_CNFG */ + u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ + u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ + u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ + u32 reserved_0[2]; /* 14: */ + u32 status; /* 1C: I2C_I2C_STATUS */ + u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ + u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ + u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ + u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ + u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ + u32 reserved_1[2]; /* 34: */ + u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ + u32 reserved_2[4]; /* 40: */ + struct i2c_control control; /* 50 ~ 68 */ +}; + +/* bit fields definitions for IO Packet Header 1 format */ +#define PKT_HDR1_PROTOCOL_SHIFT 4 +#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) +#define PKT_HDR1_CTLR_ID_SHIFT 12 +#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) +#define PKT_HDR1_PKT_ID_SHIFT 16 +#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) +#define PROTOCOL_TYPE_I2C 1 + +/* bit fields definitions for IO Packet Header 2 format */ +#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 +#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) + +/* bit fields definitions for IO Packet Header 3 format */ +#define PKT_HDR3_READ_MODE_SHIFT 19 +#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 +#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) + +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ + (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) + +/* I2C_CNFG */ +#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 +#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) +#define I2C_CNFG_PACKET_MODE_SHIFT 10 +#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) + +/* I2C_SL_CNFG */ +#define I2C_SL_CNFG_NEWSL_SHIFT 2 +#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) + +/* I2C_FIFO_STATUS */ +#define TX_FIFO_FULL_CNT_SHIFT 0 +#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) +#define TX_FIFO_EMPTY_CNT_SHIFT 4 +#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) + +/* I2C_INTERRUPT_STATUS */ +#define I2C_INT_XFER_COMPLETE_SHIFT 7 +#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) +#define I2C_INT_NO_ACK_SHIFT 3 +#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) +#define I2C_INT_ARBITRATION_LOST_SHIFT 2 +#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) + +#endif diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 504db03..f86e46c 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -41,6 +41,7 @@ COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o +COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c new file mode 100644 index 0000000..21f6897 --- /dev/null +++ b/drivers/i2c/tegra_i2c.c @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2010-2011 NVIDIA Corporation + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int i2c_bus_num; + +/* Information about i2c controller */ +struct i2c_bus { + int id; + enum periph_id periph_id; + int speed; + int pinmux_config; + struct i2c_control *control; + struct i2c_ctlr *regs; + int is_dvc; /* DVC type, rather than I2C */ + int inited; /* bus is inited */ +}; + +static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; + +static void set_packet_mode(struct i2c_bus *i2c_bus) +{ + u32 config; + + config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; + + if (i2c_bus->is_dvc) { + struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; + + writel(config, &dvc->cnfg); + } else { + writel(config, &i2c_bus->regs->cnfg); + /* + * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe + * issues, i.e., some slaves may be wrongly detected. + */ + setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); + } +} + +static void i2c_reset_controller(struct i2c_bus *i2c_bus) +{ + /* Reset I2C controller. */ + reset_periph(i2c_bus->periph_id, 1); + + /* re-program config register to packet mode */ + set_packet_mode(i2c_bus); +} + +static void i2c_init_controller(struct i2c_bus *i2c_bus) +{ + /* + * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 + * here, in section 23.3.1, but in fact we seem to need a factor of + * 16 to get the right frequency. + */ + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, + i2c_bus->speed * 2 * 8); + + /* Reset I2C controller. */ + i2c_reset_controller(i2c_bus); + + /* Configure I2C controller. */ + if (i2c_bus->is_dvc) { /* only for DVC I2C */ + struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; + + setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); + } + + funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); +} + +static void send_packet_headers( + struct i2c_bus *i2c_bus, + struct i2c_trans_info *trans, + u32 packet_id) +{ + u32 data; + + /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ + data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; + data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; + data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 1 sent (0x%x)\n", data); + + /* prepare header2 */ + data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 2 sent (0x%x)\n", data); + + /* prepare IO specific header: configure the slave address */ + data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; + + /* Enable Read if it is not a write transaction */ + if (!(trans->flags & I2C_IS_WRITE)) + data |= PKT_HDR3_READ_MODE_MASK; + + /* Write I2C specific header */ + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 3 sent (0x%x)\n", data); +} + +static int wait_for_tx_fifo_empty(struct i2c_control *control) +{ + u32 count; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) + >> TX_FIFO_EMPTY_CNT_SHIFT; + if (count == I2C_FIFO_DEPTH) + return 1; + udelay(10); + timeout_us -= 10; + } + + return 0; +} + +static int wait_for_rx_fifo_notempty(struct i2c_control *control) +{ + u32 count; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) + >> TX_FIFO_FULL_CNT_SHIFT; + if (count) + return 1; + udelay(10); + timeout_us -= 10; + } + + return 0; +} + +static int wait_for_transfer_complete(struct i2c_control *control) +{ + int int_status; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + int_status = readl(&control->int_status); + if (int_status & I2C_INT_NO_ACK_MASK) + return -int_status; + if (int_status & I2C_INT_ARBITRATION_LOST_MASK) + return -int_status; + if (int_status & I2C_INT_XFER_COMPLETE_MASK) + return 0; + + udelay(10); + timeout_us -= 10; + } + + return -1; +} + +static int send_recv_packets(struct i2c_bus *i2c_bus, + struct i2c_trans_info *trans) +{ + struct i2c_control *control = i2c_bus->control; + u32 int_status; + u32 words; + u8 *dptr; + u32 local; + uchar last_bytes; + int error = 0; + int is_write = trans->flags & I2C_IS_WRITE; + + /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ + int_status = readl(&control->int_status); + writel(int_status, &control->int_status); + + send_packet_headers(i2c_bus, trans, 1); + + words = DIV_ROUND_UP(trans->num_bytes, 4); + last_bytes = trans->num_bytes & 3; + dptr = trans->buf; + + while (words) { + u32 *wptr = (u32 *)dptr; + + if (is_write) { + /* deal with word alignment */ + if ((unsigned)dptr & 3) { + memcpy(&local, dptr, sizeof(u32)); + writel(local, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", local); + } else { + writel(*wptr, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", *wptr); + } + if (!wait_for_tx_fifo_empty(control)) { + error = -1; + goto exit; + } + } else { + if (!wait_for_rx_fifo_notempty(control)) { + error = -1; + goto exit; + } + /* + * for the last word, we read into our local buffer, + * in case that caller did not provide enough buffer. + */ + local = readl(&control->rx_fifo); + if ((words == 1) && last_bytes) + memcpy(dptr, (char *)&local, last_bytes); + else if ((unsigned)dptr & 3) + memcpy(dptr, &local, sizeof(u32)); + else + *wptr = local; + debug("pkt data received (0x%x)\n", local); + } + words--; + dptr += sizeof(u32); + } + + if (wait_for_transfer_complete(control)) { + error = -1; + goto exit; + } + return 0; +exit: + /* error, reset the controller. */ + i2c_reset_controller(i2c_bus); + + return error; +} + +static int tegra2_i2c_write_data(u32 addr, u8 *data, u32 len) +{ + int error; + struct i2c_trans_info trans_info; + + trans_info.address = addr; + trans_info.buf = data; + trans_info.flags = I2C_IS_WRITE; + trans_info.num_bytes = len; + trans_info.is_10bit_address = 0; + + error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); + if (error) + debug("tegra2_i2c_write_data: Error (%d) !!!\n", error); + + return error; +} + +static int tegra2_i2c_read_data(u32 addr, u8 *data, u32 len) +{ + int error; + struct i2c_trans_info trans_info; + + trans_info.address = addr | 1; + trans_info.buf = data; + trans_info.flags = 0; + trans_info.num_bytes = len; + trans_info.is_10bit_address = 0; + + error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); + if (error) + debug("tegra2_i2c_read_data: Error (%d) !!!\n", error); + + return error; +} + +#ifndef CONFIG_OF_CONTROL +#error "Please enable device tree support to use this driver" +#endif + +unsigned int i2c_get_bus_speed(void) +{ + return i2c_controllers[i2c_bus_num].speed; +} + +int i2c_set_bus_speed(unsigned int speed) +{ + struct i2c_bus *i2c_bus; + + i2c_bus = &i2c_controllers[i2c_bus_num]; + i2c_bus->speed = speed; + i2c_init_controller(i2c_bus); + + return 0; +} + +static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) +{ + i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); + + /* + * We don't have a binding for pinmux yet. Leave it out for now. So + * far no one needs anything other than the default. + */ + i2c_bus->pinmux_config = FUNCMUX_DEFAULT; + i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); + i2c_bus->periph_id = clock_decode_periph_id(blob, node); + + /* + * We can't specify the pinmux config in the fdt, so I2C2 will not + * work on Seaboard. It normally has no devices on it anyway. + * You could add in this little hack if you need to use it. + * The correct solution is a pinmux binding in the fdt. + * + * if (i2c_bus->periph_id == PERIPH_ID_I2C2) + * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; + */ + if (i2c_bus->periph_id == -1) + return -FDT_ERR_NOTFOUND; + + return 0; +} + +/* + * Process a list of nodes, adding them to our list of I2C ports. + * + * @param blob fdt blob + * @param node_list list of nodes to process (any <=0 are ignored) + * @param count number of nodes to process + * @param is_dvc 1 if these are DVC ports, 0 if standard I2C + * @return 0 if ok, -1 on error + */ +static int process_nodes(const void *blob, int node_list[], int count, + int is_dvc) +{ + struct i2c_bus *i2c_bus; + int i; + + /* build the i2c_controllers[] for each controller */ + for (i = 0; i < count; i++) { + int node = node_list[i]; + + if (node <= 0) + continue; + + i2c_bus = &i2c_controllers[i]; + i2c_bus->id = i; + + if (i2c_get_config(blob, node, i2c_bus)) { + printf("i2c_init_board: failed to decode bus %d\n", i); + return -1; + } + + i2c_bus->is_dvc = is_dvc; + if (is_dvc) { + i2c_bus->control = + &((struct dvc_ctlr *)i2c_bus->regs)->control; + } else { + i2c_bus->control = &i2c_bus->regs->control; + } + debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", + is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, + i2c_bus->periph_id, i2c_bus->speed); + i2c_init_controller(i2c_bus); + debug("ok\n"); + i2c_bus->inited = 1; + + /* Mark position as used */ + node_list[i] = -1; + } + + return 0; +} + +/* Sadly there is no error return from this function */ +void i2c_init_board(void) +{ + int node_list[TEGRA_I2C_NUM_CONTROLLERS]; + const void *blob = gd->fdt_blob; + int count; + + /* First get the normal i2c ports */ + count = fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_NVIDIA_TEGRA20_I2C, node_list, + TEGRA_I2C_NUM_CONTROLLERS); + if (process_nodes(blob, node_list, count, 0)) + return; + + /* Now look for dvc ports */ + count = fdtdec_add_aliases_for_id(blob, "i2c", + COMPAT_NVIDIA_TEGRA20_DVC, node_list, + TEGRA_I2C_NUM_CONTROLLERS); + if (process_nodes(blob, node_list, count, 1)) + return; +} + +void i2c_init(int speed, int slaveaddr) +{ + /* This will override the speed selected in the fdt for that port */ + debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); + i2c_set_bus_speed(speed); +} + +/* i2c write version without the register address */ +int i2c_write_data(uchar chip, uchar *buffer, int len) +{ + int rc; + + debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); + debug("write_data: "); + /* use rc for counter */ + for (rc = 0; rc < len; ++rc) + debug(" 0x%02x", buffer[rc]); + debug("\n"); + + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra2_i2c_write_data(chip << 1, buffer, len); + if (rc) + debug("i2c_write_data(): rc=%d\n", rc); + + return rc; +} + +/* i2c read version without the register address */ +int i2c_read_data(uchar chip, uchar *buffer, int len) +{ + int rc; + + debug("inside i2c_read_data():\n"); + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra2_i2c_read_data(chip << 1, buffer, len); + if (rc) { + debug("i2c_read_data(): rc=%d\n", rc); + return rc; + } + + debug("i2c_read_data: "); + /* reuse rc for counter*/ + for (rc = 0; rc < len; ++rc) + debug(" 0x%02x", buffer[rc]); + debug("\n"); + + return 0; +} + +/* Probe to see if a chip is present. */ +int i2c_probe(uchar chip) +{ + int rc; + uchar reg; + + debug("i2c_probe: addr=0x%x\n", chip); + reg = 0; + rc = i2c_write_data(chip, ®, 1); + if (rc) { + debug("Error probing 0x%x.\n", chip); + return 1; + } + return 0; +} + +static int i2c_addr_ok(const uint addr, const int alen) +{ + /* We support 7 or 10 bit addresses, so one or two bytes each */ + return alen == 1 || alen == 2; +} + +/* Read bytes */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + uint offset; + int i; + + debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", + chip, addr, len); + if (!i2c_addr_ok(addr, alen)) { + debug("i2c_read: Bad address %x.%d.\n", addr, alen); + return 1; + } + for (offset = 0; offset < len; offset++) { + if (alen) { + uchar data[alen]; + for (i = 0; i < alen; i++) { + data[alen - i - 1] = + (addr + offset) >> (8 * i); + } + if (i2c_write_data(chip, data, alen)) { + debug("i2c_read: error sending (0x%x)\n", + addr); + return 1; + } + } + if (i2c_read_data(chip, buffer + offset, 1)) { + debug("i2c_read: error reading (0x%x)\n", addr); + return 1; + } + } + + return 0; +} + +/* Write bytes */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + uint offset; + int i; + + debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", + chip, addr, len); + if (!i2c_addr_ok(addr, alen)) { + debug("i2c_write: Bad address %x.%d.\n", addr, alen); + return 1; + } + for (offset = 0; offset < len; offset++) { + uchar data[alen + 1]; + for (i = 0; i < alen; i++) + data[alen - i - 1] = (addr + offset) >> (8 * i); + data[alen] = buffer[offset]; + if (i2c_write_data(chip, data, alen + 1)) { + debug("i2c_write: error sending (0x%x)\n", addr); + return 1; + } + } + + return 0; +} + +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Functions for multiple I2C bus handling + */ +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited) + return -1; + i2c_bus_num = bus; + + return 0; +} +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 1e198f8..171c628 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -58,6 +58,8 @@ struct fdt_memory { enum fdt_compat_id { COMPAT_UNKNOWN, COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */ + COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra2 i2c */ + COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 2149bd7..bdec1a0 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -38,6 +38,8 @@ DECLARE_GLOBAL_DATA_PTR; static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, ""), COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), + COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"), + COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v0.10.2 From 33fbc9cf826c1dd54ab5a715154478fae008fcd2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 16 Mar 2012 07:55:32 +0000 Subject: sdrc.c: Fix typo in do_sdrc_init() for SPL We need to setup CS0 and CS1 not CS0 and CS0 again. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 91f42c0..f6d9b97 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -180,7 +180,7 @@ void do_sdrc_init(u32 cs, u32 early) write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr); make_cs1_contiguous(); - write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb, + write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, rfr_ctrl, mr); #endif -- cgit v0.10.2 From 3fbc6931a456b89294b5807e08df21b1a1387846 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 27 Mar 2012 23:05:07 +0000 Subject: board/ti/beagle/beagle.c: Fix build warnings Fix: beagle.c:257:13: warning: function declaration isn't a prototype [-Wstrict-prototypes] beagle.c:257:13: warning: function declaration isn't a prototype [-Wstrict-prototypes] Also make beagle_dvi_pup() checkpatch clean, fix: ERROR: open brace '{' following function declarations go on the next line Signed-off-by: Anatolij Gustschin Cc: Tom Rini diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 114ab7e..8b07eef 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -254,7 +254,8 @@ void beagle_display_init(void) /* * Enable DVI power */ -static void beagle_dvi_pup() { +static void beagle_dvi_pup(void) +{ uchar val; switch (get_board_revision()) { -- cgit v0.10.2 From 27ac87d91ef6c11ed2569bf8444f0c2cbf25dc4f Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Tue, 27 Mar 2012 23:13:43 +0000 Subject: arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warnings Fix: clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used [-Wunused-but-set-variable] clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin Cc: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 4cfe119..4e74569 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -320,11 +320,9 @@ static void setup_dplls(void) #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL static void setup_non_essential_dplls(void) { - u32 sys_clk_khz, abe_ref_clk; + u32 abe_ref_clk; const struct dpll_params *params; - sys_clk_khz = get_sys_clk_freq() / 1000; - /* IVA */ clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); -- cgit v0.10.2 From 76e2c169a525159d48dd005a371fb05e1943c64b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 28 Mar 2012 06:26:18 +0000 Subject: OMAP: Remove omap1610inn-based boards The CS_AUTOBOOT configurations have been broken for a long time. Kshitij Gupta is no longer at TI making these broken and orphaned boards, so remove. Signed-off-by: Tom Rini diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..72f8b64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -672,7 +672,6 @@ Igor Grinberg Kshitij Gupta omap1510inn ARM925T - omap1610inn ARM926EJS Stefan Herbrechtsmeier diff --git a/board/ti/omap1610inn/Makefile b/board/ti/omap1610inn/Makefile deleted file mode 100644 index 2b8641f..0000000 --- a/board/ti/omap1610inn/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := omap1610innovator.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ti/omap1610inn/config.mk b/board/ti/omap1610inn/config.mk deleted file mode 100644 index ee0aa0a..0000000 --- a/board/ti/omap1610inn/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Innovator board with OMAP1610 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - - -CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap1610inn/flash.c b/board/ti/omap1610inn/flash.c deleted file mode 100644 index a99a91c..0000000 --- a/board/ti/omap1610inn/flash.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info) -{ - int j; - for (j=2;jstart[j]); - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - if (flag) - enable_interrupts(); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag, rc = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = 1; - goto done; - } - } -done: - if (flag) - enable_interrupts(); - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return rc; -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ti/omap1610inn/lowlevel_init.S b/board/ti/omap1610inn/lowlevel_init.S deleted file mode 100644 index b376ba5..0000000 --- a/board/ti/omap1610inn/lowlevel_init.S +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - -#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */ - ldr r0, CONF_STATUS - ldr r1, [r0] - tst r1, #0x02 - beq disable_wd /* booting from RAM, skip setup */ -#endif - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x0000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ -disable_wd: - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Load physical SDRAM base. */ - mov r0, #0x10000000 - /* Get current execution location. */ - mov r1, pc - /* Compare. */ - cmp r1, r0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bge skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r2, #0x0100 -waitMDDR2: - subs r2, r2, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 -4: - subs r3, r3, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -#ifdef CONFIG_CS_AUTOBOOT -CONF_STATUS: - .word 0xfffe1130 /* 32 bits */ -#endif - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* 96 MHz Samsung Mobile DDR */ -SDRAM_CONFIG_VAL: - .word 0x001200f4 - -DLL_LRD_CONTROL_VAL: - .word 0x00800002 - -VAL_ARM_CKCTL: - .word 0x3000 -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_INNOVATOROMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001131 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_TC_EMIFF_SDRAM_CONFIG: - .word 0x010290fc -VAL_TC_EMIFF_MRS: - .word 0x00000027 - -VAL_ARM_IDLECT1: - .word 0x00000400 - -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/ti/omap1610inn/omap1610innovator.c b/board/ti/omap1610inn/omap1610innovator.c deleted file mode 100644 index 16e8237..0000000 --- a/board/ti/omap1610inn/omap1610innovator.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CS_AUTOBOOT -unsigned long omap_flash_base; -#endif - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - -#ifdef CONFIG_CS_AUTOBOOT - /* Check swapping of CS0 and CS3, set flash base accordingly */ - omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ? - PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1; -#endif - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0400030b - -#ifdef CONFIG_H2_OMAP1610 - #define LAN_RESET_REGISTER 0x0400001c - - /* The debug board on which the lan chip resides may not be powered - * ON at the same time as the OMAP chip. So wait in a loop until the - * lan reset register (on the debug board) is available (powered on) - * and reset the lan chip. - */ - - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; - udelay (3); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); - - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - udelay (3); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); -#endif - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index ade2034..c6090ba 100644 --- a/boards.cfg +++ b/boards.cfg @@ -164,14 +164,6 @@ m28evk arm arm926ejs - denx mx28evk arm arm926ejs - freescale mx28 nhk8815 arm arm926ejs nhk8815 st nomadik nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND -omap1610h2 arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610h2_cs0boot arm arm926ejs omap1610inn ti omap omap1610inn:CS0_BOOT -omap1610h2_cs3boot arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610h2_cs_autoboot arm arm926ejs omap1610inn ti omap omap1610inn:CS_AUTOBOOT -omap1610inn arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610inn_cs0boot arm arm926ejs omap1610inn ti omap omap1610inn:CS0_BOOT -omap1610inn_cs3boot arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610inn_cs_autoboot arm arm926ejs omap1610inn ti omap omap1610inn:CS_AUTOBOOT omap5912osk arm arm926ejs - ti omap omap730p2 arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2:CS0_BOOT diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h deleted file mode 100644 index d57e1a7..0000000 --- a/include/configs/omap1610h2.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Kshitij Gupta - * Configuration settings for the TI OMAP 1610 H2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ - -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_H2 - -/* input clock of PLL */ -/* the OMAP1610 H2 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CONFIG_SYS_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h deleted file mode 100644 index 7901b6c..0000000 --- a/include/configs/omap1610inn.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ - -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_INNOVATOR - -/* input clock of PLL */ -/* the OMAP1610 Innovator has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/a0875451/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CONFIG_SYS_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From ee60197e64f4daa8869a88ccc20bf6896a218657 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Nov 2011 10:49:37 +0000 Subject: Allow arch directory to contain .lds without requiring Makefile The Makefile for a CPU is in arch/($ARCH)/cpu/$(CPU). We want to support having an .lds file in arch/$(ARCH)/cpu without requiring an additional Makefile there. This change makes it clear that we expect a Makefile in the same directory as the link script except in this case. Signed-off-by: Simon Glass diff --git a/Makefile b/Makefile index 01bf2b0..e2a5a84 100644 --- a/Makefile +++ b/Makefile @@ -174,6 +174,8 @@ include $(TOPDIR)/config.mk # that (or fail if absent). Otherwise, search for a linker script in a # standard location. +LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT)) + ifndef LDSCRIPT #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug ifdef CONFIG_SYS_LDSCRIPT @@ -182,6 +184,7 @@ ifndef LDSCRIPT endif endif +# If there is no specified link script, we look in a number of places for it ifndef LDSCRIPT ifeq ($(CONFIG_NAND_U_BOOT),y) LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds @@ -196,6 +199,11 @@ ifndef LDSCRIPT LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds endif ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds + # We don't expect a Makefile here + LDSCRIPT_MAKEFILE_DIR = + endif + ifeq ($(wildcard $(LDSCRIPT)),) $(error could not find linker script) endif endif @@ -513,7 +521,7 @@ depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ $(obj)include/autoconf.mk \ $(obj)include/generated/generic-asm-offsets.h \ $(obj)include/generated/asm-offsets.h - for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \ + for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \ $(MAKE) -C $$dir _depend ; done TAG_SUBDIRS = $(SUBDIRS) diff --git a/spl/Makefile b/spl/Makefile index 3262e22..680f6dd 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -81,6 +81,9 @@ ifeq ($(wildcard $(LDSCRIPT)),) LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds endif ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds +endif +ifeq ($(wildcard $(LDSCRIPT)),) $(error could not find linker script) endif -- cgit v0.10.2 From 3a62d8c3a93c63183fdad1d52277bb15ac72ba79 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Nov 2011 10:49:39 +0000 Subject: arm: Remove zipitz2 link script This link script doesn't appear to do anything useful or unique, so drop it, and rely on the CPU one. Signed-off-by: Simon Glass diff --git a/board/zipitz2/u-boot.lds b/board/zipitz2/u-boot.lds deleted file mode 100644 index e1a1ff1..0000000 --- a/board/zipitz2/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - __bss_end__ = .; -} -- cgit v0.10.2 From 7e6403a66d9a9c939ee8146436d7d652673b2995 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Nov 2011 10:49:40 +0000 Subject: Define CPUDIR for the .lds link script Most link scripts differ only in the directory containing the start.o file. Make this a #define to remove this last difference. (Note that if start.o were disallowed outside the CPU start directory then we wouldn't even need this. But that is a separate discussion.) Signed-off-by: Simon Glass diff --git a/Makefile b/Makefile index e2a5a84..8204312 100644 --- a/Makefile +++ b/Makefile @@ -344,6 +344,7 @@ export PLATFORM_LIBS # on the fly. LDPPFLAGS += \ -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ + -DCPUDIR=$(CPUDIR) \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') diff --git a/spl/Makefile b/spl/Makefile index 680f6dd..ea7d475 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -93,6 +93,7 @@ endif LDPPFLAGS += \ -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ -include $(OBJTREE)/include/config.h \ + -DCPUDIR=$(CPUDIR) \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -- cgit v0.10.2 From 9492791ab462c586424217f4b6e34f61f9ef5461 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 21 Nov 2011 10:49:41 +0000 Subject: arm: Remove unneeded setting of LDCSRIPT This is set by the top level Makefile anyway, so drop it. This does have the effect of changing the order - now the board link script will have preference over the CPU one. But this seems more correct anyway. Signed-off-by: Simon Glass diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 45f9dca..3c5f987 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -70,13 +70,6 @@ PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \ endif endif -ifdef CONFIG_SYS_LDSCRIPT -# need to strip off double quotes -LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) -else -LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds -endif - # needed for relocation ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie -- cgit v0.10.2 From dde3b70dcf3d13b3ce173a017788f7522780b857 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 23 Feb 2012 03:28:41 +0000 Subject: arm: add a common .lds link script Most ARM CPUs use a very similar link script. This adds a basic script that can be used by most CPUs. Two new symbols are introduced which are intended to eventually be defined on all architectures to make things easier for generic relocation and reduce special-case code for each architecture: __image_copy_start is the start of the text area (equivalent to the existing _start on ARM). It marks the start of the region which must be copied to a new location during relocation. This symbol is called __text_start on x86 and microblaze. __image_copy_end is the end of the region which must be copied to a new location during relocation. It is normally equal to the start of the BSS region, but this can vary in some cases (SPL?). Making this an explicit symbol on its own removes any ambiguity and permits common code to always do the right thing. This new script makes use of CPUDIR, now defined by both Makefile and spl/Makefile, to find the directory containing the start.o object file, which is always placed first in the image. To permit MMU setup prior to relocation (as used by pxa) we add an area to the link script which contains space for this. This is taken from commit 7f4cfcf. CPUs can put the contents in there using their start.S file. BTW, shouldn't that area be 16KB-aligned? Signed-off-by: Simon Glass diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds new file mode 100644 index 0000000..e49ca0c --- /dev/null +++ b/arch/arm/cpu/u-boot.lds @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} -- cgit v0.10.2 From 4a0764858b0bdcb3508f01b96e3fa32b16cdb30f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 20 Feb 2012 20:17:52 +0000 Subject: arm: Use common .lds file where possible Each cpu directory currently has its own .lds file. This is only needed in most cases because the start.o file is in a different subdir. Now that we can factor out this difference, we can move most cpus over to the common .lds file. Signed-off-by: Simon Glass diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds deleted file mode 100644 index d1e2851..0000000 --- a/arch/arm/cpu/arm1136/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - * - * Copyright (C) 2005-2007 Samsung Electronics - * Kyungin Park - * - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds deleted file mode 100644 index 27d6638..0000000 --- a/arch/arm/cpu/arm1176/u-boot.lds +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1176/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm720t/u-boot.lds b/arch/arm/cpu/arm720t/u-boot.lds deleted file mode 100644 index 9370fad..0000000 --- a/arch/arm/cpu/arm720t/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm920t/u-boot.lds b/arch/arm/cpu/arm920t/u-boot.lds deleted file mode 100644 index 17ba604..0000000 --- a/arch/arm/cpu/arm920t/u-boot.lds +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * Ming-Len Wu - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm925t/u-boot.lds b/arch/arm/cpu/arm925t/u-boot.lds deleted file mode 100644 index 64e76f5..0000000 --- a/arch/arm/cpu/arm925t/u-boot.lds +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm925t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds deleted file mode 100644 index 1480e0c..0000000 --- a/arch/arm/cpu/arm926ejs/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm926ejs/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm946es/u-boot.lds b/arch/arm/cpu/arm946es/u-boot.lds deleted file mode 100644 index ff938e4..0000000 --- a/arch/arm/cpu/arm946es/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm946es/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/arm_intcm/u-boot.lds b/arch/arm/cpu/arm_intcm/u-boot.lds deleted file mode 100644 index f4a146c..0000000 --- a/arch/arm/cpu/arm_intcm/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm_intcm/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds deleted file mode 100644 index 40ecf78..0000000 --- a/arch/arm/cpu/armv7/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/armv7/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - __image_copy_end = .; - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/lh7a40x/u-boot.lds b/arch/arm/cpu/lh7a40x/u-boot.lds deleted file mode 100644 index 30934ff..0000000 --- a/arch/arm/cpu/lh7a40x/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/lh7a40x/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds deleted file mode 100644 index e86e781..0000000 --- a/arch/arm/cpu/pxa/u-boot.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - . = ALIGN(4096); - - .mmutable : { - *(.mmutable) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/s3c44b0/u-boot.lds b/arch/arm/cpu/s3c44b0/u-boot.lds deleted file mode 100644 index 74a259c..0000000 --- a/arch/arm/cpu/s3c44b0/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/s3c44b0/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/arch/arm/cpu/sa1100/u-boot.lds b/arch/arm/cpu/sa1100/u-boot.lds deleted file mode 100644 index e6381da..0000000 --- a/arch/arm/cpu/sa1100/u-boot.lds +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * MontaVista Software, Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} -- cgit v0.10.2