From cc434ad5c1c97baa9d7020db35f74a4998f2146a Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 26 Feb 2016 17:20:25 +0800 Subject: ARM: at91: sama5d2: add macro & field definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They will be used on SAMA5D2 PTC board. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index b040256..b805a2c 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -32,6 +32,30 @@ struct atmel_sfr { #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 +/* Bit field in EBICFG */ +#define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0) +#define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0) +#define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0) +#define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0) +#define AT91_SFR_EBICFG_PULL0 (0x3 << 2) +#define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2) +#define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2) +#define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2) +#define AT91_SFR_EBICFG_SCH0 (0x1 << 4) +#define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4) +#define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4) +#define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8) +#define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8) +#define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8) +#define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8) +#define AT91_SFR_EBICFG_PULL1 (0x3 << 10) +#define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10) +#define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10) +#define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10) +#define AT91_SFR_EBICFG_SCH1 (0x1 << 12) +#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) +#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) + /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index dd5a2a7..25c8541 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -135,7 +135,11 @@ /* * Address Memory Space */ +#define ATMEL_BASE_CS0 0x10000000 #define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_CS1 0x60000000 +#define ATMEL_BASE_CS2 0x70000000 +#define ATMEL_BASE_CS3 0x80000000 #define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 #define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 #define ATMEL_BASE_SDMMC0 0xa0000000 @@ -165,6 +169,7 @@ */ #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) +#define ATMEL_BASE_SMC (ATMEL_BASE_HSMC + 0x700) #define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) #define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) -- cgit v0.10.2 From 9989c1567d53a2558b872fabc39d1f8a9383c3ca Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 26 Feb 2016 17:20:26 +0800 Subject: board: atmel: add SAMA5D2 PTC Engineering board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 9ce775e..73a9c74 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_SAMA5D2_PTC + bool "SAMA5D2 PTC board" + select CPU_V7 + select SUPPORT_SPL + config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" select CPU_V7 @@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d2_ptc/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig new file mode 100644 index 0000000..d2661c6 --- /dev/null +++ b/board/atmel/sama5d2_ptc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_PTC + +config SYS_BOARD + default "sama5d2_ptc" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_ptc" + +endif diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS new file mode 100644 index 0000000..7ab03d6 --- /dev/null +++ b/board/atmel/sama5d2_ptc/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 PTC Engineering BOARD +M: Wenyou Yang +S: Maintained +F: board/atmel/sama5d2_ptc/ +F: include/configs/sama5d2_ptc.h +F: configs/sama5d2_ptc_spiflash_defconfig +F: configs/sama5d2_ptc_nandflash_defconfig diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile new file mode 100644 index 0000000..1fe0392 --- /dev/null +++ b/board/atmel/sama5d2_ptc/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Atmel +# Wenyou Yang +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_ptc.o diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c new file mode 100644 index 0000000..9e6544b --- /dev/null +++ b/board/atmel/sama5d2_ptc/sama5d2_ptc.c @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2016 Atmel + * Wenyou.Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + at91_periph_clk_enable(ATMEL_ID_HSMC); + + writel(AT91_SFR_EBICFG_DRIVE0_HIGH | + AT91_SFR_EBICFG_PULL0_NONE | + AT91_SFR_EBICFG_DRIVE1_HIGH | + AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */ + atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */ +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1); +} + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(CONFIG_USART_ID); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart0_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_NAND_ATMEL + board_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); + if (rc) + printf("GMAC register failed\n"); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_SERIALFLASH + board_spi0_hw_init(); +#endif + +#ifdef CONFIG_SYS_USE_NANDFLASH + board_nand_hw_init(); +#endif +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DIS_DLL | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + at91_system_clk_enable(AT91_PMC_DDR); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + at91_plla_init(AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1)); + + at91_pllicpr_init(0); + + at91_mck_init(AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA); +} +#endif diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig new file mode 100644 index 0000000..7425184 --- /dev/null +++ b/configs/sama5d2_ptc_nandflash_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_PTC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig new file mode 100644 index 0000000..27fc394 --- /dev/null +++ b/configs/sama5d2_ptc_spiflash_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_PTC=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h new file mode 100644 index 0000000..d91d75e --- /dev/null +++ b/include/configs/sama5d2_ptc.h @@ -0,0 +1,155 @@ +/* + * Configuration settings for the SAMA5D2 PTC Engineering board. + * + * Copyright (C) 2016 Atmel + * Wenyou Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_UART0 +#define CONFIG_USART_ID ATMEL_ID_UART0 + +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_AT91_GPIO +#define CONFIG_ATMEL_PIO4 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* SerialFlash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#define CONFIG_CMD_NAND + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_CMD_NAND_TRIMFFS +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC" + +#if defined(CONFIG_CMD_USB) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +#ifdef CONFIG_SYS_USE_NANDFLASH +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_OFFSET_REDUND +#undef CONFIG_BOOTCOMMAND +/* u-boot env in nand flash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x200000 +#define CONFIG_ENV_OFFSET_REDUND 0x400000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \ + "nand read 0x22000000 0x600000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#endif + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,57600 earlyprintk " \ + "mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs" + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER +#endif + +#endif -- cgit v0.10.2 From a9c89bf1669cbeb7bce6ae7a626eb9f2120af73f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 11 Apr 2016 14:07:17 +0800 Subject: board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the missing pin config of the SDMMC0 interface. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 10edf28..04422ce 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -171,6 +171,7 @@ static void board_sdhci0_hw_init(void) atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SDMMC0_CD */ at91_periph_clk_enable(ATMEL_ID_SDMMC0); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, -- cgit v0.10.2 From 4adf6a715796de4f0e858e0246c3abf5e3c118f3 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 11 Apr 2016 16:41:31 +0800 Subject: ARM: at91: clock: fix the GCK's clock source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 81e9f69..27372b3 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -162,6 +162,11 @@ int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) if (div > 0xff) return -EINVAL; + if (clk_source == GCK_CSS_UPLL_CLK) { + if (at91_upll_clk_enable()) + return -ENODEV; + } + writel(id, &pmc->pcr); regval = readl(&pmc->pcr); regval &= ~AT91_PMC_PCR_GCKCSS; -- cgit v0.10.2 From 7a91e1a3835413aac3e7c894ca1ba205e6ade887 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 11 Apr 2016 16:41:32 +0800 Subject: ARM: at91: clock: complete the GCK's clock sources MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 27372b3..76fcada 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -236,6 +236,12 @@ u32 at91_get_periph_generated_clk(u32 id) case AT91_PMC_PCR_GCKCSS_PLLA_CLK: freq = gd->arch.plla_rate_hz; break; + case AT91_PMC_PCR_GCKCSS_UPLL_CLK: + freq = AT91_UTMI_PLL_CLK_FREQ; + break; + case AT91_PMC_PCR_GCKCSS_MCK_CLK: + freq = gd->arch.mck_rate_hz; + break; default: printf("Improper GCK clock source selection!\n"); freq = 0; diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index 8577c74..ca7d7d0 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -20,6 +20,8 @@ #define GCK_CSS_MCK_CLK 4 #define GCK_CSS_AUDIO_CLK 5 +#define AT91_UTMI_PLL_CLK_FREQ 480000000 + static inline unsigned long get_cpu_clk_rate(void) { DECLARE_GLOBAL_DATA_PTR; -- cgit v0.10.2 From c043d8d8ce8bf1c1946c87a89b6639db3ebb4243 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 11 Apr 2016 16:41:33 +0800 Subject: board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 04422ce..93df7ba 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -175,7 +175,7 @@ static void board_sdhci0_hw_init(void) at91_periph_clk_enable(ATMEL_ID_SDMMC0); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); } static void board_sdhci1_hw_init(void) @@ -191,7 +191,7 @@ static void board_sdhci1_hw_init(void) at91_periph_clk_enable(ATMEL_ID_SDMMC1); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); } int board_mmc_init(bd_t *bis) -- cgit v0.10.2 From 12328f25f257c347c79562ebc7f66c1a0f48bc2b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 18 Apr 2016 18:30:41 +0200 Subject: ARM: atmel: Enable FIT image support for SAMA5Dx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the fitImage support for the entire SAMA5Dx lineup of CPUs. The fitImage is superior image format to uImage and it is useful to have it available. Signed-off-by: Marek Vasut Cc: Andreas Bießmann Cc: Wenyou Yang Reviewed-by: Andreas Bießmann [rebase on current ToT] Signed-off-by: Andreas Bießmann diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 7fd37d6..1880256 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -21,3 +21,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index de4e6bc..de8f4d9 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -21,3 +21,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 189a3e9..1dabc5f 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -19,3 +19,4 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 16e3f22..458a486 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -19,3 +19,4 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 8d3c3cf..488d950 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -21,3 +21,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 8e15286..12f28f2 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -21,3 +21,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index ffbafae..42fcc1e 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -21,3 +21,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 1ea5cda..3110269 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -22,3 +22,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 5384917..3ea4bd7 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -22,3 +22,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index b709cf6..dbec4ad 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -22,3 +22,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 45128e9..f2a5844 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -22,3 +22,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 9c1c232..58186ce 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -22,3 +22,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 59eb4dd..ab23e95 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -22,3 +22,4 @@ CONFIG_USB=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_OF_LIBFDT=y +CONFIG_FIT=y -- cgit v0.10.2 From bb0c63a5f3b05770e8cb6171be57ca69995bd447 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 22 Apr 2016 21:56:21 +0200 Subject: ARM: sama5d2: Implement boot device autodetection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for saving ARM register R4 early during boot using save_boot_params . Implement support for decoding the stored register R4 value in spl_boot_device() to obtain boot device from which the SoC booted. This way, the SPL will always load U-Boot from the same device from which the SPL itself booted instead of using hard-coded boot device. This functionality is useful for example when booting sama5d2-xplained from SD card, where by default the SPL would try loading the U-Boot from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1), while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired to always boot from BOOT_DEVICE_MMC1. Signed-off-by: Marek Vasut Cc: Andreas Bießmann Cc: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 4424523..d2abf31 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o -obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o +obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-y += spl.o diff --git a/arch/arm/mach-at91/bootparams_atmel.S b/arch/arm/mach-at91/bootparams_atmel.S new file mode 100644 index 0000000..568094b --- /dev/null +++ b/arch/arm/mach-at91/bootparams_atmel.S @@ -0,0 +1,18 @@ +/* + * Atmel SAMA5Dx boot parameter handling + * + * Copyright (c) 2016 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +ENTRY(save_boot_params) + ldr r0, =bootrom_stash + str r4, [r0, #0] + b save_boot_params_ret +ENDPROC(save_boot_params) diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 25c8541..ee841da 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -230,6 +230,18 @@ /* No PMECC Galois table in ROM */ #define NO_GALOIS_TABLE_IN_ROM +/* Boot modes stored by BootROM in r4 */ +#define ATMEL_SAMA5D2_BOOT_FROM_OFF 0 +#define ATMEL_SAMA5D2_BOOT_FROM_MASK 0xf +#define ATMEL_SAMA5D2_BOOT_FROM_SPI (0 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_MCI (1 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_SMC (2 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_TWI (3 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_QSPI (4 << 0) + +#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF 4 +#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK 0xf + #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); unsigned int get_extension_chip_id(void); diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 27a405a..c4ed224 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -23,6 +23,40 @@ void at91_disable_wdt(void) } #endif +#if defined(CONFIG_SAMA5D2) +struct { + u32 r4; +} bootrom_stash __attribute__((section(".data"))); + +u32 spl_boot_device(void) +{ + u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) & + ATMEL_SAMA5D2_BOOT_FROM_MASK; + u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) & + ATMEL_SAMA5D2_BOOT_DEV_ID_MASK; + +#if defined(CONFIG_SYS_USE_MMC) + if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) { + if (off == 0) + return BOOT_DEVICE_MMC1; + if (off == 1) + return BOOT_DEVICE_MMC2; + printf("ERROR: MMC controller %i not present!\n", dev); + hang(); + } +#endif + +#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH) + if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI) + return BOOT_DEVICE_SPI; +#endif + + printf("ERROR: SMC/TWI/QSPI boot device not supported!\n" + " Boot device %i, controller number %i\n", dev, off); + + return BOOT_DEVICE_NONE; +} +#else u32 spl_boot_device(void) { #ifdef CONFIG_SYS_USE_MMC @@ -34,12 +68,14 @@ u32 spl_boot_device(void) #endif return BOOT_DEVICE_NONE; } +#endif u32 spl_boot_mode(void) { switch (spl_boot_device()) { #ifdef CONFIG_SYS_USE_MMC case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; break; #endif -- cgit v0.10.2