From 93d3320417b16f331d5edb87409cd7a347c4eeaa Mon Sep 17 00:00:00 2001
From: Zhao Qiang <B45475@freescale.com>
Date: Thu, 25 Sep 2014 13:52:25 +0800
Subject: qe: add u-qe support to arm board

ls1021 is arm-core and support qe which is u-qe.
add u-qe init for arm board.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
[York Sun: Fix compiling error caused by u_qe_init()]
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index f2c9687..fc6a475 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -72,6 +72,10 @@
 
 #define DCU_LAYER_MAX_NUM			16
 
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+
 #define CONFIG_SYS_FSL_SRDS_1
 
 #ifdef CONFIG_LS102XA
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c69d064..438f128 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -17,6 +17,14 @@ struct arch_global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
+
+#if defined(CONFIG_U_QE)
+	u32 qe_clk;
+	u32 brg_clk;
+	uint mp_alloc_base;
+	uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
 #ifdef CONFIG_AT91FAMILY
 	/* "static data" needed by at91's clock.c */
 	unsigned long	cpu_clk_rate_hz;
diff --git a/drivers/Makefile b/drivers/Makefile
index 33227c8..3c96524 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,6 +16,7 @@ obj-y += twserial/
 obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
+obj-$(CONFIG_U_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 7f1bd06..8fa4866 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_U_QE) += qe.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index d9a7d82..dfae4bf 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -12,6 +12,7 @@
 #include <fdt_support.h>
 #include "qe.h"
 
+#ifdef CONFIG_QE
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -72,3 +73,4 @@ void ft_qe_setup(void *blob)
 		"clock-frequency", gd->arch.qe_clk / 2, 1);
 	fdt_fixup_qe_firmware(blob);
 }
+#endif
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 4358a91..b545ec9 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
 	return;
 }
 
+#ifdef CONFIG_QE
 uint qe_muram_alloc(uint size, uint align)
 {
 	uint	retloc;
@@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align)
 
 	return retloc;
 }
+#endif
 
 void *qe_muram_addr(uint offset)
 {
@@ -180,6 +182,17 @@ void qe_init(uint qe_base)
 	qe_snums_init();
 }
 
+#ifdef CONFIG_U_QE
+void u_qe_init(void)
+{
+	uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
+	qe_immr = (qe_map_t *)qe_base;
+
+	qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+	out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
 void qe_reset(void)
 {
 	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -212,6 +225,7 @@ void qe_assign_page(uint snum, uint para_ram_base)
 
 #define BRG_CLK		(gd->arch.brg_clk)
 
+#ifdef CONFIG_QE
 int qe_set_brg(uint brg, uint rate)
 {
 	volatile uint	*bp;
@@ -239,6 +253,7 @@ int qe_set_brg(uint brg, uint rate)
 
 	return 0;
 }
+#endif
 
 /* Set ethernet MII clock master
 */
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index ebb7c5f..30484b8 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -275,6 +275,7 @@ void *qe_muram_addr(uint offset);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
 void qe_init(uint qe_base);
+void u_qe_init(void);
 void qe_reset(void);
 void qe_assign_page(uint snum, uint para_ram_base);
 int qe_set_brg(uint brg, uint rate);
-- 
cgit v0.10.2


From 63e75fd7a3808df091eb50786519703c5df76b8e Mon Sep 17 00:00:00 2001
From: Zhao Qiang <B45475@freescale.com>
Date: Fri, 26 Sep 2014 16:25:32 +0800
Subject: qe: add qe support to ls1021aqds

add qe support to ls1021aqds

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 5fafc85..bcfa9b9 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -17,6 +17,9 @@
 
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -237,6 +240,11 @@ int board_init(void)
 	fsl_serdes_init();
 	config_serdes_mux();
 #endif
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
 	return 0;
 }
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d1f6ea7..6b8ee8d 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -70,6 +70,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_HAS_SERDES
 
 #define CONFIG_FSL_CAAM			/* Enable CAAM */
+
+#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#define CONFIG_U_QE
+#endif
+
 /*
  * IFC Definitions
  */
@@ -332,6 +337,8 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTDELAY		3
 
+#define CONFIG_SYS_QE_FW_ADDR     0x67f40000
+
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 	"fdt_high=0xcfffffff\0"		\
-- 
cgit v0.10.2


From eaa859e7d23172acb68b3096beb083ba2e42d6c3 Mon Sep 17 00:00:00 2001
From: Zhao Qiang <B45475@freescale.com>
Date: Fri, 26 Sep 2014 16:25:33 +0800
Subject: qe: add qe support for ls1021a-twr board

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 50d5640..a90bb09 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -17,6 +17,10 @@
 #include <fsl_mdio.h>
 #include <tsec.h>
 #include <fsl_sec.h>
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -278,6 +282,10 @@ int board_init(void)
 	config_serdes_mux();
 #endif
 
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
 	return 0;
 }
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 3c73af8..96b1547 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -50,6 +50,10 @@
 
 #define CONFIG_FSL_CAAM			/* Enable CAAM */
 
+#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#define CONFIG_U_QE
+#endif
+
 /*
  * IFC Definitions
  */
@@ -275,6 +279,8 @@
 
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
+#define CONFIG_SYS_QE_FW_ADDR     0x67f40000
+
 /*
  * Environment
  */
-- 
cgit v0.10.2


From d8222dbe42e17c49c2f904400c711ef58e3e06d8 Mon Sep 17 00:00:00 2001
From: Tang Yuantian <Yuantian.Tang@freescale.com>
Date: Thu, 9 Oct 2014 16:11:37 +0800
Subject: arm: ls102xa: Fixed a register definition error

There are 8 SCFG_SPARECR registers in SCFG memory block, not one.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b5db720 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,7 +182,7 @@ struct ccsr_scfg {
 	u32 etsecmcr;
 	u32 sdhciovserlcr;
 	u32 resv14[61];
-	u32 sparecr;
+	u32 sparecr[8];
 };
 
 /* Clocking */
-- 
cgit v0.10.2


From 5632d15cf45a6e9f0559c80e1ca675d64f1650bc Mon Sep 17 00:00:00 2001
From: Zhao Qiang <B45475@freescale.com>
Date: Tue, 4 Nov 2014 13:46:16 +0800
Subject: u_qe: add u_qe_upload_firmware for u_qe

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b545ec9..bc94673 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -188,7 +188,7 @@ void u_qe_init(void)
 	uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
 	qe_immr = (qe_map_t *)qe_base;
 
-	qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+	u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
 	out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
 }
 #endif
@@ -444,6 +444,131 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	return 0;
 }
 
+#ifdef CONFIG_U_QE
+/*
+ * Upload a microcode to the I-RAM at a specific address.
+ *
+ * See docs/README.qe_firmware for information on QE microcode uploading.
+ *
+ * Currently, only version 1 is supported, so the 'version' field must be
+ * set to 1.
+ *
+ * The SOC model and revision are not validated, they are only displayed for
+ * informational purposes.
+ *
+ * 'calc_size' is the calculated size, in bytes, of the firmware structure and
+ * all of the microcode structures, minus the CRC.
+ *
+ * 'length' is the size that the structure says it is, including the CRC.
+ */
+int u_qe_upload_firmware(const struct qe_firmware *firmware)
+{
+	unsigned int i;
+	unsigned int j;
+	u32 crc;
+	size_t calc_size = sizeof(struct qe_firmware);
+	size_t length;
+	const struct qe_header *hdr;
+#ifdef CONFIG_DEEP_SLEEP
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+	if (!firmware) {
+		printf("Invalid address\n");
+		return -EINVAL;
+	}
+
+	hdr = &firmware->header;
+	length = be32_to_cpu(hdr->length);
+
+	/* Check the magic */
+	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+	    (hdr->magic[2] != 'F')) {
+		printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
+		return -EPERM;
+	}
+
+	/* Check the version */
+	if (hdr->version != 1) {
+		printf("Unsupported version\n");
+		return -EPERM;
+	}
+
+	/* Validate some of the fields */
+	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+		printf("Invalid data\n");
+		return -EINVAL;
+	}
+
+	/* Validate the length and check if there's a CRC */
+	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
+
+	for (i = 0; i < firmware->count; i++)
+		/*
+		 * For situations where the second RISC uses the same microcode
+		 * as the first, the 'code_offset' and 'count' fields will be
+		 * zero, so it's okay to add those.
+		 */
+		calc_size += sizeof(u32) *
+			be32_to_cpu(firmware->microcode[i].count);
+
+	/* Validate the length */
+	if (length != calc_size + sizeof(u32)) {
+		printf("Invalid length\n");
+		return -EPERM;
+	}
+
+	/*
+	 * Validate the CRC.  We would normally call crc32_no_comp(), but that
+	 * function isn't available unless you turn on JFFS support.
+	 */
+	crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
+	if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
+		printf("Firmware CRC is invalid\n");
+		return -EIO;
+	}
+
+	/*
+	 * If the microcode calls for it, split the I-RAM.
+	 */
+	if (!firmware->split) {
+		out_be16(&qe_immr->cp.cercr,
+			 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+	}
+
+	if (firmware->soc.model)
+		printf("Firmware '%s' for %u V%u.%u\n",
+		       firmware->id, be16_to_cpu(firmware->soc.model),
+		       firmware->soc.major, firmware->soc.minor);
+	else
+		printf("Firmware '%s'\n", firmware->id);
+
+	/* Loop through each microcode. */
+	for (i = 0; i < firmware->count; i++) {
+		const struct qe_microcode *ucode = &firmware->microcode[i];
+
+		/* Upload a microcode if it's present */
+		if (ucode->code_offset)
+			qe_upload_microcode(firmware, ucode);
+
+		/* Program the traps for this processor */
+		for (j = 0; j < 16; j++) {
+			u32 trap = be32_to_cpu(ucode->traps[j]);
+
+			if (trap)
+				out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+		}
+
+		/* Enable traps */
+		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+	}
+
+	return 0;
+}
+#endif
+
 struct qe_firmware_info *qe_get_firmware_info(void)
 {
 	return qe_firmware_uploaded ? &qe_firmware_info : NULL;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 30484b8..33878f8 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -275,7 +275,6 @@ void *qe_muram_addr(uint offset);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
 void qe_init(uint qe_base);
-void u_qe_init(void);
 void qe_reset(void);
 void qe_assign_page(uint snum, uint para_ram_base);
 int qe_set_brg(uint brg, uint rate);
@@ -286,4 +285,9 @@ void ft_qe_setup(void *blob);
 void qe_init(uint qe_base);
 void qe_reset(void);
 
+#ifdef CONFIG_U_QE
+void u_qe_init(void);
+int u_qe_upload_firmware(const struct qe_firmware *firmware);
+#endif
+
 #endif /* __QE_H__ */
-- 
cgit v0.10.2


From c26c80a1a4e2e2e7e4c9806e9123bf027c02f711 Mon Sep 17 00:00:00 2001
From: Nikhil Badola <nikhil.badola@freescale.com>
Date: Tue, 30 Sep 2014 11:22:43 +0530
Subject: drivers: usb: fsl: Move USB Errata checking code

Move USB Errata checking code from "arch/powerpc" to architecture independent
file "fsl_usb.h" so that errata(s) become independent of the architecture.
For each erratum checking function for PPC arch, define a nop function for
non PPC arch for successful compilation in either case

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3a04a89..349ce52 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -9,6 +9,7 @@
 #include <linux/compiler.h>
 #include <asm/fsl_errata.h>
 #include <asm/processor.h>
+#include <fsl_usb.h>
 #include "fsl_corenet_serdes.h"
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index 64da4bb..b9e2fb0 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -26,59 +26,4 @@ static inline bool has_erratum_a006379(void)
 	return false;
 }
 #endif
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
-static inline bool has_erratum_a006261(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P2041:
-	case SVR_P2040:
-		return IS_SVR_REV(svr, 1, 0) ||
-			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
-	case SVR_P3041:
-		return IS_SVR_REV(svr, 1, 0) ||
-			IS_SVR_REV(svr, 1, 1) ||
-			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
-	case SVR_P5010:
-	case SVR_P5020:
-	case SVR_P5021:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_T4240:
-	case SVR_T4160:
-	case SVR_T4080:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_T1040:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_T2080:
-	case SVR_T2081:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_P5040:
-		return IS_SVR_REV(svr, 1, 0);
-	}
-
-	return false;
-}
-#endif
-
-static inline bool has_erratum_a007075(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_B4860:
-	case SVR_B4420:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_P4080:
-		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
-	}
-	return false;
-}
 #endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45062e6..d5361d7 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,7 +14,7 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 #include <hwconfig.h>
-#include <asm/fsl_errata.h>
+#include <fsl_usb.h>
 
 #include "ehci.h"
 
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 1a6c9c1..66f8934 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -85,4 +85,70 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
 #endif
 
+/* USB Erratum Checking code */
+#ifdef CONFIG_PPC
+static inline bool has_erratum_a006261(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P2041:
+	case SVR_P2040:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P3041:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) ||
+			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P5010:
+	case SVR_P5020:
+	case SVR_P5021:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T4240:
+	case SVR_T4160:
+	case SVR_T4080:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T1040:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T2080:
+	case SVR_T2081:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P5040:
+		return IS_SVR_REV(svr, 1, 0);
+	}
+
+	return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_B4860:
+	case SVR_B4420:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P4080:
+		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+	}
+	return false;
+}
+#else
+static inline bool has_erratum_a006261(void)
+{
+	return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+	return false;
+}
+
+#endif
 #endif /*_ASM_FSL_USB_H_ */
-- 
cgit v0.10.2


From f3dff695e155469c2c62edb7f3d571df8b3b20ad Mon Sep 17 00:00:00 2001
From: Nikhil Badola <nikhil.badola@freescale.com>
Date: Fri, 17 Oct 2014 09:12:07 +0530
Subject: drivers : usb: fsl: Implement usb Erratum A007798 workaround

Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 349ce52..fe3eb06 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -294,6 +294,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (has_erratum_a007075())
 		puts("Work-around for Erratum A007075 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
+	if (has_erratum_a007798())
+		puts("Work-around for Erratum A007798 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4c1774f..7860b40 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -678,6 +678,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007798
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index d5361d7..8f55464 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -130,8 +130,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	in_le32(&ehci->usbmode);
 
-	if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
-	    IS_SVR_REV(get_svr(), 2, 0))
+	if (has_erratum_a007798())
 		set_txfifothresh(ehci, TXFIFOTHRESH);
 
 	return 0;
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 66f8934..e4902aa 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -139,6 +139,12 @@ static inline bool has_erratum_a007075(void)
 	}
 	return false;
 }
+
+static inline bool has_erratum_a007798(void)
+{
+	return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+		IS_SVR_REV(get_svr(), 2, 0);
+}
 #else
 static inline bool has_erratum_a006261(void)
 {
@@ -150,5 +156,10 @@ static inline bool has_erratum_a007075(void)
 	return false;
 }
 
+static inline bool has_erratum_a007798(void)
+{
+	return false;
+}
+
 #endif
 #endif /*_ASM_FSL_USB_H_ */
-- 
cgit v0.10.2


From 3f041f011db6397e4e41faba8433e86fc04e23c2 Mon Sep 17 00:00:00 2001
From: Nikhil Badola <nikhil.badola@freescale.com>
Date: Fri, 17 Oct 2014 11:35:46 +0530
Subject: drivers: usb: fsl: Define USB configs for LS102XA

Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index fc6a475..ba86eea 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -27,7 +27,10 @@
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
+#define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
 #define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
@@ -84,6 +87,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS		1
 #define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #else
 #error SoC not defined
 #endif
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index dd77ad6..897018b 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -163,6 +163,9 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR	0
+#elif defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
 
 /*
-- 
cgit v0.10.2


From 8776cb205e25c4fdba05bd3fb13fe71973cd4c71 Mon Sep 17 00:00:00 2001
From: Nikhil Badola <nikhil.badola@freescale.com>
Date: Fri, 17 Oct 2014 11:37:25 +0530
Subject: ls1: config: Enable USB EHCI Host on LS1021AQDS

Enable USB EHCI Host on LS1021AQDS

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 6b8ee8d..8954d9d 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -279,6 +279,23 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_GENERIC_MMC
 
 /*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+/*
  * eTSEC
  */
 #define CONFIG_TSEC_ENET
-- 
cgit v0.10.2


From 644bc7ec5cee3a93ecb3adc364be6374d3f60a27 Mon Sep 17 00:00:00 2001
From: Jason Jin <Jason.Jin@freescale.com>
Date: Fri, 17 Oct 2014 15:26:32 +0800
Subject: arm: ls102xa: Add snoop disable for slave port 0, 1 and 2

Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index b5db720..9f4fbba 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -448,6 +448,7 @@ struct ccsr_ddr {
 
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index bcfa9b9..5154a85 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -233,6 +233,13 @@ int board_init(void)
 	/* Set CCI-400 control override register to
 	 * enable barrier transaction */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index a90bb09..3e8981b 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -277,6 +277,16 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	fsl_serdes_init();
 	config_serdes_mux();
-- 
cgit v0.10.2


From c207ff612903389f8b32e377fe32be43e6efd8f7 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Fri, 17 Oct 2014 15:26:33 +0800
Subject: arm: ls102xa: Remove bit reversing for SCFG registers

SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R                                   SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31

This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 9f4fbba..b0c267c 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -95,8 +95,6 @@ struct ccsr_gur {
 	u32	sdhcpcr;
 };
 
-#define SCFG_SCFGREVCR_REV		0xffffffff
-#define SCFG_SCFGREVCR_NOREV		0
 #define SCFG_ETSECDMAMCR_LE_BD_FR	0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 5154a85..913dda9 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -140,9 +140,7 @@ int board_early_init_f(void)
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 3e8981b..3f2dc1a 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -255,11 +255,8 @@ int board_early_init_f(void)
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
-	udelay(10);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC
@@ -267,9 +264,7 @@ int board_early_init_f(void)
 #endif
 
 #ifdef CONFIG_FSL_DCU_FB
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 	return 0;
-- 
cgit v0.10.2


From 272c5265ed8f4bf1f02f2d2b38828fbf8939cac3 Mon Sep 17 00:00:00 2001
From: Yuan Yao <yao.yuan@freescale.com>
Date: Fri, 17 Oct 2014 15:26:34 +0800
Subject: ls102xa: ifc: nor: fix the write issue when bytes unaligned

Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash write should swap the
bytes when handle unaligned tail bytes.

Because of the ending, if the date bus width is 16-bits and the
number of bytes is odd, we should swap the byte when write the
last one.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 8954d9d..bb9fbed 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -115,6 +115,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 96b1547..34cec65 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -99,6 +99,7 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /* CPLD */
 
-- 
cgit v0.10.2


From 5175a2885fbb47e4836dcb8ad0ad2214e9b0b3b5 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Fri, 17 Oct 2014 15:26:35 +0800
Subject: arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board

SystemID information could be read through I2C1 from EEPROM
on LS1021ATWR board.

As LS1 is a little-endian processor, getting the version ID by
be32_to_cpu() is wrong. Fix it by using e.version directly.
This change will be compatible for both ARM and PowerPC.

As there is an errata that I2C1 could not work in SD boot,
reading EEPROM through I2C1 is disabled too in SD boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 6144c53..3426b8a 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -90,7 +90,7 @@ static void show_eeprom(void)
 	/* EEPROM tag ID, either CCID or NXID */
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 34cec65..a5d2976 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -161,6 +161,17 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 
+/* EEPROM */
+#ifndef CONFIG_SD_BOOT
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#endif
+
 /*
  * MMC
  */
-- 
cgit v0.10.2


From 0ab172353e14dbdb7278755de6feae3fc4b54c2f Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Fri, 17 Oct 2014 15:26:36 +0800
Subject: arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing

EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or
SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1
as other functionality except RGMII. The workaround is to select
ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 913dda9..d64b24c 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -141,6 +141,7 @@ int board_early_init_f(void)
 
 #ifdef CONFIG_TSEC_ENET
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 #endif
 
 #ifdef CONFIG_FSL_IFC
-- 
cgit v0.10.2