From 6bfa44206e8302e8bf34d553e2b3b6bd2ab5d0dd Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 24 Mar 2014 17:15:50 +0400 Subject: axs101: increase EEPROM page write delay from 32 to 64 msec With 32 milliseconds delay on some boards EEMPROM got written inconsistently. With 64 msec all of our existig boards show properly written EEPROM. Cc: Tom Rini Signed-off-by: Alexey Brodkin diff --git a/include/configs/axs101.h b/include/configs/axs101.h index f6b569a..8d03110 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -103,7 +103,7 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64 /* * SD/MMC configuration -- cgit v0.10.2 From 0cdd762027340ad82fdc2bf7476e8e791529a251 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Thu, 27 Mar 2014 19:30:18 +0400 Subject: axs101: bump DDR size from 256 to 512 Mb Signed-off-by: Alexey Brodkin diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 8d03110..c22d6d0 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -16,7 +16,7 @@ #define CONFIG_SYS_CLK_FREQ 750000000 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -/* dwgmac doesn't work with D$ enabled now */ +/* NAND controller DMA doesn't work correctly with D$ enabled */ #define CONFIG_SYS_DCACHE_OFF /* @@ -40,7 +40,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -- cgit v0.10.2