From 7ee16de58bddaa9619c264313008d7e19300b42a Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Sat, 1 Apr 2017 12:59:25 +0200 Subject: rockchip: rk3399: spl: add UART0 support for SPL The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the serial line available via standardised pins on the edge connector and available on a RS232 connector). To support boards (such as the RK3399-Q7) that require UART0 as a debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate iomux setup to the rk3399 SPL code. As we are already touching this code, we also move the board-specific UART setup (i.e. iomux setup) into board_debug_uart_init(). This will be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT is set. As the RK3399 needs to use its board_debug_uart_init() function, we have Kconfig enable it by default for RK3399 builds. With everything set up to define CONFIG_BAUDRATE via defconfig and with to have the SPL debug UART either on UART0 or UART2, the configs for the RK3399 EVB are then update (the change for the RK3399-Q7 is left for later to not cause issues on applying the change). Signed-off-by: Philipp Tomsich Reviewed-by: Kever Yang Acked-by: Simon Glass diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index b340b05..c424753 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -337,6 +337,14 @@ enum { GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, GRF_SPI2TPM_CSN0 = 1, + /* GRF_GPIO2C_IOMUX */ + GRF_GPIO2C0_SEL_SHIFT = 0, + GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT, + GRF_UART0BT_SIN = 1, + GRF_GPIO2C1_SEL_SHIFT = 2, + GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT, + GRF_UART0BT_SOUT = 1, + /* GRF_GPIO3A_IOMUX */ GRF_GPIO3A0_SEL_SHIFT = 0, GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 5b4caec..2b752ad 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -56,6 +56,7 @@ config ROCKCHIP_RK3399 select SPL select SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index f546529..050f5e1 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -156,20 +156,24 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -#define GRF_EMMCCORE_CON11 0xff77f02c #define SGRF_DDR_RGN_CON16 0xff330040 -void board_init_f(ulong dummy) -{ - struct udevice *pinctrl; - struct udevice *dev; - int ret; - /* Example code showing how to enable the debug UART on RK3288 */ +void board_debug_uart_init(void) +{ #include - /* Enable early UART2 channel C on the RK3399 */ #define GRF_BASE 0xff770000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3399 */ + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C0_SEL_MASK, + GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C1_SEL_MASK, + GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); +#else + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); @@ -180,6 +184,16 @@ void board_init_f(ulong dummy) rk_clrsetreg(&grf->soc_con7, GRF_UART_DBG_SEL_MASK, GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); +#endif +} + +#define GRF_EMMCCORE_CON11 0xff77f02c +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + #define EARLY_UART #ifdef EARLY_UART /* -- cgit v0.10.2