Merge branch 'b4860rev2' into sdk-kernel-3.8

9 files changed, 203 insertions, 30 deletions

diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 50b626c..deb9c61 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -100,7 +100,7 @@ CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)
 CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)
 
 KBUILD_CPPFLAGS	+= -Iarch/$(ARCH)
-KBUILD_AFLAGS	+= -Iarch/$(ARCH)
+KBUILD_AFLAGS	+= -msoft-float -Iarch/$(ARCH)
 KBUILD_CFLAGS	+= -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
 CPP		= $(CC) -E $(KBUILD_CFLAGS)
 
@@ -142,11 +142,14 @@ endif
 ifeq ($(CONFIG_E500),y)
 ifeq ($(CONFIG_64BIT),y)
 KBUILD_CFLAGS		+= -mcpu=e5500
+KBUILD_AFLAGS		+= -mcpu=e5500
 else
 ifeq ($(CONFIG_PPC_E500MC),y)
 KBUILD_CFLAGS		+= -mcpu=e500mc
+KBUILD_AFLAGS		+= -mcpu=e500mc
 else
 KBUILD_CFLAGS		+= -mcpu=8540
+KBUILD_AFLAGS		+= -mcpu=8540
 endif
 endif
 endif
diff --git a/arch/powerpc/include/asm/fsl_kibo.h b/arch/powerpc/include/asm/fsl_kibo.h
new file mode 100644
index 0000000..f0a4166
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_kibo.h
@@ -0,0 +1,90 @@
+/**
+ * Freecale shared cluster L2 cache (Kibo)
+ *
+ * Authors: Varun Sethi <Varun.Sethi@freescale.com>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_FSL_KIBO_H__
+#define __ASM_POWERPC_FSL_KIBO_H__
+#ifdef __KERNEL__
+
+/**
+ * Shared cluster L2 cache(Kibo) Registers.
+ * 
+ * Shared cluster L2 cache or Kibo is a backside cache shared by e6500 and
+ * star core DSP cores in a cluster. Kibo is present on Freescale SOCs (T4/B4)
+ * following the chassis 2 specification. 
+ * 
+ * These registers are memory mapped and can be accessed through the CCSR space.
+ *
+ */
+
+#define CLUSTER_L2_STASH_MASK 0xff
+
+struct ccsr_cluster_l2 {
+	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
+	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
+	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
+	u8  res_0c[500];/* 0x00c - 0x1ff */
+	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
+	u8  res_204[4];
+	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
+	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
+	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
+	u8  res_214[4];
+	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
+	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
+	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
+	u8  res_224[4];
+	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
+	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
+	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
+	u8  res_234[4];
+	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
+	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
+	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
+	u8  res244[4];
+	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
+	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
+	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
+	u8  res_254[4];
+	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
+	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
+	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
+	u8  res_264[4];
+	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
+	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
+	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
+	u8  res274[4];
+	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
+	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
+	u8  res_280[0xb80]; /* 0x280 - 0xdff */
+	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
+	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
+	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+	u8  res_e0c[20];	/* 0xe0c - 0x01f */
+	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
+	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
+	u32 l2errdet;	/* 0xe40 L2 cache error detect */
+	u32 l2errdis;	/* 0xe44 L2 cache error disable */
+	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
+	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
+	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
+	u32 l2erraddr;	/* 0xe54 L2 cache error address */
+	u32 l2errctl;	/* 0xe58 L2 cache error control */
+	u8  res_e5c[0xa4];	/* 0xe5c - 0xf00 */
+	u32 l2hdbcr0;	/* 0xf00 L2 cache hardware debugcontrol register 0 */
+	u32 l2hdbcr1;	/* 0xf00 L2 cache hardware debugcontrol register 1 */
+	u32 l2hdbcr2;	/* 0xf00 L2 cache hardware debugcontrol register 2 */
+};
+#endif /*__KERNEL__ */
+#endif /*__ASM_POWERPC_FSL_KIBO_H__*/
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
index 4d466d6..84a5de7 100644
--- a/drivers/iommu/fsl_pamu.c
+++ b/drivers/iommu/fsl_pamu.c
@@ -32,6 +32,7 @@
 #include <asm/io.h>
 #include <asm/bitops.h>
 #include <asm/fsl_guts.h>
+#include <asm/fsl_kibo.h>
 
 #include "fsl_pamu.h"
 
@@ -529,6 +530,72 @@ void get_ome_index(u32 *omi_index, struct device *dev)
 		*omi_index = OMI_QMAN_PRIV;
 }
 
+/*
+ * We get the stash id programmed by SDOS from the shared
+ * cluster L2 l2csr1 register.
+ */
+static u32 get_dsp_l2_stash_id(u32 cluster)
+{
+	const u32 *prop;
+	struct device_node *node;
+	struct device_node *dsp_cpu_node;
+	struct ccsr_cluster_l2 *l2cache_regs;
+	u32 stash_id;
+
+	for_each_compatible_node(node, NULL, "fsl,sc3900-cluster") {
+		prop = of_get_property(node, "reg", 0);
+		if (!prop) {
+			pr_err("missing reg property in dsp cluster %s\n",
+				node->full_name);
+			of_node_put(node);
+			return ~(u32)0;
+		}
+
+		if (*prop == cluster) {
+			dsp_cpu_node = of_find_compatible_node(node, NULL, "fsl,sc3900");
+			if (!dsp_cpu_node) {
+				pr_err("missing dsp cpu node in dsp cluster %s\n",
+					node->full_name);
+				of_node_put(node);
+				return ~(u32)0;
+			}
+			of_node_put(node);
+
+			prop = of_get_property(dsp_cpu_node, "next-level-cache", 0);
+			if (!prop) {
+				pr_err("missing next level cache property in dsp cpu %s\n",
+					node->full_name);
+				of_node_put(dsp_cpu_node);
+				return ~(u32)0;
+			}
+			of_node_put(dsp_cpu_node);
+
+			node = of_find_node_by_phandle(*prop);
+			if (!node) {
+				pr_err("Invalid node for cache hierarchy %s\n",
+					node->full_name);
+				return ~(u32)0;
+			}
+
+			l2cache_regs = of_iomap(node, 0);
+			if (!l2cache_regs) {
+				pr_err("failed to map cluster l2 cache registers %s\n",
+					node->full_name);
+				of_node_put(node);
+				return ~(u32)0;
+			}
+
+			stash_id = in_be32(&l2cache_regs->l2csr1) &
+					 CLUSTER_L2_STASH_MASK;
+			of_node_put(node);
+			iounmap(l2cache_regs);
+
+			return stash_id;
+		}
+	}
+	return ~(u32)0;
+}
+
 /**
  * get_stash_id - Returns stash destination id corresponding to a
  *                cache type and vcpu.
@@ -546,6 +613,10 @@ u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
 	int len, found = 0;
 	int i;
 
+	/* check for DSP L2 cache */
+	if (stash_dest_hint == IOMMU_ATTR_CACHE_DSP_L2) {
+		return get_dsp_l2_stash_id(vcpu);
+	}
 	/* Fastpath, exit early if L3/CPC cache is target for stashing */
 	if (stash_dest_hint == IOMMU_ATTR_CACHE_L3) {
 		node = of_find_matching_node(NULL, l3_device_ids);
@@ -707,26 +778,12 @@ static void __init setup_omt(struct ome *omt)
 	ome->moe[IOE_DIRECT0_IDX] = EOE_LDEC | EOE_VALID;
 	ome->moe[IOE_DIRECT1_IDX] = EOE_LDEC | EOE_VALID;
 
-	/* Configure OMI_DMA */
-	ome = &omt[OMI_DMA];
-	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA;
-	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
-
-	/* Configure OMI_DMA_READI */
-	ome = &omt[OMI_DMA_READI];
-	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READI;
-	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_READI;
-	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA;
-	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
-
-	/* Configure OMI_MAPLE */
-	ome = &omt[OMI_MAPLE];
-	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA;
-	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
+	/* Configure OMI_DSP */
+	ome = &omt[OMI_DSP];
+	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_RWNITC;
+	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RWNITC;
+	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSAO;
+	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO;
 }
 
 /*
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index 99c182d..b7b915e 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -800,6 +800,11 @@ static  int configure_domain_geometry(struct iommu_domain *domain, void *data)
 	return 0;
 }
 
+static inline int check_attr_window(u32 wnd, struct fsl_dma_domain *dma_domain)
+{
+	return ((~wnd != 0) && (wnd >= dma_domain->win_cnt));
+}
+
 /* Set the domain operation mapping attribute */
 static int configure_domain_op_map(struct fsl_dma_domain *dma_domain,
 				    void *data)
@@ -818,7 +823,8 @@ static int configure_domain_op_map(struct fsl_dma_domain *dma_domain,
 		return -ENODEV;
 	}
 
-	if (omi_attr->omi >= OMI_MAX) {
+	if (omi_attr->omi >= OMI_MAX ||
+		check_attr_window(omi_attr->window, dma_domain)) {
 		pr_err("Invalid operation mapping index\n");
 		spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
 		return -EINVAL;
@@ -863,7 +869,8 @@ static int configure_domain_stash(struct fsl_dma_domain *dma_domain, void *data)
 
 	stash_id = get_stash_id(stash_attr->cache,
 					    stash_attr->cpu);
-	if (~stash_id == 0) {
+	if ((~stash_id == 0) ||
+		 check_attr_window(stash_attr->window, dma_domain)) {
 		pr_err("Invalid stash attributes\n");
 		spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
 		return -EINVAL;
diff --git a/drivers/net/ethernet/freescale/dpa/mac.c b/drivers/net/ethernet/freescale/dpa/mac.c
index 8959592..73f4532 100644
--- a/drivers/net/ethernet/freescale/dpa/mac.c
+++ b/drivers/net/ethernet/freescale/dpa/mac.c
@@ -351,7 +351,7 @@ static int __cold mac_probe(struct platform_device *_of_dev)
 			goto _return_dev_set_drvdata;
 		}
 
-		sprintf(mac_dev->fixed_bus_id, PHY_ID_FMT, "0", phy_id[0]);
+		sprintf(mac_dev->fixed_bus_id, PHY_ID_FMT, "fixed-0", phy_id[0]);
 	}
 
 	_errno = mac_dev->init(mac_dev);
diff --git a/drivers/net/ethernet/freescale/fman/src/wrapper/lnxwrp_fm.c b/drivers/net/ethernet/freescale/fman/src/wrapper/lnxwrp_fm.c
index b136b77..10de0ad 100644
--- a/drivers/net/ethernet/freescale/fman/src/wrapper/lnxwrp_fm.c
+++ b/drivers/net/ethernet/freescale/fman/src/wrapper/lnxwrp_fm.c
@@ -462,6 +462,12 @@ static const struct qe_firmware *FindFmanMicrocode(void)
     /* Returning NULL here forces the reuse of the IRAM content */
     return NULL;
 }
+#define SVR_SECURITY_MASK    0x00080000
+#define SVR_PERSONALITY_MASK 0x0000FF00
+#define SVR_VER_IGNORE_MASK (SVR_SECURITY_MASK | SVR_PERSONALITY_MASK)
+#define SVR_B4860_REV1_VALUE 0x86800010
+#define SVR_B4860_REV2_VALUE 0x86800020
+
 
 static t_LnxWrpFmDev * ReadFmDevTreeNode (struct platform_device *of_dev)
 {
@@ -517,6 +523,17 @@ static t_LnxWrpFmDev * ReadFmDevTreeNode (struct platform_device *of_dev)
         return NULL;
     }
 
+    {
+        uint32_t svr;
+
+        svr = mfspr(SPRN_SVR);
+
+        if ((svr & ~SVR_VER_IGNORE_MASK) == SVR_B4860_REV2_VALUE) {
+            res.end = 0x80000;
+            res.start = 0;
+        }
+    }
+
     p_LnxWrpFmDev->fmBaseAddr = 0;
     p_LnxWrpFmDev->fmPhysBaseAddr = res.start;
     p_LnxWrpFmDev->fmMemSize = res.end + 1 - res.start;
diff --git a/drivers/staging/fsl_qbman/qman_debugfs.c b/drivers/staging/fsl_qbman/qman_debugfs.c
index 6b4dc046..ede3d40 100644
--- a/drivers/staging/fsl_qbman/qman_debugfs.c
+++ b/drivers/staging/fsl_qbman/qman_debugfs.c
@@ -1387,7 +1387,7 @@ static int query_ceetm_xsfdr_show(struct seq_file *file, void *offset)
 	enum qm_dc_portal portal;
 
 
-	if ((qman_ip_rev & 0xFF00) < QMAN_REV31)
+	if (qman_ip_rev < QMAN_REV31)
 		return -EINVAL;
 
 	portal = query_ceetm_xsfdr_data.dcp_portal;
@@ -1399,7 +1399,7 @@ static int query_ceetm_xsfdr_show(struct seq_file *file, void *offset)
 	}
 
 	seq_printf(file, "DCP%d: CEETM_XSFDR_IN_USE number is %u\n", portal,
-						(xsfdr_in_use & 0x1FF));
+						(xsfdr_in_use & 0x1FFF));
 	return 0;
 }
 
diff --git a/include/linux/fsl_dpa_offload.h b/include/linux/fsl_dpa_offload.h
index c85c4c6..b5f4e6e 100644
--- a/include/linux/fsl_dpa_offload.h
+++ b/include/linux/fsl_dpa_offload.h
@@ -162,7 +162,7 @@ struct ipv4_header {
 	uint8_t				*options;
 
 	/* Size of IPv4 options buffer. Zero for no options. */
-	unsigned int			options_size;
+	uint8_t				options_size;
 };
 
 /* Description of the VLAN header */
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 5153c0c..992d45a 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -45,6 +45,7 @@ enum stash_target {
 	IOMMU_ATTR_CACHE_L1 = 1,
 	IOMMU_ATTR_CACHE_L2,
 	IOMMU_ATTR_CACHE_L3,
+	IOMMU_ATTR_CACHE_DSP_L2,
 };
 
 /* This attribute corresponds to IOMMUs capable of generating
@@ -89,9 +90,7 @@ enum omap_index {
 	OMI_QMAN_PRIV,
 	OMI_CAAM,
 	OMI_PMAN,
-	OMI_DMA,
-	OMI_DMA_READI,
-	OMI_MAPLE,
+	OMI_DSP,
 	OMI_MAX,
 };