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author | Marek Belisko <marek.belisko@gmail.com> | 2013-05-03 05:53:22 (GMT) |
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committer | Mike Turquette <mturquette@linaro.org> | 2013-05-29 22:09:15 (GMT) |
commit | 67e1e2268e598861dc771e3c976daf07db380638 (patch) | |
tree | 35318b5ab04a258c7da38578f2d614f6a8461b58 | |
parent | 056f3d58db6f7d19be7dbc2aab8d049f28e20d6e (diff) | |
download | linux-fsl-qoriq-67e1e2268e598861dc771e3c976daf07db380638.tar.xz |
clk: si5351: Fix clkout rate computation.
Rate was incorrectly computed because we read from wrong divider register.
Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
-rw-r--r-- | drivers/clk/clk-si5351.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 8927284..cf39e53 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, unsigned char reg; unsigned char rdiv; - if (hwdata->num > 5) + if (hwdata->num <= 5) reg = si5351_msynth_params_address(hwdata->num) + 2; else reg = SI5351_CLK6_7_OUTPUT_DIVIDER; |