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| author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2014-04-23 08:24:14 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-29 00:17:03 (GMT) |
| commit | ce8df95ce58feeee6fe2af8181680b3a9a5aea58 (patch) | |
| tree | a77beb2bece738d2d2ae24653270cc936fe2feb9 | |
| parent | 711f068d35a2edc26f5b039c82bc97b41b56c8ca (diff) | |
| download | linux-fsl-qoriq-ce8df95ce58feeee6fe2af8181680b3a9a5aea58.tar.xz | |
powerpc/deepsleep: Disable CPC speculation to avoid deep sleep hang
Disable CPC speculation to avoid deep sleep hang, especially
in secure boot mode. This bit will be cleared automatically
when resuming from deep sleep.
Change-Id: I2e4debed63eed39fa059c42de5b7f49b5d6c48f3
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/11362
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
| -rw-r--r-- | arch/powerpc/platforms/85xx/deepsleep.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/deepsleep.c b/arch/powerpc/platforms/85xx/deepsleep.c index 4a41020..88dee90 100644 --- a/arch/powerpc/platforms/85xx/deepsleep.c +++ b/arch/powerpc/platforms/85xx/deepsleep.c @@ -21,6 +21,9 @@ #define SIZE_1MB 0x100000 #define SIZE_2MB 0x200000 +#define CPC_CPCHDBCR0 0x10f00 +#define CPC_CPCHDBCR0_SPEC_DIS 0x08000000 + #define CCSR_SCFG_DPSLPCR 0xfc000 #define CCSR_SCFG_DPSLPCR_WDRR_EN 0x1 #define CCSR_SCFG_SPARECR2 0xfc504 @@ -169,6 +172,13 @@ int fsl_enter_epu_deepsleep(void) clrbits32(ccsr_base + CCSR_GPIO1_GPODR, CCSR_GPIO1_GPDIR_29); setbits32(ccsr_base + CCSR_GPIO1_GPDIR, CCSR_GPIO1_GPDIR_29); + /* + * Disable CPC speculation to avoid deep sleep hang, especially + * in secure boot mode. This bit will be cleared automatically + * when resuming from deep sleep. + */ + setbits32(ccsr_base + CPC_CPCHDBCR0, CPC_CPCHDBCR0_SPEC_DIS); + fsl_dp_fsm_setup(dcsr_base, NULL); fsl_dp_enter_low(ccsr_base, dcsr_base, pld_base, pld_flag); |