diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-07-02 21:23:01 (GMT) |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-07-02 21:23:01 (GMT) |
commit | ee1a8d402e7e204d57fb108aa40003b6d1633036 (patch) | |
tree | 3abf4be63d11bbbd04c89bd668a17533f942b911 /arch/arm/boot/dts/socfpga.dtsi | |
parent | 40e71e7015ab85c8606f50736525220948a3b24b (diff) | |
parent | 9686bb66a4c50e43ffee903a9fc62237ee2de1e6 (diff) | |
download | linux-fsl-qoriq-ee1a8d402e7e204d57fb108aa40003b6d1633036.tar.xz |
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree changes from Arnd Bergmann:
"These changes from 30 individual branches for the most part update
device tree files, but there are also a few source code changes that
have crept in this time, usually in order to atomically move over a
driver from using hardcoded data to DT probing.
A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
ARM: at91: dt: rm9200ek: add spi support
ARM: at91: dt: rm9200: add spi support
ARM: at91/DT: at91sam9n12: add SPI DMA client infos
ARM: at91/DT: sama5d3: add SPI DMA client infos
ARM: at91/DT: fix SPI compatibility string
ARM: Kirkwood: Fix the internal register ranges translation
ARM: dts: bcm281xx: change comment to C89 style
ARM: mmc: bcm281xx SDHCI driver (dt mods)
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
ARM: dts: omap4-panda: Fix DVI EDID reads
ARM: dts: omap4-panda: Add USB Host support
arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
ARM: shmobile: irqpin: add a DT property to enable masking on parent
ARM: dts: AM43x EPOS EVM support
ARM: dts: OMAP5: Add bandgap DT entry
ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
...
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 217 |
1 files changed, 215 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 16a6e13..bee62a2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -23,6 +23,7 @@ aliases { ethernet0 = &gmac0; + ethernet1 = &gmac1; serial0 = &uart0; serial1 = &uart1; timer0 = &timer0; @@ -94,6 +95,12 @@ compatible = "fixed-clock"; }; + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <10000000>; + }; + main_pll: main_pll { #address-cells = <1>; #size-cells = <0>; @@ -235,16 +242,222 @@ reg = <0xD4>; }; }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + s2f_user0_clk: s2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + s2f_user1_clk: s2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&s2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; }; }; - gmac0: stmmac@ff700000 { + gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = <0xff700000 0x2000>; interrupts = <0 115 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - phy-mode = "gmii"; + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + status = "disabled"; }; L2: l2-cache@fffef000 { |