diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2009-12-09 01:47:17 (GMT) |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-12-12 00:00:47 (GMT) |
| commit | 911bd7395c4aa4e74b13aab790ca1500c59fae02 (patch) | |
| tree | 6fdca6b205015558663dcfa523f87d6c6ffa7afa /arch/arm/mach-omap2/clock44xx_data.c | |
| parent | 16975a79c8e6ee424331f52649f2351d33c7b972 (diff) | |
| download | linux-fsl-qoriq-911bd7395c4aa4e74b13aab790ca1500c59fae02.tar.xz | |
ARM: OMAP4: PM: Add init api for DPLL nodes
An api at init for all dpll nodes seem to be
needed to reparent the dpll clk node to its
bypass clk in case the dpll is in bypass.
If not done this causes sequencing issues at init
during propogate_rate.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 9ae526e..2210e22 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -278,6 +278,7 @@ static struct clk dpll_abe_ck = { .name = "dpll_abe_ck", .parent = &abe_dpll_refclk_mux_ck, .dpll_data = &dpll_abe_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, @@ -439,6 +440,7 @@ static struct clk dpll_core_ck = { .name = "dpll_core_ck", .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_core_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_null, .recalc = &omap3_dpll_recalc, .flags = CLOCK_IN_OMAP4430, @@ -665,6 +667,7 @@ static struct clk dpll_iva_ck = { .name = "dpll_iva_ck", .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_iva_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, @@ -727,6 +730,7 @@ static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_mpu_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, @@ -802,6 +806,7 @@ static struct clk dpll_per_ck = { .name = "dpll_per_ck", .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_per_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, @@ -924,6 +929,7 @@ static struct clk dpll_unipro_ck = { .name = "dpll_unipro_ck", .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_unipro_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, @@ -981,6 +987,7 @@ static struct clk dpll_usb_ck = { .name = "dpll_usb_ck", .parent = &dpll_sys_ref_clk, .dpll_data = &dpll_usb_dd, + .init = &omap2_init_dpll_parent, .ops = &clkops_noncore_dpll_ops, .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, |