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| author | Mihai Caraman <mihai.caraman@freescale.com> | 2013-04-23 19:33:41 (GMT) |
|---|---|---|
| committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-04-24 13:55:42 (GMT) |
| commit | 3bbb7ca5b85b10e407126047701bbb2f76023bfd (patch) | |
| tree | 99e1f51ad9476e6d456c4dbce80e8031034ab07c /arch/powerpc/include/asm/pmac_pfunc.h | |
| parent | 71dc253e9bfd7f9930f16ba9fa158d22276ac601 (diff) | |
| download | linux-fsl-qoriq-3bbb7ca5b85b10e407126047701bbb2f76023bfd.tar.xz | |
KVM: PPC: e500mc: Workaround guest missing tlbwe conditional
e6500 has threads but does not have TLB write conditional. Currently HW
threads are exposed to guests as cores so locks are not an option.
Workaround this for guests not allowing one core's threads to use same LPID
simultaneous. The VM's LPID allocation scheme associate one LPID per HW
tread index. This limits the number of VM's to (number of LPIDs - 1)/
(threads per core), which for T4240 processor means 31.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Ib1ba743f0f81084decbb26ebcef00d49df814c6c
Reviewed-on: http://git.am.freescale.net:8181/1750
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/pmac_pfunc.h')
0 files changed, 0 insertions, 0 deletions