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| author | J. German Rivera <Jose.G.Rivera@freescale.com> | 2013-09-18 19:14:10 (GMT) |
|---|---|---|
| committer | J. German Rivera <German.Rivera@freescale.com> | 2013-09-18 19:14:10 (GMT) |
| commit | 60c3617331c9a50e9b63f9e9cdcdc7e93899d0ff (patch) | |
| tree | 9b711300b5807b5fdfc3793d65d8d46775aed499 /arch/powerpc/kernel/cpu_setup_fsl_booke.S | |
| parent | 356c21aec7dcc9046d27c43323cf031e794c4a75 (diff) | |
| parent | ca76b6d2649931245f4ca4bf7106943f978a9d42 (diff) | |
| download | linux-fsl-qoriq-60c3617331c9a50e9b63f9e9cdcdc7e93899d0ff.tar.xz | |
Merge branch 'sdk-v1.4.x' into sdk-kernel-3.8
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_fsl_booke.S')
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_fsl_booke.S | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index dbeff8c..f5ee308 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -53,12 +53,84 @@ _GLOBAL(__e500_dcache_setup) isync blr +_GLOBAL(has_pw20_altivec_idle) + /* 0 false, 1 true */ + li r3, 0 + + /* PW20 & AltiVec idle feature only exists for E6500 */ + mfspr r0, SPRN_PVR + rlwinm r11, r0, 16, 16, 31 + lis r12, 0 + ori r12, r12, PVR_VER_E6500@l + cmpw r11, r12 + bne 2f + + /* Fix erratum, e6500 rev1 does not support PW20 & AltiVec idle */ + rlwinm r11, r0, 0, 16, 31 + cmpwi r11, 0x20 + blt 2f + li r3, 1 +2: + blr + +/* + * FIXME - we haven't yet done testing to determine a reasonable default + * value for PW20_WAIT_IDLE_BIT. + */ +#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ +_GLOBAL(setup_pw20_idle) + mflr r10 + bl has_pw20_altivec_idle + mtlr r10 + cmpwi r3, 0 + beq 2f + + mfspr r3, SPRN_PWRMGTCR0 + + /* Set PW20_WAIT bit, enable pw20 state*/ + ori r3, r3, PWRMGTCR0_PW20_WAIT + li r11, PW20_WAIT_IDLE_BIT + + /* Set Automatic PW20 Core Idle Count */ + rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT + + mtspr SPRN_PWRMGTCR0, r3 +2: + blr + +/* + * FIXME - we haven't yet done testing to determine a reasonable default + * value for AV_WAIT_IDLE_BIT. + */ +#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */ +_GLOBAL(setup_altivec_idle) + mflr r10 + bl has_pw20_altivec_idle + mtlr r10 + cmpwi r3, 0 + beq 2f + + mfspr r3, SPRN_PWRMGTCR0 + + /* Enable Altivec Idle */ + oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h + li r11, AV_WAIT_IDLE_BIT + + /* Set Automatic AltiVec Idle Count */ + rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT + + mtspr SPRN_PWRMGTCR0, r3 +2: + blr + #ifdef CONFIG_PPC_BOOK3E_64 _GLOBAL(__setup_cpu_e6500) mflr r6 #ifdef CONFIG_PPC64 bl .setup_altivec_ivors #endif + bl .setup_pw20_idle + bl .setup_altivec_idle bl __setup_cpu_e5500 mtlr r6 blr @@ -121,6 +193,8 @@ _GLOBAL(__setup_cpu_e5500) _GLOBAL(__restore_cpu_e6500) mflr r5 bl .setup_altivec_ivors + bl .setup_pw20_idle + bl .setup_altivec_idle bl __restore_cpu_e5500 mtlr r5 blr |