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| author | Scott Wood <scottwood@freescale.com> | 2014-11-12 03:14:56 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:41:45 (GMT) |
| commit | 0cc812d4faea6917c73b35e4b5e91780b18522ba (patch) | |
| tree | dea139f12523405f4335ebac8e0ca9111dcc481c /arch/powerpc/mm/fsl_booke_mmu.c | |
| parent | eedd015d79372c682ce69f1804a5796aa96d928e (diff) | |
| download | linux-fsl-qoriq-0cc812d4faea6917c73b35e4b5e91780b18522ba.tar.xz | |
powerpc/fsl: Force coherent memory on e500mc derivatives
In CoreNet systems it is not allowed to mix M and non-M mappings to the
same memory, and coherent DMA accesses are considered to be M mappings
for this purpose. Ignoring this has been observed to cause hard
lockups in non-SMP kernels on e6500.
Furthermore, e6500 implements the LRAT (logical to real address table)
which allows KVM guests to control the WIMGE bits. This means that
KVM cannot force the M bit on the way it usually does, so the guest had
better set it itself.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I083bdc9dd7990d475b8ae48680a8e63012998e93
Reviewed-on: http://git.am.freescale.net:8181/24841
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Diffstat (limited to 'arch/powerpc/mm/fsl_booke_mmu.c')
| -rw-r--r-- | arch/powerpc/mm/fsl_booke_mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c index 37cb697..e52e121 100644 --- a/arch/powerpc/mm/fsl_booke_mmu.c +++ b/arch/powerpc/mm/fsl_booke_mmu.c @@ -114,7 +114,7 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys, tsize = __ilog2(size) - 10; -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) if ((flags & _PAGE_NO_CACHE) == 0) flags |= _PAGE_COHERENT; #endif |