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| author | Scott Wood <scottwood@freescale.com> | 2012-05-22 04:43:41 (GMT) |
|---|---|---|
| committer | Emil Medve <Emilian.Medve@Freescale.com> | 2013-03-21 18:42:14 (GMT) |
| commit | 0dcd97576a8a922fcb524d821b12c5128b9f516d (patch) | |
| tree | ced5aedeaf3be7bf56130ee93d6e8a119e655af0 /arch/powerpc/mm/fsl_booke_mmu.c | |
| parent | c7fc6d737f900ea7272059f02421f14578075b5a (diff) | |
| download | linux-fsl-qoriq-0dcd97576a8a922fcb524d821b12c5128b9f516d.tar.xz | |
powerpc/e6500: hardware tablewalk support
Preliminary support for e6500 hardware tablewalk. This is for simulator
(and rev2) only. On rev1 hardware, be sure to set
CONFIG_PPC_FSL_BUGGY_HW_TABLEWALK.
Locking is introduced to make TLB misses threadsafe. TODO: add locking to
the non-tablewalk miss handlers, which was the main reason for making the
locking conditional.
Signed-off-by: Scott Wood <scott@tyr.buserror.net>
Signed-off-by: Andy Fleming <afleming@freescale.net>
(cherry-picked from commit f071125a3d33816772caa91146936af0716f0f78)
Diffstat (limited to 'arch/powerpc/mm/fsl_booke_mmu.c')
| -rw-r--r-- | arch/powerpc/mm/fsl_booke_mmu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c index 07ba45b..bf06d36b 100644 --- a/arch/powerpc/mm/fsl_booke_mmu.c +++ b/arch/powerpc/mm/fsl_booke_mmu.c @@ -52,6 +52,7 @@ #include <asm/smp.h> #include <asm/machdep.h> #include <asm/setup.h> +#include <asm/paca.h> #include "mmu_decl.h" @@ -192,6 +193,13 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx) } tlbcam_index = i; +#ifdef CONFIG_PPC64 + get_paca()->tlb_per_core.esel_next = i; + get_paca()->tlb_per_core.esel_max = + mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY; + get_paca()->tlb_per_core.esel_first = i; +#endif + return amount_mapped; } |