diff options
| author | Scott Wood <scottwood@freescale.com> | 2014-03-10 22:29:38 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-03-28 14:00:19 (GMT) |
| commit | a47e780996b3bcfc715f1dede33e9351fbc5316b (patch) | |
| tree | 59e6dc8e17df635a23c13078209d35fabc961c98 /arch/powerpc/mm | |
| parent | 237ceb2db2b69f35db2f00891d1185b74a33bc8e (diff) | |
| download | linux-fsl-qoriq-a47e780996b3bcfc715f1dede33e9351fbc5316b.tar.xz | |
powerpc/booke64: Critical and machine check exception support
Add special state saving for critical and machine check exceptions.
Most of this code could be used to handle debug exceptions taken from
kernel space, but actually doing so is outside the scope of this patch.
The various critical and machine check exceptions now point to their
real handlers, rather than hanging the kernel.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: Id3ef3d2c17b582508f36c10a4d0e96e540ca5284
Reviewed-on: http://git.am.freescale.net:8181/10269
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 271ae4b..113c766 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c @@ -153,6 +153,15 @@ int mmu_vmemmap_psize; /* Page size used for the virtual mem map */ int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */ unsigned long linear_map_top; /* Top of linear mapping */ + +/* + * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug + * exceptions. This is used for bolted and e6500 TLB miss handlers which + * do not modify this SPRG in the TLB miss code; for other TLB miss handlers, + * this is set to zero. + */ +int extlb_level_exc; + #endif /* CONFIG_PPC64 */ #ifdef CONFIG_PPC_FSL_BOOK3E @@ -588,6 +597,7 @@ static void setup_mmu_htw(void) patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e); break; case PPC_HTW_FSL: + extlb_level_exc = EX_TLB_SIZE; patch_exception(0x1c0, exc_data_tlb_miss_fsl_htw_book3e); patch_exception(0x1e0, exc_instruction_tlb_miss_fsl_htw_book3e); break; @@ -682,6 +692,7 @@ static void __early_init_mmu(int boot_cpu) } if (book3e_htw_mode == PPC_HTW_NONE) { + extlb_level_exc = EX_TLB_SIZE; patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e); } |