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author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2014-04-29 09:27:51 (GMT) |
---|---|---|
committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-30 12:49:49 (GMT) |
commit | f545f6ba27c0e36c6a81a4ed003247dac938cc75 (patch) | |
tree | 070395c2495c6c08ae3177cbfe9f2086e01ba041 /arch/powerpc/platforms | |
parent | b60a25ed3b3a01a450bc4d6711025620a1a9e842 (diff) | |
download | linux-fsl-qoriq-f545f6ba27c0e36c6a81a4ed003247dac938cc75.tar.xz |
powerpc/t104x: fix deep sleep resume problem in 32-bit mode
Kernel in 32-bit mode can not resume to the command shell after waking
from deep sleep.
Changes:
* change fsl_booke_entry_mapping.S to make it work under deep sleep
context
* fix bugs in sleep.S
Change-Id: Ic5186267ae82d12165029093b49c257bba3a3cc1
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/11665
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r-- | arch/powerpc/platforms/85xx/sleep.S | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/powerpc/platforms/85xx/sleep.S b/arch/powerpc/platforms/85xx/sleep.S index cf4da3c..9c7c0f3 100644 --- a/arch/powerpc/platforms/85xx/sleep.S +++ b/arch/powerpc/platforms/85xx/sleep.S @@ -1071,8 +1071,10 @@ _GLOBAL(fsl_booke_deep_sleep_resume) /* disable interrupts */ FSL_DIS_ALL_IRQ +#define ENTRY_DEEPSLEEP_SETUP #define ENTRY_MAPPING_BOOT_SETUP #include <../../kernel/fsl_booke_entry_mapping.S> +#undef ENTRY_DEEPSLEEP_SETUP #undef ENTRY_MAPPING_BOOT_SETUP li r3, 0 @@ -1083,10 +1085,10 @@ _GLOBAL(fsl_booke_deep_sleep_resume) LOAD_REG_ADDR(r3, tlbcam_index) lwz r3, 0(r3) mtctr r3 - li r0, 0 -3: mr r3, r0 + li r9, 0 +3: mr r3, r9 bl loadcam_entry - addi r0, r0, 1 + addi r9, r9, 1 bdnz 3b /* restore cpu registers */ @@ -1095,9 +1097,11 @@ _GLOBAL(fsl_booke_deep_sleep_resume) /* restore return address */ LOAD_REG_ADDR(r3, buf_tmp) - ld r4, 0(r3) + lwz r4, 16(r3) + mtspr SPRN_TCR, r4 + lwz r4, 0(r3) mtlr r4 - ld r4, 8(r3) + lwz r4, 8(r3) mtmsr r4 blr |