Updates to device trees for B4860 for DSP clusters and their L2 caches

B4860 has 1 PPC core cluster and 3 DSP core clusters.
Similarly B4420 has 1 PPC core cluster and 1 DSP core cluster.

Each DSP core cluster consists of 2 SC3900 cores and a shared L2 cache.

1. Add DSP clusters for B4420
2. Reorganized the L2 cache nodes such that they now appear in only the
soc specific dtsi files(b4860si-post.dtsi and b4420si-post.dtsi).
Earlier they were shown partly in common b4si-post.dtsi and si specific
b4860si-post.dtsi files .
3. Fixed an issue in b4860si-pre.dtsi, now DSP cluster correctly point to their
respective L2 caches

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: Ie09007f4c596fc5947e0b4b005225b8b1f9aa443
Reviewed-on: http://git.am.freescale.net:8181/4005
Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>

5 files changed, 37 insertions, 9 deletions

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index f039c52..0198d22 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -318,5 +318,13 @@
 
 	L2: l2-cache-controller@c20000 {
 		compatible = "fsl,b4420-l2-cache-controller";
+		reg = <0xc20000 0x1000>;
+		next-level-cache = <&cpc>;
+	};
+
+	L2_2: l2-cache-controller@c60000 {
+		compatible = "fsl,b4420-l2-cache-controller";
+		reg = <0xc60000 0x1000>;
+		next-level-cache = <&cpc>;
 	};
 };
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index d56ac22..ee7263b 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -90,4 +90,27 @@
 			next-level-cache = <&L2>;
 		};
 	};
+
+	dsp-clusters {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsp-cluster0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,sc3900-cluster";
+			reg = <0>;
+
+			dsp0: dsp@0 {
+				compatible = "fsl,sc3900";
+				reg = <0>;
+				next-level-cache = <&L2_2>;
+			};
+			dsp1: dsp@1 {
+				compatible = "fsl,sc3900";
+				reg = <1>;
+				next-level-cache = <&L2_2>;
+			};
+		};
+	};
 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 80d0f90..4d35d4f 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -516,6 +516,8 @@
 
 	L2: l2-cache-controller@c20000 {
 		compatible = "fsl,b4860-l2-cache-controller";
+		reg = <0xc20000 0x1000>;
+		next-level-cache = <&cpc>;
 	};
 
 	L2_2: l2-cache-controller@c60000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 61f89b8..e344468 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -137,12 +137,12 @@
 			dsp2: dsp@2 {
 				compatible = "fsl,sc3900";
 				reg = <2>;
-				next-level-cache = <&L2_2>;
+				next-level-cache = <&L2_3>;
 			};
 			dsp3: dsp@3 {
 				compatible = "fsl,sc3900";
 				reg = <3>;
-				next-level-cache = <&L2_2>;
+				next-level-cache = <&L2_3>;
 			};
 		};
 
@@ -155,12 +155,12 @@
 			dsp4: dsp@4 {
 				compatible = "fsl,sc3900";
 				reg = <4>;
-				next-level-cache = <&L2_2>;
+				next-level-cache = <&L2_4>;
 			};
 			dsp5: dsp@5 {
 				compatible = "fsl,sc3900";
 				reg = <5>;
-				next-level-cache = <&L2_2>;
+				next-level-cache = <&L2_4>;
 			};
 		};
 	};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 6e2781e..55ced62 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -329,9 +329,4 @@
 /include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-sec5.3-0.dtsi"
 
-	L2: l2-cache-controller@c20000 {
-		compatible = "fsl,b4-l2-cache-controller";
-		reg = <0xc20000 0x1000>;
-		next-level-cache = <&cpc>;
-	};
 };