diff options
| author | Xie Xiaobo <X.Xie@freescale.com> | 2013-05-28 08:01:43 (GMT) |
|---|---|---|
| committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-05-28 19:54:53 (GMT) |
| commit | 4499236ad9b38705c6cc70177fd13031a64beb75 (patch) | |
| tree | 16d50352e403d662c572fe361313ba05c526dd23 /arch | |
| parent | c71d712ba6f4c00a48b58839e40088f94f9a82be (diff) | |
| download | linux-fsl-qoriq-4499236ad9b38705c6cc70177fd13031a64beb75.tar.xz | |
powerpc/85xx: Disable CTS pin for QE UART0
On P1025TWR board, the UCC7 acted as UART port0. However, The UCC7's
CTS pin is low level in default, it will impact the transmission in
full duplex communication. So disable the Flow control pin - CTS.
The UCC7 UART just can use RXD and TXD pins.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Change-Id: I8ab9b3edb0edb6440ce32a83fbcf0200c8eb54f7
Reviewed-on: http://git.am.freescale.net:8181/2706
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/platforms/85xx/twr_p102x.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 6ed7be5..383eb57 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -139,6 +139,15 @@ static void __init twr_p1025_setup_arch(void) MPC85xx_PMUXCR_QE(12)); iounmap(guts); +#if defined(CONFIG_SERIAL_QE) + /* On P1025TWR board, the UCC7 acted as UART port. + * However, The UCC7's CTS pin is low level in default, + * it will impact the transmission in full duplex + * communication. So disable the Flow control pin PA18. + * The UCC7 UART just can use RXD and TXD pins. + */ + par_io_config_pin(0, 18, 0, 0, 0, 0); +#endif /* Drive PB29 to CPLD low - CPLD will then change * muxing from LBC to QE */ par_io_config_pin(1, 29, 1, 0, 0, 0); |