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author | Haijun Zhang <Haijun.Zhang@freescale.com> | 2013-07-18 06:54:05 (GMT) |
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committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-07-22 22:29:54 (GMT) |
commit | da10e32107ba90d6f481981cc0f40f568e820427 (patch) | |
tree | f99f99b56ee43bc399a0a8a6434b9c1a427c2efa /arch | |
parent | b0dbadb589c333361e388ece255626531ce60fd2 (diff) | |
download | linux-fsl-qoriq-da10e32107ba90d6f481981cc0f40f568e820427.tar.xz |
Update mpc85xx soc models list
Remove some useless functions.
Add some new soc list.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Change-Id: I664c1f0b9fc0544ec1fed7304bae2fc562266676
Reviewed-on: http://git.am.freescale.net:8181/2316
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/include/asm/mpc85xx.h | 100 | ||||
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.c | 22 | ||||
-rw-r--r-- | arch/powerpc/sysdev/fsl_rio.c | 3 |
3 files changed, 62 insertions, 63 deletions
diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h index a49fead..736d4ac 100644 --- a/arch/powerpc/include/asm/mpc85xx.h +++ b/arch/powerpc/include/asm/mpc85xx.h @@ -9,88 +9,84 @@ * (at your option) any later version. */ -#ifndef __ASM_PPC_CPU_H -#define __ASM_PPC_CPU_H +#ifndef __ASM_PPC_MPC85XX_H +#define __ASM_PPC_MPC85XX_H #define SVR_REV(svr) ((svr) & 0xFF) /* SOC design resision */ #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ - -#define IS_SVR_REV(svr, maj, min) \ - ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC Version fields */ #define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 #define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 #define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 #define SVR_8540 0x803000 #define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 #define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 #define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 #define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 #define SVR_8547 0x803101 -#define SVR_8547_E 0x803901 #define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 #define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 #define SVR_8560 0x807000 #define SVR_8567 0x807501 -#define SVR_8567_E 0x807D01 #define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 #define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 -#define SVR_P1010 0x80f900 -#define SVR_P1010_E 0x80F100 +#define SVR_P1010 0x80F100 +#define SVR_P1011 0x80E500 +#define SVR_P1012 0x80E501 +#define SVR_P1013 0x80E700 +#define SVR_P1014 0x80F101 +#define SVR_P1017 0x80F700 +#define SVR_P1020 0x80E400 +#define SVR_P1021 0x80E401 +#define SVR_P1022 0x80E600 +#define SVR_P1023 0x80F600 +#define SVR_P1024 0x80E402 +#define SVR_P1025 0x80E403 +#define SVR_P2010 0x80E300 +#define SVR_P2020 0x80E200 +#define SVR_P2040 0x821000 #define SVR_P2041 0x821001 -#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 -#define SVR_P3041_E 0x821903 +#define SVR_P4040 0x820100 +#define SVR_P4080 0x820000 #define SVR_P5010 0x822100 -#define SVR_P5010_E 0x822900 #define SVR_P5020 0x822000 -#define SVR_P5020_E 0x822800 +#define SVR_P5021 0X820500 #define SVR_P5040 0x820400 -#define SVR_P5040_E 0x820B00 -#define SVR_T4240 0x824800 -#define SVR_B4860 0x868800 - - -static inline int fsl_svr_is(u32 svr) -{ - u32 id = SVR_SOC_VER(mfspr(SPRN_SVR)); - - return (id == svr); -} - -/* Check the SOC design version of this board */ -static inline int fsl_svr_rev_is(u8 maj, u8 min) -{ - u32 rev = SVR_REV(mfspr(SPRN_SVR)); - u32 cmp = (maj << 4) | min; +#define SVR_T4240 0x824000 +#define SVR_T4120 0x824001 +#define SVR_T4160 0x824100 +#define SVR_C291 0x850000 +#define SVR_C292 0x850020 +#define SVR_C293 0x850030 +#define SVR_B4860 0X868000 +#define SVR_G4860 0x868001 +#define SVR_G4060 0x868003 +#define SVR_B4440 0x868100 +#define SVR_G4440 0x868101 +#define SVR_B4420 0x868102 +#define SVR_B4220 0x868103 +#define SVR_T1040 0x852000 +#define SVR_T1041 0x852001 +#define SVR_T1042 0x852002 +#define SVR_T1020 0x852100 +#define SVR_T1021 0x852101 +#define SVR_T1022 0x852102 - return (rev == cmp); -} +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 -/* Return true if current SOC revision is prior to (maj, min) */ -static inline int fsl_svr_older_than(u8 maj, u8 min) -{ - u32 rev = SVR_REV(mfspr(SPRN_SVR)); - u32 cmp = (maj << 4) | min; +#define SVR_9130 0x860001 +#define SVR_9131 0x860000 +#define SVR_9132 0x861000 +#define SVR_9232 0x861400 - return (rev < cmp); -} +#define SVR_Unknown 0xFFFFFF #endif diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 908ac3f..5648137 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -190,6 +190,7 @@ static void setup_pci_atmu(struct pci_controller *hose) const char *name = hose->dn->full_name; const u64 *reg; int len; + u32 svr = mfspr(SPRN_SVR); if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { /* @@ -210,11 +211,11 @@ static void setup_pci_atmu(struct pci_controller *hose) */ #define OWMSV 0x10 #define ORMSV 0x08 - if ((fsl_svr_is(SVR_8543) || fsl_svr_is(SVR_8543_E) || - fsl_svr_is(SVR_8545) || fsl_svr_is(SVR_8545_E) || - fsl_svr_is(SVR_8547) || fsl_svr_is(SVR_8547_E) || - fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) && - fsl_svr_older_than(2, 1)) { + if (((SVR_SOC_VER(svr) == SVR_8543) || + (SVR_SOC_VER(svr) == SVR_8545) || + (SVR_SOC_VER(svr) == SVR_8547) || + (SVR_SOC_VER(svr) == SVR_8548)) && + (SVR_REV(svr) <= 0x20)) { if (of_device_is_compatible(hose->dn, "fsl,mpc8540-pci")) { /* disable OWMSV and ORMSV error capture */ setbits32(&pci->pcier.pecdr, OWMSV | ORMSV); @@ -506,6 +507,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) struct device_node *dev; struct ccsr_pci __iomem *pci; u16 temp; + u32 svr = mfspr(SPRN_SVR); dev = pdev->dev.of_node; @@ -582,11 +584,11 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) */ #define PCI_BUS_FUNCTION 0x44 #define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */ - if ((fsl_svr_is(SVR_8543) || fsl_svr_is(SVR_8543_E) || - fsl_svr_is(SVR_8545) || fsl_svr_is(SVR_8545_E) || - fsl_svr_is(SVR_8547) || fsl_svr_is(SVR_8547_E) || - fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) && - !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) { + if (((SVR_SOC_VER(svr) == SVR_8543) || + (SVR_SOC_VER(svr) == SVR_8545) || + (SVR_SOC_VER(svr) == SVR_8547) || + (SVR_SOC_VER(svr) == SVR_8548)) && + !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) { early_read_config_word(hose, 0, 0, PCI_BUS_FUNCTION, &temp); temp |= PCI_BUS_FUNCTION_MDS; diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c index e9f4556..d07e4a0 100644 --- a/arch/powerpc/sysdev/fsl_rio.c +++ b/arch/powerpc/sysdev/fsl_rio.c @@ -379,6 +379,7 @@ int fsl_rio_setup(struct platform_device *dev) u32 i; static int tmp; struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL}; + static u32 svr = mfspr(SPRN_SVR); if (!dev->dev.of_node) { dev_err(&dev->dev, "Device OF-Node is NULL"); @@ -393,7 +394,7 @@ int fsl_rio_setup(struct platform_device *dev) } /* Fix erratum NMG_SRIO135 */ - if (fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) { + if (SVR_SOC_VER(svr) == SVR_8548) { rc = fixup_erratum_srio135(&dev->dev); if (rc) { dev_err(&dev->dev, |