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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-24 14:00:21 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-03 09:18:09 (GMT) |
| commit | 97e1930f09e9b656e823cd841cf29bfbbe326832 (patch) | |
| tree | 6d110c18578124174ebd7fb22c14d518e241efd6 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 6b26c86d615747f67fede6ca9609b0f8b2037d11 (diff) | |
| download | linux-fsl-qoriq-97e1930f09e9b656e823cd841cf29bfbbe326832.tar.xz | |
drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.
v2: Use new masked bit handling macros.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a26bf49..93d4ce3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2776,6 +2776,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) } gen7_setup_fixed_func_scheduler(dev_priv); + + /* WaDisable4x2SubspanOptimization */ + I915_WRITE(CACHE_MODE_1, + _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); } static void valleyview_init_clock_gating(struct drm_device *dev) |