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authorAlex Deucher <alexander.deucher@amd.com>2012-03-20 21:18:21 (GMT)
committerDave Airlie <airlied@redhat.com>2012-03-21 06:55:54 (GMT)
commit347e7592beb0abd56a11ec16ca8aba9f60681f13 (patch)
tree2ba16548950e2ede2c31859133c6977f2837b5f5 /drivers/gpu/drm/radeon/sid.h
parent2ece2e8b7d02040a59bc2f3a7f192c0521e2b867 (diff)
downloadlinux-fsl-qoriq-347e7592beb0abd56a11ec16ca8aba9f60681f13.tar.xz
drm/radeon/kms: Add support for RLC init on SI
RLC handles the interrupt controller and other tasks on the GPU. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
-rw-r--r--drivers/gpu/drm/radeon/sid.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 904c4fd..78b5649 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -513,6 +513,23 @@
#define CP_DEBUG 0xC1FC
+#define RLC_CNTL 0xC300
+# define RLC_ENABLE (1 << 0)
+#define RLC_RL_BASE 0xC304
+#define RLC_RL_SIZE 0xC308
+#define RLC_LB_CNTL 0xC30C
+#define RLC_SAVE_AND_RESTORE_BASE 0xC310
+#define RLC_LB_CNTR_MAX 0xC314
+#define RLC_LB_CNTR_INIT 0xC318
+
+#define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
+
+#define RLC_UCODE_ADDR 0xC32C
+#define RLC_UCODE_DATA 0xC330
+
+#define RLC_MC_CNTL 0xC344
+#define RLC_UCODE_CNTL 0xC348
+
#define VGT_EVENT_INITIATOR 0x28a90
# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
# define SAMPLE_STREAMOUTSTATS2 (2 << 0)