diff options
author | Scott Wood <scottwood@freescale.com> | 2013-12-14 01:15:24 (GMT) |
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committer | Scott Wood <scottwood@freescale.com> | 2013-12-14 01:15:24 (GMT) |
commit | b7c81aa3ab2ac2c140e278b6d0e9a0b95112cf0b (patch) | |
tree | 87828aaf5f82c7042bfc0307bc4ac499e10f93fb /drivers/i2c/busses | |
parent | 22c782a4b14773fab7eab3c1db54ad7ad077e9b8 (diff) | |
parent | 78fd82238d0e5716578c326404184a27ba67fd6e (diff) | |
download | linux-fsl-qoriq-b7c81aa3ab2ac2c140e278b6d0e9a0b95112cf0b.tar.xz |
Merge remote-tracking branch 'linus/master' into merge
Conflicts:
Documentation/hwmon/ina2xx
arch/powerpc/Kconfig
arch/powerpc/boot/dts/b4860emu.dts
arch/powerpc/boot/dts/b4qds.dtsi
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
arch/powerpc/boot/dts/fsl/qoriq-sec6.0-0.dtsi
arch/powerpc/boot/dts/p1023rdb.dts
arch/powerpc/boot/dts/t4240emu.dts
arch/powerpc/boot/dts/t4240qds.dts
arch/powerpc/configs/85xx/p1023_defconfig
arch/powerpc/configs/corenet32_smp_defconfig
arch/powerpc/configs/corenet64_smp_defconfig
arch/powerpc/configs/mpc85xx_smp_defconfig
arch/powerpc/include/asm/cputable.h
arch/powerpc/include/asm/device.h
arch/powerpc/include/asm/epapr_hcalls.h
arch/powerpc/include/asm/kvm_host.h
arch/powerpc/include/asm/mpic.h
arch/powerpc/include/asm/pci.h
arch/powerpc/include/asm/ppc-opcode.h
arch/powerpc/include/asm/ppc_asm.h
arch/powerpc/include/asm/reg_booke.h
arch/powerpc/kernel/epapr_paravirt.c
arch/powerpc/kernel/process.c
arch/powerpc/kernel/prom.c
arch/powerpc/kernel/setup-common.c
arch/powerpc/kernel/setup_32.c
arch/powerpc/kernel/setup_64.c
arch/powerpc/kernel/smp.c
arch/powerpc/kernel/swsusp_asm64.S
arch/powerpc/kernel/swsusp_booke.S
arch/powerpc/kvm/book3s_pr.c
arch/powerpc/kvm/booke.c
arch/powerpc/kvm/booke.h
arch/powerpc/kvm/e500.c
arch/powerpc/kvm/e500.h
arch/powerpc/kvm/e500_emulate.c
arch/powerpc/kvm/e500mc.c
arch/powerpc/kvm/powerpc.c
arch/powerpc/perf/e6500-pmu.c
arch/powerpc/platforms/85xx/Kconfig
arch/powerpc/platforms/85xx/Makefile
arch/powerpc/platforms/85xx/b4_qds.c
arch/powerpc/platforms/85xx/c293pcie.c
arch/powerpc/platforms/85xx/corenet_ds.c
arch/powerpc/platforms/85xx/corenet_ds.h
arch/powerpc/platforms/85xx/p1023_rds.c
arch/powerpc/platforms/85xx/p2041_rdb.c
arch/powerpc/platforms/85xx/p3041_ds.c
arch/powerpc/platforms/85xx/p4080_ds.c
arch/powerpc/platforms/85xx/p5020_ds.c
arch/powerpc/platforms/85xx/p5040_ds.c
arch/powerpc/platforms/85xx/smp.c
arch/powerpc/platforms/85xx/t4240_qds.c
arch/powerpc/platforms/Kconfig
arch/powerpc/sysdev/Makefile
arch/powerpc/sysdev/fsl_mpic_timer_wakeup.c
arch/powerpc/sysdev/fsl_msi.c
arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pci.h
arch/powerpc/sysdev/fsl_soc.h
arch/powerpc/sysdev/mpic.c
arch/powerpc/sysdev/mpic_timer.c
drivers/Kconfig
drivers/clk/Kconfig
drivers/clk/clk-ppc-corenet.c
drivers/cpufreq/Kconfig.powerpc
drivers/cpufreq/Makefile
drivers/cpufreq/ppc-corenet-cpufreq.c
drivers/crypto/caam/Kconfig
drivers/crypto/caam/Makefile
drivers/crypto/caam/ctrl.c
drivers/crypto/caam/desc_constr.h
drivers/crypto/caam/intern.h
drivers/crypto/caam/jr.c
drivers/crypto/caam/regs.h
drivers/dma/fsldma.c
drivers/hwmon/ina2xx.c
drivers/iommu/Kconfig
drivers/iommu/fsl_pamu.c
drivers/iommu/fsl_pamu.h
drivers/iommu/fsl_pamu_domain.c
drivers/iommu/fsl_pamu_domain.h
drivers/misc/Makefile
drivers/mmc/card/block.c
drivers/mmc/core/core.c
drivers/mmc/host/sdhci-esdhc.h
drivers/mmc/host/sdhci-pltfm.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/net/ethernet/freescale/gianfar.c
drivers/net/ethernet/freescale/gianfar.h
drivers/net/ethernet/freescale/gianfar_ethtool.c
drivers/net/phy/at803x.c
drivers/net/phy/phy_device.c
drivers/net/phy/vitesse.c
drivers/pci/msi.c
drivers/staging/Kconfig
drivers/staging/Makefile
drivers/uio/Kconfig
drivers/uio/Makefile
drivers/uio/uio.c
drivers/usb/host/ehci-fsl.c
drivers/vfio/Kconfig
drivers/vfio/Makefile
include/crypto/algapi.h
include/linux/iommu.h
include/linux/mmc/sdhci.h
include/linux/msi.h
include/linux/netdev_features.h
include/linux/phy.h
include/linux/skbuff.h
include/net/ip.h
include/uapi/linux/vfio.h
net/core/ethtool.c
net/ipv4/route.c
net/ipv6/route.c
Diffstat (limited to 'drivers/i2c/busses')
51 files changed, 4998 insertions, 1936 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 631736e..3b26129 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -108,13 +108,15 @@ config I2C_I801 Lynx Point-LP (PCH) Avoton (SOC) Wellsburg (PCH) + Coleto Creek (PCH) + Wildcat Point-LP (PCH) This driver can also be built as a module. If so, the module will be called i2c-i801. config I2C_ISCH tristate "Intel SCH SMBus 1.0" - depends on PCI && GENERIC_HARDIRQS + depends on PCI select LPC_SCH help Say Y here if you want to use SMBus controller on the Intel SCH @@ -150,6 +152,7 @@ config I2C_PIIX4 ATI SB700/SP5100 ATI SB800 AMD Hudson-2 + AMD CZ Serverworks OSB4 Serverworks CSB5 Serverworks CSB6 @@ -343,6 +346,16 @@ config I2C_BCM2835 This support is also available as a module. If so, the module will be called i2c-bcm2835. +config I2C_BCM_KONA + tristate "BCM Kona I2C adapter" + depends on ARCH_BCM_MOBILE + default y + help + If you say yes to this option, support will be included for the + I2C interface on the Broadcom Kona family of processors. + + If you do not need KONA I2C inteface, say N. + config I2C_BLACKFIN_TWI tristate "Blackfin TWI I2C support" depends on BLACKFIN @@ -383,7 +396,7 @@ config I2C_CPM config I2C_DAVINCI tristate "DaVinci I2C driver" - depends on ARCH_DAVINCI + depends on ARCH_DAVINCI || ARCH_KEYSTONE help Support for TI DaVinci I2C controller driver. @@ -434,6 +447,13 @@ config I2C_EG20T ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series. ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH. +config I2C_EXYNOS5 + tristate "Exynos5 high-speed I2C driver" + depends on ARCH_EXYNOS5 && OF + help + Say Y here to include support for high-speed I2C controller in the + Exynos5 based Samsung SoCs. + config I2C_GPIO tristate "GPIO-based bitbanging I2C" depends on GPIOLIB @@ -474,16 +494,6 @@ config I2C_IMX This driver can also be built as a module. If so, the module will be called i2c-imx. -config I2C_INTEL_MID - tristate "Intel Moorestown/Medfield Platform I2C controller" - depends on PCI - help - Say Y here if you have an Intel Moorestown/Medfield platform I2C - controller. - - This support is also available as a module. If so, the module - will be called i2c-intel-mid. - config I2C_IOP3XX tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface" depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX @@ -494,6 +504,16 @@ config I2C_IOP3XX This driver can also be built as a module. If so, the module will be called i2c-iop3xx. +config I2C_KEMPLD + tristate "Kontron COM I2C Controller" + depends on MFD_KEMPLD + help + This enables support for the I2C bus interface on some Kontron ETX + and COMexpress (ETXexpress) modules. + + This driver can also be built as a module. If so, the module + will be called i2c-kempld. + config I2C_MPC tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" depends on PPC @@ -507,10 +527,11 @@ config I2C_MPC config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" - depends on (MV64X60 || PLAT_ORION) + depends on (MV64X60 || PLAT_ORION || ARCH_SUNXI) help If you say yes to this option, support will be included for the built-in I2C interface on the Marvell 64xxx line of host bridges. + This driver is also used for Allwinner SoCs I2C controllers. This driver can also be built as a module. If so, the module will be called i2c-mv64xxx. @@ -543,7 +564,6 @@ config I2C_NUC900 config I2C_OCORES tristate "OpenCores I2C Controller" - depends on GENERIC_HARDIRQS help If you say yes to this option, support will be included for the OpenCores I2C controller. For details see @@ -663,7 +683,7 @@ config I2C_SH7760 config I2C_SH_MOBILE tristate "SuperH Mobile I2C Controller" - depends on SUPERH || ARCH_SHMOBILE + depends on SUPERH || ARM || COMPILE_TEST help If you say yes to this option, support will be included for the built-in I2C interface on the Renesas SH-Mobile processor. @@ -685,7 +705,7 @@ config I2C_SIMTEC config I2C_SIRF tristate "CSR SiRFprimaII I2C interface" - depends on ARCH_PRIMA2 + depends on ARCH_SIRF help If you say yes to this option, support will be included for the CSR SiRFprimaII I2C interface. @@ -693,6 +713,16 @@ config I2C_SIRF This driver can also be built as a module. If so, the module will be called i2c-sirf. +config I2C_ST + tristate "STMicroelectronics SSC I2C support" + depends on ARCH_STI + help + Enable this option to add support for STMicroelectronics SoCs + hardware SSC (Synchronous Serial Controller) as an I2C controller. + + This driver can also be built as module. If so, the module + will be called i2c-st. + config I2C_STU300 tristate "ST Microelectronics DDC I2C interface" depends on MACH_U300 @@ -724,9 +754,19 @@ config I2C_VERSATILE This driver can also be built as a module. If so, the module will be called i2c-versatile. +config I2C_WMT + tristate "Wondermedia WM8xxx SoC I2C bus support" + depends on ARCH_VT8500 + help + Say yes if you want to support the I2C bus on Wondermedia 8xxx-series + SoCs. + + This driver can also be built as a module. If so, the module will be + called i2c-wmt. + config I2C_OCTEON tristate "Cavium OCTEON I2C bus support" - depends on CPU_CAVIUM_OCTEON + depends on CAVIUM_OCTEON_SOC help Say yes if you want to support the I2C serial bus on Cavium OCTEON SOC. @@ -756,7 +796,7 @@ config I2C_XLR config I2C_RCAR tristate "Renesas R-Car I2C Controller" - depends on ARCH_SHMOBILE && I2C + depends on ARM || COMPILE_TEST help If you say yes to this option, support will be included for the R-Car I2C controller. @@ -778,7 +818,7 @@ config I2C_DIOLAN_U2C config I2C_PARPORT tristate "Parallel port adapter" - depends on PARPORT && GENERIC_HARDIRQS + depends on PARPORT select I2C_ALGOBIT select I2C_SMBUS help @@ -803,7 +843,6 @@ config I2C_PARPORT config I2C_PARPORT_LIGHT tristate "Parallel port adapter (light)" - depends on GENERIC_HARDIRQS select I2C_ALGOBIT select I2C_SMBUS help diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 8f4fc23..c73eb0e 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -42,12 +42,13 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o i2c-designware-pci-objs := i2c-designware-pcidrv.o obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o +obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o obj-$(CONFIG_I2C_IMX) += i2c-imx.o -obj-$(CONFIG_I2C_INTEL_MID) += i2c-intel-mid.o obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o +obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o @@ -68,9 +69,11 @@ obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o +obj-$(CONFIG_I2C_ST) += i2c-st.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o +obj-$(CONFIG_I2C_WMT) += i2c-wmt.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o obj-$(CONFIG_I2C_XLR) += i2c-xlr.o @@ -86,6 +89,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o # Other I2C/SMBus bus drivers obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o +obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c index 6bb839b..8edba9d 100644 --- a/drivers/i2c/busses/i2c-at91.c +++ b/drivers/i2c/busses/i2c-at91.c @@ -28,7 +28,6 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> -#include <linux/of_i2c.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/platform_data/dma-atmel.h> @@ -372,7 +371,7 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev) dev_dbg(dev->dev, "transfer: %s %d bytes.\n", (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); - INIT_COMPLETION(dev->cmd_complete); + reinit_completion(&dev->cmd_complete); dev->transfer_status = 0; if (!dev->buf_len) { @@ -775,8 +774,6 @@ static int at91_twi_probe(struct platform_device *pdev) return rc; } - of_i2c_register_devices(&dev->adapter); - dev_info(dev->dev, "AT91 i2c bus driver.\n"); return 0; } diff --git a/drivers/i2c/busses/i2c-bcm-kona.c b/drivers/i2c/busses/i2c-bcm-kona.c new file mode 100644 index 0000000..18a74a6 --- /dev/null +++ b/drivers/i2c/busses/i2c-bcm-kona.c @@ -0,0 +1,908 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/sched.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/slab.h> + +/* Hardware register offsets and field defintions */ +#define CS_OFFSET 0x00000020 +#define CS_ACK_SHIFT 3 +#define CS_ACK_MASK 0x00000008 +#define CS_ACK_CMD_GEN_START 0x00000000 +#define CS_ACK_CMD_GEN_RESTART 0x00000001 +#define CS_CMD_SHIFT 1 +#define CS_CMD_CMD_NO_ACTION 0x00000000 +#define CS_CMD_CMD_START_RESTART 0x00000001 +#define CS_CMD_CMD_STOP 0x00000002 +#define CS_EN_SHIFT 0 +#define CS_EN_CMD_ENABLE_BSC 0x00000001 + +#define TIM_OFFSET 0x00000024 +#define TIM_PRESCALE_SHIFT 6 +#define TIM_P_SHIFT 3 +#define TIM_NO_DIV_SHIFT 2 +#define TIM_DIV_SHIFT 0 + +#define DAT_OFFSET 0x00000028 + +#define TOUT_OFFSET 0x0000002c + +#define TXFCR_OFFSET 0x0000003c +#define TXFCR_FIFO_FLUSH_MASK 0x00000080 +#define TXFCR_FIFO_EN_MASK 0x00000040 + +#define IER_OFFSET 0x00000044 +#define IER_READ_COMPLETE_INT_MASK 0x00000010 +#define IER_I2C_INT_EN_MASK 0x00000008 +#define IER_FIFO_INT_EN_MASK 0x00000002 +#define IER_NOACK_EN_MASK 0x00000001 + +#define ISR_OFFSET 0x00000048 +#define ISR_RESERVED_MASK 0xffffff60 +#define ISR_CMDBUSY_MASK 0x00000080 +#define ISR_READ_COMPLETE_MASK 0x00000010 +#define ISR_SES_DONE_MASK 0x00000008 +#define ISR_ERR_MASK 0x00000004 +#define ISR_TXFIFOEMPTY_MASK 0x00000002 +#define ISR_NOACK_MASK 0x00000001 + +#define CLKEN_OFFSET 0x0000004C +#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 +#define CLKEN_M_SHIFT 4 +#define CLKEN_N_SHIFT 1 +#define CLKEN_CLKEN_MASK 0x00000001 + +#define FIFO_STATUS_OFFSET 0x00000054 +#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 +#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 + +#define HSTIM_OFFSET 0x00000058 +#define HSTIM_HS_MODE_MASK 0x00008000 +#define HSTIM_HS_HOLD_SHIFT 10 +#define HSTIM_HS_HIGH_PHASE_SHIFT 5 +#define HSTIM_HS_SETUP_SHIFT 0 + +#define PADCTL_OFFSET 0x0000005c +#define PADCTL_PAD_OUT_EN_MASK 0x00000004 + +#define RXFCR_OFFSET 0x00000068 +#define RXFCR_NACK_EN_SHIFT 7 +#define RXFCR_READ_COUNT_SHIFT 0 +#define RXFIFORDOUT_OFFSET 0x0000006c + +/* Locally used constants */ +#define MAX_RX_FIFO_SIZE 64U /* bytes */ +#define MAX_TX_FIFO_SIZE 64U /* bytes */ + +#define STD_EXT_CLK_FREQ 13000000UL +#define HS_EXT_CLK_FREQ 104000000UL + +#define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */ + +#define I2C_TIMEOUT 100 /* msecs */ + +/* Operations that can be commanded to the controller */ +enum bcm_kona_cmd_t { + BCM_CMD_NOACTION = 0, + BCM_CMD_START, + BCM_CMD_RESTART, + BCM_CMD_STOP, +}; + +enum bus_speed_index { + BCM_SPD_100K = 0, + BCM_SPD_400K, + BCM_SPD_1MHZ, +}; + +enum hs_bus_speed_index { + BCM_SPD_3P4MHZ = 0, +}; + +/* Internal divider settings for standard mode, fast mode and fast mode plus */ +struct bus_speed_cfg { + uint8_t time_m; /* Number of cycles for setup time */ + uint8_t time_n; /* Number of cycles for hold time */ + uint8_t prescale; /* Prescale divider */ + uint8_t time_p; /* Timing coefficient */ + uint8_t no_div; /* Disable clock divider */ + uint8_t time_div; /* Post-prescale divider */ +}; + +/* Internal divider settings for high-speed mode */ +struct hs_bus_speed_cfg { + uint8_t hs_hold; /* Number of clock cycles SCL stays low until + the end of bit period */ + uint8_t hs_high_phase; /* Number of clock cycles SCL stays high + before it falls */ + uint8_t hs_setup; /* Number of clock cycles SCL stays low + before it rises */ + uint8_t prescale; /* Prescale divider */ + uint8_t time_p; /* Timing coefficient */ + uint8_t no_div; /* Disable clock divider */ + uint8_t time_div; /* Post-prescale divider */ +}; + +static const struct bus_speed_cfg std_cfg_table[] = { + [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, + [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, + [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, +}; + +static const struct hs_bus_speed_cfg hs_cfg_table[] = { + [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00}, +}; + +struct bcm_kona_i2c_dev { + struct device *device; + + void __iomem *base; + int irq; + struct clk *external_clk; + + struct i2c_adapter adapter; + + struct completion done; + + const struct bus_speed_cfg *std_cfg; + const struct hs_bus_speed_cfg *hs_cfg; +}; + +static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + dev_dbg(dev->device, "%s, %d\n", __func__, cmd); + + switch (cmd) { + case BCM_CMD_NOACTION: + writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_START: + writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_RESTART: + writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_STOP: + writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + default: + dev_err(dev->device, "Unknown command %d\n", cmd); + } +} + +static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid) +{ + struct bcm_kona_i2c_dev *dev = devid; + uint32_t status = readl(dev->base + ISR_OFFSET); + + if ((status & ~ISR_RESERVED_MASK) == 0) + return IRQ_NONE; + + /* Must flush the TX FIFO when NAK detected */ + if (status & ISR_NOACK_MASK) + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); + complete_all(&dev->done); + + return IRQ_HANDLED; +} + +/* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */ +static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); + + while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK) + if (time_after(jiffies, timeout)) { + dev_err(dev->device, "CMDBUSY timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +/* Send command to I2C bus */ +static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + int rc; + unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); + + /* Make sure the hardware is ready */ + rc = bcm_kona_i2c_wait_if_busy(dev); + if (rc < 0) + return rc; + + /* Unmask the session done interrupt */ + writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); + + /* Mark as incomplete before sending the command */ + reinit_completion(&dev->done); + + /* Send the command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); + + /* Wait for transaction to finish or timeout */ + time_left = wait_for_completion_timeout(&dev->done, time_left); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + if (!time_left) { + dev_err(dev->device, "controller timed out\n"); + rc = -ETIMEDOUT; + } + + /* Clear command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + return rc; +} + +/* Read a single RX FIFO worth of data from the i2c bus */ +static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len, + unsigned int last_byte_nak) +{ + unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); + + /* Mark as incomplete before starting the RX FIFO */ + reinit_completion(&dev->done); + + /* Unmask the read complete interrupt */ + writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET); + + /* Start the RX FIFO */ + writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | + (len << RXFCR_READ_COUNT_SHIFT), + dev->base + RXFCR_OFFSET); + + /* Wait for FIFO read to complete */ + time_left = wait_for_completion_timeout(&dev->done, time_left); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + if (!time_left) { + dev_err(dev->device, "RX FIFO time out\n"); + return -EREMOTEIO; + } + + /* Read data from FIFO */ + for (; len > 0; len--, buf++) + *buf = readl(dev->base + RXFIFORDOUT_OFFSET); + + return 0; +} + +/* Read any amount of data using the RX FIFO from the i2c bus */ +static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; + unsigned int last_byte_nak = 0; + unsigned int bytes_read = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_read < msg->len) { + if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { + last_byte_nak = 1; /* NAK last byte of transfer */ + bytes_to_read = msg->len - bytes_read; + } + + rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, + last_byte_nak); + if (rc < 0) + return -EREMOTEIO; + + bytes_read += bytes_to_read; + tmp_buf += bytes_to_read; + } + + return 0; +} + +/* Write a single byte of data to the i2c bus */ +static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, + unsigned int nak_expected) +{ + int rc; + unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); + unsigned int nak_received; + + /* Make sure the hardware is ready */ + rc = bcm_kona_i2c_wait_if_busy(dev); + if (rc < 0) + return rc; + + /* Clear pending session done interrupt */ + writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); + + /* Unmask the session done interrupt */ + writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); + + /* Mark as incomplete before sending the data */ + reinit_completion(&dev->done); + + /* Send one byte of data */ + writel(data, dev->base + DAT_OFFSET); + + /* Wait for byte to be written */ + time_left = wait_for_completion_timeout(&dev->done, time_left); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + if (!time_left) { + dev_dbg(dev->device, "controller timed out\n"); + return -ETIMEDOUT; + } + + nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; + + if (nak_received ^ nak_expected) { + dev_dbg(dev->device, "unexpected NAK/ACK\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write a single TX FIFO worth of data to the i2c bus */ +static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len) +{ + int k; + unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); + unsigned int fifo_status; + + /* Mark as incomplete before sending data to the TX FIFO */ + reinit_completion(&dev->done); + + /* Unmask the fifo empty and nak interrupt */ + writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK, + dev->base + IER_OFFSET); + + /* Disable IRQ to load a FIFO worth of data without interruption */ + disable_irq(dev->irq); + + /* Write data into FIFO */ + for (k = 0; k < len; k++) + writel(buf[k], (dev->base + DAT_OFFSET)); + + /* Enable IRQ now that data has been loaded */ + enable_irq(dev->irq); + + /* Wait for FIFO to empty */ + do { + time_left = wait_for_completion_timeout(&dev->done, time_left); + fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); + } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + /* Check if there was a NAK */ + if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { + dev_err(dev->device, "unexpected NAK\n"); + return -EREMOTEIO; + } + + /* Check if a timeout occured */ + if (!time_left) { + dev_err(dev->device, "completion timed out\n"); + return -EREMOTEIO; + } + + return 0; +} + + +/* Write any amount of data using TX FIFO to the i2c bus */ +static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; + unsigned int bytes_written = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_written < msg->len) { + if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) + bytes_to_write = msg->len - bytes_written; + + rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, + bytes_to_write); + if (rc < 0) + return -EREMOTEIO; + + bytes_written += bytes_to_write; + tmp_buf += bytes_to_write; + } + + return 0; +} + +/* Send i2c address */ +static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned char addr; + + if (msg->flags & I2C_M_TEN) { + /* First byte is 11110XX0 where XX is upper 2 bits */ + addr = 0xF0 | ((msg->addr & 0x300) >> 7); + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + /* Second byte is the remaining 8 bits */ + addr = msg->addr & 0xFF; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + if (msg->flags & I2C_M_RD) { + /* For read, send restart command */ + if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) + return -EREMOTEIO; + + /* Then re-send the first byte with the read bit set */ + addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + } else { + addr = msg->addr << 1; + + if (msg->flags & I2C_M_RD) + addr |= 1; + + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + + return 0; +} + +static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, + dev->base + HSTIM_OFFSET); + + writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | + (dev->std_cfg->time_p << TIM_P_SHIFT) | + (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | + (dev->std_cfg->time_div << TIM_DIV_SHIFT), + dev->base + TIM_OFFSET); + + writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | + (dev->std_cfg->time_n << CLKEN_N_SHIFT) | + CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev) +{ + writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) | + (dev->hs_cfg->time_p << TIM_P_SHIFT) | + (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) | + (dev->hs_cfg->time_div << TIM_DIV_SHIFT), + dev->base + TIM_OFFSET); + + writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) | + (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) | + (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT), + dev->base + HSTIM_OFFSET); + + writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK, + dev->base + HSTIM_OFFSET); +} + +static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev) +{ + int rc; + + /* Send mastercode at standard speed */ + rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1); + if (rc < 0) { + pr_err("High speed handshake failed\n"); + return rc; + } + + /* Configure external clock to higher frequency */ + rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ); + if (rc) { + dev_err(dev->device, "%s: clk_set_rate returned %d\n", + __func__, rc); + return rc; + } + + /* Reconfigure internal dividers */ + bcm_kona_i2c_config_timing_hs(dev); + + /* Send a restart command */ + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); + if (rc < 0) + dev_err(dev->device, "High speed restart command failed\n"); + + return rc; +} + +static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev) +{ + int rc; + + /* Reconfigure internal dividers */ + bcm_kona_i2c_config_timing(dev); + + /* Configure external clock to lower frequency */ + rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); + if (rc) { + dev_err(dev->device, "%s: clk_set_rate returned %d\n", + __func__, rc); + } + + return rc; +} + +/* Master transfer function */ +static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter, + struct i2c_msg msgs[], int num) +{ + struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter); + struct i2c_msg *pmsg; + int rc = 0; + int i; + + rc = clk_prepare_enable(dev->external_clk); + if (rc) { + dev_err(dev->device, "%s: peri clock enable failed. err %d\n", + __func__, rc); + return rc; + } + + /* Enable pad output */ + writel(0, dev->base + PADCTL_OFFSET); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Send start command */ + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); + if (rc < 0) { + dev_err(dev->device, "Start command failed rc = %d\n", rc); + goto xfer_disable_pad; + } + + /* Switch to high speed if applicable */ + if (dev->hs_cfg) { + rc = bcm_kona_i2c_switch_to_hs(dev); + if (rc < 0) + goto xfer_send_stop; + } + + /* Loop through all messages */ + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + + /* Send restart for subsequent messages */ + if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); + if (rc < 0) { + dev_err(dev->device, + "restart cmd failed rc = %d\n", rc); + goto xfer_send_stop; + } + } + + /* Send slave address */ + if (!(pmsg->flags & I2C_M_NOSTART)) { + rc = bcm_kona_i2c_do_addr(dev, pmsg); + if (rc < 0) { + dev_err(dev->device, + "NAK from addr %2.2x msg#%d rc = %d\n", + pmsg->addr, i, rc); + goto xfer_send_stop; + } + } + + /* Perform data transfer */ + if (pmsg->flags & I2C_M_RD) { + rc = bcm_kona_i2c_read_fifo(dev, pmsg); + if (rc < 0) { + dev_err(dev->device, "read failure\n"); + goto xfer_send_stop; + } + } else { + rc = bcm_kona_i2c_write_fifo(dev, pmsg); + if (rc < 0) { + dev_err(dev->device, "write failure"); + goto xfer_send_stop; + } + } + } + + rc = num; + +xfer_send_stop: + /* Send a STOP command */ + bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); + + /* Return from high speed if applicable */ + if (dev->hs_cfg) { + int hs_rc = bcm_kona_i2c_switch_to_std(dev); + + if (hs_rc) + rc = hs_rc; + } + +xfer_disable_pad: + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); + + /* Stop internal clock */ + bcm_kona_i2c_disable_clock(dev); + + clk_disable_unprepare(dev->external_clk); + + return rc; +} + +static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | + I2C_FUNC_NOSTART; +} + +static const struct i2c_algorithm bcm_algo = { + .master_xfer = bcm_kona_i2c_xfer, + .functionality = bcm_kona_i2c_functionality, +}; + +static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev) +{ + unsigned int bus_speed; + int ret = of_property_read_u32(dev->device->of_node, "clock-frequency", + &bus_speed); + if (ret < 0) { + dev_err(dev->device, "missing clock-frequency property\n"); + return -ENODEV; + } + + switch (bus_speed) { + case 100000: + dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; + break; + case 400000: + dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; + break; + case 1000000: + dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; + break; + case 3400000: + /* Send mastercode at 100k */ + dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; + dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ]; + break; + default: + pr_err("%d hz bus speed not supported\n", bus_speed); + pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n"); + return -EINVAL; + } + + return 0; +} + +static int bcm_kona_i2c_probe(struct platform_device *pdev) +{ + int rc = 0; + struct bcm_kona_i2c_dev *dev; + struct i2c_adapter *adap; + struct resource *iomem; + + /* Allocate memory for private data structure */ + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + platform_set_drvdata(pdev, dev); + dev->device = &pdev->dev; + init_completion(&dev->done); + + /* Map hardware registers */ + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dev->base = devm_ioremap_resource(dev->device, iomem); + if (IS_ERR(dev->base)) + return -ENOMEM; + + /* Get and enable external clock */ + dev->external_clk = devm_clk_get(dev->device, NULL); + if (IS_ERR(dev->external_clk)) { + dev_err(dev->device, "couldn't get clock\n"); + return -ENODEV; + } + + rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); + if (rc) { + dev_err(dev->device, "%s: clk_set_rate returned %d\n", + __func__, rc); + return rc; + } + + rc = clk_prepare_enable(dev->external_clk); + if (rc) { + dev_err(dev->device, "couldn't enable clock\n"); + return rc; + } + + /* Parse bus speed */ + rc = bcm_kona_i2c_assign_bus_speed(dev); + if (rc) + goto probe_disable_clk; + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Configure internal dividers */ + bcm_kona_i2c_config_timing(dev); + + /* Disable timeout */ + writel(0, dev->base + TOUT_OFFSET); + + /* Enable autosense */ + bcm_kona_i2c_enable_autosense(dev); + + /* Enable TX FIFO */ + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + /* Clear all pending interrupts */ + writel(ISR_CMDBUSY_MASK | + ISR_READ_COMPLETE_MASK | + ISR_SES_DONE_MASK | + ISR_ERR_MASK | + ISR_TXFIFOEMPTY_MASK | + ISR_NOACK_MASK, + dev->base + ISR_OFFSET); + + /* Get the interrupt number */ + dev->irq = platform_get_irq(pdev, 0); + if (dev->irq < 0) { + dev_err(dev->device, "no irq resource\n"); + rc = -ENODEV; + goto probe_disable_clk; + } + + /* register the ISR handler */ + rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr, + IRQF_SHARED, pdev->name, dev); + if (rc) { + dev_err(dev->device, "failed to request irq %i\n", dev->irq); + goto probe_disable_clk; + } + + /* Enable the controller but leave it idle */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); + + /* Disable internal clock */ + bcm_kona_i2c_disable_clock(dev); + + /* Disable external clock */ + clk_disable_unprepare(dev->external_clk); + + /* Add the i2c adapter */ + adap = &dev->adapter; + i2c_set_adapdata(adap, dev); + adap->owner = THIS_MODULE; + strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); + adap->algo = &bcm_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; + + rc = i2c_add_adapter(adap); + if (rc) { + dev_err(dev->device, "failed to add adapter\n"); + return rc; + } + + dev_info(dev->device, "device registered successfully\n"); + + return 0; + +probe_disable_clk: + bcm_kona_i2c_disable_clock(dev); + clk_disable_unprepare(dev->external_clk); + + return rc; +} + +static int bcm_kona_i2c_remove(struct platform_device *pdev) +{ + struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&dev->adapter); + + return 0; +} + +static const struct of_device_id bcm_kona_i2c_of_match[] = { + {.compatible = "brcm,kona-i2c",}, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match); + +static struct platform_driver bcm_kona_i2c_driver = { + .driver = { + .name = "bcm-kona-i2c", + .owner = THIS_MODULE, + .of_match_table = bcm_kona_i2c_of_match, + }, + .probe = bcm_kona_i2c_probe, + .remove = bcm_kona_i2c_remove, +}; +module_platform_driver(bcm_kona_i2c_driver); + +MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>"); +MODULE_DESCRIPTION("Broadcom Kona I2C Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c index ea4b08f..77df97b 100644 --- a/drivers/i2c/busses/i2c-bcm2835.c +++ b/drivers/i2c/busses/i2c-bcm2835.c @@ -151,7 +151,7 @@ static int bcm2835_i2c_xfer_msg(struct bcm2835_i2c_dev *i2c_dev, i2c_dev->msg_buf = msg->buf; i2c_dev->msg_buf_remaining = msg->len; - INIT_COMPLETION(i2c_dev->completion); + reinit_completion(&i2c_dev->completion); bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR); @@ -299,6 +299,7 @@ static int bcm2835_i2c_probe(struct platform_device *pdev) strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name)); adap->algo = &bcm2835_i2c_algo; adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0); diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c index 05080c4..3b9bd9a 100644 --- a/drivers/i2c/busses/i2c-bfin-twi.c +++ b/drivers/i2c/busses/i2c-bfin-twi.c @@ -39,33 +39,40 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, unsigned short mast_stat = read_MASTER_STAT(iface); if (twi_int_status & XMTSERV) { + if (iface->writeNum <= 0) { + /* start receive immediately after complete sending in + * combine mode. + */ + if (iface->cur_mode == TWI_I2C_MODE_COMBINED) + write_MASTER_CTL(iface, + read_MASTER_CTL(iface) | MDIR); + else if (iface->manual_stop) + write_MASTER_CTL(iface, + read_MASTER_CTL(iface) | STOP); + else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && + iface->cur_msg + 1 < iface->msg_num) { + if (iface->pmsg[iface->cur_msg + 1].flags & + I2C_M_RD) + write_MASTER_CTL(iface, + read_MASTER_CTL(iface) | + MDIR); + else + write_MASTER_CTL(iface, + read_MASTER_CTL(iface) & + ~MDIR); + } + } /* Transmit next data */ - if (iface->writeNum > 0) { + while (iface->writeNum > 0 && + (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) { SSYNC(); write_XMT_DATA8(iface, *(iface->transPtr++)); iface->writeNum--; } - /* start receive immediately after complete sending in - * combine mode. - */ - else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) - write_MASTER_CTL(iface, - read_MASTER_CTL(iface) | MDIR); - else if (iface->manual_stop) - write_MASTER_CTL(iface, - read_MASTER_CTL(iface) | STOP); - else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && - iface->cur_msg + 1 < iface->msg_num) { - if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) - write_MASTER_CTL(iface, - read_MASTER_CTL(iface) | MDIR); - else - write_MASTER_CTL(iface, - read_MASTER_CTL(iface) & ~MDIR); - } } if (twi_int_status & RCVSERV) { - if (iface->readNum > 0) { + while (iface->readNum > 0 && + (read_FIFO_STAT(iface) & RCVSTAT)) { /* Receive next data */ *(iface->transPtr) = read_RCV_DATA8(iface); if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { @@ -575,6 +582,7 @@ static struct i2c_algorithm bfin_twi_algorithm = { .functionality = bfin_twi_functionality, }; +#ifdef CONFIG_PM_SLEEP static int i2c_bfin_twi_suspend(struct device *dev) { struct bfin_twi_iface *iface = dev_get_drvdata(dev); @@ -612,6 +620,10 @@ static int i2c_bfin_twi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm, i2c_bfin_twi_suspend, i2c_bfin_twi_resume); +#define I2C_BFIN_TWI_PM_OPS (&i2c_bfin_twi_pm) +#else +#define I2C_BFIN_TWI_PM_OPS NULL +#endif static int i2c_bfin_twi_probe(struct platform_device *pdev) { @@ -662,8 +674,9 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev) p_adap->timeout = 5 * HZ; p_adap->retries = 3; - rc = peripheral_request_list((unsigned short *)pdev->dev.platform_data, - "i2c-bfin-twi"); + rc = peripheral_request_list( + dev_get_platdata(&pdev->dev), + "i2c-bfin-twi"); if (rc) { dev_err(&pdev->dev, "Can't setup pin mux!\n"); goto out_error_pin_mux; @@ -710,7 +723,7 @@ out_error_add_adapter: free_irq(iface->irq, iface); out_error_req_irq: out_error_no_irq: - peripheral_free_list((unsigned short *)pdev->dev.platform_data); + peripheral_free_list(dev_get_platdata(&pdev->dev)); out_error_pin_mux: iounmap(iface->regs_base); out_error_ioremap: @@ -726,7 +739,7 @@ static int i2c_bfin_twi_remove(struct platform_device *pdev) i2c_del_adapter(&(iface->adap)); free_irq(iface->irq, iface); - peripheral_free_list((unsigned short *)pdev->dev.platform_data); + peripheral_free_list(dev_get_platdata(&pdev->dev)); iounmap(iface->regs_base); kfree(iface); @@ -739,7 +752,7 @@ static struct platform_driver i2c_bfin_twi_driver = { .driver = { .name = "i2c-bfin-twi", .owner = THIS_MODULE, - .pm = &i2c_bfin_twi_pm, + .pm = I2C_BFIN_TWI_PM_OPS, }, }; diff --git a/drivers/i2c/busses/i2c-cbus-gpio.c b/drivers/i2c/busses/i2c-cbus-gpio.c index 1be13ac..ce7ffba 100644 --- a/drivers/i2c/busses/i2c-cbus-gpio.c +++ b/drivers/i2c/busses/i2c-cbus-gpio.c @@ -233,8 +233,9 @@ static int cbus_i2c_probe(struct platform_device *pdev) chost->clk_gpio = of_get_gpio(dnode, 0); chost->dat_gpio = of_get_gpio(dnode, 1); chost->sel_gpio = of_get_gpio(dnode, 2); - } else if (pdev->dev.platform_data) { - struct i2c_cbus_platform_data *pdata = pdev->dev.platform_data; + } else if (dev_get_platdata(&pdev->dev)) { + struct i2c_cbus_platform_data *pdata = + dev_get_platdata(&pdev->dev); chost->clk_gpio = pdata->clk_gpio; chost->dat_gpio = pdata->dat_gpio; chost->sel_gpio = pdata->sel_gpio; @@ -245,6 +246,7 @@ static int cbus_i2c_probe(struct platform_device *pdev) adapter->owner = THIS_MODULE; adapter->class = I2C_CLASS_HWMON; adapter->dev.parent = &pdev->dev; + adapter->dev.of_node = pdev->dev.of_node; adapter->nr = pdev->id; adapter->timeout = HZ; adapter->algo = &cbus_i2c_algo; @@ -288,6 +290,7 @@ static struct platform_driver cbus_i2c_driver = { .driver = { .owner = THIS_MODULE, .name = "i2c-cbus-gpio", + .of_match_table = of_match_ptr(i2c_cbus_dt_ids), }, }; module_platform_driver(cbus_i2c_driver); diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c index 3823623..3e5ea2c 100644 --- a/drivers/i2c/busses/i2c-cpm.c +++ b/drivers/i2c/busses/i2c-cpm.c @@ -42,7 +42,6 @@ #include <linux/dma-mapping.h> #include <linux/of_device.h> #include <linux/of_platform.h> -#include <linux/of_i2c.h> #include <sysdev/fsl_soc.h> #include <asm/cpm.h> @@ -338,6 +337,14 @@ static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) tptr = 0; rptr = 0; + /* + * If there was a collision in the last i2c transaction, + * Set I2COM_MASTER as it was cleared during collision. + */ + if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { + out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); + } + while (tptr < num) { pmsg = &msgs[tptr]; dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); @@ -440,7 +447,7 @@ static int cpm_i2c_setup(struct cpm_i2c *cpm) init_waitqueue_head(&cpm->i2c_wait); - cpm->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL); + cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); if (!cpm->irq) return -EINVAL; @@ -646,7 +653,7 @@ static int cpm_i2c_probe(struct platform_device *ofdev) cpm->ofdev = ofdev; - dev_set_drvdata(&ofdev->dev, cpm); + platform_set_drvdata(ofdev, cpm); cpm->adap = cpm_ops; i2c_set_adapdata(&cpm->adap, cpm); @@ -673,11 +680,6 @@ static int cpm_i2c_probe(struct platform_device *ofdev) dev_dbg(&ofdev->dev, "hw routines for %s registered.\n", cpm->adap.name); - /* - * register OF I2C devices - */ - of_i2c_register_devices(&cpm->adap); - return 0; out_shut: cpm_i2c_shutdown(cpm); @@ -689,7 +691,7 @@ out_free: static int cpm_i2c_remove(struct platform_device *ofdev) { - struct cpm_i2c *cpm = dev_get_drvdata(&ofdev->dev); + struct cpm_i2c *cpm = platform_get_drvdata(ofdev); i2c_del_adapter(&cpm->adap); diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index cf20e06..af0b583 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -38,10 +38,7 @@ #include <linux/slab.h> #include <linux/cpufreq.h> #include <linux/gpio.h> -#include <linux/of_i2c.h> #include <linux/of_device.h> - -#include <mach/hardware.h> #include <linux/platform_data/i2c-davinci.h> /* ----- global defines ----------------------------------------------- */ @@ -128,12 +125,12 @@ static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, int reg, u16 val) { - __raw_writew(val, i2c_dev->base + reg); + writew_relaxed(val, i2c_dev->base + reg); } static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) { - return __raw_readw(i2c_dev->base + reg); + return readw_relaxed(i2c_dev->base + reg); } /* Generate a pulse on the i2c clock pin. */ @@ -326,7 +323,7 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); - INIT_COMPLETION(dev->cmd_complete); + reinit_completion(&dev->cmd_complete); dev->cmd_err = 0; /* Take I2C out of reset and configure it as master */ @@ -646,13 +643,6 @@ static int davinci_i2c_probe(struct platform_device *pdev) struct resource *mem, *irq; int r; - /* NOTE: driver uses the static register mapping */ - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(&pdev->dev, "no mem resource?\n"); - return -ENODEV; - } - irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!irq) { dev_err(&pdev->dev, "no irq resource?\n"); @@ -672,7 +662,7 @@ static int davinci_i2c_probe(struct platform_device *pdev) #endif dev->dev = &pdev->dev; dev->irq = irq->start; - dev->pdata = dev->dev->platform_data; + dev->pdata = dev_get_platdata(&pdev->dev); platform_set_drvdata(pdev, dev); if (!dev->pdata && pdev->dev.of_node) { @@ -697,6 +687,7 @@ static int davinci_i2c_probe(struct platform_device *pdev) return -ENODEV; clk_prepare_enable(dev->clk); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dev->base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(dev->base)) { r = PTR_ERR(dev->base); @@ -734,7 +725,6 @@ static int davinci_i2c_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failure adding adapter\n"); goto err_unuse_clocks; } - of_i2c_register_devices(adap); return 0; @@ -805,7 +795,7 @@ static struct platform_driver davinci_i2c_driver = { .name = "i2c_davinci", .owner = THIS_MODULE, .pm = davinci_i2c_pm_ops, - .of_match_table = of_match_ptr(davinci_i2c_of_match), + .of_match_table = davinci_i2c_of_match, }, }; diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c index c41ca63..e89e3e2 100644 --- a/drivers/i2c/busses/i2c-designware-core.c +++ b/drivers/i2c/busses/i2c-designware-core.c @@ -67,9 +67,12 @@ #define DW_IC_STATUS 0x70 #define DW_IC_TXFLR 0x74 #define DW_IC_RXFLR 0x78 +#define DW_IC_SDA_HOLD 0x7c #define DW_IC_TX_ABRT_SOURCE 0x80 #define DW_IC_ENABLE_STATUS 0x9c #define DW_IC_COMP_PARAM_1 0xf4 +#define DW_IC_COMP_VERSION 0xf8 +#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A #define DW_IC_COMP_TYPE 0xfc #define DW_IC_COMP_TYPE_VALUE 0x44570140 @@ -95,6 +98,8 @@ #define DW_IC_ERR_TX_ABRT 0x1 +#define DW_IC_TAR_10BITADDR_MASTER BIT(12) + /* * status codes */ @@ -314,6 +319,12 @@ int i2c_dw_init(struct dw_i2c_dev *dev) 47, /* tLOW = 4.7 us */ 3, /* tf = 0.3 us */ 0); /* No offset */ + + /* Allow platforms to specify the ideal HCNT and LCNT values */ + if (dev->ss_hcnt && dev->ss_lcnt) { + hcnt = dev->ss_hcnt; + lcnt = dev->ss_lcnt; + } dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); @@ -328,10 +339,25 @@ int i2c_dw_init(struct dw_i2c_dev *dev) 13, /* tLOW = 1.3 us */ 3, /* tf = 0.3 us */ 0); /* No offset */ + + if (dev->fs_hcnt && dev->fs_lcnt) { + hcnt = dev->fs_hcnt; + lcnt = dev->fs_lcnt; + } dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); + /* Configure SDA Hold Time if required */ + if (dev->sda_hold_time) { + reg = dw_readl(dev, DW_IC_COMP_VERSION); + if (reg >= DW_IC_SDA_HOLD_MIN_VERS) + dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); + else + dev_warn(dev->dev, + "Hardware too old to adjust SDA hold time."); + } + /* Configure Tx/Rx FIFO threshold levels */ dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); dw_writel(dev, 0, DW_IC_RX_TL); @@ -364,22 +390,34 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) { struct i2c_msg *msgs = dev->msgs; - u32 ic_con; + u32 ic_con, ic_tar = 0; /* Disable the adapter */ __i2c_dw_enable(dev, false); - /* set the slave (target) address */ - dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); - /* if the slave address is ten bit address, enable 10BITADDR */ ic_con = dw_readl(dev, DW_IC_CON); - if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) + if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { ic_con |= DW_IC_CON_10BITADDR_MASTER; - else + /* + * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing + * mode has to be enabled via bit 12 of IC_TAR register. + * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be + * detected from registers. + */ + ic_tar = DW_IC_TAR_10BITADDR_MASTER; + } else { ic_con &= ~DW_IC_CON_10BITADDR_MASTER; + } + dw_writel(dev, ic_con, DW_IC_CON); + /* + * Set the slave (target) address and enable 10-bit addressing mode + * if applicable. + */ + dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR); + /* Enable the adapter */ __i2c_dw_enable(dev, true); @@ -403,6 +441,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) u32 addr = msgs[dev->msg_write_idx].addr; u32 buf_len = dev->tx_buf_len; u8 *buf = dev->tx_buf; + bool need_restart = false; intr_mask = DW_IC_INTR_DEFAULT_MASK; @@ -430,6 +469,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) /* new i2c_msg */ buf = msgs[dev->msg_write_idx].buf; buf_len = msgs[dev->msg_write_idx].len; + + /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and + * IC_RESTART_EN are set, we must manually + * set restart bit between messages. + */ + if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && + (dev->msg_write_idx > 0)) + need_restart = true; } tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); @@ -448,6 +495,11 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) buf_len == 1) cmd |= BIT(9); + if (need_restart) { + cmd |= BIT(10); + need_restart = false; + } + if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { /* avoid rx buffer overrun */ @@ -561,7 +613,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) mutex_lock(&dev->lock); pm_runtime_get_sync(dev->dev); - INIT_COMPLETION(dev->cmd_complete); + reinit_completion(&dev->cmd_complete); dev->msgs = msgs; dev->msgs_num = num; dev->cmd_err = 0; @@ -580,14 +632,23 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) i2c_dw_xfer_init(dev); /* wait for tx to complete */ - ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); + ret = wait_for_completion_timeout(&dev->cmd_complete, HZ); if (ret == 0) { dev_err(dev->dev, "controller timed out\n"); + /* i2c_dw_init implicitly disables the adapter */ i2c_dw_init(dev); ret = -ETIMEDOUT; goto done; - } else if (ret < 0) - goto done; + } + + /* + * We must disable the adapter before unlocking the &dev->lock mutex + * below. Otherwise the hardware might continue generating interrupts + * which in turn causes a race condition with the following transfer. + * Needs some more investigation if the additional interrupts are + * a hardware bug or this driver doesn't handle them correctly yet. + */ + __i2c_dw_enable(dev, false); if (dev->msg_err) { ret = dev->msg_err; @@ -596,8 +657,6 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) /* no error */ if (likely(!dev->cmd_err)) { - /* Disable the adapter */ - __i2c_dw_enable(dev, false); ret = num; goto done; } diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index e761ad1..e8a7565 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -61,6 +61,14 @@ * @tx_fifo_depth: depth of the hardware tx fifo * @rx_fifo_depth: depth of the hardware rx fifo * @rx_outstanding: current master-rx elements in tx fifo + * @ss_hcnt: standard speed HCNT value + * @ss_lcnt: standard speed LCNT value + * @fs_hcnt: fast speed HCNT value + * @fs_lcnt: fast speed LCNT value + * + * HCNT and LCNT parameters can be used if the platform knows more accurate + * values than the one computed based only on the input clock frequency. + * Leave them to be %0 if not used. */ struct dw_i2c_dev { struct device *dev; @@ -90,6 +98,11 @@ struct dw_i2c_dev { unsigned int tx_fifo_depth; unsigned int rx_fifo_depth; int rx_outstanding; + u32 sda_hold_time; + u16 ss_hcnt; + u16 ss_lcnt; + u16 fs_hcnt; + u16 fs_lcnt; }; #define ACCESS_SWAP 0x00000001 diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c index 35b70a1..d0bdac0 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -34,7 +34,7 @@ #include <linux/sched.h> #include <linux/err.h> #include <linux/interrupt.h> -#include <linux/of_i2c.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/pm_runtime.h> @@ -53,9 +53,33 @@ static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev) } #ifdef CONFIG_ACPI +static void dw_i2c_acpi_params(struct platform_device *pdev, char method[], + u16 *hcnt, u16 *lcnt, u32 *sda_hold) +{ + struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; + acpi_handle handle = ACPI_HANDLE(&pdev->dev); + union acpi_object *obj; + + if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf))) + return; + + obj = (union acpi_object *)buf.pointer; + if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { + const union acpi_object *objs = obj->package.elements; + + *hcnt = (u16)objs[0].integer.value; + *lcnt = (u16)objs[1].integer.value; + if (sda_hold) + *sda_hold = (u32)objs[2].integer.value; + } + + kfree(buf.pointer); +} + static int dw_i2c_acpi_configure(struct platform_device *pdev) { struct dw_i2c_dev *dev = platform_get_drvdata(pdev); + bool fs_mode = dev->master_cfg & DW_IC_CON_SPEED_FAST; if (!ACPI_HANDLE(&pdev->dev)) return -ENODEV; @@ -63,12 +87,24 @@ static int dw_i2c_acpi_configure(struct platform_device *pdev) dev->adapter.nr = -1; dev->tx_fifo_depth = 32; dev->rx_fifo_depth = 32; + + /* + * Try to get SDA hold time and *CNT values from an ACPI method if + * it exists for both supported speed modes. + */ + dw_i2c_acpi_params(pdev, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, + fs_mode ? NULL : &dev->sda_hold_time); + dw_i2c_acpi_params(pdev, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, + fs_mode ? &dev->sda_hold_time : NULL); + return 0; } static const struct acpi_device_id dw_i2c_acpi_match[] = { { "INT33C2", 0 }, { "INT33C3", 0 }, + { "INT3432", 0 }, + { "INT3433", 0 }, { "80860F41", 0 }, { } }; @@ -87,13 +123,6 @@ static int dw_i2c_probe(struct platform_device *pdev) struct resource *mem; int irq, r; - /* NOTE: driver uses the static register mapping */ - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(&pdev->dev, "no mem resource?\n"); - return -EINVAL; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq resource?\n"); @@ -104,6 +133,7 @@ static int dw_i2c_probe(struct platform_device *pdev) if (!dev) return -ENOMEM; + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dev->base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(dev->base)) return PTR_ERR(dev->base); @@ -121,6 +151,16 @@ static int dw_i2c_probe(struct platform_device *pdev) return PTR_ERR(dev->clk); clk_prepare_enable(dev->clk); + if (pdev->dev.of_node) { + u32 ht = 0; + u32 ic_clk = dev->get_clk_rate_khz(dev); + + of_property_read_u32(pdev->dev.of_node, + "i2c-sda-hold-time-ns", &ht); + dev->sda_hold_time = div_u64((u64)ic_clk * ht + 500000, + 1000000); + } + dev->functionality = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | @@ -167,8 +207,6 @@ static int dw_i2c_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failure adding adapter\n"); return r; } - of_i2c_register_devices(adap); - acpi_i2c_register_devices(adap); pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); pm_runtime_use_autosuspend(&pdev->dev); @@ -202,7 +240,7 @@ static const struct of_device_id dw_i2c_of_match[] = { MODULE_DEVICE_TABLE(of, dw_i2c_of_match); #endif -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int dw_i2c_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -223,27 +261,31 @@ static int dw_i2c_resume(struct device *dev) return 0; } -#endif static SIMPLE_DEV_PM_OPS(dw_i2c_dev_pm_ops, dw_i2c_suspend, dw_i2c_resume); +#define DW_I2C_DEV_PM_OPS (&dw_i2c_dev_pm_ops) +#else +#define DW_I2C_DEV_PM_OPS NULL +#endif /* work with hotplug and coldplug */ MODULE_ALIAS("platform:i2c_designware"); static struct platform_driver dw_i2c_driver = { - .remove = dw_i2c_remove, + .probe = dw_i2c_probe, + .remove = dw_i2c_remove, .driver = { .name = "i2c_designware", .owner = THIS_MODULE, .of_match_table = of_match_ptr(dw_i2c_of_match), .acpi_match_table = ACPI_PTR(dw_i2c_acpi_match), - .pm = &dw_i2c_dev_pm_ops, + .pm = DW_I2C_DEV_PM_OPS, }, }; static int __init dw_i2c_init_driver(void) { - return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); + return platform_driver_register(&dw_i2c_driver); } subsys_initcall(dw_i2c_init_driver); diff --git a/drivers/i2c/busses/i2c-diolan-u2c.c b/drivers/i2c/busses/i2c-diolan-u2c.c index dae3ddf..721f7eb 100644 --- a/drivers/i2c/busses/i2c-diolan-u2c.c +++ b/drivers/i2c/busses/i2c-diolan-u2c.c @@ -25,8 +25,6 @@ #define USB_VENDOR_ID_DIOLAN 0x0abf #define USB_DEVICE_ID_DIOLAN_U2C 0x3370 -#define DIOLAN_OUT_EP 0x02 -#define DIOLAN_IN_EP 0x84 /* commands via USB, must match command ids in the firmware */ #define CMD_I2C_READ 0x01 @@ -84,6 +82,7 @@ struct i2c_diolan_u2c { u8 obuffer[DIOLAN_OUTBUF_LEN]; /* output buffer */ u8 ibuffer[DIOLAN_INBUF_LEN]; /* input buffer */ + int ep_in, ep_out; /* Endpoints */ struct usb_device *usb_dev; /* the usb device for this device */ struct usb_interface *interface;/* the interface for this device */ struct i2c_adapter adapter; /* i2c related things */ @@ -109,7 +108,7 @@ static int diolan_usb_transfer(struct i2c_diolan_u2c *dev) return -EINVAL; ret = usb_bulk_msg(dev->usb_dev, - usb_sndbulkpipe(dev->usb_dev, DIOLAN_OUT_EP), + usb_sndbulkpipe(dev->usb_dev, dev->ep_out), dev->obuffer, dev->olen, &actual, DIOLAN_USB_TIMEOUT); if (!ret) { @@ -118,7 +117,7 @@ static int diolan_usb_transfer(struct i2c_diolan_u2c *dev) tmpret = usb_bulk_msg(dev->usb_dev, usb_rcvbulkpipe(dev->usb_dev, - DIOLAN_IN_EP), + dev->ep_in), dev->ibuffer, sizeof(dev->ibuffer), &actual, DIOLAN_USB_TIMEOUT); @@ -210,7 +209,7 @@ static void diolan_flush_input(struct i2c_diolan_u2c *dev) int ret; ret = usb_bulk_msg(dev->usb_dev, - usb_rcvbulkpipe(dev->usb_dev, DIOLAN_IN_EP), + usb_rcvbulkpipe(dev->usb_dev, dev->ep_in), dev->ibuffer, sizeof(dev->ibuffer), &actual, DIOLAN_USB_TIMEOUT); if (ret < 0 || actual == 0) @@ -445,9 +444,14 @@ static void diolan_u2c_free(struct i2c_diolan_u2c *dev) static int diolan_u2c_probe(struct usb_interface *interface, const struct usb_device_id *id) { + struct usb_host_interface *hostif = interface->cur_altsetting; struct i2c_diolan_u2c *dev; int ret; + if (hostif->desc.bInterfaceNumber != 0 + || hostif->desc.bNumEndpoints < 2) + return -ENODEV; + /* allocate memory for our device state and initialize it */ dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (dev == NULL) { @@ -455,6 +459,8 @@ static int diolan_u2c_probe(struct usb_interface *interface, ret = -ENOMEM; goto error; } + dev->ep_out = hostif->endpoint[0].desc.bEndpointAddress; + dev->ep_in = hostif->endpoint[1].desc.bEndpointAddress; dev->usb_dev = usb_get_dev(interface_to_usbdev(interface)); dev->interface = interface; diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c index 0f37529..ff15ae9 100644 --- a/drivers/i2c/busses/i2c-eg20t.c +++ b/drivers/i2c/busses/i2c-eg20t.c @@ -312,24 +312,6 @@ static void pch_i2c_start(struct i2c_algo_pch_data *adap) } /** - * pch_i2c_getack() - to confirm ACK/NACK - * @adap: Pointer to struct i2c_algo_pch_data. - */ -static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap) -{ - u32 reg_val; - void __iomem *p = adap->pch_base_address; - reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK; - - if (reg_val != 0) { - pch_err(adap, "return%d\n", -EPROTO); - return -EPROTO; - } - - return 0; -} - -/** * pch_i2c_stop() - generate stop condition in normal mode. * @adap: Pointer to struct i2c_algo_pch_data. */ @@ -344,6 +326,7 @@ static void pch_i2c_stop(struct i2c_algo_pch_data *adap) static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap) { long ret; + void __iomem *p = adap->pch_base_address; ret = wait_event_timeout(pch_event, (adap->pch_event_flag != 0), msecs_to_jiffies(1000)); @@ -366,10 +349,9 @@ static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap) adap->pch_event_flag = 0; - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); - return -EIO; + if (ioread32(p + PCH_I2CSR) & PCH_GETACK) { + pch_dbg(adap, "Receive NACK for slave address setting\n"); + return -ENXIO; } return 0; diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c new file mode 100644 index 0000000..c1ef228 --- /dev/null +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -0,0 +1,769 @@ +/** + * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/module.h> + +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/time.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/spinlock.h> + +/* + * HSI2C controller from Samsung supports 2 modes of operation + * 1. Auto mode: Where in master automatically controls the whole transaction + * 2. Manual mode: Software controls the transaction by issuing commands + * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. + * + * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register + * + * Special bits are available for both modes of operation to set commands + * and for checking transfer status + */ + +/* Register Map */ +#define HSI2C_CTL 0x00 +#define HSI2C_FIFO_CTL 0x04 +#define HSI2C_TRAILIG_CTL 0x08 +#define HSI2C_CLK_CTL 0x0C +#define HSI2C_CLK_SLOT 0x10 +#define HSI2C_INT_ENABLE 0x20 +#define HSI2C_INT_STATUS 0x24 +#define HSI2C_ERR_STATUS 0x2C +#define HSI2C_FIFO_STATUS 0x30 +#define HSI2C_TX_DATA 0x34 +#define HSI2C_RX_DATA 0x38 +#define HSI2C_CONF 0x40 +#define HSI2C_AUTO_CONF 0x44 +#define HSI2C_TIMEOUT 0x48 +#define HSI2C_MANUAL_CMD 0x4C +#define HSI2C_TRANS_STATUS 0x50 +#define HSI2C_TIMING_HS1 0x54 +#define HSI2C_TIMING_HS2 0x58 +#define HSI2C_TIMING_HS3 0x5C +#define HSI2C_TIMING_FS1 0x60 +#define HSI2C_TIMING_FS2 0x64 +#define HSI2C_TIMING_FS3 0x68 +#define HSI2C_TIMING_SLA 0x6C +#define HSI2C_ADDR 0x70 + +/* I2C_CTL Register bits */ +#define HSI2C_FUNC_MODE_I2C (1u << 0) +#define HSI2C_MASTER (1u << 3) +#define HSI2C_RXCHON (1u << 6) +#define HSI2C_TXCHON (1u << 7) +#define HSI2C_SW_RST (1u << 31) + +/* I2C_FIFO_CTL Register bits */ +#define HSI2C_RXFIFO_EN (1u << 0) +#define HSI2C_TXFIFO_EN (1u << 1) +#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) +#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) + +/* As per user manual FIFO max depth is 64bytes */ +#define HSI2C_FIFO_MAX 0x40 +/* default trigger levels for Tx and Rx FIFOs */ +#define HSI2C_DEF_TXFIFO_LVL (HSI2C_FIFO_MAX - 0x30) +#define HSI2C_DEF_RXFIFO_LVL (HSI2C_FIFO_MAX - 0x10) + +/* I2C_TRAILING_CTL Register bits */ +#define HSI2C_TRAILING_COUNT (0xf) + +/* I2C_INT_EN Register bits */ +#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) +#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) +#define HSI2C_INT_TRAILING_EN (1u << 6) +#define HSI2C_INT_I2C_EN (1u << 9) + +/* I2C_INT_STAT Register bits */ +#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) +#define HSI2C_INT_RX_ALMOSTFULL (1u << 1) +#define HSI2C_INT_TX_UNDERRUN (1u << 2) +#define HSI2C_INT_TX_OVERRUN (1u << 3) +#define HSI2C_INT_RX_UNDERRUN (1u << 4) +#define HSI2C_INT_RX_OVERRUN (1u << 5) +#define HSI2C_INT_TRAILING (1u << 6) +#define HSI2C_INT_I2C (1u << 9) + +/* I2C_FIFO_STAT Register bits */ +#define HSI2C_RX_FIFO_EMPTY (1u << 24) +#define HSI2C_RX_FIFO_FULL (1u << 23) +#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) +#define HSI2C_TX_FIFO_EMPTY (1u << 8) +#define HSI2C_TX_FIFO_FULL (1u << 7) +#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) + +/* I2C_CONF Register bits */ +#define HSI2C_AUTO_MODE (1u << 31) +#define HSI2C_10BIT_ADDR_MODE (1u << 30) +#define HSI2C_HS_MODE (1u << 29) + +/* I2C_AUTO_CONF Register bits */ +#define HSI2C_READ_WRITE (1u << 16) +#define HSI2C_STOP_AFTER_TRANS (1u << 17) +#define HSI2C_MASTER_RUN (1u << 31) + +/* I2C_TIMEOUT Register bits */ +#define HSI2C_TIMEOUT_EN (1u << 31) +#define HSI2C_TIMEOUT_MASK 0xff + +/* I2C_TRANS_STATUS register bits */ +#define HSI2C_MASTER_BUSY (1u << 17) +#define HSI2C_SLAVE_BUSY (1u << 16) +#define HSI2C_TIMEOUT_AUTO (1u << 4) +#define HSI2C_NO_DEV (1u << 3) +#define HSI2C_NO_DEV_ACK (1u << 2) +#define HSI2C_TRANS_ABORT (1u << 1) +#define HSI2C_TRANS_DONE (1u << 0) + +/* I2C_ADDR register bits */ +#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) +#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) +#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) +#define MASTER_ID(x) ((x & 0x7) + 0x08) + +/* + * Controller operating frequency, timing values for operation + * are calculated against this frequency + */ +#define HSI2C_HS_TX_CLOCK 1000000 +#define HSI2C_FS_TX_CLOCK 100000 +#define HSI2C_HIGH_SPD 1 +#define HSI2C_FAST_SPD 0 + +#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000)) + +struct exynos5_i2c { + struct i2c_adapter adap; + unsigned int suspended:1; + + struct i2c_msg *msg; + struct completion msg_complete; + unsigned int msg_ptr; + + unsigned int irq; + + void __iomem *regs; + struct clk *clk; + struct device *dev; + int state; + + spinlock_t lock; /* IRQ synchronization */ + + /* + * Since the TRANS_DONE bit is cleared on read, and we may read it + * either during an IRQ or after a transaction, keep track of its + * state here. + */ + int trans_done; + + /* Controller operating frequency */ + unsigned int fs_clock; + unsigned int hs_clock; + + /* + * HSI2C Controller can operate in + * 1. High speed upto 3.4Mbps + * 2. Fast speed upto 1Mbps + */ + int speed_mode; +}; + +static const struct of_device_id exynos5_i2c_match[] = { + { .compatible = "samsung,exynos5-hsi2c" }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos5_i2c_match); + +static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) +{ + writel(readl(i2c->regs + HSI2C_INT_STATUS), + i2c->regs + HSI2C_INT_STATUS); +} + +/* + * exynos5_i2c_set_timing: updates the registers with appropriate + * timing values calculated + * + * Returns 0 on success, -EINVAL if the cycle length cannot + * be calculated. + */ +static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) +{ + u32 i2c_timing_s1; + u32 i2c_timing_s2; + u32 i2c_timing_s3; + u32 i2c_timing_sla; + unsigned int t_start_su, t_start_hd; + unsigned int t_stop_su; + unsigned int t_data_su, t_data_hd; + unsigned int t_scl_l, t_scl_h; + unsigned int t_sr_release; + unsigned int t_ftl_cycle; + unsigned int clkin = clk_get_rate(i2c->clk); + unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle; + unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ? + i2c->hs_clock : i2c->fs_clock; + + /* + * FPCLK / FI2C = + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE + * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + * utemp1 = (TSCLK_L + TSCLK_H + 2) + */ + t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; + utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + + /* CLK_DIV max is 256 */ + for (div = 0; div < 256; div++) { + utemp1 = utemp0 / (div + 1); + + /* + * SCL_L and SCL_H each has max value of 255 + * Hence, For the clk_cycle to the have right value + * utemp1 has to be less then 512 and more than 4. + */ + if ((utemp1 < 512) && (utemp1 > 4)) { + clk_cycle = utemp1 - 2; + break; + } else if (div == 255) { + dev_warn(i2c->dev, "Failed to calculate divisor"); + return -EINVAL; + } + } + + t_scl_l = clk_cycle / 2; + t_scl_h = clk_cycle / 2; + t_start_su = t_scl_l; + t_start_hd = t_scl_l; + t_stop_su = t_scl_l; + t_data_su = t_scl_l / 2; + t_data_hd = t_scl_l / 2; + t_sr_release = clk_cycle; + + i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; + i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; + i2c_timing_s3 = div << 16 | t_sr_release << 0; + i2c_timing_sla = t_data_hd << 0; + + dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", + t_start_su, t_start_hd, t_stop_su); + dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", + t_data_su, t_scl_l, t_scl_h); + dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", + div, t_sr_release); + dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); + + if (mode == HSI2C_HIGH_SPD) { + writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); + writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); + } else { + writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); + writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); + writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); + } + writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); + + return 0; +} + +static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) +{ + /* + * Configure the Fast speed timing values + * Even the High Speed mode initially starts with Fast mode + */ + if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) { + dev_err(i2c->dev, "HSI2C FS Clock set up failed\n"); + return -EINVAL; + } + + /* configure the High speed timing values */ + if (i2c->speed_mode == HSI2C_HIGH_SPD) { + if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) { + dev_err(i2c->dev, "HSI2C HS Clock set up failed\n"); + return -EINVAL; + } + } + + return 0; +} + +/* + * exynos5_i2c_init: configures the controller for I2C functionality + * Programs I2C controller for Master mode operation + */ +static void exynos5_i2c_init(struct exynos5_i2c *i2c) +{ + u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); + u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); + + /* Clear to disable Timeout */ + i2c_timeout &= ~HSI2C_TIMEOUT_EN; + writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); + + writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + i2c->regs + HSI2C_CTL); + writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); + + if (i2c->speed_mode == HSI2C_HIGH_SPD) { + writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), + i2c->regs + HSI2C_ADDR); + i2c_conf |= HSI2C_HS_MODE; + } + + writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); +} + +static void exynos5_i2c_reset(struct exynos5_i2c *i2c) +{ + u32 i2c_ctl; + + /* Set and clear the bit for reset */ + i2c_ctl = readl(i2c->regs + HSI2C_CTL); + i2c_ctl |= HSI2C_SW_RST; + writel(i2c_ctl, i2c->regs + HSI2C_CTL); + + i2c_ctl = readl(i2c->regs + HSI2C_CTL); + i2c_ctl &= ~HSI2C_SW_RST; + writel(i2c_ctl, i2c->regs + HSI2C_CTL); + + /* We don't expect calculations to fail during the run */ + exynos5_hsi2c_clock_setup(i2c); + /* Initialize the configure registers */ + exynos5_i2c_init(i2c); +} + +/* + * exynos5_i2c_irq: top level IRQ servicing routine + * + * INT_STATUS registers gives the interrupt details. Further, + * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed + * state of the bus. + */ +static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) +{ + struct exynos5_i2c *i2c = dev_id; + u32 fifo_level, int_status, fifo_status, trans_status; + unsigned char byte; + int len = 0; + + i2c->state = -EINVAL; + + spin_lock(&i2c->lock); + + int_status = readl(i2c->regs + HSI2C_INT_STATUS); + writel(int_status, i2c->regs + HSI2C_INT_STATUS); + fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); + + /* handle interrupt related to the transfer status */ + if (int_status & HSI2C_INT_I2C) { + trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); + if (trans_status & HSI2C_NO_DEV_ACK) { + dev_dbg(i2c->dev, "No ACK from device\n"); + i2c->state = -ENXIO; + goto stop; + } else if (trans_status & HSI2C_NO_DEV) { + dev_dbg(i2c->dev, "No device\n"); + i2c->state = -ENXIO; + goto stop; + } else if (trans_status & HSI2C_TRANS_ABORT) { + dev_dbg(i2c->dev, "Deal with arbitration lose\n"); + i2c->state = -EAGAIN; + goto stop; + } else if (trans_status & HSI2C_TIMEOUT_AUTO) { + dev_dbg(i2c->dev, "Accessing device timed out\n"); + i2c->state = -EAGAIN; + goto stop; + } else if (trans_status & HSI2C_TRANS_DONE) { + i2c->trans_done = 1; + i2c->state = 0; + } + } + + if ((i2c->msg->flags & I2C_M_RD) && (int_status & + (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { + fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); + fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); + len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); + + while (len > 0) { + byte = (unsigned char) + readl(i2c->regs + HSI2C_RX_DATA); + i2c->msg->buf[i2c->msg_ptr++] = byte; + len--; + } + i2c->state = 0; + } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { + fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); + fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); + + len = HSI2C_FIFO_MAX - fifo_level; + if (len > (i2c->msg->len - i2c->msg_ptr)) + len = i2c->msg->len - i2c->msg_ptr; + + while (len > 0) { + byte = i2c->msg->buf[i2c->msg_ptr++]; + writel(byte, i2c->regs + HSI2C_TX_DATA); + len--; + } + i2c->state = 0; + } + + stop: + if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || + (i2c->state < 0)) { + writel(0, i2c->regs + HSI2C_INT_ENABLE); + exynos5_i2c_clr_pend_irq(i2c); + complete(&i2c->msg_complete); + } + + spin_unlock(&i2c->lock); + + return IRQ_HANDLED; +} + +/* + * exynos5_i2c_wait_bus_idle + * + * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being + * cleared. + * + * Returns -EBUSY if the bus cannot be bought to idle + */ +static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) +{ + unsigned long stop_time; + u32 trans_status; + + /* wait for 100 milli seconds for the bus to be idle */ + stop_time = jiffies + msecs_to_jiffies(100) + 1; + do { + trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); + if (!(trans_status & HSI2C_MASTER_BUSY)) + return 0; + + usleep_range(50, 200); + } while (time_before(jiffies, stop_time)); + + return -EBUSY; +} + +/* + * exynos5_i2c_message_start: Configures the bus and starts the xfer + * i2c: struct exynos5_i2c pointer for the current bus + * stop: Enables stop after transfer if set. Set for last transfer of + * in the list of messages. + * + * Configures the bus for read/write function + * Sets chip address to talk to, message length to be sent. + * Enables appropriate interrupts and sends start xfer command. + */ +static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) +{ + u32 i2c_ctl; + u32 int_en = HSI2C_INT_I2C_EN; + u32 i2c_auto_conf = 0; + u32 fifo_ctl; + unsigned long flags; + + i2c_ctl = readl(i2c->regs + HSI2C_CTL); + i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); + fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; + + if (i2c->msg->flags & I2C_M_RD) { + i2c_ctl |= HSI2C_RXCHON; + + i2c_auto_conf = HSI2C_READ_WRITE; + + fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(HSI2C_DEF_TXFIFO_LVL); + int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | + HSI2C_INT_TRAILING_EN); + } else { + i2c_ctl |= HSI2C_TXCHON; + + fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(HSI2C_DEF_RXFIFO_LVL); + int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; + } + + writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); + + writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); + writel(i2c_ctl, i2c->regs + HSI2C_CTL); + + + /* + * Enable interrupts before starting the transfer so that we don't + * miss any INT_I2C interrupts. + */ + spin_lock_irqsave(&i2c->lock, flags); + writel(int_en, i2c->regs + HSI2C_INT_ENABLE); + + if (stop == 1) + i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; + i2c_auto_conf |= i2c->msg->len; + i2c_auto_conf |= HSI2C_MASTER_RUN; + writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); + spin_unlock_irqrestore(&i2c->lock, flags); +} + +static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, + struct i2c_msg *msgs, int stop) +{ + unsigned long timeout; + int ret; + + i2c->msg = msgs; + i2c->msg_ptr = 0; + i2c->trans_done = 0; + + reinit_completion(&i2c->msg_complete); + + exynos5_i2c_message_start(i2c, stop); + + timeout = wait_for_completion_timeout(&i2c->msg_complete, + EXYNOS5_I2C_TIMEOUT); + if (timeout == 0) + ret = -ETIMEDOUT; + else + ret = i2c->state; + + /* + * If this is the last message to be transfered (stop == 1) + * Then check if the bus can be brought back to idle. + */ + if (ret == 0 && stop) + ret = exynos5_i2c_wait_bus_idle(i2c); + + if (ret < 0) { + exynos5_i2c_reset(i2c); + if (ret == -ETIMEDOUT) + dev_warn(i2c->dev, "%s timeout\n", + (msgs->flags & I2C_M_RD) ? "rx" : "tx"); + } + + /* Return the state as in interrupt routine */ + return ret; +} + +static int exynos5_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data; + int i = 0, ret = 0, stop = 0; + + if (i2c->suspended) { + dev_err(i2c->dev, "HS-I2C is not initialzed.\n"); + return -EIO; + } + + clk_prepare_enable(i2c->clk); + + for (i = 0; i < num; i++, msgs++) { + stop = (i == num - 1); + + ret = exynos5_i2c_xfer_msg(i2c, msgs, stop); + + if (ret < 0) + goto out; + } + + if (i == num) { + ret = num; + } else { + /* Only one message, cannot access the device */ + if (i == 1) + ret = -EREMOTEIO; + else + ret = i; + + dev_warn(i2c->dev, "xfer message failed\n"); + } + + out: + clk_disable_unprepare(i2c->clk); + return ret; +} + +static u32 exynos5_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); +} + +static const struct i2c_algorithm exynos5_i2c_algorithm = { + .master_xfer = exynos5_i2c_xfer, + .functionality = exynos5_i2c_func, +}; + +static int exynos5_i2c_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct exynos5_i2c *i2c; + struct resource *mem; + unsigned int op_clock; + int ret; + + i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); + if (!i2c) { + dev_err(&pdev->dev, "no memory for state\n"); + return -ENOMEM; + } + + if (of_property_read_u32(np, "clock-frequency", &op_clock)) { + i2c->speed_mode = HSI2C_FAST_SPD; + i2c->fs_clock = HSI2C_FS_TX_CLOCK; + } else { + if (op_clock >= HSI2C_HS_TX_CLOCK) { + i2c->speed_mode = HSI2C_HIGH_SPD; + i2c->fs_clock = HSI2C_FS_TX_CLOCK; + i2c->hs_clock = op_clock; + } else { + i2c->speed_mode = HSI2C_FAST_SPD; + i2c->fs_clock = op_clock; + } + } + + strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); + i2c->adap.owner = THIS_MODULE; + i2c->adap.algo = &exynos5_i2c_algorithm; + i2c->adap.retries = 3; + + i2c->dev = &pdev->dev; + i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); + if (IS_ERR(i2c->clk)) { + dev_err(&pdev->dev, "cannot get clock\n"); + return -ENOENT; + } + + clk_prepare_enable(i2c->clk); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c->regs = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(i2c->regs)) { + ret = PTR_ERR(i2c->regs); + goto err_clk; + } + + i2c->adap.dev.of_node = np; + i2c->adap.algo_data = i2c; + i2c->adap.dev.parent = &pdev->dev; + + /* Clear pending interrupts from u-boot or misc causes */ + exynos5_i2c_clr_pend_irq(i2c); + + spin_lock_init(&i2c->lock); + init_completion(&i2c->msg_complete); + + i2c->irq = ret = platform_get_irq(pdev, 0); + if (ret <= 0) { + dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); + ret = -EINVAL; + goto err_clk; + } + + ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, + IRQF_NO_SUSPEND | IRQF_ONESHOT, + dev_name(&pdev->dev), i2c); + + if (ret != 0) { + dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); + goto err_clk; + } + + ret = exynos5_hsi2c_clock_setup(i2c); + if (ret) + goto err_clk; + + exynos5_i2c_init(i2c); + + ret = i2c_add_adapter(&i2c->adap); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add bus to i2c core\n"); + goto err_clk; + } + + platform_set_drvdata(pdev, i2c); + + err_clk: + clk_disable_unprepare(i2c->clk); + return ret; +} + +static int exynos5_i2c_remove(struct platform_device *pdev) +{ + struct exynos5_i2c *i2c = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c->adap); + + return 0; +} + +static int exynos5_i2c_suspend_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct exynos5_i2c *i2c = platform_get_drvdata(pdev); + + i2c->suspended = 1; + + return 0; +} + +static int exynos5_i2c_resume_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct exynos5_i2c *i2c = platform_get_drvdata(pdev); + int ret = 0; + + clk_prepare_enable(i2c->clk); + + ret = exynos5_hsi2c_clock_setup(i2c); + if (ret) { + clk_disable_unprepare(i2c->clk); + return ret; + } + + exynos5_i2c_init(i2c); + clk_disable_unprepare(i2c->clk); + i2c->suspended = 0; + + return 0; +} + +static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_suspend_noirq, + exynos5_i2c_resume_noirq); + +static struct platform_driver exynos5_i2c_driver = { + .probe = exynos5_i2c_probe, + .remove = exynos5_i2c_remove, + .driver = { + .owner = THIS_MODULE, + .name = "exynos5-hsi2c", + .pm = &exynos5_i2c_dev_pm_ops, + .of_match_table = exynos5_i2c_match, + }, +}; + +module_platform_driver(exynos5_i2c_driver); + +MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); +MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>"); +MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c index bc6e139..d9f7e18 100644 --- a/drivers/i2c/busses/i2c-gpio.c +++ b/drivers/i2c/busses/i2c-gpio.c @@ -15,8 +15,8 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/gpio.h> +#include <linux/of.h> #include <linux/of_gpio.h> -#include <linux/of_i2c.h> struct i2c_gpio_private_data { struct i2c_adapter adap; @@ -137,9 +137,9 @@ static int i2c_gpio_probe(struct platform_device *pdev) if (ret) return ret; } else { - if (!pdev->dev.platform_data) + if (!dev_get_platdata(&pdev->dev)) return -ENXIO; - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); sda_pin = pdata->sda_pin; scl_pin = pdata->scl_pin; } @@ -171,7 +171,7 @@ static int i2c_gpio_probe(struct platform_device *pdev) pdata->scl_pin = scl_pin; of_i2c_gpio_get_props(pdev->dev.of_node, pdata); } else { - memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); + memcpy(pdata, dev_get_platdata(&pdev->dev), sizeof(*pdata)); } if (pdata->sda_is_open_drain) { @@ -224,8 +224,6 @@ static int i2c_gpio_probe(struct platform_device *pdev) if (ret) goto err_add_bus; - of_i2c_register_devices(adap); - platform_set_drvdata(pdev, priv); dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n", diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 3a6903f..737e298 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -58,6 +58,8 @@ Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes + Coleto Creek (PCH) 0x23b0 32 hard yes yes yes + Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes Features supported by this driver: Software PEC no @@ -86,7 +88,6 @@ #include <linux/slab.h> #include <linux/wait.h> #include <linux/err.h> -#include <linux/of_i2c.h> #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ defined CONFIG_DMI @@ -169,6 +170,7 @@ #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 +#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 @@ -176,6 +178,7 @@ #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 struct i801_mux_config { char *gpio_chip; @@ -817,6 +820,8 @@ static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, { 0, } }; @@ -1227,7 +1232,6 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) goto exit_free_irq; } - of_i2c_register_devices(&priv->adapter); i801_probe_optional_slaves(priv); /* We ignore errors - multiplexing is optional */ i801_add_mux(priv); diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c index 405a2e2..f744410 100644 --- a/drivers/i2c/busses/i2c-ibm_iic.c +++ b/drivers/i2c/busses/i2c-ibm_iic.c @@ -41,8 +41,9 @@ #include <asm/irq.h> #include <linux/io.h> #include <linux/i2c.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/of_i2c.h> #include "i2c-ibm_iic.h" @@ -705,7 +706,7 @@ static int iic_probe(struct platform_device *ofdev) return -ENOMEM; } - dev_set_drvdata(&ofdev->dev, dev); + platform_set_drvdata(ofdev, dev); dev->vaddr = of_iomap(np, 0); if (dev->vaddr == NULL) { @@ -759,9 +760,6 @@ static int iic_probe(struct platform_device *ofdev) dev_info(&ofdev->dev, "using %s mode\n", dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)"); - /* Now register all the child nodes */ - of_i2c_register_devices(adap); - return 0; error_cleanup: @@ -782,7 +780,7 @@ error_cleanup: */ static int iic_remove(struct platform_device *ofdev) { - struct ibm_iic_private *dev = dev_get_drvdata(&ofdev->dev); + struct ibm_iic_private *dev = platform_get_drvdata(ofdev); i2c_del_adapter(&dev->adap); diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index 82f20c6..1d7efa3 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -30,6 +30,8 @@ * Copyright (C) 2007 RightHand Technologies, Inc. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> * + * Copyright 2013 Freescale Semiconductor, Inc. + * */ /** Includes ******************************************************************* @@ -50,8 +52,6 @@ #include <linux/slab.h> #include <linux/of.h> #include <linux/of_device.h> -#include <linux/of_i2c.h> -#include <linux/pinctrl/consumer.h> #include <linux/platform_data/i2c-imx.h> /** Defines ******************************************************************** @@ -63,12 +63,22 @@ /* Default value */ #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ -/* IMX I2C registers */ +/* IMX I2C registers: + * the I2C register offset is different between SoCs, + * to provid support for all these chips, split the + * register offset into a fixed base address and a + * variable shift value, then the full register offset + * will be calculated by + * reg_off = ( reg_base_addr << reg_shift) + */ #define IMX_I2C_IADR 0x00 /* i2c slave address */ -#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ -#define IMX_I2C_I2CR 0x08 /* i2c control */ -#define IMX_I2C_I2SR 0x0C /* i2c status */ -#define IMX_I2C_I2DR 0x10 /* i2c transfer data */ +#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ +#define IMX_I2C_I2CR 0x02 /* i2c control */ +#define IMX_I2C_I2SR 0x03 /* i2c status */ +#define IMX_I2C_I2DR 0x04 /* i2c transfer data */ + +#define IMX_I2C_REGSHIFT 2 +#define VF610_I2C_REGSHIFT 0 /* Bits of IMX I2C registers */ #define I2SR_RXAK 0x01 @@ -85,6 +95,19 @@ #define I2CR_IIEN 0x40 #define I2CR_IEN 0x80 +/* register bits different operating codes definition: + * 1) I2SR: Interrupt flags clear operation differ between SoCs: + * - write zero to clear(w0c) INT flag on i.MX, + * - but write one to clear(w1c) INT flag on Vybrid. + * 2) I2CR: I2C module enable operation also differ between SoCs: + * - set I2CR_IEN bit enable the module on i.MX, + * - but clear I2CR_IEN bit enable the module on Vybrid. + */ +#define I2SR_CLR_OPCODE_W0C 0x0 +#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) +#define I2CR_IEN_OPCODE_0 0x0 +#define I2CR_IEN_OPCODE_1 I2CR_IEN + /** Variables ****************************************************************** *******************************************************************************/ @@ -96,8 +119,12 @@ * * Duplicated divider values removed from list */ +struct imx_i2c_clk_pair { + u16 div; + u16 val; +}; -static u16 __initdata i2c_clk_div[50][2] = { +static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, @@ -113,9 +140,38 @@ static u16 __initdata i2c_clk_div[50][2] = { { 3072, 0x1E }, { 3840, 0x1F } }; +/* Vybrid VF610 clock divider, register value pairs */ +static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, +}; + enum imx_i2c_type { IMX1_I2C, IMX21_I2C, + VF610_I2C, +}; + +struct imx_i2c_hwdata { + enum imx_i2c_type devtype; + unsigned regshift; + struct imx_i2c_clk_pair *clk_div; + unsigned ndivs; + unsigned i2sr_clr_opcode; + unsigned i2cr_ien_opcode; }; struct imx_i2c_struct { @@ -127,16 +183,46 @@ struct imx_i2c_struct { unsigned int disable_delay; int stopped; unsigned int ifdr; /* IMX_I2C_IFDR */ - enum imx_i2c_type devtype; + const struct imx_i2c_hwdata *hwdata; +}; + +static const struct imx_i2c_hwdata imx1_i2c_hwdata = { + .devtype = IMX1_I2C, + .regshift = IMX_I2C_REGSHIFT, + .clk_div = imx_i2c_clk_div, + .ndivs = ARRAY_SIZE(imx_i2c_clk_div), + .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, + .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, + +}; + +static const struct imx_i2c_hwdata imx21_i2c_hwdata = { + .devtype = IMX21_I2C, + .regshift = IMX_I2C_REGSHIFT, + .clk_div = imx_i2c_clk_div, + .ndivs = ARRAY_SIZE(imx_i2c_clk_div), + .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, + .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, + +}; + +static struct imx_i2c_hwdata vf610_i2c_hwdata = { + .devtype = VF610_I2C, + .regshift = VF610_I2C_REGSHIFT, + .clk_div = vf610_i2c_clk_div, + .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), + .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, + .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, + }; static struct platform_device_id imx_i2c_devtype[] = { { .name = "imx1-i2c", - .driver_data = IMX1_I2C, + .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, }, { .name = "imx21-i2c", - .driver_data = IMX21_I2C, + .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, }, { /* sentinel */ } @@ -144,14 +230,28 @@ static struct platform_device_id imx_i2c_devtype[] = { MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); static const struct of_device_id i2c_imx_dt_ids[] = { - { .compatible = "fsl,imx1-i2c", .data = &imx_i2c_devtype[IMX1_I2C], }, - { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], }, + { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, + { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, + { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) { - return i2c_imx->devtype == IMX1_I2C; + return i2c_imx->hwdata->devtype == IMX1_I2C; +} + +static inline void imx_i2c_write_reg(unsigned int val, + struct imx_i2c_struct *i2c_imx, unsigned int reg) +{ + writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); +} + +static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, + unsigned int reg) +{ + return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); } /** Functions for IMX I2C adapter driver *************************************** @@ -165,7 +265,7 @@ static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); while (1) { - temp = readb(i2c_imx->base + IMX_I2C_I2SR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); if (for_busy && (temp & I2SR_IBB)) break; if (!for_busy && !(temp & I2SR_IBB)) @@ -196,7 +296,7 @@ static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) { - if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) { + if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); return -EIO; /* No ACK */ } @@ -213,25 +313,25 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); clk_prepare_enable(i2c_imx->clk); - writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR); + imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); /* Enable I2C controller */ - writeb(0, i2c_imx->base + IMX_I2C_I2SR); - writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); /* Wait controller to be stable */ udelay(50); /* Start I2C transaction */ - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); temp |= I2CR_MSTA; - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); result = i2c_imx_bus_busy(i2c_imx, 1); if (result) return result; i2c_imx->stopped = 0; temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); return result; } @@ -242,9 +342,9 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) if (!i2c_imx->stopped) { /* Stop I2C transaction */ dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); temp &= ~(I2CR_MSTA | I2CR_MTX); - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); } if (is_imx1_i2c(i2c_imx)) { /* @@ -260,13 +360,15 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) } /* Disable I2C controller */ - writeb(0, i2c_imx->base + IMX_I2C_I2CR); + temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); clk_disable_unprepare(i2c_imx->clk); } -static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, +static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, unsigned int rate) { + struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; unsigned int i2c_clk_rate; unsigned int div; int i; @@ -274,15 +376,15 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, /* Divider value calculation */ i2c_clk_rate = clk_get_rate(i2c_imx->clk); div = (i2c_clk_rate + rate - 1) / rate; - if (div < i2c_clk_div[0][0]) + if (div < i2c_clk_div[0].div) i = 0; - else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) - i = ARRAY_SIZE(i2c_clk_div) - 1; + else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) + i = i2c_imx->hwdata->ndivs - 1; else - for (i = 0; i2c_clk_div[i][0] < div; i++); + for (i = 0; i2c_clk_div[i].div < div; i++); /* Store divider value */ - i2c_imx->ifdr = i2c_clk_div[i][1]; + i2c_imx->ifdr = i2c_clk_div[i].val; /* * There dummy delay is calculated. @@ -290,7 +392,7 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, * This delay is used in I2C bus disable function * to fix chip hardware bug. */ - i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0] + i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); /* dev_dbg() can't be used, because adapter is not yet registered */ @@ -298,7 +400,7 @@ static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n", __func__, i2c_clk_rate, div); dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n", - __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]); + __func__, i2c_clk_div[i].val, i2c_clk_div[i].div); #endif } @@ -307,12 +409,13 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id) struct imx_i2c_struct *i2c_imx = dev_id; unsigned int temp; - temp = readb(i2c_imx->base + IMX_I2C_I2SR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); if (temp & I2SR_IIF) { /* save status register */ i2c_imx->i2csr = temp; temp &= ~I2SR_IIF; - writeb(temp, i2c_imx->base + IMX_I2C_I2SR); + temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); wake_up(&i2c_imx->queue); return IRQ_HANDLED; } @@ -328,7 +431,7 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) __func__, msgs->addr << 1); /* write slave address */ - writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR); + imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR); result = i2c_imx_trx_complete(i2c_imx); if (result) return result; @@ -342,7 +445,7 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) dev_dbg(&i2c_imx->adapter.dev, "<%s> write byte: B%d=0x%X\n", __func__, i, msgs->buf[i]); - writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR); + imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); result = i2c_imx_trx_complete(i2c_imx); if (result) return result; @@ -363,7 +466,7 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) __func__, (msgs->addr << 1) | 0x01); /* write slave address */ - writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR); + imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR); result = i2c_imx_trx_complete(i2c_imx); if (result) return result; @@ -374,12 +477,12 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); /* setup bus to read data */ - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); temp &= ~I2CR_MTX; if (msgs->len - 1) temp &= ~I2CR_TXAK; - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); - readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */ + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); @@ -393,19 +496,19 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) controller from generating another clock cycle */ dev_dbg(&i2c_imx->adapter.dev, "<%s> clear MSTA\n", __func__); - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); temp &= ~(I2CR_MSTA | I2CR_MTX); - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); i2c_imx_bus_busy(i2c_imx, 0); i2c_imx->stopped = 1; } else if (i == (msgs->len - 2)) { dev_dbg(&i2c_imx->adapter.dev, "<%s> set TXAK\n", __func__); - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); temp |= I2CR_TXAK; - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); } - msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR); + msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); dev_dbg(&i2c_imx->adapter.dev, "<%s> read byte: B%d=0x%X\n", __func__, i, msgs->buf[i]); @@ -432,9 +535,9 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter, if (i) { dev_dbg(&i2c_imx->adapter.dev, "<%s> repeated start\n", __func__); - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); temp |= I2CR_RSTA; - writeb(temp, i2c_imx->base + IMX_I2C_I2CR); + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); result = i2c_imx_bus_busy(i2c_imx, 1); if (result) goto fail0; @@ -443,13 +546,13 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter, "<%s> transfer message: %d\n", __func__, i); /* write/read data */ #ifdef CONFIG_I2C_DEBUG_BUS - temp = readb(i2c_imx->base + IMX_I2C_I2CR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); - temp = readb(i2c_imx->base + IMX_I2C_I2SR); + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); dev_dbg(&i2c_imx->adapter.dev, "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, @@ -486,31 +589,26 @@ static struct i2c_algorithm i2c_imx_algo = { .functionality = i2c_imx_func, }; -static int __init i2c_imx_probe(struct platform_device *pdev) +static int i2c_imx_probe(struct platform_device *pdev) { const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, &pdev->dev); struct imx_i2c_struct *i2c_imx; struct resource *res; - struct imxi2c_platform_data *pdata = pdev->dev.platform_data; - struct pinctrl *pinctrl; + struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); void __iomem *base; int irq, ret; u32 bitrate; dev_dbg(&pdev->dev, "<%s>\n", __func__); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "can't get device resources\n"); - return -ENOENT; - } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "can't get irq number\n"); return -ENOENT; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); @@ -523,8 +621,10 @@ static int __init i2c_imx_probe(struct platform_device *pdev) } if (of_id) - pdev->id_entry = of_id->data; - i2c_imx->devtype = pdev->id_entry->driver_data; + i2c_imx->hwdata = of_id->data; + else + i2c_imx->hwdata = (struct imx_i2c_hwdata *) + platform_get_device_id(pdev)->driver_data; /* Setup i2c_imx driver structure */ strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); @@ -535,12 +635,6 @@ static int __init i2c_imx_probe(struct platform_device *pdev) i2c_imx->adapter.dev.of_node = pdev->dev.of_node; i2c_imx->base = base; - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) { - dev_err(&pdev->dev, "can't get/select pinctrl\n"); - return PTR_ERR(pinctrl); - } - /* Get I2C clock */ i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(i2c_imx->clk)) { @@ -548,6 +642,11 @@ static int __init i2c_imx_probe(struct platform_device *pdev) return PTR_ERR(i2c_imx->clk); } + ret = clk_prepare_enable(i2c_imx->clk); + if (ret) { + dev_err(&pdev->dev, "can't enable I2C clock\n"); + return ret; + } /* Request IRQ */ ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0, pdev->name, i2c_imx); @@ -571,8 +670,9 @@ static int __init i2c_imx_probe(struct platform_device *pdev) i2c_imx_set_clk(i2c_imx, bitrate); /* Set up chip registers to defaults */ - writeb(0, i2c_imx->base + IMX_I2C_I2CR); - writeb(0, i2c_imx->base + IMX_I2C_I2SR); + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, + i2c_imx, IMX_I2C_I2CR); + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); /* Add I2C adapter */ ret = i2c_add_numbered_adapter(&i2c_imx->adapter); @@ -581,10 +681,9 @@ static int __init i2c_imx_probe(struct platform_device *pdev) return ret; } - of_i2c_register_devices(&i2c_imx->adapter); - /* Set up platform driver data */ platform_set_drvdata(pdev, i2c_imx); + clk_disable_unprepare(i2c_imx->clk); dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n", @@ -598,7 +697,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev) return 0; /* Return OK */ } -static int __exit i2c_imx_remove(struct platform_device *pdev) +static int i2c_imx_remove(struct platform_device *pdev) { struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); @@ -607,16 +706,17 @@ static int __exit i2c_imx_remove(struct platform_device *pdev) i2c_del_adapter(&i2c_imx->adapter); /* setup chip registers to defaults */ - writeb(0, i2c_imx->base + IMX_I2C_IADR); - writeb(0, i2c_imx->base + IMX_I2C_IFDR); - writeb(0, i2c_imx->base + IMX_I2C_I2CR); - writeb(0, i2c_imx->base + IMX_I2C_I2SR); + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); return 0; } static struct platform_driver i2c_imx_driver = { - .remove = __exit_p(i2c_imx_remove), + .probe = i2c_imx_probe, + .remove = i2c_imx_remove, .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, @@ -627,7 +727,7 @@ static struct platform_driver i2c_imx_driver = { static int __init i2c_adap_imx_init(void) { - return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe); + return platform_driver_register(&i2c_imx_driver); } subsys_initcall(i2c_adap_imx_init); diff --git a/drivers/i2c/busses/i2c-intel-mid.c b/drivers/i2c/busses/i2c-intel-mid.c deleted file mode 100644 index 0fb6597..0000000 --- a/drivers/i2c/busses/i2c-intel-mid.c +++ /dev/null @@ -1,1121 +0,0 @@ -/* - * Support for Moorestown/Medfield I2C chip - * - * Copyright (c) 2009 Intel Corporation. - * Copyright (c) 2009 Synopsys. Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, version - * 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT ANY - * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., 51 - * Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/stat.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/pm_runtime.h> -#include <linux/io.h> - -#define DRIVER_NAME "i2c-intel-mid" -#define VERSION "Version 0.5ac2" -#define PLATFORM "Moorestown/Medfield" - -/* Tables use: 0 Moorestown, 1 Medfield */ -#define NUM_PLATFORMS 2 -enum platform_enum { - MOORESTOWN = 0, - MEDFIELD = 1, -}; - -enum mid_i2c_status { - STATUS_IDLE = 0, - STATUS_READ_START, - STATUS_READ_IN_PROGRESS, - STATUS_READ_SUCCESS, - STATUS_WRITE_START, - STATUS_WRITE_SUCCESS, - STATUS_XFER_ABORT, - STATUS_STANDBY -}; - -/** - * struct intel_mid_i2c_private - per device I²C context - * @adap: core i2c layer adapter information - * @dev: device reference for power management - * @base: register base - * @speed: speed mode for this port - * @complete: completion object for transaction wait - * @abort: reason for last abort - * @rx_buf: pointer into working receive buffer - * @rx_buf_len: receive buffer length - * @status: adapter state machine - * @msg: the message we are currently processing - * @platform: the MID device type we are part of - * @lock: transaction serialization - * - * We allocate one of these per device we discover, it holds the core - * i2c layer objects and the data we need to track privately. - */ -struct intel_mid_i2c_private { - struct i2c_adapter adap; - struct device *dev; - void __iomem *base; - int speed; - struct completion complete; - int abort; - u8 *rx_buf; - int rx_buf_len; - enum mid_i2c_status status; - struct i2c_msg *msg; - enum platform_enum platform; - struct mutex lock; -}; - -#define NUM_SPEEDS 3 - -#define ACTIVE 0 -#define STANDBY 1 - - -/* Control register */ -#define IC_CON 0x00 -#define SLV_DIS (1 << 6) /* Disable slave mode */ -#define RESTART (1 << 5) /* Send a Restart condition */ -#define ADDR_10BIT (1 << 4) /* 10-bit addressing */ -#define STANDARD_MODE (1 << 1) /* standard mode */ -#define FAST_MODE (2 << 1) /* fast mode */ -#define HIGH_MODE (3 << 1) /* high speed mode */ -#define MASTER_EN (1 << 0) /* Master mode */ - -/* Target address register */ -#define IC_TAR 0x04 -#define IC_TAR_10BIT_ADDR (1 << 12) /* 10-bit addressing */ -#define IC_TAR_SPECIAL (1 << 11) /* Perform special I2C cmd */ -#define IC_TAR_GC_OR_START (1 << 10) /* 0: Gerneral Call Address */ - /* 1: START BYTE */ -/* Slave Address Register */ -#define IC_SAR 0x08 /* Not used in Master mode */ - -/* High Speed Master Mode Code Address Register */ -#define IC_HS_MADDR 0x0c - -/* Rx/Tx Data Buffer and Command Register */ -#define IC_DATA_CMD 0x10 -#define IC_RD (1 << 8) /* 1: Read 0: Write */ - -/* Standard Speed Clock SCL High Count Register */ -#define IC_SS_SCL_HCNT 0x14 - -/* Standard Speed Clock SCL Low Count Register */ -#define IC_SS_SCL_LCNT 0x18 - -/* Fast Speed Clock SCL High Count Register */ -#define IC_FS_SCL_HCNT 0x1c - -/* Fast Spedd Clock SCL Low Count Register */ -#define IC_FS_SCL_LCNT 0x20 - -/* High Speed Clock SCL High Count Register */ -#define IC_HS_SCL_HCNT 0x24 - -/* High Speed Clock SCL Low Count Register */ -#define IC_HS_SCL_LCNT 0x28 - -/* Interrupt Status Register */ -#define IC_INTR_STAT 0x2c /* Read only */ -#define R_GEN_CALL (1 << 11) -#define R_START_DET (1 << 10) -#define R_STOP_DET (1 << 9) -#define R_ACTIVITY (1 << 8) -#define R_RX_DONE (1 << 7) -#define R_TX_ABRT (1 << 6) -#define R_RD_REQ (1 << 5) -#define R_TX_EMPTY (1 << 4) -#define R_TX_OVER (1 << 3) -#define R_RX_FULL (1 << 2) -#define R_RX_OVER (1 << 1) -#define R_RX_UNDER (1 << 0) - -/* Interrupt Mask Register */ -#define IC_INTR_MASK 0x30 /* Read and Write */ -#define M_GEN_CALL (1 << 11) -#define M_START_DET (1 << 10) -#define M_STOP_DET (1 << 9) -#define M_ACTIVITY (1 << 8) -#define M_RX_DONE (1 << 7) -#define M_TX_ABRT (1 << 6) -#define M_RD_REQ (1 << 5) -#define M_TX_EMPTY (1 << 4) -#define M_TX_OVER (1 << 3) -#define M_RX_FULL (1 << 2) -#define M_RX_OVER (1 << 1) -#define M_RX_UNDER (1 << 0) - -/* Raw Interrupt Status Register */ -#define IC_RAW_INTR_STAT 0x34 /* Read Only */ -#define GEN_CALL (1 << 11) /* General call */ -#define START_DET (1 << 10) /* (RE)START occurred */ -#define STOP_DET (1 << 9) /* STOP occurred */ -#define ACTIVITY (1 << 8) /* Bus busy */ -#define RX_DONE (1 << 7) /* Not used in Master mode */ -#define TX_ABRT (1 << 6) /* Transmit Abort */ -#define RD_REQ (1 << 5) /* Not used in Master mode */ -#define TX_EMPTY (1 << 4) /* TX FIFO <= threshold */ -#define TX_OVER (1 << 3) /* TX FIFO overflow */ -#define RX_FULL (1 << 2) /* RX FIFO >= threshold */ -#define RX_OVER (1 << 1) /* RX FIFO overflow */ -#define RX_UNDER (1 << 0) /* RX FIFO empty */ - -/* Receive FIFO Threshold Register */ -#define IC_RX_TL 0x38 - -/* Transmit FIFO Treshold Register */ -#define IC_TX_TL 0x3c - -/* Clear Combined and Individual Interrupt Register */ -#define IC_CLR_INTR 0x40 -#define CLR_INTR (1 << 0) - -/* Clear RX_UNDER Interrupt Register */ -#define IC_CLR_RX_UNDER 0x44 -#define CLR_RX_UNDER (1 << 0) - -/* Clear RX_OVER Interrupt Register */ -#define IC_CLR_RX_OVER 0x48 -#define CLR_RX_OVER (1 << 0) - -/* Clear TX_OVER Interrupt Register */ -#define IC_CLR_TX_OVER 0x4c -#define CLR_TX_OVER (1 << 0) - -#define IC_CLR_RD_REQ 0x50 - -/* Clear TX_ABRT Interrupt Register */ -#define IC_CLR_TX_ABRT 0x54 -#define CLR_TX_ABRT (1 << 0) -#define IC_CLR_RX_DONE 0x58 - -/* Clear ACTIVITY Interrupt Register */ -#define IC_CLR_ACTIVITY 0x5c -#define CLR_ACTIVITY (1 << 0) - -/* Clear STOP_DET Interrupt Register */ -#define IC_CLR_STOP_DET 0x60 -#define CLR_STOP_DET (1 << 0) - -/* Clear START_DET Interrupt Register */ -#define IC_CLR_START_DET 0x64 -#define CLR_START_DET (1 << 0) - -/* Clear GEN_CALL Interrupt Register */ -#define IC_CLR_GEN_CALL 0x68 -#define CLR_GEN_CALL (1 << 0) - -/* Enable Register */ -#define IC_ENABLE 0x6c -#define ENABLE (1 << 0) - -/* Status Register */ -#define IC_STATUS 0x70 /* Read Only */ -#define STAT_SLV_ACTIVITY (1 << 6) /* Slave not in idle */ -#define STAT_MST_ACTIVITY (1 << 5) /* Master not in idle */ -#define STAT_RFF (1 << 4) /* RX FIFO Full */ -#define STAT_RFNE (1 << 3) /* RX FIFO Not Empty */ -#define STAT_TFE (1 << 2) /* TX FIFO Empty */ -#define STAT_TFNF (1 << 1) /* TX FIFO Not Full */ -#define STAT_ACTIVITY (1 << 0) /* Activity Status */ - -/* Transmit FIFO Level Register */ -#define IC_TXFLR 0x74 /* Read Only */ -#define TXFLR (1 << 0) /* TX FIFO level */ - -/* Receive FIFO Level Register */ -#define IC_RXFLR 0x78 /* Read Only */ -#define RXFLR (1 << 0) /* RX FIFO level */ - -/* Transmit Abort Source Register */ -#define IC_TX_ABRT_SOURCE 0x80 -#define ABRT_SLVRD_INTX (1 << 15) -#define ABRT_SLV_ARBLOST (1 << 14) -#define ABRT_SLVFLUSH_TXFIFO (1 << 13) -#define ARB_LOST (1 << 12) -#define ABRT_MASTER_DIS (1 << 11) -#define ABRT_10B_RD_NORSTRT (1 << 10) -#define ABRT_SBYTE_NORSTRT (1 << 9) -#define ABRT_HS_NORSTRT (1 << 8) -#define ABRT_SBYTE_ACKDET (1 << 7) -#define ABRT_HS_ACKDET (1 << 6) -#define ABRT_GCALL_READ (1 << 5) -#define ABRT_GCALL_NOACK (1 << 4) -#define ABRT_TXDATA_NOACK (1 << 3) -#define ABRT_10ADDR2_NOACK (1 << 2) -#define ABRT_10ADDR1_NOACK (1 << 1) -#define ABRT_7B_ADDR_NOACK (1 << 0) - -/* Enable Status Register */ -#define IC_ENABLE_STATUS 0x9c -#define IC_EN (1 << 0) /* I2C in an enabled state */ - -/* Component Parameter Register 1*/ -#define IC_COMP_PARAM_1 0xf4 -#define APB_DATA_WIDTH (0x3 << 0) - -/* added by xiaolin --begin */ -#define SS_MIN_SCL_HIGH 4000 -#define SS_MIN_SCL_LOW 4700 -#define FS_MIN_SCL_HIGH 600 -#define FS_MIN_SCL_LOW 1300 -#define HS_MIN_SCL_HIGH_100PF 60 -#define HS_MIN_SCL_LOW_100PF 120 - -#define STANDARD 0 -#define FAST 1 -#define HIGH 2 - -#define NUM_SPEEDS 3 - -static int speed_mode[6] = { - FAST, - FAST, - FAST, - STANDARD, - FAST, - FAST -}; - -static int ctl_num = 6; -module_param_array(speed_mode, int, &ctl_num, S_IRUGO); -MODULE_PARM_DESC(speed_mode, "Set the speed of the i2c interface (0-2)"); - -/** - * intel_mid_i2c_disable - Disable I2C controller - * @adap: struct pointer to i2c_adapter - * - * Return Value: - * 0 success - * -EBUSY if device is busy - * -ETIMEDOUT if i2c cannot be disabled within the given time - * - * I2C bus state should be checked prior to disabling the hardware. If bus is - * not in idle state, an errno is returned. Write "0" to IC_ENABLE to disable - * I2C controller. - */ -static int intel_mid_i2c_disable(struct i2c_adapter *adap) -{ - struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap); - int err = 0; - int count = 0; - int ret1, ret2; - static const u16 delay[NUM_SPEEDS] = {100, 25, 3}; - - /* Set IC_ENABLE to 0 */ - writel(0, i2c->base + IC_ENABLE); - - /* Check if device is busy */ - dev_dbg(&adap->dev, "mrst i2c disable\n"); - while ((ret1 = readl(i2c->base + IC_ENABLE_STATUS) & 0x1) - || (ret2 = readl(i2c->base + IC_STATUS) & 0x1)) { - udelay(delay[i2c->speed]); - writel(0, i2c->base + IC_ENABLE); - dev_dbg(&adap->dev, "i2c is busy, count is %d speed %d\n", - count, i2c->speed); - if (count++ > 10) { - err = -ETIMEDOUT; - break; - } - } - - /* Clear all interrupts */ - readl(i2c->base + IC_CLR_INTR); - readl(i2c->base + IC_CLR_STOP_DET); - readl(i2c->base + IC_CLR_START_DET); - readl(i2c->base + IC_CLR_ACTIVITY); - readl(i2c->base + IC_CLR_TX_ABRT); - readl(i2c->base + IC_CLR_RX_OVER); - readl(i2c->base + IC_CLR_RX_UNDER); - readl(i2c->base + IC_CLR_TX_OVER); - readl(i2c->base + IC_CLR_RX_DONE); - readl(i2c->base + IC_CLR_GEN_CALL); - - /* Disable all interupts */ - writel(0x0000, i2c->base + IC_INTR_MASK); - - return err; -} - -/** - * intel_mid_i2c_hwinit - Initialize the I2C hardware registers - * @dev: pci device struct pointer - * - * This function will be called in intel_mid_i2c_probe() before device - * registration. - * - * Return Values: - * 0 success - * -EBUSY i2c cannot be disabled - * -ETIMEDOUT i2c cannot be disabled - * -EFAULT If APB data width is not 32-bit wide - * - * I2C should be disabled prior to other register operation. If failed, an - * errno is returned. Mask and Clear all interrpts, this should be done at - * first. Set common registers which will not be modified during normal - * transfers, including: control register, FIFO threshold and clock freq. - * Check APB data width at last. - */ -static int intel_mid_i2c_hwinit(struct intel_mid_i2c_private *i2c) -{ - int err; - - static const u16 hcnt[NUM_PLATFORMS][NUM_SPEEDS] = { - { 0x75, 0x15, 0x07 }, - { 0x04c, 0x10, 0x06 } - }; - static const u16 lcnt[NUM_PLATFORMS][NUM_SPEEDS] = { - { 0x7C, 0x21, 0x0E }, - { 0x053, 0x19, 0x0F } - }; - - /* Disable i2c first */ - err = intel_mid_i2c_disable(&i2c->adap); - if (err) - return err; - - /* - * Setup clock frequency and speed mode - * Enable restart condition, - * enable master FSM, disable slave FSM, - * use target address when initiating transfer - */ - - writel((i2c->speed + 1) << 1 | SLV_DIS | RESTART | MASTER_EN, - i2c->base + IC_CON); - writel(hcnt[i2c->platform][i2c->speed], - i2c->base + (IC_SS_SCL_HCNT + (i2c->speed << 3))); - writel(lcnt[i2c->platform][i2c->speed], - i2c->base + (IC_SS_SCL_LCNT + (i2c->speed << 3))); - - /* Set tranmit & receive FIFO threshold to zero */ - writel(0x0, i2c->base + IC_RX_TL); - writel(0x0, i2c->base + IC_TX_TL); - - return 0; -} - -/** - * intel_mid_i2c_func - Return the supported three I2C operations. - * @adapter: i2c_adapter struct pointer - */ -static u32 intel_mid_i2c_func(struct i2c_adapter *adapter) -{ - return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; -} - -/** - * intel_mid_i2c_address_neq - To check if the addresses for different i2c messages - * are equal. - * @p1: first i2c_msg - * @p2: second i2c_msg - * - * Return Values: - * 0 if addresses are equal - * 1 if not equal - * - * Within a single transfer, the I2C client may need to send its address more - * than once. So a check if the addresses match is needed. - */ -static inline bool intel_mid_i2c_address_neq(const struct i2c_msg *p1, - const struct i2c_msg *p2) -{ - if (p1->addr != p2->addr) - return 1; - if ((p1->flags ^ p2->flags) & I2C_M_TEN) - return 1; - return 0; -} - -/** - * intel_mid_i2c_abort - To handle transfer abortions and print error messages. - * @adap: i2c_adapter struct pointer - * - * By reading register IC_TX_ABRT_SOURCE, various transfer errors can be - * distingushed. At present, no circumstances have been found out that - * multiple errors would be occurred simutaneously, so we simply use the - * register value directly. - * - * At last the error bits are cleared. (Note clear ABRT_SBYTE_NORSTRT bit need - * a few extra steps) - */ -static void intel_mid_i2c_abort(struct intel_mid_i2c_private *i2c) -{ - /* Read about source register */ - int abort = i2c->abort; - struct i2c_adapter *adap = &i2c->adap; - - /* Single transfer error check: - * According to databook, TX/RX FIFOs would be flushed when - * the abort interrupt occurred. - */ - if (abort & ABRT_MASTER_DIS) - dev_err(&adap->dev, - "initiate master operation with master mode disabled.\n"); - if (abort & ABRT_10B_RD_NORSTRT) - dev_err(&adap->dev, - "RESTART disabled and master sent READ cmd in 10-bit addressing.\n"); - - if (abort & ABRT_SBYTE_NORSTRT) { - dev_err(&adap->dev, - "RESTART disabled and user is trying to send START byte.\n"); - writel(~ABRT_SBYTE_NORSTRT, i2c->base + IC_TX_ABRT_SOURCE); - writel(RESTART, i2c->base + IC_CON); - writel(~IC_TAR_SPECIAL, i2c->base + IC_TAR); - } - - if (abort & ABRT_SBYTE_ACKDET) - dev_err(&adap->dev, - "START byte was not acknowledged.\n"); - if (abort & ABRT_TXDATA_NOACK) - dev_dbg(&adap->dev, - "No acknowledgement received from slave.\n"); - if (abort & ABRT_10ADDR2_NOACK) - dev_dbg(&adap->dev, - "The 2nd address byte of the 10-bit address was not acknowledged.\n"); - if (abort & ABRT_10ADDR1_NOACK) - dev_dbg(&adap->dev, - "The 1st address byte of 10-bit address was not acknowledged.\n"); - if (abort & ABRT_7B_ADDR_NOACK) - dev_dbg(&adap->dev, - "I2C slave device not acknowledged.\n"); - - /* Clear TX_ABRT bit */ - readl(i2c->base + IC_CLR_TX_ABRT); - i2c->status = STATUS_XFER_ABORT; -} - -/** - * xfer_read - Internal function to implement master read transfer. - * @adap: i2c_adapter struct pointer - * @buf: buffer in i2c_msg - * @length: number of bytes to be read - * - * Return Values: - * 0 if the read transfer succeeds - * -ETIMEDOUT if cannot read the "raw" interrupt register - * -EINVAL if a transfer abort occurred - * - * For every byte, a "READ" command will be loaded into IC_DATA_CMD prior to - * data transfer. The actual "read" operation will be performed if an RX_FULL - * interrupt occurred. - * - * Note there may be two interrupt signals captured, one should read - * IC_RAW_INTR_STAT to separate between errors and actual data. - */ -static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length) -{ - struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap); - int i = length; - int err; - - if (length >= 256) { - dev_err(&adap->dev, - "I2C FIFO cannot support larger than 256 bytes\n"); - return -EMSGSIZE; - } - - INIT_COMPLETION(i2c->complete); - - readl(i2c->base + IC_CLR_INTR); - writel(0x0044, i2c->base + IC_INTR_MASK); - - i2c->status = STATUS_READ_START; - - while (i--) - writel(IC_RD, i2c->base + IC_DATA_CMD); - - i2c->status = STATUS_READ_START; - err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ); - if (!err) { - dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n"); - intel_mid_i2c_hwinit(i2c); - return -ETIMEDOUT; - } - if (i2c->status == STATUS_READ_SUCCESS) - return 0; - else - return -EIO; -} - -/** - * xfer_write - Internal function to implement master write transfer. - * @adap: i2c_adapter struct pointer - * @buf: buffer in i2c_msg - * @length: number of bytes to be read - * - * Return Values: - * 0 if the read transfer succeeds - * -ETIMEDOUT if we cannot read the "raw" interrupt register - * -EINVAL if a transfer abort occurred - * - * For every byte, a "WRITE" command will be loaded into IC_DATA_CMD prior to - * data transfer. The actual "write" operation will be performed when the - * RX_FULL interrupt signal occurs. - * - * Note there may be two interrupt signals captured, one should read - * IC_RAW_INTR_STAT to separate between errors and actual data. - */ -static int xfer_write(struct i2c_adapter *adap, - unsigned char *buf, int length) -{ - struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap); - int i, err; - - if (length >= 256) { - dev_err(&adap->dev, - "I2C FIFO cannot support larger than 256 bytes\n"); - return -EMSGSIZE; - } - - INIT_COMPLETION(i2c->complete); - - readl(i2c->base + IC_CLR_INTR); - writel(0x0050, i2c->base + IC_INTR_MASK); - - i2c->status = STATUS_WRITE_START; - for (i = 0; i < length; i++) - writel((u16)(*(buf + i)), i2c->base + IC_DATA_CMD); - - i2c->status = STATUS_WRITE_START; - err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ); - if (!err) { - dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n"); - intel_mid_i2c_hwinit(i2c); - return -ETIMEDOUT; - } else { - if (i2c->status == STATUS_WRITE_SUCCESS) - return 0; - else - return -EIO; - } -} - -static int intel_mid_i2c_setup(struct i2c_adapter *adap, struct i2c_msg *pmsg) -{ - struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap); - int err; - u32 reg; - u32 bit_mask; - u32 mode; - - /* Disable device first */ - err = intel_mid_i2c_disable(adap); - if (err) { - dev_err(&adap->dev, - "Cannot disable i2c controller, timeout\n"); - return err; - } - - mode = (1 + i2c->speed) << 1; - /* set the speed mode */ - reg = readl(i2c->base + IC_CON); - if ((reg & 0x06) != mode) { - dev_dbg(&adap->dev, "set mode %d\n", i2c->speed); - writel((reg & ~0x6) | mode, i2c->base + IC_CON); - } - - reg = readl(i2c->base + IC_CON); - /* use 7-bit addressing */ - if (pmsg->flags & I2C_M_TEN) { - if ((reg & ADDR_10BIT) != ADDR_10BIT) { - dev_dbg(&adap->dev, "set i2c 10 bit address mode\n"); - writel(reg | ADDR_10BIT, i2c->base + IC_CON); - } - } else { - if ((reg & ADDR_10BIT) != 0x0) { - dev_dbg(&adap->dev, "set i2c 7 bit address mode\n"); - writel(reg & ~ADDR_10BIT, i2c->base + IC_CON); - } - } - /* enable restart conditions */ - reg = readl(i2c->base + IC_CON); - if ((reg & RESTART) != RESTART) { - dev_dbg(&adap->dev, "enable restart conditions\n"); - writel(reg | RESTART, i2c->base + IC_CON); - } - - /* enable master FSM */ - reg = readl(i2c->base + IC_CON); - dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg); - writel(reg | MASTER_EN, i2c->base + IC_CON); - if ((reg & SLV_DIS) != SLV_DIS) { - dev_dbg(&adap->dev, "enable master FSM\n"); - writel(reg | SLV_DIS, i2c->base + IC_CON); - dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg); - } - - /* use target address when initiating transfer */ - reg = readl(i2c->base + IC_TAR); - bit_mask = IC_TAR_SPECIAL | IC_TAR_GC_OR_START; - - if ((reg & bit_mask) != 0x0) { - dev_dbg(&adap->dev, - "WR: use target address when intiating transfer, i2c_tx_target\n"); - writel(reg & ~bit_mask, i2c->base + IC_TAR); - } - - /* set target address to the I2C slave address */ - dev_dbg(&adap->dev, - "set target address to the I2C slave address, addr is %x\n", - pmsg->addr); - writel(pmsg->addr | (pmsg->flags & I2C_M_TEN ? IC_TAR_10BIT_ADDR : 0), - i2c->base + IC_TAR); - - /* Enable I2C controller */ - writel(ENABLE, i2c->base + IC_ENABLE); - - return 0; -} - -/** - * intel_mid_i2c_xfer - Main master transfer routine. - * @adap: i2c_adapter struct pointer - * @pmsg: i2c_msg struct pointer - * @num: number of i2c_msg - * - * Return Values: - * + number of messages transferred - * -ETIMEDOUT If cannot disable I2C controller or read IC_STATUS - * -EINVAL If the address in i2c_msg is invalid - * - * This function will be registered in i2c-core and exposed to external - * I2C clients. - * 1. Disable I2C controller - * 2. Unmask three interrupts: RX_FULL, TX_EMPTY, TX_ABRT - * 3. Check if address in i2c_msg is valid - * 4. Enable I2C controller - * 5. Perform real transfer (call xfer_read or xfer_write) - * 6. Wait until the current transfer is finished (check bus state) - * 7. Mask and clear all interrupts - */ -static int intel_mid_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg *pmsg, - int num) -{ - struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap); - int i, err = 0; - - /* if number of messages equal 0*/ - if (num == 0) - return 0; - - pm_runtime_get(i2c->dev); - - mutex_lock(&i2c->lock); - dev_dbg(&adap->dev, "intel_mid_i2c_xfer, process %d msg(s)\n", num); - dev_dbg(&adap->dev, "slave address is %x\n", pmsg->addr); - - - if (i2c->status != STATUS_IDLE) { - dev_err(&adap->dev, "Adapter %d in transfer/standby\n", - adap->nr); - mutex_unlock(&i2c->lock); - pm_runtime_put(i2c->dev); - return -1; - } - - - for (i = 1; i < num; i++) { - /* Message address equal? */ - if (unlikely(intel_mid_i2c_address_neq(&pmsg[0], &pmsg[i]))) { - dev_err(&adap->dev, "Invalid address in msg[%d]\n", i); - mutex_unlock(&i2c->lock); - pm_runtime_put(i2c->dev); - return -EINVAL; - } - } - - if (intel_mid_i2c_setup(adap, pmsg)) { - mutex_unlock(&i2c->lock); - pm_runtime_put(i2c->dev); - return -EINVAL; - } - - for (i = 0; i < num; i++) { - i2c->msg = pmsg; - i2c->status = STATUS_IDLE; - /* Read or Write */ - if (pmsg->flags & I2C_M_RD) { - dev_dbg(&adap->dev, "I2C_M_RD\n"); - err = xfer_read(adap, pmsg->buf, pmsg->len); - } else { - dev_dbg(&adap->dev, "I2C_M_WR\n"); - err = xfer_write(adap, pmsg->buf, pmsg->len); - } - if (err < 0) - break; - dev_dbg(&adap->dev, "msg[%d] transfer complete\n", i); - pmsg++; /* next message */ - } - - /* Mask interrupts */ - writel(0x0000, i2c->base + IC_INTR_MASK); - /* Clear all interrupts */ - readl(i2c->base + IC_CLR_INTR); - - i2c->status = STATUS_IDLE; - mutex_unlock(&i2c->lock); - pm_runtime_put(i2c->dev); - - return err; -} - -static int intel_mid_i2c_runtime_suspend(struct device *dev) -{ - struct pci_dev *pdev = to_pci_dev(dev); - struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev); - struct i2c_adapter *adap = to_i2c_adapter(dev); - int err; - - if (i2c->status != STATUS_IDLE) - return -1; - - intel_mid_i2c_disable(adap); - - err = pci_save_state(pdev); - if (err) { - dev_err(dev, "pci_save_state failed\n"); - return err; - } - - err = pci_set_power_state(pdev, PCI_D3hot); - if (err) { - dev_err(dev, "pci_set_power_state failed\n"); - return err; - } - i2c->status = STATUS_STANDBY; - - return 0; -} - -static int intel_mid_i2c_runtime_resume(struct device *dev) -{ - struct pci_dev *pdev = to_pci_dev(dev); - struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev); - int err; - - if (i2c->status != STATUS_STANDBY) - return 0; - - pci_set_power_state(pdev, PCI_D0); - pci_restore_state(pdev); - err = pci_enable_device(pdev); - if (err) { - dev_err(dev, "pci_enable_device failed\n"); - return err; - } - - i2c->status = STATUS_IDLE; - - intel_mid_i2c_hwinit(i2c); - return err; -} - -static void i2c_isr_read(struct intel_mid_i2c_private *i2c) -{ - struct i2c_msg *msg = i2c->msg; - int rx_num; - u32 len; - u8 *buf; - - if (!(msg->flags & I2C_M_RD)) - return; - - if (i2c->status != STATUS_READ_IN_PROGRESS) { - len = msg->len; - buf = msg->buf; - } else { - len = i2c->rx_buf_len; - buf = i2c->rx_buf; - } - - rx_num = readl(i2c->base + IC_RXFLR); - - for (; len > 0 && rx_num > 0; len--, rx_num--) - *buf++ = readl(i2c->base + IC_DATA_CMD); - - if (len > 0) { - i2c->status = STATUS_READ_IN_PROGRESS; - i2c->rx_buf_len = len; - i2c->rx_buf = buf; - } else - i2c->status = STATUS_READ_SUCCESS; - - return; -} - -static irqreturn_t intel_mid_i2c_isr(int this_irq, void *dev) -{ - struct intel_mid_i2c_private *i2c = dev; - u32 stat = readl(i2c->base + IC_INTR_STAT); - - if (!stat) - return IRQ_NONE; - - dev_dbg(&i2c->adap.dev, "%s, stat = 0x%x\n", __func__, stat); - stat &= 0x54; - - if (i2c->status != STATUS_WRITE_START && - i2c->status != STATUS_READ_START && - i2c->status != STATUS_READ_IN_PROGRESS) - goto err; - - if (stat & TX_ABRT) - i2c->abort = readl(i2c->base + IC_TX_ABRT_SOURCE); - - readl(i2c->base + IC_CLR_INTR); - - if (stat & TX_ABRT) { - intel_mid_i2c_abort(i2c); - goto exit; - } - - if (stat & RX_FULL) { - i2c_isr_read(i2c); - goto exit; - } - - if (stat & TX_EMPTY) { - if (readl(i2c->base + IC_STATUS) & 0x4) - i2c->status = STATUS_WRITE_SUCCESS; - } - -exit: - if (i2c->status == STATUS_READ_SUCCESS || - i2c->status == STATUS_WRITE_SUCCESS || - i2c->status == STATUS_XFER_ABORT) { - /* Clear all interrupts */ - readl(i2c->base + IC_CLR_INTR); - /* Mask interrupts */ - writel(0, i2c->base + IC_INTR_MASK); - complete(&i2c->complete); - } -err: - return IRQ_HANDLED; -} - -static struct i2c_algorithm intel_mid_i2c_algorithm = { - .master_xfer = intel_mid_i2c_xfer, - .functionality = intel_mid_i2c_func, -}; - - -static const struct dev_pm_ops intel_mid_i2c_pm_ops = { - .runtime_suspend = intel_mid_i2c_runtime_suspend, - .runtime_resume = intel_mid_i2c_runtime_resume, -}; - -/** - * intel_mid_i2c_probe - I2C controller initialization routine - * @dev: pci device - * @id: device id - * - * Return Values: - * 0 success - * -ENODEV If cannot allocate pci resource - * -ENOMEM If the register base remapping failed, or - * if kzalloc failed - * - * Initialization steps: - * 1. Request for PCI resource - * 2. Remap the start address of PCI resource to register base - * 3. Request for device memory region - * 4. Fill in the struct members of intel_mid_i2c_private - * 5. Call intel_mid_i2c_hwinit() for hardware initialization - * 6. Register I2C adapter in i2c-core - */ -static int intel_mid_i2c_probe(struct pci_dev *dev, - const struct pci_device_id *id) -{ - struct intel_mid_i2c_private *mrst; - unsigned long start, len; - int err, busnum; - void __iomem *base = NULL; - - dev_dbg(&dev->dev, "Get into probe function for I2C\n"); - err = pci_enable_device(dev); - if (err) { - dev_err(&dev->dev, "Failed to enable I2C PCI device (%d)\n", - err); - goto exit; - } - - /* Determine the address of the I2C area */ - start = pci_resource_start(dev, 0); - len = pci_resource_len(dev, 0); - if (!start || len == 0) { - dev_err(&dev->dev, "base address not set\n"); - err = -ENODEV; - goto exit; - } - dev_dbg(&dev->dev, "%s i2c resource start 0x%lx, len=%ld\n", - PLATFORM, start, len); - - err = pci_request_region(dev, 0, DRIVER_NAME); - if (err) { - dev_err(&dev->dev, "failed to request I2C region " - "0x%lx-0x%lx\n", start, - (unsigned long)pci_resource_end(dev, 0)); - goto exit; - } - - base = ioremap_nocache(start, len); - if (!base) { - dev_err(&dev->dev, "I/O memory remapping failed\n"); - err = -ENOMEM; - goto fail0; - } - - /* Allocate the per-device data structure, intel_mid_i2c_private */ - mrst = kzalloc(sizeof(struct intel_mid_i2c_private), GFP_KERNEL); - if (mrst == NULL) { - dev_err(&dev->dev, "can't allocate interface\n"); - err = -ENOMEM; - goto fail1; - } - - /* Initialize struct members */ - snprintf(mrst->adap.name, sizeof(mrst->adap.name), - "Intel MID I2C at %lx", start); - mrst->adap.owner = THIS_MODULE; - mrst->adap.algo = &intel_mid_i2c_algorithm; - mrst->adap.dev.parent = &dev->dev; - mrst->dev = &dev->dev; - mrst->base = base; - mrst->speed = STANDARD; - mrst->abort = 0; - mrst->rx_buf_len = 0; - mrst->status = STATUS_IDLE; - - pci_set_drvdata(dev, mrst); - i2c_set_adapdata(&mrst->adap, mrst); - - mrst->adap.nr = busnum = id->driver_data; - if (dev->device <= 0x0804) - mrst->platform = MOORESTOWN; - else - mrst->platform = MEDFIELD; - - dev_dbg(&dev->dev, "I2C%d\n", busnum); - - if (ctl_num > busnum) { - if (speed_mode[busnum] < 0 || speed_mode[busnum] >= NUM_SPEEDS) - dev_warn(&dev->dev, "invalid speed %d ignored.\n", - speed_mode[busnum]); - else - mrst->speed = speed_mode[busnum]; - } - - /* Initialize i2c controller */ - err = intel_mid_i2c_hwinit(mrst); - if (err < 0) { - dev_err(&dev->dev, "I2C interface initialization failed\n"); - goto fail2; - } - - mutex_init(&mrst->lock); - init_completion(&mrst->complete); - - /* Clear all interrupts */ - readl(mrst->base + IC_CLR_INTR); - writel(0x0000, mrst->base + IC_INTR_MASK); - - err = request_irq(dev->irq, intel_mid_i2c_isr, IRQF_SHARED, - mrst->adap.name, mrst); - if (err) { - dev_err(&dev->dev, "Failed to request IRQ for I2C controller: " - "%s", mrst->adap.name); - goto fail2; - } - - /* Adapter registration */ - err = i2c_add_numbered_adapter(&mrst->adap); - if (err) { - dev_err(&dev->dev, "Adapter %s registration failed\n", - mrst->adap.name); - goto fail3; - } - - dev_dbg(&dev->dev, "%s I2C bus %d driver bind success.\n", - (mrst->platform == MOORESTOWN) ? "Moorestown" : "Medfield", - busnum); - - pm_runtime_enable(&dev->dev); - return 0; - -fail3: - free_irq(dev->irq, mrst); -fail2: - kfree(mrst); -fail1: - iounmap(base); -fail0: - pci_release_region(dev, 0); -exit: - return err; -} - -static void intel_mid_i2c_remove(struct pci_dev *dev) -{ - struct intel_mid_i2c_private *mrst = pci_get_drvdata(dev); - intel_mid_i2c_disable(&mrst->adap); - i2c_del_adapter(&mrst->adap); - - free_irq(dev->irq, mrst); - iounmap(mrst->base); - kfree(mrst); - pci_release_region(dev, 0); -} - -static DEFINE_PCI_DEVICE_TABLE(intel_mid_i2c_ids) = { - /* Moorestown */ - { PCI_VDEVICE(INTEL, 0x0802), 0 }, - { PCI_VDEVICE(INTEL, 0x0803), 1 }, - { PCI_VDEVICE(INTEL, 0x0804), 2 }, - /* Medfield */ - { PCI_VDEVICE(INTEL, 0x0817), 3,}, - { PCI_VDEVICE(INTEL, 0x0818), 4 }, - { PCI_VDEVICE(INTEL, 0x0819), 5 }, - { PCI_VDEVICE(INTEL, 0x082C), 0 }, - { PCI_VDEVICE(INTEL, 0x082D), 1 }, - { PCI_VDEVICE(INTEL, 0x082E), 2 }, - { 0,} -}; -MODULE_DEVICE_TABLE(pci, intel_mid_i2c_ids); - -static struct pci_driver intel_mid_i2c_driver = { - .name = DRIVER_NAME, - .id_table = intel_mid_i2c_ids, - .probe = intel_mid_i2c_probe, - .remove = intel_mid_i2c_remove, -}; - -module_pci_driver(intel_mid_i2c_driver); - -MODULE_AUTHOR("Ba Zheng <zheng.ba@intel.com>"); -MODULE_DESCRIPTION("I2C driver for Moorestown Platform"); -MODULE_LICENSE("GPL"); -MODULE_VERSION(VERSION); diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index bc99333..dd24aa0 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -176,7 +176,7 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, interrupted = wait_event_interruptible_timeout ( iop3xx_adap->waitq, (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )), - 1 * HZ; + 1 * HZ ); if ((rc = iop3xx_i2c_error(sr)) < 0) { *status = sr; diff --git a/drivers/i2c/busses/i2c-ismt.c b/drivers/i2c/busses/i2c-ismt.c index cd82eb4..0043ede 100644 --- a/drivers/i2c/busses/i2c-ismt.c +++ b/drivers/i2c/busses/i2c-ismt.c @@ -393,6 +393,9 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr, desc = &priv->hw[priv->head]; + /* Initialize the DMA buffer */ + memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer)); + /* Initialize the descriptor */ memset(desc, 0, sizeof(struct ismt_desc)); desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); @@ -538,7 +541,7 @@ static int ismt_access(struct i2c_adapter *adap, u16 addr, desc->dptr_high = upper_32_bits(dma_addr); } - INIT_COMPLETION(priv->cmp); + reinit_completion(&priv->cmp); /* Add the descriptor */ ismt_submit_desc(priv); @@ -879,6 +882,7 @@ ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) DMA_BIT_MASK(32)) != 0)) { dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", pdev); + err = -ENODEV; goto fail; } } diff --git a/drivers/i2c/busses/i2c-kempld.c b/drivers/i2c/busses/i2c-kempld.c new file mode 100644 index 0000000..af8f65f --- /dev/null +++ b/drivers/i2c/busses/i2c-kempld.c @@ -0,0 +1,410 @@ +/* + * I2C bus driver for Kontron COM modules + * + * Copyright (c) 2010-2013 Kontron Europe GmbH + * Author: Michael Brunner <michael.brunner@kontron.com> + * + * The driver is based on the i2c-ocores driver by Peter Korsgaard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/mfd/kempld.h> + +#define KEMPLD_I2C_PRELOW 0x0b +#define KEMPLD_I2C_PREHIGH 0x0c +#define KEMPLD_I2C_DATA 0x0e + +#define KEMPLD_I2C_CTRL 0x0d +#define I2C_CTRL_IEN 0x40 +#define I2C_CTRL_EN 0x80 + +#define KEMPLD_I2C_STAT 0x0f +#define I2C_STAT_IF 0x01 +#define I2C_STAT_TIP 0x02 +#define I2C_STAT_ARBLOST 0x20 +#define I2C_STAT_BUSY 0x40 +#define I2C_STAT_NACK 0x80 + +#define KEMPLD_I2C_CMD 0x0f +#define I2C_CMD_START 0x91 +#define I2C_CMD_STOP 0x41 +#define I2C_CMD_READ 0x21 +#define I2C_CMD_WRITE 0x11 +#define I2C_CMD_READ_ACK 0x21 +#define I2C_CMD_READ_NACK 0x29 +#define I2C_CMD_IACK 0x01 + +#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ +#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ + +enum { + STATE_DONE = 0, + STATE_INIT, + STATE_ADDR, + STATE_ADDR10, + STATE_START, + STATE_WRITE, + STATE_READ, + STATE_ERROR, +}; + +struct kempld_i2c_data { + struct device *dev; + struct kempld_device_data *pld; + struct i2c_adapter adap; + struct i2c_msg *msg; + int pos; + int nmsgs; + int state; + bool was_active; +}; + +static unsigned int bus_frequency = KEMPLD_I2C_FREQ_STD; +module_param(bus_frequency, uint, 0); +MODULE_PARM_DESC(bus_frequency, "Set I2C bus frequency in kHz (default=" + __MODULE_STRING(KEMPLD_I2C_FREQ_STD)")"); + +static int i2c_bus = -1; +module_param(i2c_bus, int, 0); +MODULE_PARM_DESC(i2c_bus, "Set I2C bus number (default=-1 for dynamic assignment)"); + +static bool i2c_gpio_mux; +module_param(i2c_gpio_mux, bool, 0); +MODULE_PARM_DESC(i2c_gpio_mux, "Enable I2C port on GPIO out (default=false)"); + +/* + * kempld_get_mutex must be called prior to calling this function. + */ +static int kempld_i2c_process(struct kempld_i2c_data *i2c) +{ + struct kempld_device_data *pld = i2c->pld; + u8 stat = kempld_read8(pld, KEMPLD_I2C_STAT); + struct i2c_msg *msg = i2c->msg; + u8 addr; + + /* Ready? */ + if (stat & I2C_STAT_TIP) + return -EBUSY; + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { + /* Stop has been sent */ + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_IACK); + if (i2c->state == STATE_ERROR) + return -EIO; + return 0; + } + + /* Error? */ + if (stat & I2C_STAT_ARBLOST) { + i2c->state = STATE_ERROR; + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP); + return -EAGAIN; + } + + if (i2c->state == STATE_INIT) { + if (stat & I2C_STAT_BUSY) + return -EBUSY; + + i2c->state = STATE_ADDR; + } + + if (i2c->state == STATE_ADDR) { + /* 10 bit address? */ + if (i2c->msg->flags & I2C_M_TEN) { + addr = 0xf0 | ((i2c->msg->addr >> 7) & 0x6); + i2c->state = STATE_ADDR10; + } else { + addr = (i2c->msg->addr << 1); + i2c->state = STATE_START; + } + + /* Set read bit if necessary */ + addr |= (i2c->msg->flags & I2C_M_RD) ? 1 : 0; + + kempld_write8(pld, KEMPLD_I2C_DATA, addr); + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_START); + + return 0; + } + + /* Second part of 10 bit addressing */ + if (i2c->state == STATE_ADDR10) { + kempld_write8(pld, KEMPLD_I2C_DATA, i2c->msg->addr & 0xff); + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_WRITE); + + i2c->state = STATE_START; + return 0; + } + + if (i2c->state == STATE_START || i2c->state == STATE_WRITE) { + i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; + + if (stat & I2C_STAT_NACK) { + i2c->state = STATE_ERROR; + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP); + return -ENXIO; + } + } else { + msg->buf[i2c->pos++] = kempld_read8(pld, KEMPLD_I2C_DATA); + } + + if (i2c->pos >= msg->len) { + i2c->nmsgs--; + i2c->msg++; + i2c->pos = 0; + msg = i2c->msg; + + if (i2c->nmsgs) { + if (!(msg->flags & I2C_M_NOSTART)) { + i2c->state = STATE_ADDR; + return 0; + } else { + i2c->state = (msg->flags & I2C_M_RD) + ? STATE_READ : STATE_WRITE; + } + } else { + i2c->state = STATE_DONE; + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP); + return 0; + } + } + + if (i2c->state == STATE_READ) { + kempld_write8(pld, KEMPLD_I2C_CMD, i2c->pos == (msg->len - 1) ? + I2C_CMD_READ_NACK : I2C_CMD_READ_ACK); + } else { + kempld_write8(pld, KEMPLD_I2C_DATA, msg->buf[i2c->pos++]); + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_WRITE); + } + + return 0; +} + +static int kempld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct kempld_i2c_data *i2c = i2c_get_adapdata(adap); + struct kempld_device_data *pld = i2c->pld; + unsigned long timeout = jiffies + HZ; + int ret; + + i2c->msg = msgs; + i2c->pos = 0; + i2c->nmsgs = num; + i2c->state = STATE_INIT; + + /* Handle the transfer */ + while (time_before(jiffies, timeout)) { + kempld_get_mutex(pld); + ret = kempld_i2c_process(i2c); + kempld_release_mutex(pld); + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) + return (i2c->state == STATE_DONE) ? num : ret; + + if (ret == 0) + timeout = jiffies + HZ; + + usleep_range(5, 15); + } + + i2c->state = STATE_ERROR; + + return -ETIMEDOUT; +} + +/* + * kempld_get_mutex must be called prior to calling this function. + */ +static void kempld_i2c_device_init(struct kempld_i2c_data *i2c) +{ + struct kempld_device_data *pld = i2c->pld; + u16 prescale_corr; + long prescale; + u8 ctrl; + u8 stat; + u8 cfg; + + /* Make sure the device is disabled */ + ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); + ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); + kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); + + if (bus_frequency > KEMPLD_I2C_FREQ_MAX) + bus_frequency = KEMPLD_I2C_FREQ_MAX; + + if (pld->info.spec_major == 1) + prescale = pld->pld_clock / (bus_frequency * 5) - 1000; + else + prescale = pld->pld_clock / (bus_frequency * 4) - 3000; + + if (prescale < 0) + prescale = 0; + + /* Round to the best matching value */ + prescale_corr = prescale / 1000; + if (prescale % 1000 >= 500) + prescale_corr++; + + kempld_write8(pld, KEMPLD_I2C_PRELOW, prescale_corr & 0xff); + kempld_write8(pld, KEMPLD_I2C_PREHIGH, prescale_corr >> 8); + + /* Activate I2C bus output on GPIO pins */ + cfg = kempld_read8(pld, KEMPLD_CFG); + if (i2c_gpio_mux) + cfg |= KEMPLD_CFG_GPIO_I2C_MUX; + else + cfg &= ~KEMPLD_CFG_GPIO_I2C_MUX; + kempld_write8(pld, KEMPLD_CFG, cfg); + + /* Enable the device */ + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_IACK); + ctrl |= I2C_CTRL_EN; + kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); + + stat = kempld_read8(pld, KEMPLD_I2C_STAT); + if (stat & I2C_STAT_BUSY) + kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP); +} + +static u32 kempld_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm kempld_i2c_algorithm = { + .master_xfer = kempld_i2c_xfer, + .functionality = kempld_i2c_func, +}; + +static struct i2c_adapter kempld_i2c_adapter = { + .owner = THIS_MODULE, + .name = "i2c-kempld", + .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, + .algo = &kempld_i2c_algorithm, +}; + +static int kempld_i2c_probe(struct platform_device *pdev) +{ + struct kempld_device_data *pld = dev_get_drvdata(pdev->dev.parent); + struct kempld_i2c_data *i2c; + int ret; + u8 ctrl; + + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + i2c->pld = pld; + i2c->dev = &pdev->dev; + i2c->adap = kempld_i2c_adapter; + i2c->adap.dev.parent = i2c->dev; + i2c_set_adapdata(&i2c->adap, i2c); + platform_set_drvdata(pdev, i2c); + + kempld_get_mutex(pld); + ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); + + if (ctrl & I2C_CTRL_EN) + i2c->was_active = true; + + kempld_i2c_device_init(i2c); + kempld_release_mutex(pld); + + /* Add I2C adapter to I2C tree */ + if (i2c_bus >= -1) + i2c->adap.nr = i2c_bus; + ret = i2c_add_numbered_adapter(&i2c->adap); + if (ret) + return ret; + + dev_info(i2c->dev, "I2C bus initialized at %dkHz\n", + bus_frequency); + + return 0; +} + +static int kempld_i2c_remove(struct platform_device *pdev) +{ + struct kempld_i2c_data *i2c = platform_get_drvdata(pdev); + struct kempld_device_data *pld = i2c->pld; + u8 ctrl; + + kempld_get_mutex(pld); + /* + * Disable I2C logic if it was not activated before the + * driver loaded + */ + if (!i2c->was_active) { + ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); + ctrl &= ~I2C_CTRL_EN; + kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); + } + kempld_release_mutex(pld); + + i2c_del_adapter(&i2c->adap); + + return 0; +} + +#ifdef CONFIG_PM +static int kempld_i2c_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct kempld_i2c_data *i2c = platform_get_drvdata(pdev); + struct kempld_device_data *pld = i2c->pld; + u8 ctrl; + + kempld_get_mutex(pld); + ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); + ctrl &= ~I2C_CTRL_EN; + kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); + kempld_release_mutex(pld); + + return 0; +} + +static int kempld_i2c_resume(struct platform_device *pdev) +{ + struct kempld_i2c_data *i2c = platform_get_drvdata(pdev); + struct kempld_device_data *pld = i2c->pld; + + kempld_get_mutex(pld); + kempld_i2c_device_init(i2c); + kempld_release_mutex(pld); + + return 0; +} +#else +#define kempld_i2c_suspend NULL +#define kempld_i2c_resume NULL +#endif + +static struct platform_driver kempld_i2c_driver = { + .driver = { + .name = "kempld-i2c", + .owner = THIS_MODULE, + }, + .probe = kempld_i2c_probe, + .remove = kempld_i2c_remove, + .suspend = kempld_i2c_suspend, + .resume = kempld_i2c_resume, +}; + +module_platform_driver(kempld_i2c_driver); + +MODULE_DESCRIPTION("KEM PLD I2C Driver"); +MODULE_AUTHOR("Michael Brunner <michael.brunner@kontron.com>"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:kempld_i2c"); diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 9c55aae..8a2e2cd 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -17,10 +17,12 @@ #include <linux/module.h> #include <linux/sched.h> #include <linux/init.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/of_i2c.h> #include <linux/slab.h> +#include <linux/clk.h> #include <linux/io.h> #include <linux/fsl_devices.h> #include <linux/i2c.h> @@ -64,9 +66,10 @@ struct mpc_i2c { struct i2c_adapter adap; int irq; u32 real_clk; -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP u8 fdr, dfsrr; #endif + struct clk *clk_per; }; struct mpc_i2c_divider { @@ -618,7 +621,6 @@ static const struct i2c_algorithm mpc_algo = { static struct i2c_adapter mpc_ops = { .owner = THIS_MODULE, - .name = "MPC adapter", .algo = &mpc_algo, .timeout = HZ, }; @@ -632,6 +634,9 @@ static int fsl_i2c_probe(struct platform_device *op) u32 clock = MPC_I2C_CLOCK_LEGACY; int result = 0; int plen; + struct resource res; + struct clk *clk; + int err; match = of_match_device(mpc_i2c_of_match, &op->dev); if (!match) @@ -662,6 +667,21 @@ static int fsl_i2c_probe(struct platform_device *op) } } + /* + * enable clock for the I2C peripheral (non fatal), + * keep a reference upon successful allocation + */ + clk = devm_clk_get(&op->dev, NULL); + if (!IS_ERR(clk)) { + err = clk_prepare_enable(clk); + if (err) { + dev_err(&op->dev, "failed to enable clock\n"); + goto fail_request; + } else { + i2c->clk_per = clk; + } + } + if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) { clock = MPC_I2C_CLOCK_PRESERVE; } else { @@ -688,9 +708,12 @@ static int fsl_i2c_probe(struct platform_device *op) } dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); - dev_set_drvdata(&op->dev, i2c); + platform_set_drvdata(op, i2c); i2c->adap = mpc_ops; + of_address_to_resource(op->dev.of_node, 0, &res); + scnprintf(i2c->adap.name, sizeof(i2c->adap.name), + "MPC adapter at 0x%llx", (unsigned long long)res.start); i2c_set_adapdata(&i2c->adap, i2c); i2c->adap.dev.parent = &op->dev; i2c->adap.dev.of_node = of_node_get(op->dev.of_node); @@ -700,11 +723,12 @@ static int fsl_i2c_probe(struct platform_device *op) dev_err(i2c->dev, "failed to add adapter\n"); goto fail_add; } - of_i2c_register_devices(&i2c->adap); return result; fail_add: + if (i2c->clk_per) + clk_disable_unprepare(i2c->clk_per); free_irq(i2c->irq, i2c); fail_request: irq_dispose_mapping(i2c->irq); @@ -716,10 +740,13 @@ static int fsl_i2c_probe(struct platform_device *op) static int fsl_i2c_remove(struct platform_device *op) { - struct mpc_i2c *i2c = dev_get_drvdata(&op->dev); + struct mpc_i2c *i2c = platform_get_drvdata(op); i2c_del_adapter(&i2c->adap); + if (i2c->clk_per) + clk_disable_unprepare(i2c->clk_per); + if (i2c->irq) free_irq(i2c->irq, i2c); @@ -729,7 +756,7 @@ static int fsl_i2c_remove(struct platform_device *op) return 0; }; -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int mpc_i2c_suspend(struct device *dev) { struct mpc_i2c *i2c = dev_get_drvdata(dev); @@ -750,7 +777,10 @@ static int mpc_i2c_resume(struct device *dev) return 0; } -SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); +static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); +#define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops) +#else +#define MPC_I2C_PM_OPS NULL #endif static const struct mpc_i2c_data mpc_i2c_data_512x = { @@ -797,9 +827,7 @@ static struct platform_driver mpc_i2c_driver = { .owner = THIS_MODULE, .name = DRV_NAME, .of_match_table = mpc_i2c_of_match, -#ifdef CONFIG_PM - .pm = &mpc_i2c_pm_ops, -#endif + .pm = MPC_I2C_PM_OPS, }, }; diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 1a3abd6..8be7e42 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -19,19 +19,15 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/of_irq.h> -#include <linux/of_i2c.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/delay.h> -/* Register defines */ -#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 -#define MV64XXX_I2C_REG_DATA 0x04 -#define MV64XXX_I2C_REG_CONTROL 0x08 -#define MV64XXX_I2C_REG_STATUS 0x0c -#define MV64XXX_I2C_REG_BAUD 0x0c -#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 -#define MV64XXX_I2C_REG_SOFT_RESET 0x1c +#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) +#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) +#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 @@ -59,6 +55,32 @@ #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 +/* Register defines (I2C bridge) */ +#define MV64XXX_I2C_REG_TX_DATA_LO 0xc0 +#define MV64XXX_I2C_REG_TX_DATA_HI 0xc4 +#define MV64XXX_I2C_REG_RX_DATA_LO 0xc8 +#define MV64XXX_I2C_REG_RX_DATA_HI 0xcc +#define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0 +#define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4 +#define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8 +#define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC +#define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0 + +/* Bridge Control values */ +#define MV64XXX_I2C_BRIDGE_CONTROL_WR 0x00000001 +#define MV64XXX_I2C_BRIDGE_CONTROL_RD 0x00000002 +#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2 +#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT 0x00001000 +#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13 +#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16 +#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE 0x00080000 + +/* Bridge Status values */ +#define MV64XXX_I2C_BRIDGE_STATUS_ERROR 0x00000001 +#define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001 +#define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000 + + /* Driver states */ enum { MV64XXX_I2C_STATE_INVALID, @@ -75,25 +97,39 @@ enum { enum { MV64XXX_I2C_ACTION_INVALID, MV64XXX_I2C_ACTION_CONTINUE, + MV64XXX_I2C_ACTION_OFFLOAD_SEND_START, MV64XXX_I2C_ACTION_SEND_START, MV64XXX_I2C_ACTION_SEND_RESTART, + MV64XXX_I2C_ACTION_OFFLOAD_RESTART, MV64XXX_I2C_ACTION_SEND_ADDR_1, MV64XXX_I2C_ACTION_SEND_ADDR_2, MV64XXX_I2C_ACTION_SEND_DATA, MV64XXX_I2C_ACTION_RCV_DATA, MV64XXX_I2C_ACTION_RCV_DATA_STOP, MV64XXX_I2C_ACTION_SEND_STOP, + MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP, +}; + +struct mv64xxx_i2c_regs { + u8 addr; + u8 ext_addr; + u8 data; + u8 control; + u8 status; + u8 clock; + u8 soft_reset; }; struct mv64xxx_i2c_data { + struct i2c_msg *msgs; + int num_msgs; int irq; u32 state; u32 action; u32 aborting; u32 cntl_bits; void __iomem *reg_base; - u32 reg_base_p; - u32 reg_size; + struct mv64xxx_i2c_regs reg_offsets; u32 addr1; u32 addr2; u32 bytes_left; @@ -110,8 +146,128 @@ struct mv64xxx_i2c_data { spinlock_t lock; struct i2c_msg *msg; struct i2c_adapter adapter; + bool offload_enabled; +/* 5us delay in order to avoid repeated start timing violation */ + bool errata_delay; +}; + +static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { + .addr = 0x00, + .ext_addr = 0x10, + .data = 0x04, + .control = 0x08, + .status = 0x0c, + .clock = 0x0c, + .soft_reset = 0x1c, }; +static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = { + .addr = 0x00, + .ext_addr = 0x04, + .data = 0x08, + .control = 0x0c, + .status = 0x10, + .clock = 0x14, + .soft_reset = 0x18, +}; + +static void +mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, + struct i2c_msg *msg) +{ + u32 dir = 0; + + drv_data->msg = msg; + drv_data->byte_posn = 0; + drv_data->bytes_left = msg->len; + drv_data->aborting = 0; + drv_data->rc = 0; + drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | + MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; + + if (msg->flags & I2C_M_RD) + dir = 1; + + if (msg->flags & I2C_M_TEN) { + drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; + drv_data->addr2 = (u32)msg->addr & 0xff; + } else { + drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir; + drv_data->addr2 = 0; + } +} + +static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data) +{ + unsigned long data_reg_hi = 0; + unsigned long data_reg_lo = 0; + unsigned long ctrl_reg; + struct i2c_msg *msg = drv_data->msgs; + + drv_data->msg = msg; + drv_data->byte_posn = 0; + drv_data->bytes_left = msg->len; + drv_data->aborting = 0; + drv_data->rc = 0; + /* Only regular transactions can be offloaded */ + if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0) + return -EINVAL; + + /* Only 1-8 byte transfers can be offloaded */ + if (msg->len < 1 || msg->len > 8) + return -EINVAL; + + /* Build transaction */ + ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE | + (msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT); + + if ((msg->flags & I2C_M_TEN) != 0) + ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT; + + if ((msg->flags & I2C_M_RD) == 0) { + u8 local_buf[8] = { 0 }; + + memcpy(local_buf, msg->buf, msg->len); + data_reg_lo = cpu_to_le32(*((u32 *)local_buf)); + data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4))); + + ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR | + (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT; + + writel(data_reg_lo, + drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); + writel(data_reg_hi, + drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); + + } else { + ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD | + (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT; + } + + /* Execute transaction */ + writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); + + return 0; +} + +static void +mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data) +{ + struct i2c_msg *msg = drv_data->msg; + + if (msg->flags & I2C_M_RD) { + u32 data_reg_lo = readl(drv_data->reg_base + + MV64XXX_I2C_REG_RX_DATA_LO); + u32 data_reg_hi = readl(drv_data->reg_base + + MV64XXX_I2C_REG_RX_DATA_HI); + u8 local_buf[8] = { 0 }; + + *((u32 *)local_buf) = le32_to_cpu(data_reg_lo); + *((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi); + memcpy(msg->buf, local_buf, msg->len); + } + +} /* ***************************************************************************** * @@ -124,13 +280,22 @@ struct mv64xxx_i2c_data { static void mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) { - writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); - writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), - drv_data->reg_base + MV64XXX_I2C_REG_BAUD); - writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); - writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); + if (drv_data->offload_enabled) { + writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); + writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); + writel(0, drv_data->reg_base + + MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); + writel(0, drv_data->reg_base + + MV64XXX_I2C_REG_BRIDGE_INTR_MASK); + } + + writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); + writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), + drv_data->reg_base + drv_data->reg_offsets.clock); + writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); + writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); drv_data->state = MV64XXX_I2C_STATE_IDLE; } @@ -170,7 +335,7 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) if ((drv_data->bytes_left == 0) || (drv_data->aborting && (drv_data->byte_posn != 0))) { - if (drv_data->send_stop) { + if (drv_data->send_stop || drv_data->aborting) { drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; drv_data->state = MV64XXX_I2C_STATE_IDLE; } else { @@ -227,7 +392,17 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) /* Doesn't seem to be a device at other end */ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; drv_data->state = MV64XXX_I2C_STATE_IDLE; - drv_data->rc = -ENODEV; + drv_data->rc = -ENXIO; + break; + + case MV64XXX_I2C_STATUS_OFFLOAD_OK: + if (drv_data->send_stop || drv_data->aborting) { + drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP; + drv_data->state = MV64XXX_I2C_STATE_IDLE; + } else { + drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART; + drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART; + } break; default: @@ -246,60 +421,92 @@ static void mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) { switch(drv_data->action) { + case MV64XXX_I2C_ACTION_OFFLOAD_RESTART: + mv64xxx_i2c_update_offload_data(drv_data); + writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); + writel(0, drv_data->reg_base + + MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); + /* FALLTHRU */ case MV64XXX_I2C_ACTION_SEND_RESTART: - drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START; - drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); - drv_data->block = 0; - wake_up(&drv_data->waitq); + /* We should only get here if we have further messages */ + BUG_ON(drv_data->num_msgs == 0); + + drv_data->msgs++; + drv_data->num_msgs--; + if (!(drv_data->offload_enabled && + mv64xxx_i2c_offload_msg(drv_data))) { + drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START; + writel(drv_data->cntl_bits, + drv_data->reg_base + drv_data->reg_offsets.control); + + /* Setup for the next message */ + mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs); + } + if (drv_data->errata_delay) + udelay(5); + + /* + * We're never at the start of the message here, and by this + * time it's already too late to do any protocol mangling. + * Thankfully, do not advertise support for that feature. + */ + drv_data->send_stop = drv_data->num_msgs == 1; break; case MV64XXX_I2C_ACTION_CONTINUE: writel(drv_data->cntl_bits, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); break; + case MV64XXX_I2C_ACTION_OFFLOAD_SEND_START: + if (!mv64xxx_i2c_offload_msg(drv_data)) + break; + else + drv_data->action = MV64XXX_I2C_ACTION_SEND_START; + /* FALLTHRU */ case MV64XXX_I2C_ACTION_SEND_START: writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); break; case MV64XXX_I2C_ACTION_SEND_ADDR_1: writel(drv_data->addr1, - drv_data->reg_base + MV64XXX_I2C_REG_DATA); + drv_data->reg_base + drv_data->reg_offsets.data); writel(drv_data->cntl_bits, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); break; case MV64XXX_I2C_ACTION_SEND_ADDR_2: writel(drv_data->addr2, - drv_data->reg_base + MV64XXX_I2C_REG_DATA); + drv_data->reg_base + drv_data->reg_offsets.data); writel(drv_data->cntl_bits, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); break; case MV64XXX_I2C_ACTION_SEND_DATA: writel(drv_data->msg->buf[drv_data->byte_posn++], - drv_data->reg_base + MV64XXX_I2C_REG_DATA); + drv_data->reg_base + drv_data->reg_offsets.data); writel(drv_data->cntl_bits, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); break; case MV64XXX_I2C_ACTION_RCV_DATA: drv_data->msg->buf[drv_data->byte_posn++] = - readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); + readl(drv_data->reg_base + drv_data->reg_offsets.data); writel(drv_data->cntl_bits, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); break; case MV64XXX_I2C_ACTION_RCV_DATA_STOP: drv_data->msg->buf[drv_data->byte_posn++] = - readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); + readl(drv_data->reg_base + drv_data->reg_offsets.data); drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); drv_data->block = 0; + if (drv_data->errata_delay) + udelay(5); + wake_up(&drv_data->waitq); break; @@ -309,11 +516,21 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) "mv64xxx_i2c_do_action: Invalid action: %d\n", drv_data->action); drv_data->rc = -EIO; + /* FALLTHRU */ case MV64XXX_I2C_ACTION_SEND_STOP: drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, - drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); + drv_data->reg_base + drv_data->reg_offsets.control); + drv_data->block = 0; + wake_up(&drv_data->waitq); + break; + + case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP: + mv64xxx_i2c_update_offload_data(drv_data); + writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); + writel(0, drv_data->reg_base + + MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE); drv_data->block = 0; wake_up(&drv_data->waitq); break; @@ -329,9 +546,24 @@ mv64xxx_i2c_intr(int irq, void *dev_id) irqreturn_t rc = IRQ_NONE; spin_lock_irqsave(&drv_data->lock, flags); - while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & + + if (drv_data->offload_enabled) { + while (readl(drv_data->reg_base + + MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) { + int reg_status = readl(drv_data->reg_base + + MV64XXX_I2C_REG_BRIDGE_STATUS); + if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) + status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR; + else + status = MV64XXX_I2C_STATUS_OFFLOAD_OK; + mv64xxx_i2c_fsm(drv_data, status); + mv64xxx_i2c_do_action(drv_data); + rc = IRQ_HANDLED; + } + } + while (readl(drv_data->reg_base + drv_data->reg_offsets.control) & MV64XXX_I2C_REG_CONTROL_IFLG) { - status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); + status = readl(drv_data->reg_base + drv_data->reg_offsets.status); mv64xxx_i2c_fsm(drv_data, status); mv64xxx_i2c_do_action(drv_data); rc = IRQ_HANDLED; @@ -349,32 +581,6 @@ mv64xxx_i2c_intr(int irq, void *dev_id) ***************************************************************************** */ static void -mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, - struct i2c_msg *msg) -{ - u32 dir = 0; - - drv_data->msg = msg; - drv_data->byte_posn = 0; - drv_data->bytes_left = msg->len; - drv_data->aborting = 0; - drv_data->rc = 0; - drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | - MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; - - if (msg->flags & I2C_M_RD) - dir = 1; - - if (msg->flags & I2C_M_TEN) { - drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; - drv_data->addr2 = (u32)msg->addr & 0xff; - } else { - drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; - drv_data->addr2 = 0; - } -} - -static void mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) { long time_left; @@ -414,37 +620,20 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) static int mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, - int is_first, int is_last) + int is_last) { unsigned long flags; spin_lock_irqsave(&drv_data->lock, flags); - mv64xxx_i2c_prepare_for_io(drv_data, msg); - - if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ - if (drv_data->msg->flags & I2C_M_RD) { - /* No action to do, wait for slave to send a byte */ - drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; - drv_data->state = - MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; - } else { - drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; - drv_data->state = - MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; - drv_data->bytes_left--; - } + if (drv_data->offload_enabled) { + drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_START; + drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; } else { - if (is_first) { - drv_data->action = MV64XXX_I2C_ACTION_SEND_START; - drv_data->state = - MV64XXX_I2C_STATE_WAITING_FOR_START_COND; - } else { - drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; - drv_data->state = - MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; - } - } + mv64xxx_i2c_prepare_for_io(drv_data, msg); + drv_data->action = MV64XXX_I2C_ACTION_SEND_START; + drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; + } drv_data->send_stop = is_last; drv_data->block = 1; mv64xxx_i2c_do_action(drv_data); @@ -471,16 +660,20 @@ static int mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); - int i, rc; + int rc, ret = num; - for (i = 0; i < num; i++) { - rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i], - i == 0, i + 1 == num); - if (rc < 0) - return rc; - } + BUG_ON(drv_data->msgs != NULL); + drv_data->msgs = msgs; + drv_data->num_msgs = num; - return num; + rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1); + if (rc < 0) + ret = rc; + + drv_data->num_msgs = 0; + drv_data->msgs = NULL; + + return ret; } static const struct i2c_algorithm mv64xxx_i2c_algo = { @@ -495,41 +688,16 @@ static const struct i2c_algorithm mv64xxx_i2c_algo = { * ***************************************************************************** */ -static int -mv64xxx_i2c_map_regs(struct platform_device *pd, - struct mv64xxx_i2c_data *drv_data) -{ - int size; - struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0); - - if (!r) - return -ENODEV; - - size = resource_size(r); - - if (!request_mem_region(r->start, size, drv_data->adapter.name)) - return -EBUSY; - - drv_data->reg_base = ioremap(r->start, size); - drv_data->reg_base_p = r->start; - drv_data->reg_size = size; - - return 0; -} - -static void -mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) -{ - if (drv_data->reg_base) { - iounmap(drv_data->reg_base); - release_mem_region(drv_data->reg_base_p, drv_data->reg_size); - } - - drv_data->reg_base = NULL; - drv_data->reg_base_p = 0; -} +static const struct of_device_id mv64xxx_i2c_of_match_table[] = { + { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i}, + { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, + { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx}, + {} +}; +MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); #ifdef CONFIG_OF +#ifdef CONFIG_HAVE_CLK static int mv64xxx_calc_freq(const int tclk, const int n, const int m) { @@ -559,14 +727,12 @@ mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n, return false; return true; } +#endif /* CONFIG_HAVE_CLK */ static int mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, - struct device_node *np) + struct device *dev) { - u32 bus_freq, tclk; - int rc = 0; - /* CLK is mandatory when using DT to describe the i2c bus. We * need to know tclk in order to calculate bus clock * factors. @@ -575,12 +741,21 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, /* Have OF but no CLK */ return -ENODEV; #else + const struct of_device_id *device; + struct device_node *np = dev->of_node; + u32 bus_freq, tclk; + int rc = 0; + if (IS_ERR(drv_data->clk)) { rc = -ENODEV; goto out; } tclk = clk_get_rate(drv_data->clk); - of_property_read_u32(np, "clock-frequency", &bus_freq); + + rc = of_property_read_u32(np, "clock-frequency", &bus_freq); + if (rc) + bus_freq = 100000; /* 100kHz by default */ + if (!mv64xxx_find_baud_factors(bus_freq, tclk, &drv_data->freq_n, &drv_data->freq_m)) { rc = -EINVAL; @@ -592,6 +767,22 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, * So hard code the value to 1 second. */ drv_data->adapter.timeout = HZ; + + device = of_match_device(mv64xxx_i2c_of_match_table, dev); + if (!device) + return -ENODEV; + + memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets)); + + /* + * For controllers embedded in new SoCs activate the + * Transaction Generator support and the errata fix. + */ + if (of_device_is_compatible(np, "marvell,mv78230-i2c")) { + drv_data->offload_enabled = true; + drv_data->errata_delay = true; + } + out: return rc; #endif @@ -599,7 +790,7 @@ out: #else /* CONFIG_OF */ static int mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, - struct device_node *np) + struct device *dev) { return -ENODEV; } @@ -609,20 +800,22 @@ static int mv64xxx_i2c_probe(struct platform_device *pd) { struct mv64xxx_i2c_data *drv_data; - struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; + struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev); + struct resource *r; int rc; if ((!pdata && !pd->dev.of_node)) return -ENODEV; - drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); + drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data), + GFP_KERNEL); if (!drv_data) return -ENOMEM; - if (mv64xxx_i2c_map_regs(pd, drv_data)) { - rc = -ENODEV; - goto exit_kfree; - } + r = platform_get_resource(pd, IORESOURCE_MEM, 0); + drv_data->reg_base = devm_ioremap_resource(&pd->dev, r); + if (IS_ERR(drv_data->reg_base)) + return PTR_ERR(drv_data->reg_base); strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", sizeof(drv_data->adapter.name)); @@ -632,7 +825,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) #if defined(CONFIG_HAVE_CLK) /* Not all platforms have a clk */ - drv_data->clk = clk_get(&pd->dev, NULL); + drv_data->clk = devm_clk_get(&pd->dev, NULL); if (!IS_ERR(drv_data->clk)) { clk_prepare(drv_data->clk); clk_enable(drv_data->clk); @@ -643,14 +836,16 @@ mv64xxx_i2c_probe(struct platform_device *pd) drv_data->freq_n = pdata->freq_n; drv_data->irq = platform_get_irq(pd, 0); drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); + drv_data->offload_enabled = false; + memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets)); } else if (pd->dev.of_node) { - rc = mv64xxx_of_config(drv_data, pd->dev.of_node); + rc = mv64xxx_of_config(drv_data, &pd->dev); if (rc) - goto exit_unmap_regs; + goto exit_clk; } if (drv_data->irq < 0) { rc = -ENXIO; - goto exit_unmap_regs; + goto exit_clk; } drv_data->adapter.dev.parent = &pd->dev; @@ -664,26 +859,24 @@ mv64xxx_i2c_probe(struct platform_device *pd) mv64xxx_i2c_hw_init(drv_data); - if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, - MV64XXX_I2C_CTLR_NAME, drv_data)) { + rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, + MV64XXX_I2C_CTLR_NAME, drv_data); + if (rc) { dev_err(&drv_data->adapter.dev, - "mv64xxx: Can't register intr handler irq: %d\n", - drv_data->irq); - rc = -EINVAL; - goto exit_unmap_regs; + "mv64xxx: Can't register intr handler irq%d: %d\n", + drv_data->irq, rc); + goto exit_clk; } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { dev_err(&drv_data->adapter.dev, "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); goto exit_free_irq; } - of_i2c_register_devices(&drv_data->adapter); - return 0; - exit_free_irq: - free_irq(drv_data->irq, drv_data); - exit_unmap_regs: +exit_free_irq: + free_irq(drv_data->irq, drv_data); +exit_clk: #if defined(CONFIG_HAVE_CLK) /* Not all platforms have a clk */ if (!IS_ERR(drv_data->clk)) { @@ -691,9 +884,6 @@ mv64xxx_i2c_probe(struct platform_device *pd) clk_unprepare(drv_data->clk); } #endif - mv64xxx_i2c_unmap_regs(drv_data); - exit_kfree: - kfree(drv_data); return rc; } @@ -704,7 +894,6 @@ mv64xxx_i2c_remove(struct platform_device *dev) i2c_del_adapter(&drv_data->adapter); free_irq(drv_data->irq, drv_data); - mv64xxx_i2c_unmap_regs(drv_data); #if defined(CONFIG_HAVE_CLK) /* Not all platforms have a clk */ if (!IS_ERR(drv_data->clk)) { @@ -712,24 +901,17 @@ mv64xxx_i2c_remove(struct platform_device *dev) clk_unprepare(drv_data->clk); } #endif - kfree(drv_data); return 0; } -static const struct of_device_id mv64xxx_i2c_of_match_table[] = { - { .compatible = "marvell,mv64xxx-i2c", }, - {} -}; -MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); - static struct platform_driver mv64xxx_i2c_driver = { .probe = mv64xxx_i2c_probe, .remove = mv64xxx_i2c_remove, .driver = { .owner = THIS_MODULE, .name = MV64XXX_I2C_CTLR_NAME, - .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table), + .of_match_table = mv64xxx_i2c_of_match_table, }, }; diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c index 2039f23..0cde4e6 100644 --- a/drivers/i2c/busses/i2c-mxs.c +++ b/drivers/i2c/busses/i2c-mxs.c @@ -1,6 +1,7 @@ /* * Freescale MXS I2C bus driver * + * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. * * based on a (non-working) driver which was: @@ -24,11 +25,9 @@ #include <linux/platform_device.h> #include <linux/jiffies.h> #include <linux/io.h> -#include <linux/pinctrl/consumer.h> #include <linux/stmp_device.h> #include <linux/of.h> #include <linux/of_device.h> -#include <linux/of_i2c.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> @@ -36,10 +35,12 @@ #define MXS_I2C_CTRL0 (0x00) #define MXS_I2C_CTRL0_SET (0x04) +#define MXS_I2C_CTRL0_CLR (0x08) #define MXS_I2C_CTRL0_SFTRST 0x80000000 #define MXS_I2C_CTRL0_RUN 0x20000000 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define MXS_I2C_CTRL0_PIO_MODE 0x01000000 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 @@ -66,13 +67,13 @@ #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 #define MXS_I2C_STAT (0x50) +#define MXS_I2C_STAT_GOT_A_NAK 0x10000000 #define MXS_I2C_STAT_BUS_BUSY 0x00000800 #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400 -#define MXS_I2C_DATA (0xa0) +#define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0) -#define MXS_I2C_DEBUG0 (0xb0) -#define MXS_I2C_DEBUG0_CLR (0xb8) +#define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8) #define MXS_I2C_DEBUG0_DMAREQ 0x80000000 @@ -97,10 +98,17 @@ #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ MXS_I2C_CTRL0_MASTER_MODE) +enum mxs_i2c_devtype { + MXS_I2C_UNKNOWN = 0, + MXS_I2C_V1, + MXS_I2C_V2, +}; + /** * struct mxs_i2c_dev - per device, private MXS-I2C data * * @dev: driver model device node + * @dev_type: distinguish i.MX23/i.MX28 features * @regs: IO registers pointer * @cmd_complete: completion object for transaction wait * @cmd_err: error code for last transaction @@ -108,6 +116,7 @@ */ struct mxs_i2c_dev { struct device *dev; + enum mxs_i2c_devtype dev_type; void __iomem *regs; struct completion cmd_complete; int cmd_err; @@ -115,18 +124,21 @@ struct mxs_i2c_dev { uint32_t timing0; uint32_t timing1; + uint32_t timing2; /* DMA support components */ - struct dma_chan *dmach; + struct dma_chan *dmach; uint32_t pio_data[2]; uint32_t addr_data; struct scatterlist sg_io[2]; bool dma_read; }; -static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) +static int mxs_i2c_reset(struct mxs_i2c_dev *i2c) { - stmp_reset_block(i2c->regs); + int ret = stmp_reset_block(i2c->regs); + if (ret) + return ret; /* * Configure timing for the I2C block. The I2C TIMING2 register has to @@ -137,9 +149,11 @@ static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) */ writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0); writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1); - writel(0x00300030, i2c->regs + MXS_I2C_TIMING2); + writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2); writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); + + return 0; } static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) @@ -288,48 +302,11 @@ write_init_pio_fail: return -EINVAL; } -static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(1000); - - while (!(readl(i2c->regs + MXS_I2C_DEBUG0) & - MXS_I2C_DEBUG0_DMAREQ)) { - if (time_after(jiffies, timeout)) - return -ETIMEDOUT; - cond_resched(); - } - - return 0; -} - -static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last) +static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c) { unsigned long timeout = jiffies + msecs_to_jiffies(1000); - /* - * We do not use interrupts in the PIO mode. Due to the - * maximum transfer length being 8 bytes in PIO mode, the - * overhead of interrupt would be too large and this would - * neglect the gain from using the PIO mode. - */ - - while (!(readl(i2c->regs + MXS_I2C_CTRL1) & - MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) { - if (time_after(jiffies, timeout)) - return -ETIMEDOUT; - cond_resched(); - } - - writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ, - i2c->regs + MXS_I2C_CTRL1_CLR); - - /* - * When ending a transfer with a stop, we have to wait for the bus to - * go idle before we report the transfer as completed. Otherwise the - * start of the next transfer may race with the end of the current one. - */ - while (last && (readl(i2c->regs + MXS_I2C_STAT) & - (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) { + while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) { if (time_after(jiffies, timeout)) return -ETIMEDOUT; cond_resched(); @@ -367,106 +344,215 @@ static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd) writel(reg, i2c->regs + MXS_I2C_CTRL0); } +/* + * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet, + * CTRL0::PIO_MODE bit description clarifies the order in which the registers + * must be written during PIO mode operation. First, the CTRL0 register has + * to be programmed with all the necessary bits but the RUN bit. Then the + * payload has to be written into the DATA register. Finally, the transmission + * is executed by setting the RUN bit in CTRL0. + */ +static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd, + u32 data) +{ + writel(cmd, i2c->regs + MXS_I2C_CTRL0); + + if (i2c->dev_type == MXS_I2C_V1) + writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET); + + writel(data, i2c->regs + MXS_I2C_DATA(i2c)); + writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET); +} + static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, uint32_t flags) { struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); uint32_t addr_data = msg->addr << 1; uint32_t data = 0; - int i, shifts_left, ret; + int i, ret, xlen = 0, xmit = 0; + uint32_t start; /* Mute IRQs coming from this block. */ writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR); + /* + * MX23 idea: + * - Enable CTRL0::PIO_MODE (1 << 24) + * - Enable CTRL1::ACK_MODE (1 << 27) + * + * WARNING! The MX23 is broken in some way, even if it claims + * to support PIO, when we try to transfer any amount of data + * that is not aligned to 4 bytes, the DMA engine will have + * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the + * transfer. This in turn will mess up the next transfer as + * the block it emit one byte write onto the bus terminated + * with a NAK+STOP. A possible workaround is to reset the IP + * block after every PIO transmission, which might just work. + * + * NOTE: The CTRL0::PIO_MODE description is important, since + * it outlines how the PIO mode is really supposed to work. + */ if (msg->flags & I2C_M_RD) { + /* + * PIO READ transfer: + * + * This transfer MUST be limited to 4 bytes maximum. It is not + * possible to transfer more than four bytes via PIO, since we + * can not in any way make sure we can read the data from the + * DATA register fast enough. Besides, the RX FIFO is only four + * bytes deep, thus we can only really read up to four bytes at + * time. Finally, there is no bit indicating us that new data + * arrived at the FIFO and can thus be fetched from the DATA + * register. + */ + BUG_ON(msg->len > 4); + addr_data |= I2C_SMBUS_READ; /* SELECT command. */ - mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT); - - ret = mxs_i2c_pio_wait_dmareq(i2c); - if (ret) - return ret; - - writel(addr_data, i2c->regs + MXS_I2C_DATA); - writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR); - - ret = mxs_i2c_pio_wait_cplt(i2c, 0); - if (ret) - return ret; + mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT, + addr_data); - if (mxs_i2c_pio_check_error_state(i2c)) + ret = mxs_i2c_pio_wait_xfer_end(i2c); + if (ret) { + dev_err(i2c->dev, + "PIO: Failed to send SELECT command!\n"); goto cleanup; + } /* READ command. */ mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_READ | flags | MXS_I2C_CTRL0_XFER_COUNT(msg->len)); + ret = mxs_i2c_pio_wait_xfer_end(i2c); + if (ret) { + dev_err(i2c->dev, + "PIO: Failed to send SELECT command!\n"); + goto cleanup; + } + + data = readl(i2c->regs + MXS_I2C_DATA(i2c)); for (i = 0; i < msg->len; i++) { - if ((i & 3) == 0) { - ret = mxs_i2c_pio_wait_dmareq(i2c); - if (ret) - return ret; - data = readl(i2c->regs + MXS_I2C_DATA); - writel(MXS_I2C_DEBUG0_DMAREQ, - i2c->regs + MXS_I2C_DEBUG0_CLR); - } msg->buf[i] = data & 0xff; data >>= 8; } } else { + /* + * PIO WRITE transfer: + * + * The code below implements clock stretching to circumvent + * the possibility of kernel not being able to supply data + * fast enough. It is possible to transfer arbitrary amount + * of data using PIO write. + */ addr_data |= I2C_SMBUS_WRITE; - /* WRITE command. */ - mxs_i2c_pio_trigger_cmd(i2c, - MXS_CMD_I2C_WRITE | flags | - MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1)); - /* * The LSB of data buffer is the first byte blasted across * the bus. Higher order bytes follow. Thus the following * filling schematic. */ + data = addr_data << 24; + + /* Start the transfer with START condition. */ + start = MXS_I2C_CTRL0_PRE_SEND_START; + + /* If the transfer is long, use clock stretching. */ + if (msg->len > 3) + start |= MXS_I2C_CTRL0_RETAIN_CLOCK; + for (i = 0; i < msg->len; i++) { data >>= 8; data |= (msg->buf[i] << 24); - if ((i & 3) == 2) { - ret = mxs_i2c_pio_wait_dmareq(i2c); - if (ret) - return ret; - writel(data, i2c->regs + MXS_I2C_DATA); - writel(MXS_I2C_DEBUG0_DMAREQ, - i2c->regs + MXS_I2C_DEBUG0_CLR); + + xmit = 0; + + /* This is the last transfer of the message. */ + if (i + 1 == msg->len) { + /* Add optional STOP flag. */ + start |= flags; + /* Remove RETAIN_CLOCK bit. */ + start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK; + xmit = 1; } - } - shifts_left = 24 - (i & 3) * 8; - if (shifts_left) { - data >>= shifts_left; - ret = mxs_i2c_pio_wait_dmareq(i2c); - if (ret) - return ret; - writel(data, i2c->regs + MXS_I2C_DATA); + /* Four bytes are ready in the "data" variable. */ + if ((i & 3) == 2) + xmit = 1; + + /* Nothing interesting happened, continue stuffing. */ + if (!xmit) + continue; + + /* + * Compute the size of the transfer and shift the + * data accordingly. + * + * i = (4k + 0) .... xlen = 2 + * i = (4k + 1) .... xlen = 3 + * i = (4k + 2) .... xlen = 4 + * i = (4k + 3) .... xlen = 1 + */ + + if ((i % 4) == 3) + xlen = 1; + else + xlen = (i % 4) + 2; + + data >>= (4 - xlen) * 8; + + dev_dbg(i2c->dev, + "PIO: len=%i pos=%i total=%i [W%s%s%s]\n", + xlen, i, msg->len, + start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "", + start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "", + start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : ""); + writel(MXS_I2C_DEBUG0_DMAREQ, - i2c->regs + MXS_I2C_DEBUG0_CLR); + i2c->regs + MXS_I2C_DEBUG0_CLR(i2c)); + + mxs_i2c_pio_trigger_write_cmd(i2c, + start | MXS_I2C_CTRL0_MASTER_MODE | + MXS_I2C_CTRL0_DIRECTION | + MXS_I2C_CTRL0_XFER_COUNT(xlen), data); + + /* The START condition is sent only once. */ + start &= ~MXS_I2C_CTRL0_PRE_SEND_START; + + /* Wait for the end of the transfer. */ + ret = mxs_i2c_pio_wait_xfer_end(i2c); + if (ret) { + dev_err(i2c->dev, + "PIO: Failed to finish WRITE cmd!\n"); + break; + } + + /* Check NAK here. */ + ret = readl(i2c->regs + MXS_I2C_STAT) & + MXS_I2C_STAT_GOT_A_NAK; + if (ret) { + ret = -ENXIO; + goto cleanup; + } } } - ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP); - if (ret) - return ret; - /* make sure we capture any occurred error into cmd_err */ - mxs_i2c_pio_check_error_state(i2c); + ret = mxs_i2c_pio_check_error_state(i2c); cleanup: /* Clear any dangling IRQs and re-enable interrupts. */ writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR); writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); - return 0; + /* Clear the PIO_MODE on i.MX23 */ + if (i2c->dev_type == MXS_I2C_V1) + writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR); + + return ret; } /* @@ -478,6 +564,7 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); int ret; int flags; + int use_pio = 0; flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; @@ -488,18 +575,23 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, return -EINVAL; /* - * The current boundary to select between PIO/DMA transfer method - * is set to 8 bytes, transfers shorter than 8 bytes are transfered - * using PIO mode while longer transfers use DMA. The 8 byte border is - * based on this empirical measurement and a lot of previous frobbing. + * The MX28 I2C IP block can only do PIO READ for transfer of to up + * 4 bytes of length. The write transfer is not limited as it can use + * clock stretching to avoid FIFO underruns. */ + if ((msg->flags & I2C_M_RD) && (msg->len <= 4)) + use_pio = 1; + if (!(msg->flags & I2C_M_RD) && (msg->len < 7)) + use_pio = 1; + i2c->cmd_err = 0; - if (msg->len < 8) { + if (use_pio) { ret = mxs_i2c_pio_setup_xfer(adap, msg, flags); - if (ret) + /* No need to reset the block if NAK was received. */ + if (ret && (ret != -ENXIO)) mxs_i2c_reset(i2c); } else { - INIT_COMPLETION(i2c->cmd_complete); + reinit_completion(&i2c->cmd_complete); ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); if (ret) return ret; @@ -508,9 +600,11 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, msecs_to_jiffies(1000)); if (ret == 0) goto timeout; + + ret = i2c->cmd_err; } - if (i2c->cmd_err == -ENXIO) { + if (ret == -ENXIO) { /* * If the transfer fails with a NAK from the slave the * controller halts until it gets told to return to idle state. @@ -519,7 +613,19 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, i2c->regs + MXS_I2C_CTRL1_SET); } - ret = i2c->cmd_err; + /* + * WARNING! + * The i.MX23 is strange. After each and every operation, it's I2C IP + * block must be reset, otherwise the IP block will misbehave. This can + * be observed on the bus by the block sending out one single byte onto + * the bus. In case such an error happens, bit 27 will be set in the + * DEBUG0 register. This bit is not documented in the i.MX23 datasheet + * and is marked as "TBD" instead. To reset this bit to a correct state, + * reset the whole block. Since the block reset does not take long, do + * reset the block after every transfer to play safe. + */ + if (i2c->dev_type == MXS_I2C_V1) + mxs_i2c_reset(i2c); dev_dbg(i2c->dev, "Done with err=%d\n", ret); @@ -528,7 +634,10 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, timeout: dev_dbg(i2c->dev, "Timeout!\n"); mxs_i2c_dma_finish(i2c); - mxs_i2c_reset(i2c); + ret = mxs_i2c_reset(i2c); + if (ret) + return ret; + return -ETIMEDOUT; } @@ -578,41 +687,79 @@ static const struct i2c_algorithm mxs_i2c_algo = { .functionality = mxs_i2c_func, }; -static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, int speed) +static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed) { - /* The I2C block clock run at 24MHz */ + /* The I2C block clock runs at 24MHz */ const uint32_t clk = 24000000; - uint32_t base; + uint32_t divider; uint16_t high_count, low_count, rcv_count, xmit_count; + uint32_t bus_free, leadin; struct device *dev = i2c->dev; - if (speed > 540000) { - dev_warn(dev, "Speed too high (%d Hz), using 540 kHz\n", speed); - speed = 540000; - } else if (speed < 12000) { - dev_warn(dev, "Speed too low (%d Hz), using 12 kHz\n", speed); - speed = 12000; + divider = DIV_ROUND_UP(clk, speed); + + if (divider < 25) { + /* + * limit the divider, so that min(low_count, high_count) + * is >= 1 + */ + divider = 25; + dev_warn(dev, + "Speed too high (%u.%03u kHz), using %u.%03u kHz\n", + speed / 1000, speed % 1000, + clk / divider / 1000, clk / divider % 1000); + } else if (divider > 1897) { + /* + * limit the divider, so that max(low_count, high_count) + * cannot exceed 1023 + */ + divider = 1897; + dev_warn(dev, + "Speed too low (%u.%03u kHz), using %u.%03u kHz\n", + speed / 1000, speed % 1000, + clk / divider / 1000, clk / divider % 1000); } /* - * The timing derivation algorithm. There is no documentation for this - * algorithm available, it was derived by using the scope and fiddling - * with constants until the result observed on the scope was good enough - * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be - * possible to assume the algorithm works for other frequencies as well. + * The I2C spec specifies the following timing data: + * standard mode fast mode Bitfield name + * tLOW (SCL LOW period) 4700 ns 1300 ns + * tHIGH (SCL HIGH period) 4000 ns 600 ns + * tSU;DAT (data setup time) 250 ns 100 ns + * tHD;STA (START hold time) 4000 ns 600 ns + * tBUF (bus free time) 4700 ns 1300 ns * - * Note it was necessary to cap the frequency on both ends as it's not - * possible to configure completely arbitrary frequency for the I2C bus - * clock. + * The hardware (of the i.MX28 at least) seems to add 2 additional + * clock cycles to the low_count and 7 cycles to the high_count. + * This is compensated for by subtracting the respective constants + * from the values written to the timing registers. */ - base = ((clk / speed) - 38) / 2; - high_count = base + 3; - low_count = base - 3; - rcv_count = (high_count * 3) / 4; - xmit_count = low_count / 4; + if (speed > 100000) { + /* fast mode */ + low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6)); + high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6)); + leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000); + bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000); + } else { + /* normal mode */ + low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40)); + high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40)); + leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); + bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); + } + rcv_count = high_count * 3 / 8; + xmit_count = low_count * 3 / 8; + dev_dbg(dev, + "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n", + speed, clk / divider, divider, low_count, high_count, + xmit_count, rcv_count, leadin, bus_free); + + low_count -= 2; + high_count -= 7; i2c->timing0 = (high_count << 16) | rcv_count; i2c->timing1 = (low_count << 16) | xmit_count; + i2c->timing2 = (bus_free << 16 | leadin); } static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) @@ -633,24 +780,44 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) return 0; } +static struct platform_device_id mxs_i2c_devtype[] = { + { + .name = "imx23-i2c", + .driver_data = MXS_I2C_V1, + }, { + .name = "imx28-i2c", + .driver_data = MXS_I2C_V2, + }, { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype); + +static const struct of_device_id mxs_i2c_dt_ids[] = { + { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], }, + { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); + static int mxs_i2c_probe(struct platform_device *pdev) { + const struct of_device_id *of_id = + of_match_device(mxs_i2c_dt_ids, &pdev->dev); struct device *dev = &pdev->dev; struct mxs_i2c_dev *i2c; struct i2c_adapter *adap; - struct pinctrl *pinctrl; struct resource *res; resource_size_t res_size; int err, irq; - pinctrl = devm_pinctrl_get_select_default(dev); - if (IS_ERR(pinctrl)) - return PTR_ERR(pinctrl); - i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); if (!i2c) return -ENOMEM; + if (of_id) { + const struct platform_device_id *device_id = of_id->data; + i2c->dev_type = device_id->driver_data; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); @@ -689,7 +856,9 @@ static int mxs_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, i2c); /* Do reset to enforce correct startup after pinmuxing */ - mxs_i2c_reset(i2c); + err = mxs_i2c_reset(i2c); + if (err) + return err; adap = &i2c->adapter; strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); @@ -707,8 +876,6 @@ static int mxs_i2c_probe(struct platform_device *pdev) return err; } - of_i2c_register_devices(adap); - return 0; } @@ -726,24 +893,19 @@ static int mxs_i2c_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id mxs_i2c_dt_ids[] = { - { .compatible = "fsl,imx28-i2c", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); - static struct platform_driver mxs_i2c_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, .of_match_table = mxs_i2c_dt_ids, }, + .probe = mxs_i2c_probe, .remove = mxs_i2c_remove, }; static int __init mxs_i2c_init(void) { - return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe); + return platform_driver_register(&mxs_i2c_driver); } subsys_initcall(mxs_i2c_init); @@ -753,6 +915,7 @@ static void __exit mxs_i2c_exit(void) } module_exit(mxs_i2c_exit); +MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); MODULE_DESCRIPTION("MXS I2C Bus Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c index 650293f..8bf9ac0 100644 --- a/drivers/i2c/busses/i2c-nomadik.c +++ b/drivers/i2c/busses/i2c-nomadik.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/amba/bus.h> -#include <linux/atomic.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/i2c.h> @@ -25,7 +24,6 @@ #include <linux/pm_runtime.h> #include <linux/platform_data/i2c-nomadik.h> #include <linux/of.h> -#include <linux/of_i2c.h> #include <linux/pinctrl/consumer.h> #define DRIVER_NAME "nmk-i2c" @@ -106,6 +104,16 @@ /* maximum threshold value */ #define MAX_I2C_FIFO_THRESHOLD 15 +/** + * struct i2c_vendor_data - per-vendor variations + * @has_mtdws: variant has the MTDWS bit + * @fifodepth: variant FIFO depth + */ +struct i2c_vendor_data { + bool has_mtdws; + u32 fifodepth; +}; + enum i2c_status { I2C_NOP, I2C_ON_GOING, @@ -138,6 +146,7 @@ struct i2c_nmk_client { /** * struct nmk_i2c_dev - private data structure of the controller. + * @vendor: vendor data for this variant. * @adev: parent amba device. * @adap: corresponding I2C adapter. * @irq: interrupt line for the controller. @@ -148,13 +157,10 @@ struct i2c_nmk_client { * @stop: stop condition. * @xfer_complete: acknowledge completion for a I2C message. * @result: controller propogated result. - * @pinctrl: pinctrl handle. - * @pins_default: default state for the pins. - * @pins_idle: idle state for the pins. - * @pins_sleep: sleep state for the pins. * @busy: Busy doing transfer. */ struct nmk_i2c_dev { + struct i2c_vendor_data *vendor; struct amba_device *adev; struct i2c_adapter adap; int irq; @@ -165,11 +171,6 @@ struct nmk_i2c_dev { int stop; struct completion xfer_complete; int result; - /* Three pin states - default, idle & sleep */ - struct pinctrl *pinctrl; - struct pinctrl_state *pins_default; - struct pinctrl_state *pins_idle; - struct pinctrl_state *pins_sleep; bool busy; }; @@ -431,7 +432,7 @@ static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | I2C_IT_MAL | I2C_IT_BERR); - if (dev->stop) + if (dev->stop || !dev->vendor->has_mtdws) irq_mask |= I2C_IT_MTD; else irq_mask |= I2C_IT_MTDWS; @@ -511,7 +512,7 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) * set the MTDWS bit (Master Transaction Done Without Stop) * to start repeated start operation */ - if (dev->stop) + if (dev->stop || !dev->vendor->has_mtdws) irq_mask |= I2C_IT_MTD; else irq_mask |= I2C_IT_MTDWS; @@ -645,13 +646,7 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, } /* Optionaly enable pins to be muxed in and configured */ - if (!IS_ERR(dev->pins_default)) { - status = pinctrl_select_state(dev->pinctrl, - dev->pins_default); - if (status) - dev_err(&dev->adev->dev, - "could not set default pins\n"); - } + pinctrl_pm_select_default_state(&dev->adev->dev); status = init_hw(dev); if (status) @@ -681,13 +676,7 @@ out: clk_disable_unprepare(dev->clk); out_clk: /* Optionally let pins go into idle state */ - if (!IS_ERR(dev->pins_idle)) { - status = pinctrl_select_state(dev->pinctrl, - dev->pins_idle); - if (status) - dev_err(&dev->adev->dev, - "could not set pins to idle state\n"); - } + pinctrl_pm_select_idle_state(&dev->adev->dev); pm_runtime_put_sync(&dev->adev->dev); @@ -882,41 +871,22 @@ static int nmk_i2c_suspend(struct device *dev) { struct amba_device *adev = to_amba_device(dev); struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); - int ret; if (nmk_i2c->busy) return -EBUSY; - if (!IS_ERR(nmk_i2c->pins_sleep)) { - ret = pinctrl_select_state(nmk_i2c->pinctrl, - nmk_i2c->pins_sleep); - if (ret) - dev_err(dev, "could not set pins to sleep state\n"); - } + pinctrl_pm_select_sleep_state(dev); return 0; } static int nmk_i2c_resume(struct device *dev) { - struct amba_device *adev = to_amba_device(dev); - struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); - int ret; - /* First go to the default state */ - if (!IS_ERR(nmk_i2c->pins_default)) { - ret = pinctrl_select_state(nmk_i2c->pinctrl, - nmk_i2c->pins_default); - if (ret) - dev_err(dev, "could not set pins to default state\n"); - } + pinctrl_pm_select_default_state(dev); /* Then let's idle the pins until the next transfer happens */ - if (!IS_ERR(nmk_i2c->pins_idle)) { - ret = pinctrl_select_state(nmk_i2c->pinctrl, - nmk_i2c->pins_idle); - if (ret) - dev_err(dev, "could not set pins to idle state\n"); - } + pinctrl_pm_select_idle_state(dev); + return 0; } #else @@ -969,15 +939,15 @@ static void nmk_i2c_of_probe(struct device_node *np, pdata->sm = I2C_FREQ_MODE_FAST; } -static atomic_t adapter_id = ATOMIC_INIT(0); - static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) { int ret = 0; - struct nmk_i2c_controller *pdata = adev->dev.platform_data; + struct nmk_i2c_controller *pdata = dev_get_platdata(&adev->dev); struct device_node *np = adev->dev.of_node; struct nmk_i2c_dev *dev; struct i2c_adapter *adap; + struct i2c_vendor_data *vendor = id->data; + u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; if (!pdata) { if (np) { @@ -994,49 +964,33 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) pdata = &u8500_i2c; } + if (pdata->tft > max_fifo_threshold) { + dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n", + pdata->tft, max_fifo_threshold); + pdata->tft = max_fifo_threshold; + } + + if (pdata->rft > max_fifo_threshold) { + dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n", + pdata->rft, max_fifo_threshold); + pdata->rft = max_fifo_threshold; + } + dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); if (!dev) { dev_err(&adev->dev, "cannot allocate memory\n"); ret = -ENOMEM; goto err_no_mem; } + dev->vendor = vendor; dev->busy = false; dev->adev = adev; amba_set_drvdata(adev, dev); - dev->pinctrl = devm_pinctrl_get(&adev->dev); - if (IS_ERR(dev->pinctrl)) { - ret = PTR_ERR(dev->pinctrl); - goto err_pinctrl; - } - - dev->pins_default = pinctrl_lookup_state(dev->pinctrl, - PINCTRL_STATE_DEFAULT); - if (IS_ERR(dev->pins_default)) { - dev_err(&adev->dev, "could not get default pinstate\n"); - } else { - ret = pinctrl_select_state(dev->pinctrl, - dev->pins_default); - if (ret) - dev_dbg(&adev->dev, "could not set default pinstate\n"); - } - - dev->pins_idle = pinctrl_lookup_state(dev->pinctrl, - PINCTRL_STATE_IDLE); - if (IS_ERR(dev->pins_idle)) { - dev_dbg(&adev->dev, "could not get idle pinstate\n"); - } else { - /* If possible, let's go to idle until the first transfer */ - ret = pinctrl_select_state(dev->pinctrl, - dev->pins_idle); - if (ret) - dev_dbg(&adev->dev, "could not set idle pinstate\n"); - } - - dev->pins_sleep = pinctrl_lookup_state(dev->pinctrl, - PINCTRL_STATE_SLEEP); - if (IS_ERR(dev->pins_sleep)) - dev_dbg(&adev->dev, "could not get sleep pinstate\n"); + /* Select default pin state */ + pinctrl_pm_select_default_state(&adev->dev); + /* If possible, let's go to idle until the first transfer */ + pinctrl_pm_select_idle_state(&adev->dev); dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); if (!dev->virtbase) { @@ -1068,10 +1022,8 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; adap->algo = &nmk_i2c_algo; adap->timeout = msecs_to_jiffies(pdata->timeout); - adap->nr = atomic_read(&adapter_id); snprintf(adap->name, sizeof(adap->name), - "Nomadik I2C%d at %pR", adap->nr, &adev->res); - atomic_inc(&adapter_id); + "Nomadik I2C at %pR", &adev->res); /* fetch the controller configuration from machine */ dev->cfg.clk_freq = pdata->clk_freq; @@ -1086,14 +1038,12 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) "initialize %s on virtual base %p\n", adap->name, dev->virtbase); - ret = i2c_add_numbered_adapter(adap); + ret = i2c_add_adapter(adap); if (ret) { dev_err(&adev->dev, "failed to add adapter\n"); goto err_add_adap; } - of_i2c_register_devices(adap); - pm_runtime_put(&adev->dev); return 0; @@ -1106,7 +1056,6 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) iounmap(dev->virtbase); err_no_ioremap: kfree(dev); - err_pinctrl: err_no_mem: return ret; @@ -1134,14 +1083,26 @@ static int nmk_i2c_remove(struct amba_device *adev) return 0; } +static struct i2c_vendor_data vendor_stn8815 = { + .has_mtdws = false, + .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ +}; + +static struct i2c_vendor_data vendor_db8500 = { + .has_mtdws = true, + .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ +}; + static struct amba_id nmk_i2c_ids[] = { { .id = 0x00180024, .mask = 0x00ffffff, + .data = &vendor_stn8815, }, { .id = 0x00380024, .mask = 0x00ffffff, + .data = &vendor_db8500, }, {}, }; diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c index 865ee35..36394d7 100644 --- a/drivers/i2c/busses/i2c-nuc900.c +++ b/drivers/i2c/busses/i2c-nuc900.c @@ -525,7 +525,7 @@ static int nuc900_i2c_probe(struct platform_device *pdev) struct resource *res; int ret; - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (!pdata) { dev_err(&pdev->dev, "no platform data\n"); return -EINVAL; diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c index 0e1f824..c61f37a 100644 --- a/drivers/i2c/busses/i2c-ocores.c +++ b/drivers/i2c/busses/i2c-ocores.c @@ -24,7 +24,6 @@ #include <linux/i2c-ocores.h> #include <linux/slab.h> #include <linux/io.h> -#include <linux/of_i2c.h> #include <linux/log2.h> struct ocores_i2c { @@ -353,10 +352,6 @@ static int ocores_i2c_probe(struct platform_device *pdev) int ret; int i; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -365,11 +360,12 @@ static int ocores_i2c_probe(struct platform_device *pdev) if (!i2c) return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); i2c->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(i2c->base)) return PTR_ERR(i2c->base); - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (pdata) { i2c->reg_shift = pdata->reg_shift; i2c->reg_io_width = pdata->reg_io_width; @@ -435,8 +431,6 @@ static int ocores_i2c_probe(struct platform_device *pdev) if (pdata) { for (i = 0; i < pdata->num_devices; i++) i2c_new_device(&i2c->adap, pdata->devices + i); - } else { - of_i2c_register_devices(&i2c->adap); } return 0; @@ -456,7 +450,7 @@ static int ocores_i2c_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int ocores_i2c_suspend(struct device *dev) { struct ocores_i2c *i2c = dev_get_drvdata(dev); diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c index 956fe32..b929ba2 100644 --- a/drivers/i2c/busses/i2c-octeon.c +++ b/drivers/i2c/busses/i2c-octeon.c @@ -15,7 +15,6 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_i2c.h> #include <linux/delay.h> #include <linux/sched.h> #include <linux/slab.h> @@ -599,8 +598,6 @@ static int octeon_i2c_probe(struct platform_device *pdev) } dev_info(i2c->dev, "version %s\n", DRV_VERSION); - of_i2c_register_devices(&i2c->adap); - return 0; out: diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index e02f9e3..90dcc2e 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -38,12 +38,10 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_i2c.h> #include <linux/of_device.h> #include <linux/slab.h> #include <linux/i2c-omap.h> #include <linux/pm_runtime.h> -#include <linux/pinctrl/consumer.h> /* I2C controller revisions */ #define OMAP_I2C_OMAP1_REV_2 0x20 @@ -180,6 +178,8 @@ enum { #define I2C_OMAP_ERRATA_I207 (1 << 0) #define I2C_OMAP_ERRATA_I462 (1 << 1) +#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF + struct omap_i2c_dev { spinlock_t lock; /* IRQ synchronization */ struct device *dev; @@ -193,6 +193,7 @@ struct omap_i2c_dev { long latency); u32 speed; /* Speed of bus in kHz */ u32 flags; + u16 scheme; u16 cmd_err; u8 *buf; u8 *regs; @@ -213,8 +214,6 @@ struct omap_i2c_dev { u16 syscstate; u16 westate; u16 errata; - - struct pinctrl *pins; }; static const u8 reg_map_ip_v1[] = { @@ -267,13 +266,13 @@ static const u8 reg_map_ip_v2[] = { static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, int reg, u16 val) { - __raw_writew(val, i2c_dev->base + + writew_relaxed(val, i2c_dev->base + (i2c_dev->regs[reg] << i2c_dev->reg_shift)); } static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) { - return __raw_readw(i2c_dev->base + + return readw_relaxed(i2c_dev->base + (i2c_dev->regs[reg] << i2c_dev->reg_shift)); } @@ -544,7 +543,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); - INIT_COMPLETION(dev->cmd_complete); + reinit_completion(&dev->cmd_complete); dev->cmd_err = 0; w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; @@ -615,11 +614,10 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, if (dev->cmd_err & OMAP_I2C_STAT_NACK) { if (msg->flags & I2C_M_IGNORE_NAK) return 0; - if (stop) { - w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); - w |= OMAP_I2C_CON_STP; - omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); - } + + w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); + w |= OMAP_I2C_CON_STP; + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); return -EREMOTEIO; } return -EIO; @@ -941,6 +939,9 @@ omap_i2c_isr_thread(int this_irq, void *dev_id) /* * ProDB0017052: Clear ARDY bit twice */ + if (stat & OMAP_I2C_STAT_ARDY) + omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY); + if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | @@ -1036,6 +1037,20 @@ static const struct i2c_algorithm omap_i2c_algo = { }; #ifdef CONFIG_OF +static struct omap_i2c_bus_platform_data omap2420_pdata = { + .rev = OMAP_I2C_IP_VERSION_1, + .flags = OMAP_I2C_FLAG_NO_FIFO | + OMAP_I2C_FLAG_SIMPLE_CLOCK | + OMAP_I2C_FLAG_16BIT_DATA_REG | + OMAP_I2C_FLAG_BUS_SHIFT_2, +}; + +static struct omap_i2c_bus_platform_data omap2430_pdata = { + .rev = OMAP_I2C_IP_VERSION_1, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | + OMAP_I2C_FLAG_FORCE_19200_INT_CLK, +}; + static struct omap_i2c_bus_platform_data omap3_pdata = { .rev = OMAP_I2C_IP_VERSION_1, .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, @@ -1054,6 +1069,14 @@ static const struct of_device_id omap_i2c_of_match[] = { .compatible = "ti,omap3-i2c", .data = &omap3_pdata, }, + { + .compatible = "ti,omap2430-i2c", + .data = &omap2430_pdata, + }, + { + .compatible = "ti,omap2420-i2c", + .data = &omap2420_pdata, + }, { }, }; MODULE_DEVICE_TABLE(of, omap_i2c_of_match); @@ -1076,20 +1099,13 @@ omap_i2c_probe(struct platform_device *pdev) struct i2c_adapter *adap; struct resource *mem; const struct omap_i2c_bus_platform_data *pdata = - pdev->dev.platform_data; + dev_get_platdata(&pdev->dev); struct device_node *node = pdev->dev.of_node; const struct of_device_id *match; int irq; int r; u32 rev; - u16 minor, major, scheme; - - /* NOTE: driver uses the static register mapping */ - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(&pdev->dev, "no mem resource?\n"); - return -ENODEV; - } + u16 minor, major; irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -1103,6 +1119,7 @@ omap_i2c_probe(struct platform_device *pdev) return -ENOMEM; } + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dev->base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(dev->base)) return PTR_ERR(dev->base); @@ -1123,16 +1140,6 @@ omap_i2c_probe(struct platform_device *pdev) dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; } - dev->pins = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(dev->pins)) { - if (PTR_ERR(dev->pins) == -EPROBE_DEFER) - return -EPROBE_DEFER; - - dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n", - PTR_ERR(dev->pins)); - dev->pins = NULL; - } - dev->dev = &pdev->dev; dev->irq = irq; @@ -1155,12 +1162,12 @@ omap_i2c_probe(struct platform_device *pdev) * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. * Also since the omap_i2c_read_reg uses reg_map_ip_* a - * raw_readw is done. + * readw_relaxed is done. */ - rev = __raw_readw(dev->base + 0x04); + rev = readw_relaxed(dev->base + 0x04); - scheme = OMAP_I2C_SCHEME(rev); - switch (scheme) { + dev->scheme = OMAP_I2C_SCHEME(rev); + switch (dev->scheme) { case OMAP_I2C_SCHEME_0: dev->regs = (u8 *)reg_map_ip_v1; dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); @@ -1248,8 +1255,6 @@ omap_i2c_probe(struct platform_device *pdev) dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr, major, minor, dev->speed); - of_i2c_register_devices(adap); - pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -1289,7 +1294,11 @@ static int omap_i2c_runtime_suspend(struct device *dev) _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); - omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); + if (_dev->scheme == OMAP_I2C_SCHEME_0) + omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); + else + omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, + OMAP_I2C_IP_V2_INTERRUPTS_MASK); if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ diff --git a/drivers/i2c/busses/i2c-pca-platform.c b/drivers/i2c/busses/i2c-pca-platform.c index aa00df1..39e2755 100644 --- a/drivers/i2c/busses/i2c-pca-platform.c +++ b/drivers/i2c/busses/i2c-pca-platform.c @@ -136,7 +136,7 @@ static int i2c_pca_pf_probe(struct platform_device *pdev) struct i2c_pca_pf_data *i2c; struct resource *res; struct i2c_pca9564_pf_platform_data *platform_data = - pdev->dev.platform_data; + dev_get_platdata(&pdev->dev); int ret = 0; int irq; diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 39ab78c..a028617 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -22,7 +22,7 @@ Intel PIIX4, 440MX Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 - AMD Hudson-2 + AMD Hudson-2, CZ SMSC Victory66 Note: we assume there can only be one device, with one or more @@ -231,11 +231,11 @@ static int piix4_setup(struct pci_dev *PIIX4_dev, } static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, - const struct pci_device_id *id) + const struct pci_device_id *id, u8 aux) { unsigned short piix4_smba; unsigned short smba_idx = 0xcd6; - u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c; + u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en; /* SB800 and later SMBus does not support forcing address */ if (force || force_addr) { @@ -245,6 +245,8 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, } /* Determine the address of the SMBus areas */ + smb_en = (aux) ? 0x28 : 0x2c; + if (!request_region(smba_idx, 2, "smba_idx")) { dev_err(&PIIX4_dev->dev, "SMBus base address index region " "0x%x already in use!\n", smba_idx); @@ -272,6 +274,13 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, return -EBUSY; } + /* Aux SMBus does not support IRQ information */ + if (aux) { + dev_info(&PIIX4_dev->dev, + "SMBus Host Controller at 0x%x\n", piix4_smba); + return piix4_smba; + } + /* Request the SMBus I2C bus config region */ if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " @@ -522,6 +531,7 @@ static DEFINE_PCI_DEVICE_TABLE(piix4_ids) = { { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x790b) }, { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4) }, { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, @@ -596,7 +606,7 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) dev->revision >= 0x40) || dev->vendor == PCI_VENDOR_ID_AMD) /* base address location etc changed in SB800 */ - retval = piix4_setup_sb800(dev, id); + retval = piix4_setup_sb800(dev, id, 0); else retval = piix4_setup(dev, id); @@ -610,17 +620,29 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) return retval; /* Check for auxiliary SMBus on some AMD chipsets */ + retval = -ENODEV; + if (dev->vendor == PCI_VENDOR_ID_ATI && - dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && - dev->revision < 0x40) { - retval = piix4_setup_aux(dev, id, 0x58); - if (retval > 0) { - /* Try to add the aux adapter if it exists, - * piix4_add_adapter will clean up if this fails */ - piix4_add_adapter(dev, retval, &piix4_aux_adapter); + dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { + if (dev->revision < 0x40) { + retval = piix4_setup_aux(dev, id, 0x58); + } else { + /* SB800 added aux bus too */ + retval = piix4_setup_sb800(dev, id, 1); } } + if (dev->vendor == PCI_VENDOR_ID_AMD && + dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { + retval = piix4_setup_sb800(dev, id, 1); + } + + if (retval > 0) { + /* Try to add the aux adapter if it exists, + * piix4_add_adapter will clean up if this fails */ + piix4_add_adapter(dev, retval, &piix4_aux_adapter); + } + return 0; } diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c index 5f39c6d..c9a352f 100644 --- a/drivers/i2c/busses/i2c-pnx.c +++ b/drivers/i2c/busses/i2c-pnx.c @@ -23,7 +23,7 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/slab.h> -#include <linux/of_i2c.h> +#include <linux/of.h> #define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */ #define I2C_PNX_SPEED_KHZ_DEFAULT 100 @@ -595,7 +595,7 @@ static struct i2c_algorithm pnx_algorithm = { .functionality = i2c_pnx_func, }; -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int i2c_pnx_controller_suspend(struct device *dev) { struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev); @@ -727,7 +727,8 @@ static int i2c_pnx_probe(struct platform_device *pdev) alg_data->irq = platform_get_irq(pdev, 0); if (alg_data->irq < 0) { dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n"); - goto out_irq; + ret = alg_data->irq; + goto out_clock; } ret = request_irq(alg_data->irq, i2c_pnx_interrupt, 0, pdev->name, alg_data); @@ -741,8 +742,6 @@ static int i2c_pnx_probe(struct platform_device *pdev) goto out_irq; } - of_i2c_register_devices(&alg_data->adapter); - dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", alg_data->adapter.name, res->start, alg_data->irq); diff --git a/drivers/i2c/busses/i2c-powermac.c b/drivers/i2c/busses/i2c-powermac.c index 8dc90da..8c87f4a 100644 --- a/drivers/i2c/busses/i2c-powermac.c +++ b/drivers/i2c/busses/i2c-powermac.c @@ -27,6 +27,7 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/platform_device.h> +#include <linux/of_irq.h> #include <asm/prom.h> #include <asm/pmac_low_i2c.h> @@ -398,7 +399,7 @@ static void i2c_powermac_register_devices(struct i2c_adapter *adap, static int i2c_powermac_probe(struct platform_device *dev) { - struct pmac_i2c_bus *bus = dev->dev.platform_data; + struct pmac_i2c_bus *bus = dev_get_platdata(&dev->dev); struct device_node *parent = NULL; struct i2c_adapter *adapter; const char *basename; @@ -440,22 +441,24 @@ static int i2c_powermac_probe(struct platform_device *dev) adapter->algo = &i2c_powermac_algorithm; i2c_set_adapdata(adapter, bus); adapter->dev.parent = &dev->dev; - adapter->dev.of_node = dev->dev.of_node; + + /* Clear of_node to skip automatic registration of i2c child nodes */ + adapter->dev.of_node = NULL; rc = i2c_add_adapter(adapter); if (rc) { printk(KERN_ERR "i2c-powermac: Adapter %s registration " "failed\n", adapter->name); memset(adapter, 0, sizeof(*adapter)); + return rc; } printk(KERN_INFO "PowerMac i2c bus %s registered\n", adapter->name); - /* Cannot use of_i2c_register_devices() due to Apple device-tree - * funkyness - */ + /* Use custom child registration due to Apple device-tree funkyness */ + adapter->dev.of_node = dev->dev.of_node; i2c_powermac_register_devices(adapter, bus); - return rc; + return 0; } static struct platform_driver i2c_powermac_driver = { diff --git a/drivers/i2c/busses/i2c-puv3.c b/drivers/i2c/busses/i2c-puv3.c index 37a84c8..ac80199 100644 --- a/drivers/i2c/busses/i2c-puv3.c +++ b/drivers/i2c/busses/i2c-puv3.c @@ -245,7 +245,7 @@ static int puv3_i2c_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int puv3_i2c_suspend(struct device *dev) { int poll_count; diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index ea6d45d..bbe6dfb 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -31,7 +31,6 @@ #include <linux/i2c-pxa.h> #include <linux/of.h> #include <linux/of_device.h> -#include <linux/of_i2c.h> #include <linux/platform_device.h> #include <linux/err.h> #include <linux/clk.h> @@ -110,6 +109,8 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); #define ICR_SADIE (1 << 13) /* slave address detected int enable */ #define ICR_UR (1 << 14) /* unit reset */ #define ICR_FM (1 << 15) /* fast mode */ +#define ICR_HS (1 << 16) /* High Speed mode */ +#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */ #define ISR_RWM (1 << 0) /* read/write mode */ #define ISR_ACKNAK (1 << 1) /* ack/nak status */ @@ -155,6 +156,10 @@ struct pxa_i2c { int irq; unsigned int use_pio :1; unsigned int fast_mode :1; + unsigned int high_mode:1; + unsigned char master_code; + unsigned long rate; + bool highmode_enter; }; #define _IBMR(i2c) ((i2c)->reg_ibmr) @@ -459,6 +464,7 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c) /* set control register values */ writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c)); + writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c)); #ifdef CONFIG_I2C_PXA_SLAVE dev_info(&i2c->adap.dev, "Enabling slave mode\n"); @@ -680,6 +686,34 @@ static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) return 0; } +/* + * PXA I2C send master code + * 1. Load master code to IDBR and send it. + * Note for HS mode, set ICR [GPIOEN]. + * 2. Wait until win arbitration. + */ +static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c) +{ + u32 icr; + long timeout; + + spin_lock_irq(&i2c->lock); + i2c->highmode_enter = true; + writel(i2c->master_code, _IDBR(i2c)); + + icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); + icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE; + writel(icr, _ICR(i2c)); + + spin_unlock_irq(&i2c->lock); + timeout = wait_event_timeout(i2c->wait, + i2c->highmode_enter == false, HZ * 1); + + i2c->highmode_enter = false; + + return (timeout == 0) ? I2C_RETRY : 0; +} + static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) { @@ -743,6 +777,14 @@ static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) goto out; } + if (i2c->high_mode) { + ret = i2c_pxa_send_mastercode(i2c); + if (ret) { + dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n"); + goto out; + } + } + spin_lock_irq(&i2c->lock); i2c->msg = msg; @@ -990,11 +1032,14 @@ static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) i2c_pxa_slave_txempty(i2c, isr); if (isr & ISR_IRF) i2c_pxa_slave_rxfull(i2c, isr); - } else if (i2c->msg) { + } else if (i2c->msg && (!i2c->highmode_enter)) { if (isr & ISR_ITE) i2c_pxa_irq_txempty(i2c, isr); if (isr & ISR_IRF) i2c_pxa_irq_rxfull(i2c, isr); + } else if ((isr & ISR_ITE) && i2c->highmode_enter) { + i2c->highmode_enter = false; + wake_up(&i2c->wait); } else { i2c_pxa_scream_blue_murder(i2c, "spurious irq"); } @@ -1072,20 +1117,25 @@ static int i2c_pxa_probe_pdata(struct platform_device *pdev, struct pxa_i2c *i2c, enum pxa_i2c_types *i2c_types) { - struct i2c_pxa_platform_data *plat = pdev->dev.platform_data; + struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev); const struct platform_device_id *id = platform_get_device_id(pdev); *i2c_types = id->driver_data; if (plat) { i2c->use_pio = plat->use_pio; i2c->fast_mode = plat->fast_mode; + i2c->high_mode = plat->high_mode; + i2c->master_code = plat->master_code; + if (!i2c->master_code) + i2c->master_code = 0xe; + i2c->rate = plat->rate; } return 0; } static int i2c_pxa_probe(struct platform_device *dev) { - struct i2c_pxa_platform_data *plat = dev->dev.platform_data; + struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev); enum pxa_i2c_types i2c_type; struct pxa_i2c *i2c; struct resource *res = NULL; @@ -1151,6 +1201,7 @@ static int i2c_pxa_probe(struct platform_device *dev) i2c->irq = irq; i2c->slave_addr = I2C_PXA_SLAVE_ADDR; + i2c->highmode_enter = false; if (plat) { #ifdef CONFIG_I2C_PXA_SLAVE @@ -1160,7 +1211,17 @@ static int i2c_pxa_probe(struct platform_device *dev) i2c->adap.class = plat->class; } - clk_enable(i2c->clk); + if (i2c->high_mode) { + if (i2c->rate) { + clk_set_rate(i2c->clk, i2c->rate); + pr_info("i2c: <%s> set rate to %ld\n", + i2c->adap.name, clk_get_rate(i2c->clk)); + } else + pr_warn("i2c: <%s> clock rate not set\n", + i2c->adap.name); + } + + clk_prepare_enable(i2c->clk); if (i2c->use_pio) { i2c->adap.algo = &i2c_pxa_pio_algorithm; @@ -1185,7 +1246,6 @@ static int i2c_pxa_probe(struct platform_device *dev) printk(KERN_INFO "I2C: Failed to add bus\n"); goto eadapt; } - of_i2c_register_devices(&i2c->adap); platform_set_drvdata(dev, i2c); @@ -1202,7 +1262,7 @@ eadapt: if (!i2c->use_pio) free_irq(irq, i2c); ereqirq: - clk_disable(i2c->clk); + clk_disable_unprepare(i2c->clk); iounmap(i2c->reg_base); eremap: clk_put(i2c->clk); @@ -1221,7 +1281,7 @@ static int i2c_pxa_remove(struct platform_device *dev) if (!i2c->use_pio) free_irq(i2c->irq, i2c); - clk_disable(i2c->clk); + clk_disable_unprepare(i2c->clk); clk_put(i2c->clk); iounmap(i2c->reg_base); diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c index 4ba4a95..2c2fd7c 100644 --- a/drivers/i2c/busses/i2c-rcar.c +++ b/drivers/i2c/busses/i2c-rcar.c @@ -33,6 +33,7 @@ #include <linux/i2c/i2c-rcar.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> @@ -101,6 +102,11 @@ enum { #define ID_ARBLOST (1 << 3) #define ID_NACK (1 << 4) +enum rcar_i2c_type { + I2C_RCAR_GEN1, + I2C_RCAR_GEN2, +}; + struct rcar_i2c_priv { void __iomem *io; struct i2c_adapter adap; @@ -113,6 +119,7 @@ struct rcar_i2c_priv { int irq; u32 icccr; u32 flags; + enum rcar_i2c_type devtype; }; #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) @@ -220,13 +227,27 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, u32 bus_speed, struct device *dev) { - struct clk *clkp = clk_get(NULL, "peripheral_clk"); + struct clk *clkp = clk_get(dev, NULL); u32 scgd, cdf; u32 round, ick; u32 scl; + u32 cdf_width; + unsigned long rate; + + if (IS_ERR(clkp)) { + dev_err(dev, "couldn't get clock\n"); + return PTR_ERR(clkp); + } - if (!clkp) { - dev_err(dev, "there is no peripheral_clk\n"); + switch (priv->devtype) { + case I2C_RCAR_GEN1: + cdf_width = 2; + break; + case I2C_RCAR_GEN2: + cdf_width = 3; + break; + default: + dev_err(dev, "device type error\n"); return -EIO; } @@ -245,15 +266,14 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, * clkp : peripheral_clk * F[] : integer up-valuation */ - for (cdf = 0; cdf < 4; cdf++) { - ick = clk_get_rate(clkp) / (1 + cdf); - if (ick < 20000000) - goto ick_find; + rate = clk_get_rate(clkp); + cdf = rate / 20000000; + if (cdf >= 1 << cdf_width) { + dev_err(dev, "Input clock %lu too high\n", rate); + return -EIO; } - dev_err(dev, "there is no best CDF\n"); - return -EIO; + ick = rate / (cdf + 1); -ick_find: /* * it is impossible to calculate large scale * number on u32. separate it @@ -271,6 +291,12 @@ ick_find: * * Calculation result (= SCL) should be less than * bus_speed for hardware safety + * + * We could use something along the lines of + * div = ick / (bus_speed + 1) + 1; + * scgd = (div - 20 - round + 7) / 8; + * scl = ick / (20 + (scgd * 8) + round); + * (not fully verified) but that would get pretty involved */ for (scgd = 0; scgd < 0x40; scgd++) { scl = ick / (20 + (scgd * 8) + round); @@ -287,7 +313,7 @@ scgd_find: /* * keep icccr value */ - priv->icccr = (scgd << 2 | cdf); + priv->icccr = scgd << cdf_width | cdf; return 0; } @@ -613,9 +639,18 @@ static const struct i2c_algorithm rcar_i2c_algo = { .functionality = rcar_i2c_func, }; +static const struct of_device_id rcar_i2c_dt_ids[] = { + { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, + { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, + { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, + { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, + {}, +}; +MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); + static int rcar_i2c_probe(struct platform_device *pdev) { - struct i2c_rcar_platform_data *pdata = pdev->dev.platform_data; + struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev); struct rcar_i2c_priv *priv; struct i2c_adapter *adap; struct resource *res; @@ -623,12 +658,6 @@ static int rcar_i2c_probe(struct platform_device *pdev) u32 bus_speed; int ret; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "no mmio resources\n"); - return -ENODEV; - } - priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); if (!priv) { dev_err(dev, "no mem for private data\n"); @@ -636,12 +665,21 @@ static int rcar_i2c_probe(struct platform_device *pdev) } bus_speed = 100000; /* default 100 kHz */ - if (pdata && pdata->bus_speed) + ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed); + if (ret < 0 && pdata && pdata->bus_speed) bus_speed = pdata->bus_speed; + + if (pdev->dev.of_node) + priv->devtype = (long)of_match_device(rcar_i2c_dt_ids, + dev)->data; + else + priv->devtype = platform_get_device_id(pdev)->driver_data; + ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); if (ret < 0) return ret; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->io = devm_ioremap_resource(dev, res); if (IS_ERR(priv->io)) return PTR_ERR(priv->io); @@ -656,6 +694,7 @@ static int rcar_i2c_probe(struct platform_device *pdev) adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; adap->retries = 3; adap->dev.parent = dev; + adap->dev.of_node = dev->of_node; i2c_set_adapdata(adap, priv); strlcpy(adap->name, pdev->name, sizeof(adap->name)); @@ -691,13 +730,23 @@ static int rcar_i2c_remove(struct platform_device *pdev) return 0; } +static struct platform_device_id rcar_i2c_id_table[] = { + { "i2c-rcar", I2C_RCAR_GEN1 }, + { "i2c-rcar_gen1", I2C_RCAR_GEN1 }, + { "i2c-rcar_gen2", I2C_RCAR_GEN2 }, + {}, +}; +MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table); + static struct platform_driver rcar_i2c_driver = { .driver = { .name = "i2c-rcar", .owner = THIS_MODULE, + .of_match_table = rcar_i2c_dt_ids, }, .probe = rcar_i2c_probe, .remove = rcar_i2c_remove, + .id_table = rcar_i2c_id_table, }; module_platform_driver(rcar_i2c_driver); diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index cab1c91..bf8fb94 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -36,7 +36,7 @@ #include <linux/cpufreq.h> #include <linux/slab.h> #include <linux/io.h> -#include <linux/of_i2c.h> +#include <linux/of.h> #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> @@ -1033,7 +1033,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev) int ret; if (!pdev->dev.of_node) { - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (!pdata) { dev_err(&pdev->dev, "no platform data\n"); return -EINVAL; @@ -1154,7 +1154,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev) return ret; } - of_i2c_register_devices(&i2c->adap); platform_set_drvdata(pdev, i2c); pm_runtime_enable(&pdev->dev); @@ -1180,8 +1179,6 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&i2c->adap); - clk_disable_unprepare(i2c->clk); - if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) s3c24xx_i2c_dt_gpio_free(i2c); diff --git a/drivers/i2c/busses/i2c-s6000.c b/drivers/i2c/busses/i2c-s6000.c index 7c1ca5a..dd186a0 100644 --- a/drivers/i2c/busses/i2c-s6000.c +++ b/drivers/i2c/busses/i2c-s6000.c @@ -290,8 +290,9 @@ static int s6i2c_probe(struct platform_device *dev) clock = 0; bus_num = -1; - if (dev->dev.platform_data) { - struct s6_i2c_platform_data *pdata = dev->dev.platform_data; + if (dev_get_platdata(&dev->dev)) { + struct s6_i2c_platform_data *pdata = + dev_get_platdata(&dev->dev); bus_num = pdata->bus_num; clock = pdata->clock; } diff --git a/drivers/i2c/busses/i2c-scmi.c b/drivers/i2c/busses/i2c-scmi.c index c447e8d..5992355 100644 --- a/drivers/i2c/busses/i2c-scmi.c +++ b/drivers/i2c/busses/i2c-scmi.c @@ -223,7 +223,7 @@ acpi_smbus_cmi_access(struct i2c_adapter *adap, u16 addr, unsigned short flags, goto out; obj = pkg->package.elements + 1; - if (obj == NULL || obj->type != ACPI_TYPE_INTEGER) { + if (obj->type != ACPI_TYPE_INTEGER) { ACPI_ERROR((AE_INFO, "Invalid argument type")); result = -EIO; goto out; @@ -235,7 +235,7 @@ acpi_smbus_cmi_access(struct i2c_adapter *adap, u16 addr, unsigned short flags, case I2C_SMBUS_BYTE: case I2C_SMBUS_BYTE_DATA: case I2C_SMBUS_WORD_DATA: - if (obj == NULL || obj->type != ACPI_TYPE_INTEGER) { + if (obj->type != ACPI_TYPE_INTEGER) { ACPI_ERROR((AE_INFO, "Invalid argument type")); result = -EIO; goto out; @@ -246,7 +246,7 @@ acpi_smbus_cmi_access(struct i2c_adapter *adap, u16 addr, unsigned short flags, data->byte = obj->integer.value; break; case I2C_SMBUS_BLOCK_DATA: - if (obj == NULL || obj->type != ACPI_TYPE_BUFFER) { + if (obj->type != ACPI_TYPE_BUFFER) { ACPI_ERROR((AE_INFO, "Invalid argument type")); result = -EIO; goto out; diff --git a/drivers/i2c/busses/i2c-sh7760.c b/drivers/i2c/busses/i2c-sh7760.c index 5351a2f..5e8f136 100644 --- a/drivers/i2c/busses/i2c-sh7760.c +++ b/drivers/i2c/busses/i2c-sh7760.c @@ -437,7 +437,7 @@ static int sh7760_i2c_probe(struct platform_device *pdev) struct cami2c *id; int ret; - pd = pdev->dev.platform_data; + pd = dev_get_platdata(&pdev->dev); if (!pd) { dev_err(&pdev->dev, "no platform_data!\n"); ret = -ENODEV; diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c index debf745..1d79585 100644 --- a/drivers/i2c/busses/i2c-sh_mobile.c +++ b/drivers/i2c/busses/i2c-sh_mobile.c @@ -27,7 +27,6 @@ #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/i2c.h> -#include <linux/of_i2c.h> #include <linux/err.h> #include <linux/pm_runtime.h> #include <linux/clk.h> @@ -236,7 +235,7 @@ static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) int offset; /* Get clock rate after clock is enabled */ - clk_enable(pd->clk); + clk_prepare_enable(pd->clk); i2c_clk_khz = clk_get_rate(pd->clk) / 1000; i2c_clk_khz /= pd->clks_per_count; @@ -271,14 +270,14 @@ static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) pd->icic &= ~ICIC_ICCHB8; out: - clk_disable(pd->clk); + clk_disable_unprepare(pd->clk); } static void activate_ch(struct sh_mobile_i2c_data *pd) { /* Wake up device and enable clock */ pm_runtime_get_sync(pd->dev); - clk_enable(pd->clk); + clk_prepare_enable(pd->clk); /* Enable channel and configure rx ack */ iic_set_clr(pd, ICCR, ICCR_ICE, 0); @@ -301,7 +300,7 @@ static void deactivate_ch(struct sh_mobile_i2c_data *pd) iic_set_clr(pd, ICCR, 0, ICCR_ICE); /* Disable clock and mark device as idle */ - clk_disable(pd->clk); + clk_disable_unprepare(pd->clk); pm_runtime_put_sync(pd->dev); } @@ -658,7 +657,7 @@ static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook) static int sh_mobile_i2c_probe(struct platform_device *dev) { - struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data; + struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); struct sh_mobile_i2c_data *pd; struct i2c_adapter *adap; struct resource *res; @@ -758,7 +757,6 @@ static int sh_mobile_i2c_probe(struct platform_device *dev) "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n", adap->nr, pd->bus_speed, pd->iccl, pd->icch); - of_i2c_register_devices(adap); return 0; err_all: diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c index a63c7d5..6784f7f 100644 --- a/drivers/i2c/busses/i2c-sirf.c +++ b/drivers/i2c/busses/i2c-sirf.c @@ -12,7 +12,6 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/i2c.h> -#include <linux/of_i2c.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> @@ -65,6 +64,8 @@ #define SIRFSOC_I2C_START BIT(7) #define SIRFSOC_I2C_DEFAULT_SPEED 100000 +#define SIRFSOC_I2C_ERR_NOACK 1 +#define SIRFSOC_I2C_ERR_TIMEOUT 2 struct sirfsoc_i2c { void __iomem *base; @@ -143,14 +144,24 @@ static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id) if (i2c_stat & SIRFSOC_I2C_STAT_ERR) { /* Error conditions */ - siic->err_status = 1; + siic->err_status = SIRFSOC_I2C_ERR_NOACK; writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); if (i2c_stat & SIRFSOC_I2C_STAT_NACK) - dev_err(&siic->adapter.dev, "ACK not received\n"); + dev_dbg(&siic->adapter.dev, "ACK not received\n"); else dev_err(&siic->adapter.dev, "I2C error\n"); + /* + * Due to hardware ANOMALY, we need to reset I2C earlier after + * we get NOACK while accessing non-existing clients, otherwise + * we will get errors even we access existing clients later + */ + writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, + siic->base + SIRFSOC_I2C_CTRL); + while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) + cpu_relax(); + complete(&siic->done); } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) { /* CMD buffer execution complete */ @@ -183,6 +194,10 @@ static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic, if (msg->flags & I2C_M_RD) addr |= 1; + /* Reverse direction bit */ + if (msg->flags & I2C_M_REV_DIR_ADDR) + addr ^= 1; + writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); } @@ -191,7 +206,6 @@ static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg) u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); /* timeout waiting for the xfer to finish or fail */ int timeout = msecs_to_jiffies((msg->len + 1) * 50); - int ret = 0; i2c_sirfsoc_set_address(siic, msg); @@ -200,7 +214,7 @@ static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg) i2c_sirfsoc_queue_cmd(siic); if (wait_for_completion_timeout(&siic->done, timeout) == 0) { - siic->err_status = 1; + siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT; dev_err(&siic->adapter.dev, "Transfer timeout\n"); } @@ -208,16 +222,14 @@ static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg) siic->base + SIRFSOC_I2C_CTRL); writel(0, siic->base + SIRFSOC_I2C_CMD_START); - if (siic->err_status) { + /* i2c control doesn't response, reset it */ + if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) { writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) cpu_relax(); - - ret = -EIO; } - - return ret; + return siic->err_status ? -EAGAIN : 0; } static u32 i2c_sirfsoc_func(struct i2c_adapter *adap) @@ -321,6 +333,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev) adap->algo = &i2c_sirfsoc_algo; adap->algo_data = siic; + adap->retries = 3; adap->dev.of_node = pdev->dev.of_node; adap->dev.parent = &pdev->dev; @@ -348,7 +361,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev) if (bitrate < 100000) regval = - (2 * ctrl_speed) / (2 * bitrate * 11); + (2 * ctrl_speed) / (bitrate * 11); else regval = ctrl_speed / (bitrate * 5); @@ -366,8 +379,6 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev) clk_disable(clk); - of_i2c_register_devices(adap); - dev_info(&pdev->dev, " I2C adapter ready to operate\n"); return 0; @@ -416,6 +427,8 @@ static int i2c_sirfsoc_resume(struct device *dev) clk_enable(siic->clk); writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); + while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) + cpu_relax(); writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, siic->base + SIRFSOC_I2C_CTRL); writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL); diff --git a/drivers/i2c/busses/i2c-st.c b/drivers/i2c/busses/i2c-st.c new file mode 100644 index 0000000..9cf715d --- /dev/null +++ b/drivers/i2c/busses/i2c-st.c @@ -0,0 +1,872 @@ +/* + * Copyright (C) 2013 STMicroelectronics + * + * I2C master mode controller driver, used in STMicroelectronics devices. + * + * Author: Maxime Coquelin <maxime.coquelin@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> + +/* SSC registers */ +#define SSC_BRG 0x000 +#define SSC_TBUF 0x004 +#define SSC_RBUF 0x008 +#define SSC_CTL 0x00C +#define SSC_IEN 0x010 +#define SSC_STA 0x014 +#define SSC_I2C 0x018 +#define SSC_SLAD 0x01C +#define SSC_REP_START_HOLD 0x020 +#define SSC_START_HOLD 0x024 +#define SSC_REP_START_SETUP 0x028 +#define SSC_DATA_SETUP 0x02C +#define SSC_STOP_SETUP 0x030 +#define SSC_BUS_FREE 0x034 +#define SSC_TX_FSTAT 0x038 +#define SSC_RX_FSTAT 0x03C +#define SSC_PRE_SCALER_BRG 0x040 +#define SSC_CLR 0x080 +#define SSC_NOISE_SUPP_WIDTH 0x100 +#define SSC_PRSCALER 0x104 +#define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108 +#define SSC_PRSCALER_DATAOUT 0x10c + +/* SSC Control */ +#define SSC_CTL_DATA_WIDTH_9 0x8 +#define SSC_CTL_DATA_WIDTH_MSK 0xf +#define SSC_CTL_BM 0xf +#define SSC_CTL_HB BIT(4) +#define SSC_CTL_PH BIT(5) +#define SSC_CTL_PO BIT(6) +#define SSC_CTL_SR BIT(7) +#define SSC_CTL_MS BIT(8) +#define SSC_CTL_EN BIT(9) +#define SSC_CTL_LPB BIT(10) +#define SSC_CTL_EN_TX_FIFO BIT(11) +#define SSC_CTL_EN_RX_FIFO BIT(12) +#define SSC_CTL_EN_CLST_RX BIT(13) + +/* SSC Interrupt Enable */ +#define SSC_IEN_RIEN BIT(0) +#define SSC_IEN_TIEN BIT(1) +#define SSC_IEN_TEEN BIT(2) +#define SSC_IEN_REEN BIT(3) +#define SSC_IEN_PEEN BIT(4) +#define SSC_IEN_AASEN BIT(6) +#define SSC_IEN_STOPEN BIT(7) +#define SSC_IEN_ARBLEN BIT(8) +#define SSC_IEN_NACKEN BIT(10) +#define SSC_IEN_REPSTRTEN BIT(11) +#define SSC_IEN_TX_FIFO_HALF BIT(12) +#define SSC_IEN_RX_FIFO_HALF_FULL BIT(14) + +/* SSC Status */ +#define SSC_STA_RIR BIT(0) +#define SSC_STA_TIR BIT(1) +#define SSC_STA_TE BIT(2) +#define SSC_STA_RE BIT(3) +#define SSC_STA_PE BIT(4) +#define SSC_STA_CLST BIT(5) +#define SSC_STA_AAS BIT(6) +#define SSC_STA_STOP BIT(7) +#define SSC_STA_ARBL BIT(8) +#define SSC_STA_BUSY BIT(9) +#define SSC_STA_NACK BIT(10) +#define SSC_STA_REPSTRT BIT(11) +#define SSC_STA_TX_FIFO_HALF BIT(12) +#define SSC_STA_TX_FIFO_FULL BIT(13) +#define SSC_STA_RX_FIFO_HALF BIT(14) + +/* SSC I2C Control */ +#define SSC_I2C_I2CM BIT(0) +#define SSC_I2C_STRTG BIT(1) +#define SSC_I2C_STOPG BIT(2) +#define SSC_I2C_ACKG BIT(3) +#define SSC_I2C_AD10 BIT(4) +#define SSC_I2C_TXENB BIT(5) +#define SSC_I2C_REPSTRTG BIT(11) +#define SSC_I2C_SLAVE_DISABLE BIT(12) + +/* SSC Tx FIFO Status */ +#define SSC_TX_FSTAT_STATUS 0x07 + +/* SSC Rx FIFO Status */ +#define SSC_RX_FSTAT_STATUS 0x07 + +/* SSC Clear bit operation */ +#define SSC_CLR_SSCAAS BIT(6) +#define SSC_CLR_SSCSTOP BIT(7) +#define SSC_CLR_SSCARBL BIT(8) +#define SSC_CLR_NACK BIT(10) +#define SSC_CLR_REPSTRT BIT(11) + +/* SSC Clock Prescaler */ +#define SSC_PRSC_VALUE 0x0f + + +#define SSC_TXFIFO_SIZE 0x8 +#define SSC_RXFIFO_SIZE 0x8 + +enum st_i2c_mode { + I2C_MODE_STANDARD, + I2C_MODE_FAST, + I2C_MODE_END, +}; + +/** + * struct st_i2c_timings - per-Mode tuning parameters + * @rate: I2C bus rate + * @rep_start_hold: I2C repeated start hold time requirement + * @rep_start_setup: I2C repeated start set up time requirement + * @start_hold: I2C start hold time requirement + * @data_setup_time: I2C data set up time requirement + * @stop_setup_time: I2C stop set up time requirement + * @bus_free_time: I2C bus free time requirement + * @sda_pulse_min_limit: I2C SDA pulse mini width limit + */ +struct st_i2c_timings { + u32 rate; + u32 rep_start_hold; + u32 rep_start_setup; + u32 start_hold; + u32 data_setup_time; + u32 stop_setup_time; + u32 bus_free_time; + u32 sda_pulse_min_limit; +}; + +/** + * struct st_i2c_client - client specific data + * @addr: 8-bit slave addr, including r/w bit + * @count: number of bytes to be transfered + * @xfered: number of bytes already transferred + * @buf: data buffer + * @result: result of the transfer + * @stop: last I2C msg to be sent, i.e. STOP to be generated + */ +struct st_i2c_client { + u8 addr; + u32 count; + u32 xfered; + u8 *buf; + int result; + bool stop; +}; + +/** + * struct st_i2c_dev - private data of the controller + * @adap: I2C adapter for this controller + * @dev: device for this controller + * @base: virtual memory area + * @complete: completion of I2C message + * @irq: interrupt line for th controller + * @clk: hw ssc block clock + * @mode: I2C mode of the controller. Standard or Fast only supported + * @scl_min_width_us: SCL line minimum pulse width in us + * @sda_min_width_us: SDA line minimum pulse width in us + * @client: I2C transfert information + * @busy: I2C transfer on-going + */ +struct st_i2c_dev { + struct i2c_adapter adap; + struct device *dev; + void __iomem *base; + struct completion complete; + int irq; + struct clk *clk; + int mode; + u32 scl_min_width_us; + u32 sda_min_width_us; + struct st_i2c_client client; + bool busy; +}; + +static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) +{ + writel_relaxed(readl_relaxed(reg) | mask, reg); +} + +static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) +{ + writel_relaxed(readl_relaxed(reg) & ~mask, reg); +} + +/* From I2C Specifications v0.5 */ +static struct st_i2c_timings i2c_timings[] = { + [I2C_MODE_STANDARD] = { + .rate = 100000, + .rep_start_hold = 4000, + .rep_start_setup = 4700, + .start_hold = 4000, + .data_setup_time = 250, + .stop_setup_time = 4000, + .bus_free_time = 4700, + }, + [I2C_MODE_FAST] = { + .rate = 400000, + .rep_start_hold = 600, + .rep_start_setup = 600, + .start_hold = 600, + .data_setup_time = 100, + .stop_setup_time = 600, + .bus_free_time = 1300, + }, +}; + +static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev) +{ + int count, i; + + /* + * Counter only counts up to 7 but fifo size is 8... + * When fifo is full, counter is 0 and RIR bit of status register is + * set + */ + if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) + count = SSC_RXFIFO_SIZE; + else + count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & + SSC_RX_FSTAT_STATUS; + + for (i = 0; i < count; i++) + readl_relaxed(i2c_dev->base + SSC_RBUF); +} + +static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev) +{ + /* + * FIFO needs to be emptied before reseting the IP, + * else the controller raises a BUSY error. + */ + st_i2c_flush_rx_fifo(i2c_dev); + + st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); + st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); +} + +/** + * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings + * @i2c_dev: Controller's private data + */ +static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev) +{ + unsigned long rate; + u32 val, ns_per_clk; + struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode]; + + st_i2c_soft_reset(i2c_dev); + + val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL | + SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP; + writel_relaxed(val, i2c_dev->base + SSC_CLR); + + /* SSC Control register setup */ + val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9; + writel_relaxed(val, i2c_dev->base + SSC_CTL); + + rate = clk_get_rate(i2c_dev->clk); + ns_per_clk = 1000000000 / rate; + + /* Baudrate */ + val = rate / (2 * t->rate); + writel_relaxed(val, i2c_dev->base + SSC_BRG); + + /* Pre-scaler baudrate */ + writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); + + /* Enable I2C mode */ + writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); + + /* Repeated start hold time */ + val = t->rep_start_hold / ns_per_clk; + writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); + + /* Repeated start set up time */ + val = t->rep_start_setup / ns_per_clk; + writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); + + /* Start hold time */ + val = t->start_hold / ns_per_clk; + writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); + + /* Data set up time */ + val = t->data_setup_time / ns_per_clk; + writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); + + /* Stop set up time */ + val = t->stop_setup_time / ns_per_clk; + writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); + + /* Bus free time */ + val = t->bus_free_time / ns_per_clk; + writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); + + /* Prescalers set up */ + val = rate / 10000000; + writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); + writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); + + /* Noise suppression witdh */ + val = i2c_dev->scl_min_width_us * rate / 100000000; + writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); + + /* Noise suppression max output data delay width */ + val = i2c_dev->sda_min_width_us * rate / 100000000; + writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); +} + +static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev) +{ + u32 sta; + int i; + + for (i = 0; i < 10; i++) { + sta = readl_relaxed(i2c_dev->base + SSC_STA); + if (!(sta & SSC_STA_BUSY)) + return 0; + + usleep_range(2000, 4000); + } + + dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta); + + return -EBUSY; +} + +/** + * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO + * @i2c_dev: Controller's private data + * @byte: Data to write in the Tx FIFO + */ +static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte) +{ + u16 tbuf = byte << 1; + + writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); +} + +/** + * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode + * @i2c_dev: Controller's private data + * + * This functions fills the Tx FIFO with I2C transfert buffer when + * in write mode. + */ +static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev) +{ + struct st_i2c_client *c = &i2c_dev->client; + u32 tx_fstat, sta; + int i; + + sta = readl_relaxed(i2c_dev->base + SSC_STA); + if (sta & SSC_STA_TX_FIFO_FULL) + return; + + tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); + tx_fstat &= SSC_TX_FSTAT_STATUS; + + if (c->count < (SSC_TXFIFO_SIZE - tx_fstat)) + i = c->count; + else + i = SSC_TXFIFO_SIZE - tx_fstat; + + for (; i > 0; i--, c->count--, c->buf++) + st_i2c_write_tx_fifo(i2c_dev, *c->buf); +} + +/** + * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode + * @i2c_dev: Controller's private data + * + * This functions fills the Tx FIFO with fixed pattern when + * in read mode to trigger clock. + */ +static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max) +{ + struct st_i2c_client *c = &i2c_dev->client; + u32 tx_fstat, sta; + int i; + + sta = readl_relaxed(i2c_dev->base + SSC_STA); + if (sta & SSC_STA_TX_FIFO_FULL) + return; + + tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); + tx_fstat &= SSC_TX_FSTAT_STATUS; + + if (max < (SSC_TXFIFO_SIZE - tx_fstat)) + i = max; + else + i = SSC_TXFIFO_SIZE - tx_fstat; + + for (; i > 0; i--, c->xfered++) + st_i2c_write_tx_fifo(i2c_dev, 0xff); +} + +static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev) +{ + struct st_i2c_client *c = &i2c_dev->client; + u32 i, sta; + u16 rbuf; + + sta = readl_relaxed(i2c_dev->base + SSC_STA); + if (sta & SSC_STA_RIR) { + i = SSC_RXFIFO_SIZE; + } else { + i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); + i &= SSC_RX_FSTAT_STATUS; + } + + for (; (i > 0) && (c->count > 0); i--, c->count--) { + rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; + *c->buf++ = (u8)rbuf & 0xff; + } + + if (i) { + dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i); + st_i2c_flush_rx_fifo(i2c_dev); + } +} + +/** + * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition + * @i2c_dev: Controller's private data + */ +static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev) +{ + struct st_i2c_client *c = &i2c_dev->client; + + st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); + st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); + + if (c->stop) { + st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); + st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); + } else { + st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); + st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); + } +} + +/** + * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write + * @i2c_dev: Controller's private data + */ +static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev) +{ + struct st_i2c_client *c = &i2c_dev->client; + + st_i2c_flush_rx_fifo(i2c_dev); + + if (!c->count) + /* End of xfer, send stop or repstart */ + st_i2c_terminate_xfer(i2c_dev); + else + st_i2c_wr_fill_tx_fifo(i2c_dev); +} + +/** + * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read + * @i2c_dev: Controller's private data + */ +static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev) +{ + struct st_i2c_client *c = &i2c_dev->client; + u32 ien; + + /* Trash the address read back */ + if (!c->xfered) { + readl_relaxed(i2c_dev->base + SSC_RBUF); + st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); + } else { + st_i2c_read_rx_fifo(i2c_dev); + } + + if (!c->count) { + /* End of xfer, send stop or repstart */ + st_i2c_terminate_xfer(i2c_dev); + } else if (c->count == 1) { + /* Penultimate byte to xfer, disable ACK gen. */ + st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); + + /* Last received byte is to be handled by NACK interrupt */ + ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN; + writel_relaxed(ien, i2c_dev->base + SSC_IEN); + + st_i2c_rd_fill_tx_fifo(i2c_dev, c->count); + } else { + st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1); + } +} + +/** + * st_i2c_isr() - Interrupt routine + * @irq: interrupt number + * @data: Controller's private data + */ +static irqreturn_t st_i2c_isr_thread(int irq, void *data) +{ + struct st_i2c_dev *i2c_dev = data; + struct st_i2c_client *c = &i2c_dev->client; + u32 sta, ien; + int it; + + ien = readl_relaxed(i2c_dev->base + SSC_IEN); + sta = readl_relaxed(i2c_dev->base + SSC_STA); + + /* Use __fls() to check error bits first */ + it = __fls(sta & ien); + if (it < 0) { + dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n", + sta, ien); + return IRQ_NONE; + } + + switch (1 << it) { + case SSC_STA_TE: + if (c->addr & I2C_M_RD) + st_i2c_handle_read(i2c_dev); + else + st_i2c_handle_write(i2c_dev); + break; + + case SSC_STA_STOP: + case SSC_STA_REPSTRT: + writel_relaxed(0, i2c_dev->base + SSC_IEN); + complete(&i2c_dev->complete); + break; + + case SSC_STA_NACK: + writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); + + /* Last received byte handled by NACK interrupt */ + if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) { + st_i2c_handle_read(i2c_dev); + break; + } + + it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; + writel_relaxed(it, i2c_dev->base + SSC_IEN); + + st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); + c->result = -EIO; + break; + + case SSC_STA_ARBL: + writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); + + it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN; + writel_relaxed(it, i2c_dev->base + SSC_IEN); + + st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); + c->result = -EIO; + break; + + default: + dev_err(i2c_dev->dev, + "it %d unhandled (sta=0x%04x)\n", it, sta); + } + + /* + * Read IEN register to ensure interrupt mask write is effective + * before re-enabling interrupt at GIC level, and thus avoid spurious + * interrupts. + */ + readl(i2c_dev->base + SSC_IEN); + + return IRQ_HANDLED; +} + +/** + * st_i2c_xfer_msg() - Transfer a single I2C message + * @i2c_dev: Controller's private data + * @msg: I2C message to transfer + * @is_first: first message of the sequence + * @is_last: last message of the sequence + */ +static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg, + bool is_first, bool is_last) +{ + struct st_i2c_client *c = &i2c_dev->client; + u32 ctl, i2c, it; + unsigned long timeout; + int ret; + + c->addr = (u8)(msg->addr << 1); + c->addr |= (msg->flags & I2C_M_RD); + c->buf = msg->buf; + c->count = msg->len; + c->xfered = 0; + c->result = 0; + c->stop = is_last; + + reinit_completion(&i2c_dev->complete); + + ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO; + st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); + + i2c = SSC_I2C_TXENB; + if (c->addr & I2C_M_RD) + i2c |= SSC_I2C_ACKG; + st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); + + /* Write slave address */ + st_i2c_write_tx_fifo(i2c_dev, c->addr); + + /* Pre-fill Tx fifo with data in case of write */ + if (!(c->addr & I2C_M_RD)) + st_i2c_wr_fill_tx_fifo(i2c_dev); + + it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN; + writel_relaxed(it, i2c_dev->base + SSC_IEN); + + if (is_first) { + ret = st_i2c_wait_free_bus(i2c_dev); + if (ret) + return ret; + + st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); + } + + timeout = wait_for_completion_timeout(&i2c_dev->complete, + i2c_dev->adap.timeout); + ret = c->result; + + if (!timeout) { + dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n", + c->addr); + ret = -ETIMEDOUT; + } + + i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG; + st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); + + writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT, + i2c_dev->base + SSC_CLR); + + return ret; +} + +/** + * st_i2c_xfer() - Transfer a single I2C message + * @i2c_adap: Adapter pointer to the controller + * @msgs: Pointer to data to be written. + * @num: Number of messages to be executed + */ +static int st_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msgs[], int num) +{ + struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); + int ret, i; + + i2c_dev->busy = true; + + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) { + dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); + return ret; + } + + pinctrl_pm_select_default_state(i2c_dev->dev); + + st_i2c_hw_config(i2c_dev); + + for (i = 0; (i < num) && !ret; i++) + ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1); + + pinctrl_pm_select_idle_state(i2c_dev->dev); + + clk_disable_unprepare(i2c_dev->clk); + + i2c_dev->busy = false; + + return (ret < 0) ? ret : i; +} + +#ifdef CONFIG_PM_SLEEP +static int st_i2c_suspend(struct device *dev) +{ + struct platform_device *pdev = + container_of(dev, struct platform_device, dev); + struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); + + if (i2c_dev->busy) + return -EBUSY; + + pinctrl_pm_select_sleep_state(dev); + + return 0; +} + +static int st_i2c_resume(struct device *dev) +{ + pinctrl_pm_select_default_state(dev); + /* Go in idle state if available */ + pinctrl_pm_select_idle_state(dev); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume); +#define ST_I2C_PM (&st_i2c_pm) +#else +#define ST_I2C_PM NULL +#endif + +static u32 st_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static struct i2c_algorithm st_i2c_algo = { + .master_xfer = st_i2c_xfer, + .functionality = st_i2c_func, +}; + +static int st_i2c_of_get_deglitch(struct device_node *np, + struct st_i2c_dev *i2c_dev) +{ + int ret; + + ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us", + &i2c_dev->scl_min_width_us); + if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { + dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n"); + return ret; + } + + ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us", + &i2c_dev->sda_min_width_us); + if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { + dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n"); + return ret; + } + + return 0; +} + +static int st_i2c_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct st_i2c_dev *i2c_dev; + struct resource *res; + u32 clk_rate; + struct i2c_adapter *adap; + int ret; + + i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + i2c_dev->irq = irq_of_parse_and_map(np, 0); + if (!i2c_dev->irq) { + dev_err(&pdev->dev, "IRQ missing or invalid\n"); + return -EINVAL; + } + + i2c_dev->clk = of_clk_get_by_name(np, "ssc"); + if (IS_ERR(i2c_dev->clk)) { + dev_err(&pdev->dev, "Unable to request clock\n"); + return PTR_ERR(i2c_dev->clk); + } + + i2c_dev->mode = I2C_MODE_STANDARD; + ret = of_property_read_u32(np, "clock-frequency", &clk_rate); + if ((!ret) && (clk_rate == 400000)) + i2c_dev->mode = I2C_MODE_FAST; + + i2c_dev->dev = &pdev->dev; + + ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq, + NULL, st_i2c_isr_thread, + IRQF_ONESHOT, pdev->name, i2c_dev); + if (ret) { + dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); + return ret; + } + + pinctrl_pm_select_default_state(i2c_dev->dev); + /* In case idle state available, select it */ + pinctrl_pm_select_idle_state(i2c_dev->dev); + + ret = st_i2c_of_get_deglitch(np, i2c_dev); + if (ret) + return ret; + + adap = &i2c_dev->adap; + i2c_set_adapdata(adap, i2c_dev); + snprintf(adap->name, sizeof(adap->name), "ST I2C(0x%x)", res->start); + adap->owner = THIS_MODULE; + adap->timeout = 2 * HZ; + adap->retries = 0; + adap->algo = &st_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; + + init_completion(&i2c_dev->complete); + + ret = i2c_add_adapter(adap); + if (ret) { + dev_err(&pdev->dev, "Failed to add adapter\n"); + return ret; + } + + platform_set_drvdata(pdev, i2c_dev); + + dev_info(i2c_dev->dev, "%s initialized\n", adap->name); + + return 0; +} + +static int st_i2c_remove(struct platform_device *pdev) +{ + struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&i2c_dev->adap); + + return 0; +} + +static struct of_device_id st_i2c_match[] = { + { .compatible = "st,comms-ssc-i2c", }, + { .compatible = "st,comms-ssc4-i2c", }, + {}, +}; +MODULE_DEVICE_TABLE(of, st_i2c_match); + +static struct platform_driver st_i2c_driver = { + .driver = { + .name = "st-i2c", + .owner = THIS_MODULE, + .of_match_table = st_i2c_match, + .pm = ST_I2C_PM, + }, + .probe = st_i2c_probe, + .remove = st_i2c_remove, +}; + +module_platform_driver(st_i2c_driver); + +MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>"); +MODULE_DESCRIPTION("STMicroelectronics I2C driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c index 0a6f941..04a17b9 100644 --- a/drivers/i2c/busses/i2c-stu300.c +++ b/drivers/i2c/busses/i2c-stu300.c @@ -859,15 +859,13 @@ static const struct i2c_algorithm stu300_algo = { .functionality = stu300_func, }; -static int __init -stu300_probe(struct platform_device *pdev) +static int stu300_probe(struct platform_device *pdev) { struct stu300_dev *dev; struct i2c_adapter *adap; struct resource *res; int bus_nr; int ret = 0; - char clk_name[] = "I2C0"; dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL); if (!dev) { @@ -876,8 +874,7 @@ stu300_probe(struct platform_device *pdev) } bus_nr = pdev->id; - clk_name[3] += (char)bus_nr; - dev->clk = devm_clk_get(&pdev->dev, clk_name); + dev->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { dev_err(&pdev->dev, "could not retrieve i2c bus clock\n"); return PTR_ERR(dev->clk); @@ -885,9 +882,6 @@ stu300_probe(struct platform_device *pdev) dev->pdev = pdev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; - dev->virtbase = devm_ioremap_resource(&pdev->dev, res); dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual " "base %p\n", bus_nr, dev->virtbase); @@ -923,6 +917,7 @@ stu300_probe(struct platform_device *pdev) adap->nr = bus_nr; adap->algo = &stu300_algo; adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; i2c_set_adapdata(adap, dev); /* i2c device drivers may be active on return from add_adapter() */ @@ -934,10 +929,13 @@ stu300_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, dev); + dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n", + dev->virtbase, dev->irq); + return 0; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int stu300_suspend(struct device *device) { struct stu300_dev *dev = dev_get_drvdata(device); @@ -967,8 +965,7 @@ static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume); #define STU300_I2C_PM NULL #endif -static int __exit -stu300_remove(struct platform_device *pdev) +static int stu300_remove(struct platform_device *pdev) { struct stu300_dev *dev = platform_get_drvdata(pdev); @@ -978,19 +975,26 @@ stu300_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id stu300_dt_match[] = { + { .compatible = "st,ddci2c" }, + {}, +}; + static struct platform_driver stu300_i2c_driver = { .driver = { .name = NAME, .owner = THIS_MODULE, .pm = STU300_I2C_PM, + .of_match_table = stu300_dt_match, }, - .remove = __exit_p(stu300_remove), + .probe = stu300_probe, + .remove = stu300_remove, }; static int __init stu300_init(void) { - return platform_driver_probe(&stu300_i2c_driver, stu300_probe); + return platform_driver_register(&stu300_i2c_driver); } static void __exit stu300_exit(void) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9aa1b60..e661ede 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -25,7 +25,6 @@ #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/slab.h> -#include <linux/of_i2c.h> #include <linux/of_device.h> #include <linux/module.h> #include <linux/clk/tegra.h> @@ -545,7 +544,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, i2c_dev->msg_buf_remaining = msg->len; i2c_dev->msg_err = I2C_ERR_NONE; i2c_dev->msg_read = (msg->flags & I2C_M_RD); - INIT_COMPLETION(i2c_dev->msg_complete); + reinit_completion(&i2c_dev->msg_complete); packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | PACKET_HEADER0_PROTOCOL_I2C | @@ -802,8 +801,6 @@ static int tegra_i2c_probe(struct platform_device *pdev) return ret; } - of_i2c_register_devices(&i2c_dev->adapter); - return 0; } diff --git a/drivers/i2c/busses/i2c-tiny-usb.c b/drivers/i2c/busses/i2c-tiny-usb.c index 0510636..e7d3b75 100644 --- a/drivers/i2c/busses/i2c-tiny-usb.c +++ b/drivers/i2c/busses/i2c-tiny-usb.c @@ -54,12 +54,16 @@ static int usb_write(struct i2c_adapter *adapter, int cmd, static int usb_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { - unsigned char status; + unsigned char *pstatus; struct i2c_msg *pmsg; - int i; + int i, ret; dev_dbg(&adapter->dev, "master xfer %d messages:\n", num); + pstatus = kmalloc(sizeof(*pstatus), GFP_KERNEL); + if (!pstatus) + return -ENOMEM; + for (i = 0 ; i < num ; i++) { int cmd = CMD_I2C_IO; @@ -84,7 +88,8 @@ static int usb_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) pmsg->buf, pmsg->len) != pmsg->len) { dev_err(&adapter->dev, "failure reading data\n"); - return -EREMOTEIO; + ret = -EREMOTEIO; + goto out; } } else { /* write data */ @@ -93,36 +98,50 @@ static int usb_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) pmsg->buf, pmsg->len) != pmsg->len) { dev_err(&adapter->dev, "failure writing data\n"); - return -EREMOTEIO; + ret = -EREMOTEIO; + goto out; } } /* read status */ - if (usb_read(adapter, CMD_GET_STATUS, 0, 0, &status, 1) != 1) { + if (usb_read(adapter, CMD_GET_STATUS, 0, 0, pstatus, 1) != 1) { dev_err(&adapter->dev, "failure reading status\n"); - return -EREMOTEIO; + ret = -EREMOTEIO; + goto out; } - dev_dbg(&adapter->dev, " status = %d\n", status); - if (status == STATUS_ADDRESS_NAK) - return -EREMOTEIO; + dev_dbg(&adapter->dev, " status = %d\n", *pstatus); + if (*pstatus == STATUS_ADDRESS_NAK) { + ret = -EREMOTEIO; + goto out; + } } - return i; + ret = i; +out: + kfree(pstatus); + return ret; } static u32 usb_func(struct i2c_adapter *adapter) { - __le32 func; + __le32 *pfunc; + u32 ret; + + pfunc = kmalloc(sizeof(*pfunc), GFP_KERNEL); /* get functionality from adapter */ - if (usb_read(adapter, CMD_GET_FUNC, 0, 0, &func, sizeof(func)) != - sizeof(func)) { + if (!pfunc || usb_read(adapter, CMD_GET_FUNC, 0, 0, pfunc, + sizeof(*pfunc)) != sizeof(*pfunc)) { dev_err(&adapter->dev, "failure reading functionality\n"); - return 0; + ret = 0; + goto out; } - return le32_to_cpu(func); + ret = le32_to_cpup(pfunc); +out: + kfree(pfunc); + return ret; } /* This is the actual algorithm we define */ diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index f3a8790..6bb3a89 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c @@ -16,7 +16,6 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/io.h> -#include <linux/of_i2c.h> #define I2C_CONTROL 0x00 #define I2C_CONTROLS 0x00 @@ -108,7 +107,6 @@ static int i2c_versatile_probe(struct platform_device *dev) ret = i2c_bit_add_numbered_bus(&i2c->adap); if (ret >= 0) { platform_set_drvdata(dev, i2c); - of_i2c_register_devices(&i2c->adap); return 0; } diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c new file mode 100644 index 0000000..2c8a3e4 --- /dev/null +++ b/drivers/i2c/busses/i2c-wmt.c @@ -0,0 +1,477 @@ +/* + * Wondermedia I2C Master Mode Driver + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Derived from GPLv2+ licensed source: + * - Copyright (C) 2008 WonderMedia Technologies, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, or + * (at your option) any later version. as published by the Free Software + * Foundation + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> + +#define REG_CR 0x00 +#define REG_TCR 0x02 +#define REG_CSR 0x04 +#define REG_ISR 0x06 +#define REG_IMR 0x08 +#define REG_CDR 0x0A +#define REG_TR 0x0C +#define REG_MCR 0x0E +#define REG_SLAVE_CR 0x10 +#define REG_SLAVE_SR 0x12 +#define REG_SLAVE_ISR 0x14 +#define REG_SLAVE_IMR 0x16 +#define REG_SLAVE_DR 0x18 +#define REG_SLAVE_TR 0x1A + +/* REG_CR Bit fields */ +#define CR_TX_NEXT_ACK 0x0000 +#define CR_ENABLE 0x0001 +#define CR_TX_NEXT_NO_ACK 0x0002 +#define CR_TX_END 0x0004 +#define CR_CPU_RDY 0x0008 +#define SLAV_MODE_SEL 0x8000 + +/* REG_TCR Bit fields */ +#define TCR_STANDARD_MODE 0x0000 +#define TCR_MASTER_WRITE 0x0000 +#define TCR_HS_MODE 0x2000 +#define TCR_MASTER_READ 0x4000 +#define TCR_FAST_MODE 0x8000 +#define TCR_SLAVE_ADDR_MASK 0x007F + +/* REG_ISR Bit fields */ +#define ISR_NACK_ADDR 0x0001 +#define ISR_BYTE_END 0x0002 +#define ISR_SCL_TIMEOUT 0x0004 +#define ISR_WRITE_ALL 0x0007 + +/* REG_IMR Bit fields */ +#define IMR_ENABLE_ALL 0x0007 + +/* REG_CSR Bit fields */ +#define CSR_RCV_NOT_ACK 0x0001 +#define CSR_RCV_ACK_MASK 0x0001 +#define CSR_READY_MASK 0x0002 + +/* REG_TR */ +#define SCL_TIMEOUT(x) (((x) & 0xFF) << 8) +#define TR_STD 0x0064 +#define TR_HS 0x0019 + +/* REG_MCR */ +#define MCR_APB_96M 7 +#define MCR_APB_166M 12 + +#define I2C_MODE_STANDARD 0 +#define I2C_MODE_FAST 1 + +#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000)) + +struct wmt_i2c_dev { + struct i2c_adapter adapter; + struct completion complete; + struct device *dev; + void __iomem *base; + struct clk *clk; + int mode; + int irq; + u16 cmd_status; +}; + +static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev) +{ + unsigned long timeout; + + timeout = jiffies + WMT_I2C_TIMEOUT; + while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { + if (time_after(jiffies, timeout)) { + dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n"); + return -EBUSY; + } + msleep(20); + } + + return 0; +} + +static int wmt_check_status(struct wmt_i2c_dev *i2c_dev) +{ + int ret = 0; + + if (i2c_dev->cmd_status & ISR_NACK_ADDR) + ret = -EIO; + + if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT) + ret = -ETIMEDOUT; + + return ret; +} + +static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg, + int last) +{ + struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + u16 val, tcr_val; + int ret, wait_result; + int xfer_len = 0; + + if (!(pmsg->flags & I2C_M_NOSTART)) { + ret = wmt_i2c_wait_bus_not_busy(i2c_dev); + if (ret < 0) + return ret; + } + + if (pmsg->len == 0) { + /* + * We still need to run through the while (..) once, so + * start at -1 and break out early from the loop + */ + xfer_len = -1; + writew(0, i2c_dev->base + REG_CDR); + } else { + writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); + } + + if (!(pmsg->flags & I2C_M_NOSTART)) { + val = readw(i2c_dev->base + REG_CR); + val &= ~CR_TX_END; + writew(val, i2c_dev->base + REG_CR); + + val = readw(i2c_dev->base + REG_CR); + val |= CR_CPU_RDY; + writew(val, i2c_dev->base + REG_CR); + } + + reinit_completion(&i2c_dev->complete); + + if (i2c_dev->mode == I2C_MODE_STANDARD) + tcr_val = TCR_STANDARD_MODE; + else + tcr_val = TCR_FAST_MODE; + + tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK)); + + writew(tcr_val, i2c_dev->base + REG_TCR); + + if (pmsg->flags & I2C_M_NOSTART) { + val = readw(i2c_dev->base + REG_CR); + val |= CR_CPU_RDY; + writew(val, i2c_dev->base + REG_CR); + } + + while (xfer_len < pmsg->len) { + wait_result = wait_for_completion_timeout(&i2c_dev->complete, + 500 * HZ / 1000); + + if (wait_result == 0) + return -ETIMEDOUT; + + ret = wmt_check_status(i2c_dev); + if (ret) + return ret; + + xfer_len++; + + val = readw(i2c_dev->base + REG_CSR); + if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { + dev_dbg(i2c_dev->dev, "write RCV NACK error\n"); + return -EIO; + } + + if (pmsg->len == 0) { + val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; + writew(val, i2c_dev->base + REG_CR); + break; + } + + if (xfer_len == pmsg->len) { + if (last != 1) + writew(CR_ENABLE, i2c_dev->base + REG_CR); + } else { + writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + + REG_CDR); + writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); + } + } + + return 0; +} + +static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg, + int last) +{ + struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + u16 val, tcr_val; + int ret, wait_result; + u32 xfer_len = 0; + + if (!(pmsg->flags & I2C_M_NOSTART)) { + ret = wmt_i2c_wait_bus_not_busy(i2c_dev); + if (ret < 0) + return ret; + } + + val = readw(i2c_dev->base + REG_CR); + val &= ~CR_TX_END; + writew(val, i2c_dev->base + REG_CR); + + val = readw(i2c_dev->base + REG_CR); + val &= ~CR_TX_NEXT_NO_ACK; + writew(val, i2c_dev->base + REG_CR); + + if (!(pmsg->flags & I2C_M_NOSTART)) { + val = readw(i2c_dev->base + REG_CR); + val |= CR_CPU_RDY; + writew(val, i2c_dev->base + REG_CR); + } + + if (pmsg->len == 1) { + val = readw(i2c_dev->base + REG_CR); + val |= CR_TX_NEXT_NO_ACK; + writew(val, i2c_dev->base + REG_CR); + } + + reinit_completion(&i2c_dev->complete); + + if (i2c_dev->mode == I2C_MODE_STANDARD) + tcr_val = TCR_STANDARD_MODE; + else + tcr_val = TCR_FAST_MODE; + + tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK); + + writew(tcr_val, i2c_dev->base + REG_TCR); + + if (pmsg->flags & I2C_M_NOSTART) { + val = readw(i2c_dev->base + REG_CR); + val |= CR_CPU_RDY; + writew(val, i2c_dev->base + REG_CR); + } + + while (xfer_len < pmsg->len) { + wait_result = wait_for_completion_timeout(&i2c_dev->complete, + 500 * HZ / 1000); + + if (!wait_result) + return -ETIMEDOUT; + + ret = wmt_check_status(i2c_dev); + if (ret) + return ret; + + pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; + xfer_len++; + + if (xfer_len == pmsg->len - 1) { + val = readw(i2c_dev->base + REG_CR); + val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY); + writew(val, i2c_dev->base + REG_CR); + } else { + val = readw(i2c_dev->base + REG_CR); + val |= CR_CPU_RDY; + writew(val, i2c_dev->base + REG_CR); + } + } + + return 0; +} + +static int wmt_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg msgs[], + int num) +{ + struct i2c_msg *pmsg; + int i, is_last; + int ret = 0; + + for (i = 0; ret >= 0 && i < num; i++) { + is_last = ((i + 1) == num); + + pmsg = &msgs[i]; + if (pmsg->flags & I2C_M_RD) + ret = wmt_i2c_read(adap, pmsg, is_last); + else + ret = wmt_i2c_write(adap, pmsg, is_last); + } + + return (ret < 0) ? ret : i; +} + +static u32 wmt_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART; +} + +static const struct i2c_algorithm wmt_i2c_algo = { + .master_xfer = wmt_i2c_xfer, + .functionality = wmt_i2c_func, +}; + +static irqreturn_t wmt_i2c_isr(int irq, void *data) +{ + struct wmt_i2c_dev *i2c_dev = data; + + /* save the status and write-clear it */ + i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); + writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); + + complete(&i2c_dev->complete); + + return IRQ_HANDLED; +} + +static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev) +{ + int err; + + err = clk_prepare_enable(i2c_dev->clk); + if (err) { + dev_err(i2c_dev->dev, "failed to enable clock\n"); + return err; + } + + err = clk_set_rate(i2c_dev->clk, 20000000); + if (err) { + dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n"); + clk_disable_unprepare(i2c_dev->clk); + return err; + } + + writew(0, i2c_dev->base + REG_CR); + writew(MCR_APB_166M, i2c_dev->base + REG_MCR); + writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); + writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); + writew(CR_ENABLE, i2c_dev->base + REG_CR); + readw(i2c_dev->base + REG_CSR); /* read clear */ + writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); + + if (i2c_dev->mode == I2C_MODE_STANDARD) + writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); + else + writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); + + return 0; +} + +static int wmt_i2c_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct wmt_i2c_dev *i2c_dev; + struct i2c_adapter *adap; + struct resource *res; + int err; + u32 clk_rate; + + i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) { + dev_err(&pdev->dev, "device memory allocation failed\n"); + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + i2c_dev->irq = irq_of_parse_and_map(np, 0); + if (!i2c_dev->irq) { + dev_err(&pdev->dev, "irq missing or invalid\n"); + return -EINVAL; + } + + i2c_dev->clk = of_clk_get(np, 0); + if (IS_ERR(i2c_dev->clk)) { + dev_err(&pdev->dev, "unable to request clock\n"); + return PTR_ERR(i2c_dev->clk); + } + + i2c_dev->mode = I2C_MODE_STANDARD; + err = of_property_read_u32(np, "clock-frequency", &clk_rate); + if ((!err) && (clk_rate == 400000)) + i2c_dev->mode = I2C_MODE_FAST; + + i2c_dev->dev = &pdev->dev; + + err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0, + "i2c", i2c_dev); + if (err) { + dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq); + return err; + } + + adap = &i2c_dev->adapter; + i2c_set_adapdata(adap, i2c_dev); + strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); + adap->owner = THIS_MODULE; + adap->algo = &wmt_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; + + init_completion(&i2c_dev->complete); + + err = wmt_i2c_reset_hardware(i2c_dev); + if (err) { + dev_err(&pdev->dev, "error initializing hardware\n"); + return err; + } + + err = i2c_add_adapter(adap); + if (err) { + dev_err(&pdev->dev, "failed to add adapter\n"); + return err; + } + + platform_set_drvdata(pdev, i2c_dev); + + return 0; +} + +static int wmt_i2c_remove(struct platform_device *pdev) +{ + struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev); + + /* Disable interrupts, clock and delete adapter */ + writew(0, i2c_dev->base + REG_IMR); + clk_disable_unprepare(i2c_dev->clk); + i2c_del_adapter(&i2c_dev->adapter); + + return 0; +} + +static struct of_device_id wmt_i2c_dt_ids[] = { + { .compatible = "wm,wm8505-i2c" }, + { /* Sentinel */ }, +}; + +static struct platform_driver wmt_i2c_driver = { + .probe = wmt_i2c_probe, + .remove = wmt_i2c_remove, + .driver = { + .name = "wmt-i2c", + .owner = THIS_MODULE, + .of_match_table = wmt_i2c_dt_ids, + }, +}; + +module_platform_driver(wmt_i2c_driver); + +MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter"); +MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids); diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 3d0f052..fc2716a 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -40,7 +40,7 @@ #include <linux/i2c-xiic.h> #include <linux/io.h> #include <linux/slab.h> -#include <linux/of_i2c.h> +#include <linux/of.h> #define DRIVER_NAME "xiic-i2c" @@ -703,7 +703,7 @@ static int xiic_i2c_probe(struct platform_device *pdev) if (irq < 0) goto resource_missing; - pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); if (!i2c) @@ -752,8 +752,6 @@ static int xiic_i2c_probe(struct platform_device *pdev) i2c_new_device(&i2c->adap, pdata->devices + i); } - of_i2c_register_devices(&i2c->adap); - return 0; add_adapter_failed: |