diff options
| author | Varun Sethi <Varun.Sethi@freescale.com> | 2013-08-21 13:29:54 (GMT) |
|---|---|---|
| committer | Rivera Jose-B46482 <German.Rivera@freescale.com> | 2013-08-27 18:50:06 (GMT) |
| commit | a8b2a8b56e9bce84ef3512c39fc154a7ae082406 (patch) | |
| tree | 7a5f6c325fc70a2ba623a767ba0c0798a2116786 /drivers/iommu | |
| parent | 03f7a7ce577c7fbe4cb84d23f23009ae21f8880f (diff) | |
| download | linux-fsl-qoriq-a8b2a8b56e9bce84ef3512c39fc154a7ae082406.tar.xz | |
Update the operation mapping settings required by the DSP side for Maple
and DMA.
For the DSP side the basic requirement for stashing is to prevent device
initiated reads and writes going to the DDR. RWNITC and WWSOT operation
mappings aid in achieving these objectives.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I1634ff877d9c8e7c6a3de95aee4a3848cc149973
Reviewed-on: http://git.am.freescale.net:8181/4128
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Tested-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/fsl_pamu.c | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c index e4064cf..84a5de7 100644 --- a/drivers/iommu/fsl_pamu.c +++ b/drivers/iommu/fsl_pamu.c @@ -778,26 +778,12 @@ static void __init setup_omt(struct ome *omt) ome->moe[IOE_DIRECT0_IDX] = EOE_LDEC | EOE_VALID; ome->moe[IOE_DIRECT1_IDX] = EOE_LDEC | EOE_VALID; - /* Configure OMI_DMA */ - ome = &omt[OMI_DMA]; - ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_RSA; - ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA; - ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA; - ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA; - - /* Configure OMI_DMA_READI */ - ome = &omt[OMI_DMA_READI]; - ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READI; - ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_READI; - ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA; - ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA; - - /* Configure OMI_MAPLE */ - ome = &omt[OMI_MAPLE]; - ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_RSA; - ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA; - ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA; - ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA; + /* Configure OMI_DSP */ + ome = &omt[OMI_DSP]; + ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_RWNITC; + ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RWNITC; + ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSAO; + ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO; } /* |