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authorAlexander Duyck <alexander.h.duyck@intel.com>2009-11-19 12:42:01 (GMT)
committerDavid S. Miller <davem@davemloft.net>2009-11-20 18:00:11 (GMT)
commitbb2ac47bcfd47ed9431ff1676ec8d79250c941c9 (patch)
tree2c717135feb469a84382f9532ed6dd70b1ef024c /drivers/net/igb/e1000_phy.c
parent2909c3f79d933b55bf2485addb1dca762210b6af (diff)
downloadlinux-fsl-qoriq-bb2ac47bcfd47ed9431ff1676ec8d79250c941c9.tar.xz
igb: add support for 82580 MAC
This patch adds support for the 82580 MAC. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_phy.c')
-rw-r--r--drivers/net/igb/e1000_phy.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c
index b8fbc85..5c9d73e 100644
--- a/drivers/net/igb/e1000_phy.c
+++ b/drivers/net/igb/e1000_phy.c
@@ -136,7 +136,7 @@ out:
* Reads the MDI control regsiter in the PHY at offset and stores the
* information read to data.
**/
-static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{
struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
@@ -194,7 +194,7 @@ out:
*
* Writes data to MDI control register in the PHY at offset.
**/
-static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0;
@@ -1947,7 +1947,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
*
* Polarity is determined based on the PHY specific status register.
**/
-s32 igb_check_polarity_82580(struct e1000_hw *hw)
+static s32 igb_check_polarity_82580(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;