diff options
author | Philipp Zabel <p.zabel@pengutronix.de> | 2013-04-08 16:04:35 (GMT) |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-04-09 23:16:16 (GMT) |
commit | 2ea42608ba977bd05ce7b2d8a1f65efacfc84352 (patch) | |
tree | 9e146cffb7167ec34bb40001a00cc2cab957271b /drivers/staging/imx-drm/ipu-v3/ipu-di.c | |
parent | db5225d4050d5ef4bd7e9aced161c87d6a90decc (diff) | |
download | linux-fsl-qoriq-2ea42608ba977bd05ce7b2d8a1f65efacfc84352.tar.xz |
staging: drm/imx: Add support for VGA via TVE on i.MX53
This adds display interface timings for the Television Encoder
connected to IPU DI1 on i.MX53 and adds some configuration
glue code to select which IPU signal generators / pins are to
be used for HSYNC/VSYNC signals.
The default configuration is pin2/pin3 for hsync/vsync. The
VGA connector on i.MX53-QSB uses pin7/pin8, and the analog
part of the DVI-I connector on MBa53 connects to pin4/pin6.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/imx-drm/ipu-v3/ipu-di.c')
-rw-r--r-- | drivers/staging/imx-drm/ipu-v3/ipu-di.c | 93 |
1 files changed, 86 insertions, 7 deletions
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-di.c b/drivers/staging/imx-drm/ipu-v3/ipu-di.c index 26534b7..19d777e 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-di.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-di.c @@ -440,7 +440,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, .repeat_count = sig->height, .cnt_clr_src = DI_SYNC_VSYNC, } , { - /* 5: DE, referenced by DC */ + /* 5: Pixel Active, referenced by DC */ .run_src = DI_SYNC_CLK, .offset_count = sig->h_sync_width + sig->h_start_width, .offset_src = DI_SYNC_CLK, @@ -454,13 +454,78 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, /* unused */ } , { /* unused */ + }, + }; + /* can't use #7 and #8 for line active and pixel active counters */ + struct di_sync_config cfg_vga[] = { + { + /* 1: INT_HSYNC */ + .run_count = h_total - 1, + .run_src = DI_SYNC_CLK, + } , { + /* 2: VSYNC */ + .run_count = v_total - 1, + .run_src = DI_SYNC_INT_HSYNC, + } , { + /* 3: Line Active */ + .run_src = DI_SYNC_INT_HSYNC, + .offset_count = sig->v_sync_width + sig->v_start_width, + .offset_src = DI_SYNC_INT_HSYNC, + .repeat_count = sig->height, + .cnt_clr_src = 3 /* VSYNC */, + } , { + /* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */ + .run_count = h_total - 1, + .run_src = DI_SYNC_CLK, + .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ + .offset_src = DI_SYNC_CLK, + .cnt_polarity_gen_en = 1, + .cnt_polarity_trigger_src = DI_SYNC_CLK, + .cnt_down = sig->h_sync_width * 2, + } , { + /* 5: Pixel Active signal to DC */ + .run_src = DI_SYNC_CLK, + .offset_count = sig->h_sync_width + sig->h_start_width, + .offset_src = DI_SYNC_CLK, + .repeat_count = sig->width, + .cnt_clr_src = 4, /* Line Active */ + } , { + /* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */ + .run_count = v_total - 1, + .run_src = DI_SYNC_INT_HSYNC, + .offset_count = 1, /* magic value from Freescale TVE driver */ + .offset_src = DI_SYNC_INT_HSYNC, + .cnt_polarity_gen_en = 1, + .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, + .cnt_down = sig->v_sync_width * 2, + } , { + /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */ + .run_count = h_total - 1, + .run_src = DI_SYNC_CLK, + .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ + .offset_src = DI_SYNC_CLK, + .cnt_polarity_gen_en = 1, + .cnt_polarity_trigger_src = DI_SYNC_CLK, + .cnt_down = sig->h_sync_width * 2, + } , { + /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */ + .run_count = v_total - 1, + .run_src = DI_SYNC_INT_HSYNC, + .offset_count = 1, /* magic value from Freescale TVE driver */ + .offset_src = DI_SYNC_INT_HSYNC, + .cnt_polarity_gen_en = 1, + .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, + .cnt_down = sig->v_sync_width * 2, } , { /* unused */ }, }; ipu_di_write(di, v_total - 1, DI_SCR_CONF); - ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); + if (sig->hsync_pin == 2 && sig->vsync_pin == 3) + ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); + else + ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga)); } int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) @@ -537,11 +602,25 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) ipu_di_sync_config_noninterlaced(di, sig, div); vsync_cnt = 3; - - if (sig->Hsync_pol) - di_gen |= DI_GEN_POLARITY_2; - if (sig->Vsync_pol) - di_gen |= DI_GEN_POLARITY_3; + if (di->id == 1) + vsync_cnt = 6; + + if (sig->Hsync_pol) { + if (sig->hsync_pin == 2) + di_gen |= DI_GEN_POLARITY_2; + else if (sig->hsync_pin == 4) + di_gen |= DI_GEN_POLARITY_4; + else if (sig->hsync_pin == 7) + di_gen |= DI_GEN_POLARITY_7; + } + if (sig->Vsync_pol) { + if (sig->hsync_pin == 3) + di_gen |= DI_GEN_POLARITY_3; + else if (sig->hsync_pin == 6) + di_gen |= DI_GEN_POLARITY_6; + else if (sig->hsync_pin == 8) + di_gen |= DI_GEN_POLARITY_8; + } } if (!sig->clk_pol) |