diff options
| author | Ramneek Mehresh <ramneek.mehresh@freescale.com> | 2013-04-11 04:27:14 (GMT) |
|---|---|---|
| committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-04-29 15:13:51 (GMT) |
| commit | 8674d9510f86cf78002f31692dcc3f5432257236 (patch) | |
| tree | 57f494b3ed0cc2d14211c0b451488e244ac76d06 /drivers/usb | |
| parent | 2ca2892b3e84029a37c9fba103e9eeaad9b99001 (diff) | |
| download | linux-fsl-qoriq-8674d9510f86cf78002f31692dcc3f5432257236.tar.xz | |
fsl/otg: Add controller version based ULPI and UTMI phy
Add controller version based ULPI and UTMI phy initialization for
otg driver
Change-Id: I5f64d5e70ecec7ad341a0e4a1a201f965d628ca6
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1366
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/otg/fsl_otg.c | 20 | ||||
| -rw-r--r-- | drivers/usb/otg/fsl_otg.h | 8 |
2 files changed, 28 insertions, 0 deletions
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c index d16adb4..cd5a5fd 100644 --- a/drivers/usb/otg/fsl_otg.c +++ b/drivers/usb/otg/fsl_otg.c @@ -911,12 +911,32 @@ int usb_otg_start(struct platform_device *pdev) temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW); switch (pdata->phy_mode) { case FSL_USB2_PHY_ULPI: + if (pdata->controller_ver) { + /* controller version 1.6 or above */ + setbits32(&p_otg->dr_mem_map->control, + USB_CTRL_ULPI_PHY_CLK_SEL); + /* + * Due to controller issue of PHY_CLK_VALID in ULPI + * mode, we set USB_CTRL_USB_EN before checking + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work. + */ + clrsetbits_be32(&p_otg->dr_mem_map->control, + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB); + } temp |= PORTSC_PTS_ULPI; break; case FSL_USB2_PHY_UTMI_WIDE: temp |= PORTSC_PTW_16BIT; /* fall through */ case FSL_USB2_PHY_UTMI: + if (pdata->controller_ver) { + /* controller version 1.6 or above */ + setbits32(&p_otg->dr_mem_map->control, + USB_CTRL_UTMI_PHY_EN); + /* Delay for UTMI PHY CLK to become stable - 10ms */ + mdelay(FSL_UTMI_PHY_DLY); + } + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN); temp |= PORTSC_PTS_UTMI; /* fall through */ default: diff --git a/drivers/usb/otg/fsl_otg.h b/drivers/usb/otg/fsl_otg.h index ca26628..1a9d360 100644 --- a/drivers/usb/otg/fsl_otg.h +++ b/drivers/usb/otg/fsl_otg.h @@ -199,6 +199,14 @@ /* control Register Bit Masks */ #define USB_CTRL_IOENB (0x1<<2) #define USB_CTRL_ULPI_INT0EN (0x1<<0) +#define USB_CTRL_WU_INT_EN (0x1<<1) +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3) +#define USB_CTRL_KEEP_OTG_ON (0x1<<4) +#define USB_CTRL_OTG_PORT (0x1<<5) +#define USB_CTRL_PLL_RESET (0x1<<8) +#define USB_CTRL_UTMI_PHY_EN (0x1<<9) +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10) +#define USB_CTRL_PHY_CLK_VALID (0x1<<17) /* BCSR5 */ #define BCSR5_INT_USB (0x02) |