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author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-08-12 22:28:32 (GMT) |
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committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-08-19 18:57:12 (GMT) |
commit | b095cd0a0ccdbc00c9fd99d90b22f8563687971f (patch) | |
tree | e75b0061ad30d7ee8df4e35ff90b1d0cdfe006b4 /mm/mincore.c | |
parent | 4e6343898fe7eed6b3c0c3c809347bc88d5b4a1e (diff) | |
download | linux-fsl-qoriq-b095cd0a0ccdbc00c9fd99d90b22f8563687971f.tar.xz |
drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge
Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that
MI_FLUSH would flush the TLBs in addition to the rest of the caches
indicated in the MI_FLUSH command. However starting with Ivybridge, the
register defaults to 0x2800 out of reset, meaning that to invalidate the
TLB we need to use PIPE_CONTROL. Since we're not doing that yet, go
back to the old default so things work.
v2: don't forget to actually *clear* the new bit
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'mm/mincore.c')
0 files changed, 0 insertions, 0 deletions