diff options
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/DocBook/uio-howto.tmpl | 12 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 12 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/board.txt | 18 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt | 43 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cpus.txt | 22 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/guts.txt | 13 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/pamu.txt | 140 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/rman.txt | 178 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/tdm/fsl-tdm.txt | 65 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/tdm/pq-mds-t1.txt | 63 | ||||
| -rw-r--r-- | Documentation/mmc/mmc-dev-attrs.txt | 2 |
11 files changed, 565 insertions, 3 deletions
diff --git a/Documentation/DocBook/uio-howto.tmpl b/Documentation/DocBook/uio-howto.tmpl index ddb05e9..e23f986 100644 --- a/Documentation/DocBook/uio-howto.tmpl +++ b/Documentation/DocBook/uio-howto.tmpl @@ -510,6 +510,18 @@ interrupts from userspace by writing to <filename>/dev/uioX</filename>, you can implement this function. The parameter <varname>irq_on</varname> will be 0 to disable interrupts and 1 to enable them. </para></listitem> + +<listitem><para> +<varname>pgprot_t (*set_pgprot)(struct uio_info *info, unsigned int mem_idx, +pgprot_t prot)</varname>: Optional. If special flags are required when mapping +certain hardware regions, then this callback can be used to specify those flags. +The default flags are given by the host architecture's definition of +<function>pgprot_noncached()</function> and are passed to the callback as the +<varname>prot</varname> parameter, but the return value is what is used for the +resulting mapping. Note that this callback is only used by the built in mapping +logic (when the <function>mmap()</function> callback has not been set), and then +only for UIO_MEM_PHYS regions. +</para></listitem> </itemizedlist> <para> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt index 2c6be03..7d61c7e 100644 --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt @@ -92,6 +92,16 @@ Clock Properties: - fsl,tmr-fiper1 Fixed interval period pulse generator. - fsl,tmr-fiper2 Fixed interval period pulse generator. - fsl,max-adj Maximum frequency adjustment in parts per billion. + - fsl,clock-source-select Value type: <u32>, + select 1588 Timer reference clock source. + 0. External high precision timer reference + clock (TSEC_1588_CLK_IN) + 1. eTSEC system clock + 2. eTSEC1 transmit clock + 3. RTC clock input. + - fsl,ts-to-buffer Value type <none>, if present, indicates that TSEC + has ability to write time stamp of the transmitted + frame to memory in the padding. These properties set the operational parameters for the PTP clock. You must choose these carefully for the clock to work right. @@ -127,4 +137,6 @@ Example: fsl,tmr-fiper1 = <0x3B9AC9F6>; fsl,tmr-fiper2 = <0x00018696>; fsl,max-adj = <659999998>; + fsl,clock-source-select = <1>; + fsl,ts-to-buffer; }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt index 380914e..ecc2e52 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt @@ -67,3 +67,21 @@ Example: gpio-controller; }; }; + +* Freescale on-board FPGA connected on I2C bus + +Some Freescale boards like BSC9132QDS have on board FPGA connected on +the i2c bus. + +Required properties: +- compatible: Should be a board-specific string followed by a string + indicating the type of FPGA. Example: + "fsl,<board>-fpga", "fsl,fpga-qixis-i2c" +- reg: Should contain the address of the FPGA + +Example: + fpga: fpga@66 { + compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c"; + reg = <0x66>; + }; + diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt index e47734b..b1b569f 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt @@ -2,8 +2,9 @@ Required properties: - device_type : should be "network", "hldc", "uart", "transparent" - "bisync", "atm", or "serial". -- compatible : could be "ucc_geth" or "fsl_atm" and so on. + "bisync", "atm", "tdm" or "serial". +- compatible : Describes the specific device attached to the UCC. + Examples include "ucc_geth", "fsl_atm", "ucc_uart" and "fsl,ucc-tdm". - cell-index : the ucc number(1-8), corresponding to UCCx in UM. - reg : Offset and length of the register set for the device - interrupts : <a b> where a is the interrupt number and b is a @@ -53,6 +54,24 @@ Recommended properties: Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only), "tbi", or "rtbi". +Required properties for fsl, ucc-tdm, compatible: +- fsl,rx-sync-clock, fsl,tx-sync-clock: the TDM sync clock source for + receive/transmit + "none": clock source is disabled + "rsync_pin" : clock source is TDM_A1 RSYNC pin + "brg9" through "brg15" : clock source is BRG9-BRG15, respectively +- fsl,tdm-tx-timeslot, fsl,tdm-rx-timeslot: time slot mask for transmit/receive + Each bit (LSB first) corresponds to a time slot. The time slot is enabled + if the bit is set +- fsl,tdm-id : It is the tdm port number. e.g. P1021E has 4 ports - port + A/B/C/D mapping to number 0/1/2/3. +- fsl,tdm-framer-type : It should be "t1" or "e1", "t1" for T1 line rate, and + "e1" for E1 line rate +- fsl,tdm-mode : It is tsa working mode. It should be "normal" or + "internal-loopback" +- fsl,siram-entry-id : This number is used for setting index siram entry + It should be 0/2/4.../14. Each TDM should not use the same number + with others Example: ucc@2000 { device_type = "network"; @@ -68,3 +87,23 @@ Example: phy-connection-type = "gmii"; pio-handle = <140001>; }; + + tdmc: ucc@2400 { + compatible = "fsl,ucc-tdm"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + rx-clock-name = "clk7"; + tx-clock-name = "clk13"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot = <0x00ffffff>; + fsl,rx-timeslot = <0x00ffffff>; + pio-handle = <&pio_tdmc>; + fsl,tdm-framer-type = "t1"; + fsl,tdm-mode = "normal"; + fsl,tdm-id = <2>; + fsl,siram-entry-id = <4>; + phy-handle = <&tdmphy>; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt new file mode 100644 index 0000000..922c30a --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt @@ -0,0 +1,22 @@ +=================================================================== +Power Architecture CPU Binding +Copyright 2013 Freescale Semiconductor Inc. + +Power Architecture CPUs in Freescale SOCs are represented in device trees as +per the definition in ePAPR. + +In addition to the ePAPR definitions, the properties defined below may be +present on CPU nodes. + +PROPERTIES + + - fsl,eref-* + Usage: optional + Value type: <empty> + Definition: The EREF (EREF: A Programmer.s Reference Manual for + Freescale Power Architecture) defines the architecture for Freescale + Power CPUs. The EREF defines some architecture categories not defined + by the Power ISA. For these EREF-specific categories, the existence of + a property named fsl,eref-[CAT], where [CAT] is the abbreviated category + name with all uppercase letters converted to lowercase, indicates that + the category is supported by the implementation. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt index 9e7a241..7f150b5 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/guts.txt @@ -17,9 +17,20 @@ Recommended properties: contains a functioning "reset control register" (i.e. the board is wired to reset upon setting the HRESET_REQ bit in this register). -Example: + - fsl,liodn-bits : Indicates the number of defined bits in the LIODN + registers, for those SOCs that have a PAMU device. + +Examples: global-utilities@e0000 { /* global utilities block */ compatible = "fsl,mpc8548-guts"; reg = <e0000 1000>; fsl,has-rstcr; }; + + guts: global-utilities@e0000 { + compatible = "fsl,qoriq-device-config-1.0"; + reg = <0xe0000 0xe00>; + fsl,has-rstcr; + #sleep-cells = <1>; + fsl,liodn-bits = <12>; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt new file mode 100644 index 0000000..1f5e329 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt @@ -0,0 +1,140 @@ +Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding + +DESCRIPTION + +The PAMU is an I/O MMU that provides device-to-memory access control and +address translation capabilities. + +Required properties: + +- compatible : <string> + First entry is a version-specific string, such as + "fsl,pamu-v1.0". The second is "fsl,pamu". +- ranges : <prop-encoded-array> + A standard property. Utilized to describe the memory mapped + I/O space utilized by the controller. The size should + be set to the total size of the register space of all + physically present PAMU controllers. For example, for + PAMU v1.0, on an SOC that has five PAMU devices, the size + is 0x5000. +- interrupts : <prop-encoded-array> + Interrupt mappings. The first tuple is the normal PAMU + interrupt, used for reporting access violations. The second + is for PAMU hardware errors, such as PAMU operation errors + and ECC errors. +- #address-cells: <u32> + A standard property. +- #size-cells : <u32> + A standard property. + +Optional properties: +- reg : <prop-encoded-array> + A standard property. It represents the CCSR registers of + all child PAMUs combined. Include it to provide support + for legacy drivers. +- interrupt-parent : <phandle> + Phandle to interrupt controller + +Child nodes: + +Each child node represents one PAMU controller. Each SOC device that is +connected to a specific PAMU device should have a "fsl,pamu-phandle" property +that links to the corresponding specific child PAMU controller. + +- reg : <prop-encoded-array> + A standard property. Specifies the physical address and + length (relative to the parent 'ranges' property) of this + PAMU controller's configuration registers. The size should + be set to the size of this PAMU controllers's register space. + For PAMU v1.0, this size is 0x1000. +- fsl,primary-cache-geometry + : <prop-encoded-array> + Two cells that specify the geometry of the primary PAMU + cache. The first is the number of cache lines, and the + second is the number of "ways". For direct-mapped caches, + specify a value of 1. +- fsl,secondary-cache-geometry + : <prop-encoded-array> + Two cells that specify the geometry of the secondary PAMU + cache. The first is the number of cache lines, and the + second is the number of "ways". For direct-mapped caches, + specify a value of 1. + +Device nodes: + +Devices that have LIODNs need to specify links to the parent PAMU controller +(the actual PAMU controller that this device is connected to) and a pointer to +the LIODN register, if applicable. + +- fsl,iommu-parent + : <phandle> + Phandle to the single, specific PAMU controller node to which + this device is connect. The PAMU topology is represented in + the device tree to assist code that dynamically determines the + best LIODN values to minimize PAMU cache thrashing. + +- fsl,liodn-reg : <prop-encoded-array> + Two cells that specify the location of the LIODN register + for this device. Required for devices that have a single + LIODN. The first cell is a phandle to a node that contains + the registers where the LIODN is to be set. The second is + the offset from the first "reg" resource of the node where + the specific LIODN register is located. + + +Example: + + iommu@20000 { + compatible = "fsl,pamu-v1.0", "fsl,pamu"; + reg = <0x20000 0x5000>; + ranges = <0 0x20000 0x5000>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = < + 24 2 0 0 + 16 2 1 30>; + + pamu0: pamu@0 { + reg = <0 0x1000>; + fsl,primary-cache-geometry = <32 1>; + fsl,secondary-cache-geometry = <128 2>; + }; + + pamu1: pamu@1000 { + reg = <0x1000 0x1000>; + fsl,primary-cache-geometry = <32 1>; + fsl,secondary-cache-geometry = <128 2>; + }; + + pamu2: pamu@2000 { + reg = <0x2000 0x1000>; + fsl,primary-cache-geometry = <32 1>; + fsl,secondary-cache-geometry = <128 2>; + }; + + pamu3: pamu@3000 { + reg = <0x3000 0x1000>; + fsl,primary-cache-geometry = <32 1>; + fsl,secondary-cache-geometry = <128 2>; + }; + + pamu4: pamu@4000 { + reg = <0x4000 0x1000>; + fsl,primary-cache-geometry = <32 1>; + fsl,secondary-cache-geometry = <128 2>; + }; + }; + + guts: global-utilities@e0000 { + compatible = "fsl,qoriq-device-config-1.0"; + reg = <0xe0000 0xe00>; + fsl,has-rstcr; + #sleep-cells = <1>; + fsl,liodn-bits = <12>; + }; + +/include/ "qoriq-dma-0.dtsi" + dma@100300 { + fsl,iommu-parent = <&pamu0>; + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/rman.txt b/Documentation/devicetree/bindings/powerpc/fsl/rman.txt new file mode 100644 index 0000000..76a86fd --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/rman.txt @@ -0,0 +1,178 @@ +================================================================================= +Freescale RapidIO Message Manager Device Bindings +Copyright 2013 Freescale Semiconductor Inc. + +CONTENTS + - RMan Node + - RMan Inbound Block Node + - RMan Global CFG Node + - Example + +NOTE: The bindings described in this document are preliminary and subject to +change. + +================================================================================= +RMan Node + +DESCRIPTION + +The RapidIO message manager (RMan) supports a message passing programming model +for inter-processor and inter-device communication. Due to the fact RMan has +multiple inbound blocks, the RMan node will have child nodes for each block. +The RMan's revision information can be get from IPBRRO and IPBRR1 registers. + +PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,rman". + Definition: Must include "fsl,rman" for IP blocks with IP Block + Revision Register (SRIO IPBRR1) Major ID equal to 0x0a20. + + Optionally, a compatiable string of "fsl,rman-vX.Y" where X is Major + version in IP Block Revision Register and Y is Minor version. If this + compatiable is provided it should be ordered before "fsl,rman". + + - #address-cells + Usage: required + Value type: <u32> + Definition: A standard property. Defines the number of cells for + representing physical addresses in child nodes. Must have a + value of 1. + + - #size-cells + Usage: required + Value type: <u32> + Definition: A standard property. Defines the number of cells for + representing the size of physical addresses in child nodes. + Must have a value of 1. + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical address and + length of the RMan configuration registers within the CCSR + address space. + + - ranges + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical address and= + length of the RMan memory space. + + - interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: Interrupt mapping for RMAN error IRQ. + + - fsl,qman-channels-id + Usage: required + Value type: <prop-encoded-array> + Definition: This property represents the ID value for the specific QMan + dequeue channel(s) asssociate with RMan. Typically there is a + dequeue channel per RapidIO port. + +================================================================================= +RMan Inbound Block Node + +DESCRIPTION + +RMan has multiple inbound blocks. Each inbound block has eight classification +units. + +PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: A standard property. Must include "fsl,rman-inbound-block". + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical address offset + and length of the RMan inbound block configuration registers + within the RMan node's address space. + + - fsl,liodn + Usage: see definition + Value type: <u32> + Definition: The logical I/O device number (LIODN) for this device. The + LIODN is a number expressed by this device and used to perform + look-ups in the IOMMU (PAMU) address table when performing DMAs. + This property is required if the PAMU is enabled. + +Example + +inbound-block@0 { + fsl,liodn = <203>; + compatible = "fsl,rman-inbound-block"; + reg = <0x0 0x800>; +}; + +================================================================================= +RMan Global CFG Node + +DESCRIPTION + +This node describes the RMan global registers located within the first 4K bytes +resource block. + +PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: A standard property. Must include "fsl,rman-global-cfg". + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical address offset + and length of the RMan global configuration registers within the + RMan node's address space. + +Example + +global-cfg@b00 { + compatible = "fsl,rman-global-cfg"; + reg = <0xb00 0x500>; +}; + +================================================================================= +Example + +rman: rman@1e0000 { + compatible = "fsl,rman"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e0000 0x20000>; + reg = <0x1e0000 0x20000>; + interrupts = <16 2 1 11>; /* err_irq */ + fsl,qman-channels-id = <0x62 0x63>; + inbound-block@0 { + fsl,liodn = <203>; + compatible = "fsl,rman-inbound-block"; + reg = <0x0 0x800>; + }; + global-cfg@b00 { + compatible = "fsl,rman-global-cfg"; + reg = <0xb00 0x500>; + }; + inbound-block@1000 { + fsl,liodn = <204>; + compatible = "fsl,rman-inbound-block"; + reg = <0x1000 0x800>; + }; + inbound-block@2000 { + fsl,liodn = <205>; + compatible = "fsl,rman-inbound-block"; + reg = <0x2000 0x800>; + }; + inbound-block@3000 { + fsl,liodn = <206>; + compatible = "fsl,rman-inbound-block"; + reg = <0x3000 0x800>; + }; +}; diff --git a/Documentation/devicetree/bindings/tdm/fsl-tdm.txt b/Documentation/devicetree/bindings/tdm/fsl-tdm.txt new file mode 100644 index 0000000..1258b89 --- /dev/null +++ b/Documentation/devicetree/bindings/tdm/fsl-tdm.txt @@ -0,0 +1,65 @@ +===================================================================== +TDM Device Tree Binding +Copyright (C) 2012 Freescale Semiconductor Inc. + +NOTE: The bindings described in this document are preliminary +and subject to change. + +===================================================================== +TDM (Time Division Multiplexing) + +DESCRIPTION + +The TDM is full duplex serial port designed to allow various devices including +digital signal processors (DSPs) to communicate with a variety of serial devices +including industry standard framers, codecs, other DSPs and microprocessors. + +The below properties describe the device tree bindings for Freescale TDM +controller. +This TDM controller is available on various Freescale Processors like +MPC8313, P1020, P1022 and P1010. + +PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: Should contain "fsl,tdm1.0". + + - reg + Usage: required + Definition: A standard property. The first reg specifier describes the + TDM registers, and the second describes the TDM DMAC registers. + + - clock-frequency + Usage: optional + Value type: <u32 or u64> + Definition: The frequency at which the TDM block is operating. + + - interrupts + Usage: required + Definition: Definition: Two interrupt specifiers. The first is TDM + error, and the second is TDM EMAC. + + - phy-handle + Usage: optional + Value type: <phandle> + Definition: Phandle of the line controller node or framer node eg. SLIC, + E1/T1 etc. + + - fsl,max-time-slots + Usage: required + Value type: <u32> + Definition: Maximum number of 8-bit time slots in one TDM frame. + This is the maximum number which TDM hardware supports. + +EXAMPLE + + tdm@16000 { + compatible = "fsl,tdm1.0"; + reg = <0x16000 0x200 0x2c000 0x2000>; + clock-frequency = <0>; + interrupts = <16 8 62 8>; + phy-handle = <&zarlink1>; + fsl,max-time-slots = <128>; + }; diff --git a/Documentation/devicetree/bindings/tdm/pq-mds-t1.txt b/Documentation/devicetree/bindings/tdm/pq-mds-t1.txt new file mode 100644 index 0000000..d5a9240 --- /dev/null +++ b/Documentation/devicetree/bindings/tdm/pq-mds-t1.txt @@ -0,0 +1,63 @@ +===================================================================== +FSL PQ_MDS_T1 Device Tree Binding +Copyright (C) 2012 Freescale Semiconductor Inc. + +===================================================================== +Introduction + +The PQ-MDS-T1 - A board card with the T1/E1/DS3/T3/SLIC-SLAC module + which serves as a platform for S/W and H/W development + around the host device, it is connected by PMC sockets. + +1.TDM PHY + Function : DS26528 T1/E1/J1 transceiver + +Properties + - compatible + Usage: required + Value type: <string> + Definition: Should be "fsl,pq-mds-t1". + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: The first reg specifier describes the the address, + and the second describes the length. + - line-rate + Usage: required + Value type: <string> + Definition: It descrbets the line rate "e1" or "t1". "e1" is 2.048MHz + "t1" is 1.544MHz. + - fsl,trans-mode + Usage: required + Value type: <string> + Definition: TDM controller transfer mode setting + Normal operation: set fsl,trans-mode = "normal". In this mode, + controller sends and receives data normally. + Loopback operation: set fsl,trans-mode = "internal-loopback". + In this mode, the data is sent via tsa tx pin and + received from tsa rx pin. +Example + + ds26528: tdm-phy@0 { + compatible = "dallas,ds26528"; + reg = <0 0x2000>; + line-rate = "e1"; + fsl,trans-mode = "normal"; + }; + +2.PQ-MDS-T1 PLD + Function: Board identification, control and clock/signal routing + +Properties + - fsl,card-support + Usage: required + Value type: <u32> + Definition: This property use phandle to describe which it serves as, + ds26528 or zarlink. + +Example + pld-reg@2000 { + compatible = "fsl,pq-mds-t1-pld"; + reg = <0x2000 0x1000>; + fsl,card-support = <&ds26528>; + } diff --git a/Documentation/mmc/mmc-dev-attrs.txt b/Documentation/mmc/mmc-dev-attrs.txt index 0d98fac..492fd96 100644 --- a/Documentation/mmc/mmc-dev-attrs.txt +++ b/Documentation/mmc/mmc-dev-attrs.txt @@ -7,6 +7,8 @@ SD or MMC device. The following attributes are read/write. force_ro Enforce read-only access even if write protect switch is off. + bouncesz Support dynamic adjustment of bounce buffer size at runtime, + from 4096 to 4194304, integer multiple of 512 bytes only. SD and MMC Device Attributes ============================ |