diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/platforms/85xx/twr_p102x.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 6ed7be5..383eb57 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -139,6 +139,15 @@ static void __init twr_p1025_setup_arch(void) MPC85xx_PMUXCR_QE(12)); iounmap(guts); +#if defined(CONFIG_SERIAL_QE) + /* On P1025TWR board, the UCC7 acted as UART port. + * However, The UCC7's CTS pin is low level in default, + * it will impact the transmission in full duplex + * communication. So disable the Flow control pin PA18. + * The UCC7 UART just can use RXD and TXD pins. + */ + par_io_config_pin(0, 18, 0, 0, 0, 0); +#endif /* Drive PB29 to CPLD low - CPLD will then change * muxing from LBC to QE */ par_io_config_pin(1, 29, 1, 0, 0, 0); |