diff options
Diffstat (limited to 'drivers/staging/brcm80211/brcmsmac/aiutils.c')
| -rw-r--r-- | drivers/staging/brcm80211/brcmsmac/aiutils.c | 508 |
1 files changed, 403 insertions, 105 deletions
diff --git a/drivers/staging/brcm80211/brcmsmac/aiutils.c b/drivers/staging/brcm80211/brcmsmac/aiutils.c index a61185f..fee8966 100644 --- a/drivers/staging/brcm80211/brcmsmac/aiutils.c +++ b/drivers/staging/brcm80211/brcmsmac/aiutils.c @@ -17,32 +17,357 @@ #include <linux/delay.h> #include <linux/kernel.h> #include <linux/string.h> -#include <bcmdefs.h> +#include <defs.h> +#include "types.h" #include <linux/module.h> #include <linux/pci.h> -#include <bcmutils.h> +#include <brcmu_utils.h> #include <aiutils.h> -#include <hndsoc.h> -#include <sbchipc.h> -#include <pcicfg.h> -#include <bcmdevs.h> +#include <soc.h> +#include <chipcommon.h> +#include <brcm_hw_ids.h> /* ********** from siutils.c *********** */ -#include <pci_core.h> -#include <pcie_core.h> #include <nicpci.h> -#include <bcmnvram.h> -#include <bcmsrom.h> -#include <wlc_pmu.h> +#include "srom.h" +#include <pmu.h> +#include <scb.h> +#include <pub.h> + +/* slow_clk_ctl */ +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */ +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, + * 0: LPO is enabled + */ +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, + * 0: power logic control + */ +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors + * PLL clock disable requests from core + */ +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't + * disable crystal when appropriate + */ +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ +#define SCC_CD_SHIFT 16 + +/* system_clk_ctl */ +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ +#define SYCC_FP 0x00000004 /* ForcePLLOn */ +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ +#define SYCC_HR 0x00000010 /* Force HT */ +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ +#define SYCC_CD_SHIFT 16 + +#define CST4329_SPROM_OTP_SEL_MASK 0x00000003 +#define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ +#define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ +#define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */ +#define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ +#define CST4329_SPI_SDIO_MODE_MASK 0x00000004 +#define CST4329_SPI_SDIO_MODE_SHIFT 2 + +/* 43224 chip-specific ChipControl register bits */ +#define CCTRL43224_GPIO_TOGGLE 0x8000 +#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ +#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ + +/* 43236 Chip specific ChipStatus register bits */ +#define CST43236_SFLASH_MASK 0x00000040 +#define CST43236_OTP_MASK 0x00000080 +#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ +#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ +#define CST43236_BOOT_MASK 0x00001800 +#define CST43236_BOOT_SHIFT 11 +#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ +#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ +#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ +#define CST43236_BOOT_FROM_INVALID 3 + +/* 4331 chip-specific ChipControl register bits */ +#define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ +#define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ +#define CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ +#define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ +#define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ +#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ +#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ +#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ +#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ +#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ +#define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ +#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ +#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ +#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ + +/* 4331 Chip specific ChipStatus register bits */ +#define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ +#define CST4331_SPROM_PRESENT 0x00000002 +#define CST4331_OTP_PRESENT 0x00000004 +#define CST4331_LDO_RF 0x00000008 +#define CST4331_LDO_PAR 0x00000010 + +/* 4319 chip-specific ChipStatus register bits */ +#define CST4319_SPI_CPULESSUSB 0x00000001 +#define CST4319_SPI_CLK_POL 0x00000002 +#define CST4319_SPI_CLK_PH 0x00000008 +#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */ +#define CST4319_SPROM_OTP_SEL_SHIFT 6 +#define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ +#define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */ +#define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */ +#define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */ +#define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ +#define CST4319_REMAP_SEL_MASK 0x00000600 +#define CST4319_ILPDIV_EN 0x00000800 +#define CST4319_XTAL_PD_POL 0x00001000 +#define CST4319_LPO_SEL 0x00002000 +#define CST4319_RES_INIT_MODE 0x0000c000 +#define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ +#define CST4319_CBUCK_MODE_MASK 0x00060000 +#define CST4319_CBUCK_MODE_BURST 0x00020000 +#define CST4319_CBUCK_MODE_LPBURST 0x00060000 +#define CST4319_RCAL_VALID 0x01000000 +#define CST4319_RCAL_VALUE_MASK 0x3e000000 +#define CST4319_RCAL_VALUE_SHIFT 25 + +/* 4336 chip-specific ChipStatus register bits */ +#define CST4336_SPI_MODE_MASK 0x00000001 +#define CST4336_SPROM_PRESENT 0x00000002 +#define CST4336_OTP_PRESENT 0x00000004 +#define CST4336_ARMREMAP_0 0x00000008 +#define CST4336_ILPDIV_EN_MASK 0x00000010 +#define CST4336_ILPDIV_EN_SHIFT 4 +#define CST4336_XTAL_PD_POL_MASK 0x00000020 +#define CST4336_XTAL_PD_POL_SHIFT 5 +#define CST4336_LPO_SEL_MASK 0x00000040 +#define CST4336_LPO_SEL_SHIFT 6 +#define CST4336_RES_INIT_MODE_MASK 0x00000180 +#define CST4336_RES_INIT_MODE_SHIFT 7 +#define CST4336_CBUCK_MODE_MASK 0x00000600 +#define CST4336_CBUCK_MODE_SHIFT 9 + +/* 4313 chip-specific ChipStatus register bits */ +#define CST4313_SPROM_PRESENT 1 +#define CST4313_OTP_PRESENT 2 +#define CST4313_SPROM_OTP_SEL_MASK 0x00000002 +#define CST4313_SPROM_OTP_SEL_SHIFT 0 + +/* 4313 Chip specific ChipControl register bits */ +#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ #define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \ (sih->chiprev == 0) && \ (sii->coreid[sii->curidx] == MIPS74K_CORE_ID)) +/* Manufacturer Ids */ +#define MFGID_ARM 0x43b +#define MFGID_BRCM 0x4bf +#define MFGID_MIPS 0x4a7 + +/* Enumeration ROM registers */ +#define ER_EROMENTRY 0x000 +#define ER_REMAPCONTROL 0xe00 +#define ER_REMAPSELECT 0xe04 +#define ER_MASTERSELECT 0xe10 +#define ER_ITCR 0xf00 +#define ER_ITIP 0xf04 + +/* Erom entries */ +#define ER_TAG 0xe +#define ER_TAG1 0x6 +#define ER_VALID 1 +#define ER_CI 0 +#define ER_MP 2 +#define ER_ADD 4 +#define ER_END 0xe +#define ER_BAD 0xffffffff + +/* EROM CompIdentA */ +#define CIA_MFG_MASK 0xfff00000 +#define CIA_MFG_SHIFT 20 +#define CIA_CID_MASK 0x000fff00 +#define CIA_CID_SHIFT 8 +#define CIA_CCL_MASK 0x000000f0 +#define CIA_CCL_SHIFT 4 + +/* EROM CompIdentB */ +#define CIB_REV_MASK 0xff000000 +#define CIB_REV_SHIFT 24 +#define CIB_NSW_MASK 0x00f80000 +#define CIB_NSW_SHIFT 19 +#define CIB_NMW_MASK 0x0007c000 +#define CIB_NMW_SHIFT 14 +#define CIB_NSP_MASK 0x00003e00 +#define CIB_NSP_SHIFT 9 +#define CIB_NMP_MASK 0x000001f0 +#define CIB_NMP_SHIFT 4 + +/* EROM AddrDesc */ +#define AD_ADDR_MASK 0xfffff000 +#define AD_SP_MASK 0x00000f00 +#define AD_SP_SHIFT 8 +#define AD_ST_MASK 0x000000c0 +#define AD_ST_SHIFT 6 +#define AD_ST_SLAVE 0x00000000 +#define AD_ST_BRIDGE 0x00000040 +#define AD_ST_SWRAP 0x00000080 +#define AD_ST_MWRAP 0x000000c0 +#define AD_SZ_MASK 0x00000030 +#define AD_SZ_SHIFT 4 +#define AD_SZ_4K 0x00000000 +#define AD_SZ_8K 0x00000010 +#define AD_SZ_16K 0x00000020 +#define AD_SZ_SZD 0x00000030 +#define AD_AG32 0x00000008 +#define AD_ADDR_ALIGN 0x00000fff +#define AD_SZ_BASE 0x00001000 /* 4KB */ + +/* EROM SizeDesc */ +#define SD_SZ_MASK 0xfffff000 +#define SD_SG32 0x00000008 +#define SD_SZ_ALIGN 0x00000fff + +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */ +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */ + +/* power control defines */ +#define PLL_DELAY 150 /* us pll on delay */ +#define FREF_DELAY 200 /* us fref change delay */ +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ + +/* resetctrl */ +#define AIRC_RESET 1 + +typedef volatile struct _aidmp { + u32 oobselina30; /* 0x000 */ + u32 oobselina74; /* 0x004 */ + u32 PAD[6]; + u32 oobselinb30; /* 0x020 */ + u32 oobselinb74; /* 0x024 */ + u32 PAD[6]; + u32 oobselinc30; /* 0x040 */ + u32 oobselinc74; /* 0x044 */ + u32 PAD[6]; + u32 oobselind30; /* 0x060 */ + u32 oobselind74; /* 0x064 */ + u32 PAD[38]; + u32 oobselouta30; /* 0x100 */ + u32 oobselouta74; /* 0x104 */ + u32 PAD[6]; + u32 oobseloutb30; /* 0x120 */ + u32 oobseloutb74; /* 0x124 */ + u32 PAD[6]; + u32 oobseloutc30; /* 0x140 */ + u32 oobseloutc74; /* 0x144 */ + u32 PAD[6]; + u32 oobseloutd30; /* 0x160 */ + u32 oobseloutd74; /* 0x164 */ + u32 PAD[38]; + u32 oobsynca; /* 0x200 */ + u32 oobseloutaen; /* 0x204 */ + u32 PAD[6]; + u32 oobsyncb; /* 0x220 */ + u32 oobseloutben; /* 0x224 */ + u32 PAD[6]; + u32 oobsyncc; /* 0x240 */ + u32 oobseloutcen; /* 0x244 */ + u32 PAD[6]; + u32 oobsyncd; /* 0x260 */ + u32 oobseloutden; /* 0x264 */ + u32 PAD[38]; + u32 oobaextwidth; /* 0x300 */ + u32 oobainwidth; /* 0x304 */ + u32 oobaoutwidth; /* 0x308 */ + u32 PAD[5]; + u32 oobbextwidth; /* 0x320 */ + u32 oobbinwidth; /* 0x324 */ + u32 oobboutwidth; /* 0x328 */ + u32 PAD[5]; + u32 oobcextwidth; /* 0x340 */ + u32 oobcinwidth; /* 0x344 */ + u32 oobcoutwidth; /* 0x348 */ + u32 PAD[5]; + u32 oobdextwidth; /* 0x360 */ + u32 oobdinwidth; /* 0x364 */ + u32 oobdoutwidth; /* 0x368 */ + u32 PAD[37]; + u32 ioctrlset; /* 0x400 */ + u32 ioctrlclear; /* 0x404 */ + u32 ioctrl; /* 0x408 */ + u32 PAD[61]; + u32 iostatus; /* 0x500 */ + u32 PAD[127]; + u32 ioctrlwidth; /* 0x700 */ + u32 iostatuswidth; /* 0x704 */ + u32 PAD[62]; + u32 resetctrl; /* 0x800 */ + u32 resetstatus; /* 0x804 */ + u32 resetreadid; /* 0x808 */ + u32 resetwriteid; /* 0x80c */ + u32 PAD[60]; + u32 errlogctrl; /* 0x900 */ + u32 errlogdone; /* 0x904 */ + u32 errlogstatus; /* 0x908 */ + u32 errlogaddrlo; /* 0x90c */ + u32 errlogaddrhi; /* 0x910 */ + u32 errlogid; /* 0x914 */ + u32 errloguser; /* 0x918 */ + u32 errlogflags; /* 0x91c */ + u32 PAD[56]; + u32 intstatus; /* 0xa00 */ + u32 PAD[127]; + u32 config; /* 0xe00 */ + u32 PAD[63]; + u32 itcr; /* 0xf00 */ + u32 PAD[3]; + u32 itipooba; /* 0xf10 */ + u32 itipoobb; /* 0xf14 */ + u32 itipoobc; /* 0xf18 */ + u32 itipoobd; /* 0xf1c */ + u32 PAD[4]; + u32 itipoobaout; /* 0xf30 */ + u32 itipoobbout; /* 0xf34 */ + u32 itipoobcout; /* 0xf38 */ + u32 itipoobdout; /* 0xf3c */ + u32 PAD[4]; + u32 itopooba; /* 0xf50 */ + u32 itopoobb; /* 0xf54 */ + u32 itopoobc; /* 0xf58 */ + u32 itopoobd; /* 0xf5c */ + u32 PAD[4]; + u32 itopoobain; /* 0xf70 */ + u32 itopoobbin; /* 0xf74 */ + u32 itopoobcin; /* 0xf78 */ + u32 itopoobdin; /* 0xf7c */ + u32 PAD[4]; + u32 itopreset; /* 0xf90 */ + u32 PAD[15]; + u32 peripherialid4; /* 0xfd0 */ + u32 peripherialid5; /* 0xfd4 */ + u32 peripherialid6; /* 0xfd8 */ + u32 peripherialid7; /* 0xfdc */ + u32 peripherialid0; /* 0xfe0 */ + u32 peripherialid1; /* 0xfe4 */ + u32 peripherialid2; /* 0xfe8 */ + u32 peripherialid3; /* 0xfec */ + u32 componentid0; /* 0xff0 */ + u32 componentid1; /* 0xff4 */ + u32 componentid2; /* 0xff8 */ + u32 componentid3; /* 0xffc */ +} aidmp_t; + /* EROM parsing */ static u32 -get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match) +get_erom_ent(struct si_pub *sih, u32 **eromptr, u32 mask, u32 match) { u32 ent; uint inv = 0, nom = 0; @@ -77,7 +402,7 @@ get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match) } static u32 -get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st, +get_asd(struct si_pub *sih, u32 **eromptr, uint sp, uint ad, uint st, u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh) { u32 asd, sz, szd; @@ -116,7 +441,7 @@ static void ai_hwfixup(si_info_t *sii) } /* parse the enumeration rom to identify all cores */ -void ai_scan(si_t *sih, void *regs, uint devid) +void ai_scan(struct si_pub *sih, void *regs, uint devid) { si_info_t *sii = SI_INFO(sih); chipcregs_t *cc = (chipcregs_t *) regs; @@ -319,7 +644,7 @@ void ai_scan(si_t *sih, void *regs, uint devid) /* This function changes the logical "focus" to the indicated core. * Return the current core's virtual address. */ -void *ai_setcoreidx(si_t *sih, uint coreidx) +void *ai_setcoreidx(struct si_pub *sih, uint coreidx) { si_info_t *sii = SI_INFO(sih); u32 addr = sii->coresba[coreidx]; @@ -368,13 +693,13 @@ void *ai_setcoreidx(si_t *sih, uint coreidx) } /* Return the number of address spaces in current core */ -int ai_numaddrspaces(si_t *sih) +int ai_numaddrspaces(struct si_pub *sih) { return 2; } /* Return the address of the nth address space in the current core */ -u32 ai_addrspace(si_t *sih, uint asidx) +u32 ai_addrspace(struct si_pub *sih, uint asidx) { si_info_t *sii; uint cidx; @@ -393,7 +718,7 @@ u32 ai_addrspace(si_t *sih, uint asidx) } /* Return the size of the nth address space in the current core */ -u32 ai_addrspacesize(si_t *sih, uint asidx) +u32 ai_addrspacesize(struct si_pub *sih, uint asidx) { si_info_t *sii; uint cidx; @@ -411,7 +736,7 @@ u32 ai_addrspacesize(si_t *sih, uint asidx) } } -uint ai_flag(si_t *sih) +uint ai_flag(struct si_pub *sih) { si_info_t *sii; aidmp_t *ai; @@ -426,11 +751,11 @@ uint ai_flag(si_t *sih) return R_REG(&ai->oobselouta30) & 0x1f; } -void ai_setint(si_t *sih, int siflag) +void ai_setint(struct si_pub *sih, int siflag) { } -uint ai_corevendor(si_t *sih) +uint ai_corevendor(struct si_pub *sih) { si_info_t *sii; u32 cia; @@ -440,7 +765,7 @@ uint ai_corevendor(si_t *sih) return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT; } -uint ai_corerev(si_t *sih) +uint ai_corerev(struct si_pub *sih) { si_info_t *sii; u32 cib; @@ -450,7 +775,7 @@ uint ai_corerev(si_t *sih) return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT; } -bool ai_iscoreup(si_t *sih) +bool ai_iscoreup(struct si_pub *sih) { si_info_t *sii; aidmp_t *ai; @@ -463,7 +788,7 @@ bool ai_iscoreup(si_t *sih) && ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0)); } -void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val) +void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val) { si_info_t *sii; aidmp_t *ai; @@ -485,7 +810,7 @@ void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val) } } -u32 ai_core_cflags(si_t *sih, u32 mask, u32 val) +u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val) { si_info_t *sii; aidmp_t *ai; @@ -508,7 +833,7 @@ u32 ai_core_cflags(si_t *sih, u32 mask, u32 val) return R_REG(&ai->ioctrl); } -u32 ai_core_sflags(si_t *sih, u32 mask, u32 val) +u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val) { si_info_t *sii; aidmp_t *ai; @@ -542,7 +867,8 @@ static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, static void ai_nvram_process(si_info_t *sii, char *pvars); /* dev path concatenation util */ -static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name); +static char *ai_devpathvar(struct si_pub *sih, char *var, int len, + const char *name); static bool _ai_clkctl_cc(si_info_t *sii, uint mode); static bool ai_ispcie(si_info_t *sii); @@ -558,7 +884,7 @@ static u32 ai_gpioreservation; * vars - pointer to a pointer area for "environment" variables * varsz - pointer to int to return the size of the vars */ -si_t *ai_attach(uint devid, void *regs, uint bustype, +struct si_pub *ai_attach(uint devid, void *regs, uint bustype, void *sdh, char **vars, uint *varsz) { si_info_t *sii; @@ -578,7 +904,7 @@ si_t *ai_attach(uint devid, void *regs, uint bustype, sii->vars = vars ? *vars : NULL; sii->varsz = varsz ? *varsz : 0; - return (si_t *) sii; + return (struct si_pub *) sii; } /* global kernel resource */ @@ -859,9 +1185,6 @@ static si_info_t *ai_doattach(si_info_t *sii, uint devid, udelay(10); } - /* Init nvram from flash if it exists */ - nvram_init(); - /* Init nvram from sprom/otp if they exist */ if (srom_var_init (&sii->pub, bustype, regs, vars, varsz)) { @@ -950,13 +1273,13 @@ static si_info_t *ai_doattach(si_info_t *sii, uint devid, } /* may be called with core in reset */ -void ai_detach(si_t *sih) +void ai_detach(struct si_pub *sih) { si_info_t *sii; uint idx; struct si_pub *si_local = NULL; - bcopy(&sih, &si_local, sizeof(si_t **)); + memcpy(&si_local, &sih, sizeof(struct si_pub **)); sii = SI_INFO(sih); @@ -970,8 +1293,6 @@ void ai_detach(si_t *sih) sii->regs[idx] = NULL; } - nvram_exit(); /* free up nvram buffers */ - if (sih->bustype == PCI_BUS) { if (sii->pch) pcicore_deinit(sii->pch); @@ -984,7 +1305,8 @@ void ai_detach(si_t *sih) /* register driver interrupt disabling and restoring callback functions */ void -ai_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, +ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn, + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg) { si_info_t *sii; @@ -1000,7 +1322,7 @@ ai_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, sii->dev_coreid = sii->coreid[sii->curidx]; } -void ai_deregister_intr_callback(si_t *sih) +void ai_deregister_intr_callback(struct si_pub *sih) { si_info_t *sii; @@ -1008,7 +1330,7 @@ void ai_deregister_intr_callback(si_t *sih) sii->intrsoff_fn = NULL; } -uint ai_coreid(si_t *sih) +uint ai_coreid(struct si_pub *sih) { si_info_t *sii; @@ -1016,7 +1338,7 @@ uint ai_coreid(si_t *sih) return sii->coreid[sii->curidx]; } -uint ai_coreidx(si_t *sih) +uint ai_coreidx(struct si_pub *sih) { si_info_t *sii; @@ -1024,13 +1346,13 @@ uint ai_coreidx(si_t *sih) return sii->curidx; } -bool ai_backplane64(si_t *sih) +bool ai_backplane64(struct si_pub *sih) { return (sih->cccaps & CC_CAP_BKPLN64) != 0; } /* return index of coreid or BADIDX if not found */ -uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit) +uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit) { si_info_t *sii; uint found; @@ -1056,7 +1378,7 @@ uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit) * Moreover, callers should keep interrupts off during switching * out of and back to d11 core. */ -void *ai_setcore(si_t *sih, uint coreid, uint coreunit) +void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit) { uint idx; @@ -1068,7 +1390,8 @@ void *ai_setcore(si_t *sih, uint coreid, uint coreunit) } /* Turn off interrupt as required by ai_setcore, before switch core */ -void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val) +void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx, + uint *intr_val) { void *cc; si_info_t *sii; @@ -1093,7 +1416,7 @@ void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val) } /* restore coreidx and restore interrupt */ -void ai_restore_core(si_t *sih, uint coreid, uint intr_val) +void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val) { si_info_t *sii; @@ -1106,7 +1429,7 @@ void ai_restore_core(si_t *sih, uint coreid, uint intr_val) INTR_RESTORE(sii, intr_val); } -void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val) +void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val) { si_info_t *sii = SI_INFO(sih); u32 *w = (u32 *) sii->curwrap; @@ -1124,7 +1447,8 @@ void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val) * Also, when using pci/pcie, we can optimize away the core switching for pci * registers and (on newer pci cores) chipcommon registers. */ -uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) +uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask, + uint val) { uint origidx = 0; u32 *r = NULL; @@ -1208,7 +1532,7 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) return w; } -void ai_core_disable(si_t *sih, u32 bits) +void ai_core_disable(struct si_pub *sih, u32 bits) { si_info_t *sii; u32 dummy; @@ -1235,7 +1559,7 @@ void ai_core_disable(si_t *sih, u32 bits) * bits - core specific bits that are set during and after reset sequence * resetbits - core specific bits that are set only during reset sequence */ -void ai_core_reset(si_t *sih, u32 bits, u32 resetbits) +void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits) { si_info_t *sii; aidmp_t *ai; @@ -1352,7 +1676,7 @@ static void ai_clkctl_setdelay(si_info_t *sii, void *chipcregs) } /* initialize power control delay registers */ -void ai_clkctl_init(si_t *sih) +void ai_clkctl_init(struct si_pub *sih) { si_info_t *sii; uint origidx = 0; @@ -1390,7 +1714,7 @@ void ai_clkctl_init(si_t *sih) * return the value suitable for writing to the * dot11 core FAST_PWRUP_DELAY register */ -u16 ai_clkctl_fast_pwrup_delay(si_t *sih) +u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) { si_info_t *sii; uint origidx = 0; @@ -1438,7 +1762,7 @@ u16 ai_clkctl_fast_pwrup_delay(si_t *sih) } /* turn primary xtal and/or pll off/on */ -int ai_clkctl_xtal(si_t *sih, uint what, bool on) +int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on) { si_info_t *sii; u32 in, out, outen; @@ -1515,7 +1839,7 @@ int ai_clkctl_xtal(si_t *sih, uint what, bool on) * this is a wrapper over the next internal function * to allow flexible policy settings for outside caller */ -bool ai_clkctl_cc(si_t *sih, uint mode) +bool ai_clkctl_cc(struct si_pub *sih, uint mode) { si_info_t *sii; @@ -1624,7 +1948,7 @@ static bool _ai_clkctl_cc(si_info_t *sii, uint mode) } /* Build device path. Support SI, PCI, and JTAG for now. */ -int ai_devpath(si_t *sih, char *path, int size) +int ai_devpath(struct si_pub *sih, char *path, int size) { int slen; @@ -1657,7 +1981,7 @@ int ai_devpath(si_t *sih, char *path, int size) } /* Get a variable, but only if it has a devpath prefix */ -char *ai_getdevpathvar(si_t *sih, const char *name) +char *ai_getdevpathvar(struct si_pub *sih, const char *name) { char varname[SI_DEVPATH_BUFSZ + 32]; @@ -1667,7 +1991,7 @@ char *ai_getdevpathvar(si_t *sih, const char *name) } /* Get a variable, but only if it has a devpath prefix */ -int ai_getdevpathintvar(si_t *sih, const char *name) +int ai_getdevpathintvar(struct si_pub *sih, const char *name) { #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS) return getintvar(NULL, name); @@ -1680,7 +2004,7 @@ int ai_getdevpathintvar(si_t *sih, const char *name) #endif } -char *ai_getnvramflvar(si_t *sih, const char *name) +char *ai_getnvramflvar(struct si_pub *sih, const char *name) { return getvar(NULL, name); } @@ -1690,7 +2014,8 @@ char *ai_getnvramflvar(si_t *sih, const char *name) * len == 0 or var is NULL, var is still returned. On overflow, the * first char will be set to '\0'. */ -static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name) +static char *ai_devpathvar(struct si_pub *sih, char *var, int len, + const char *name) { uint path_len; @@ -1726,7 +2051,7 @@ static __used bool ai_ispcie(si_info_t *sii) return true; } -bool ai_pci_war16165(si_t *sih) +bool ai_pci_war16165(struct si_pub *sih) { si_info_t *sii; @@ -1735,7 +2060,7 @@ bool ai_pci_war16165(si_t *sih) return PCI(sii) && (sih->buscorerev <= 10); } -void ai_pci_up(si_t *sih) +void ai_pci_up(struct si_pub *sih) { si_info_t *sii; @@ -1754,7 +2079,7 @@ void ai_pci_up(si_t *sih) } /* Unconfigure and/or apply various WARs when system is going to sleep mode */ -void ai_pci_sleep(si_t *sih) +void ai_pci_sleep(struct si_pub *sih) { si_info_t *sii; @@ -1764,7 +2089,7 @@ void ai_pci_sleep(si_t *sih) } /* Unconfigure and/or apply various WARs when going down */ -void ai_pci_down(si_t *sih) +void ai_pci_down(struct si_pub *sih) { si_info_t *sii; @@ -1785,10 +2110,10 @@ void ai_pci_down(si_t *sih) * Configure the pci core for pci client (NIC) action * coremask is the bitvec of cores by index to be enabled. */ -void ai_pci_setup(si_t *sih, uint coremask) +void ai_pci_setup(struct si_pub *sih, uint coremask) { si_info_t *sii; - struct sbpciregs *pciregs = NULL; + void *regs = NULL; u32 siflag = 0, w; uint idx = 0; @@ -1805,7 +2130,7 @@ void ai_pci_setup(si_t *sih, uint coremask) siflag = ai_flag(sih); /* switch over to pci core */ - pciregs = ai_setcoreidx(sih, sii->pub.buscoreidx); + regs = ai_setcoreidx(sih, sii->pub.buscoreidx); } /* @@ -1823,16 +2148,7 @@ void ai_pci_setup(si_t *sih, uint coremask) } if (PCI(sii)) { - OR_REG(&pciregs->sbtopci2, - (SBTOPCI_PREF | SBTOPCI_BURST)); - if (sii->pub.buscorerev >= 11) { - OR_REG(&pciregs->sbtopci2, - SBTOPCI_RC_READMULTI); - w = R_REG(&pciregs->clkrun); - W_REG(&pciregs->clkrun, - (w | PCI_CLKRUN_DSBL)); - w = R_REG(&pciregs->clkrun); - } + pcicore_pci_setup(sii->pch, regs); /* switch back to previous core */ ai_setcoreidx(sih, idx); @@ -1843,13 +2159,10 @@ void ai_pci_setup(si_t *sih, uint coremask) * Fixup SROMless PCI device's configuration. * The current core may be changed upon return. */ -int ai_pci_fixcfg(si_t *sih) +int ai_pci_fixcfg(struct si_pub *sih) { - uint origidx, pciidx; - struct sbpciregs *pciregs = NULL; - sbpcieregs_t *pcieregs = NULL; + uint origidx; void *regs = NULL; - u16 val16, *reg16 = NULL; si_info_t *sii = SI_INFO(sih); @@ -1858,23 +2171,8 @@ int ai_pci_fixcfg(si_t *sih) origidx = ai_coreidx(&sii->pub); /* check 'pi' is correct and fix it if not */ - if (sii->pub.buscoretype == PCIE_CORE_ID) { - pcieregs = ai_setcore(&sii->pub, PCIE_CORE_ID, 0); - regs = pcieregs; - reg16 = &pcieregs->sprom[SRSH_PI_OFFSET]; - } else if (sii->pub.buscoretype == PCI_CORE_ID) { - pciregs = ai_setcore(&sii->pub, PCI_CORE_ID, 0); - regs = pciregs; - reg16 = &pciregs->sprom[SRSH_PI_OFFSET]; - } - pciidx = ai_coreidx(&sii->pub); - val16 = R_REG(reg16); - if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) { - val16 = - (u16) (pciidx << SRSH_PI_SHIFT) | (val16 & - ~SRSH_PI_MASK); - W_REG(reg16, val16); - } + regs = ai_setcore(&sii->pub, sii->pub.buscoretype, 0); + pcicore_fixcfg(sii->pch, regs); /* restore the original index */ ai_setcoreidx(&sii->pub, origidx); @@ -1884,7 +2182,7 @@ int ai_pci_fixcfg(si_t *sih) } /* mask&set gpiocontrol bits */ -u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority) +u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority) { uint regoff; @@ -1904,7 +2202,7 @@ u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority) return ai_corereg(sih, SI_CC_IDX, regoff, mask, val); } -void ai_chipcontrl_epa4331(si_t *sih, bool on) +void ai_chipcontrl_epa4331(struct si_pub *sih, bool on) { si_info_t *sii; chipcregs_t *cc; @@ -1938,7 +2236,7 @@ void ai_chipcontrl_epa4331(si_t *sih, bool on) } /* Enable BT-COEX & Ex-PA for 4313 */ -void ai_epa_4313war(si_t *sih) +void ai_epa_4313war(struct si_pub *sih) { si_info_t *sii; chipcregs_t *cc; @@ -1957,7 +2255,7 @@ void ai_epa_4313war(si_t *sih) } /* check if the device is removed */ -bool ai_deviceremoved(si_t *sih) +bool ai_deviceremoved(struct si_pub *sih) { u32 w; si_info_t *sii; @@ -1974,7 +2272,7 @@ bool ai_deviceremoved(si_t *sih) return false; } -bool ai_is_sprom_available(si_t *sih) +bool ai_is_sprom_available(struct si_pub *sih) { if (sih->ccrev >= 31) { si_info_t *sii; @@ -2011,7 +2309,7 @@ bool ai_is_sprom_available(si_t *sih) } } -bool ai_is_otp_disabled(si_t *sih) +bool ai_is_otp_disabled(struct si_pub *sih) { switch (sih->chip) { case BCM4329_CHIP_ID: @@ -2039,14 +2337,14 @@ bool ai_is_otp_disabled(si_t *sih) } } -bool ai_is_otp_powered(si_t *sih) +bool ai_is_otp_powered(struct si_pub *sih) { if (PMUCTL_ENAB(sih)) return si_pmu_is_otp_powered(sih); return true; } -void ai_otp_power(si_t *sih, bool on) +void ai_otp_power(struct si_pub *sih, bool on) { if (PMUCTL_ENAB(sih)) si_pmu_otp_power(sih, on); |