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2014-03-26Remove mapping from DMA map list during unmapRoy Pledge
The DMA mapping record was not being removed from a processes DMA map when dma_mem_destroy() is called. This made it impossible to remap the same named segment without restarting the process Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: I2b92a022e6cb7815056567487688c39774a5008f Reviewed-on: http://git.am.freescale.net:8181/10180 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-26qbman: Added DQRR cleanup when portal is not in cdc modeVakul Garg
To acknowledge a DQRR entry, the portal should be preserved in same mode as it was when the DQRR entry was created. Function qm_dqrr_init() is invoked when a raw portal is released back. The raw portal could be either in one of cci or cci or cdc modes. So while cleaning up a portal using qm_dqrr_init(), the dqrr consumption mode should be read and accordingly approriate DQRR consumption routine should be invoked. Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: I07b412915cd483060147a845cfe935d0bd7f2024 Reviewed-on: http://git.am.freescale.net:8181/9634 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Roy Pledge <roy.pledge@freescale.com> Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-26gianfar: Compile out multi-queue pollingClaudiu Manoil
Multi-Queue polling support is phasing out, as it imposes unnecessary processing overhead that degenerates in Tx congestion and even Tx timeout. Its place is taken by Single-Queue polling and all the currently supported gianfar devices already work in Single-Queue polling mode. So the Multi-Queue polling may be compiled out, for better performance (i.e. icache utilization). Change-Id: I1f1ff4edd112606135e6c99780fd54f333cdb0e9 Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9990 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25Add 64byte FiFo mode UART support for FSL platformsPriyanka Jain
T1040 FSL SoC has new version of UART controller which can support 64byte FiFo. Add suuport to enable 64byte FiFO mode -FCR[EN64] needs to be programmed to 1 to enable it. -Also, when FCR[EN64]==1, RTL bits to be used as below to define various Receive Trigger Levels: -FCR[RTL] = 00 1 byte -FCR[RTL] = 01 16 bytes -FCR[RTL] = 10 32 bytes -FCR[RTL] = 11 56 bytes -tx_loadsz is set tp 32bytes, As some issues are observed with 64-byte mode which looks to be Si issue. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Change-Id: I0b32f3230bd1c9674a2e85cc4e5a16869dbaa9af Reviewed-on: http://git.am.freescale.net:8181/10215 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/fsl-booke: Add T1042RDB_PI board supportPriyanka Jain
T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port Add support for T1040 RDB board: -add device tree -Add entry corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: If3b9122a044312ce458739883aafa65c2436e1e1 Reviewed-on: http://git.am.freescale.net:8181/10136 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/fsl-booke: Add initial T1040RDB board supportPriyanka Jain
T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Add support for T1040 RDB board: -add device tree -add entry in Kconfig to build -Add entry corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Signed-off-by: Alex MARGINEAN <alexandru.marginean@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: I74d0240522572912995754aecfc3b2d15a48f9fe Reviewed-on: http://git.am.freescale.net:8181/10135 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/fsl-booke: Add initial T104x_QDS board supportPriyanka Jain
T104xQDS board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI Express: supporting Gen 1 and Gen 2 - SGMII - QSGMII - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. - IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep (T1040 only) - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - Second port can be converted to OTG mini-AB - SD/MMC Interface - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC - Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - TDM - QE-TDM - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Add support for T104x QDS board (T1040QDS, T1042QDS): -add device tree -add entry is added in corenet_generic.c as it is similar to other corenet platforms. -add entry in Kconfig to build -add t1040_32bit_smp_defconfig, t1040_64bit_smp_defconfig -T1040 has FMANv3, hence CONFIG_FMAN_T4240 needs to be defined. -So corenet32_smp_defconfig and corenet64_smp_defconfig cannot be used. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Signed-off-by: Alex Marginean <alexandru.marginean@freescale.com> Signed-off-by: Razvan Stefanescu <razvan.stefanescu@freescale.com> Signed-off-by: Nikhil Badola <Nikhil.Badola@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: Icfd66c050fbbc39a8693e6b00550736fa9313e12 Reviewed-on: http://git.am.freescale.net:8181/10134 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/mpc85xx:Add T104x device tree supportPriyanka Jain
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA processor cores with high-performance data path acceleration architecture and network peripheral interfaces required for networking & telecommunications. T1042 personality is a reduced personality of T1040 without Integrated 8-port Gigabit Ethernet switch. The T1040/T1042 SoC includes the following function and features: - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration (SEC 5.0) - RegEx Pattern Matching Acceleration (PME 2.2) - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch (T1040 only) - Four 1 Gbps Ethernet controllers - Two RGMII interfaces or one RGMII and one MII interfaces - High speed peripheral interfaces - Four PCI Express 2.0 controllers running at up to 5 GHz - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation - Upto two QSGMII interface - Upto six SGMII interface supporting 1000 Mbps - One SGMII interface supporting upto 2500 Mbps - Additional peripheral interfaces - Two USB 2.0 controllers with integrated PHY - SD/eSDHC/eMMC - eSPI controller - Four I2C controllers - Four UARTs - Four GPIO controllers - Integrated flash controller (IFC) - LCD/ HDMI interface (DIU) with 12 bit dual data rate - TDM interface: QE, SLIC - Multicore programmable interrupt controller (PIC) - Two 8-channel DMA engines - Single source clocking implementation - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Signed-off-by: Alex Marginean <alexandru.marginean@freescale.com> Signed-off-by: Razvan Stefanescu <razvan.stefanescu@freescale.com> Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Ganga Negi <ganga.negi@freescale.com> Signed-off-by: Nikhil Badola <Nikhil.Badola@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: Ib0a9e1a717080fd246b308a049f0f57beb4fe048 Reviewed-on: http://git.am.freescale.net:8181/10133 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24drivers/net: support hdlc function for QE-UCCZhao Qiang
The driver add hdlc support for Freescale QUICC Engine. It support NMSI and TSA mode. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: Iece969b4934241f0f1cb574c5014600ef63cfb95 Reviewed-on: http://git.am.freescale.net:8181/10113 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24dpaa_eth: add print for proxy probeMarian Rotariu
There is no indication that the proxy interface successfully initialized the attached MAC device. In this way, the user does not know if the device tree is misconfigured or the MAC device successfully probed. Other ways to check the MAC initialization exists, like MAC mem mapped registers, but a simple message in the bootlog seems way more user-friendly. Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com> Change-Id: I79b38719e6b49d8a4557b885a2b13854961f9b32 Reviewed-on: http://git.am.freescale.net:8181/9258 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit f217d812c07a1be0563dffe40f4736442b5f99ee) Reviewed-on: http://git.am.freescale.net:8181/9263
2014-03-24dpaa_eth: fix bp initializationMarian Rotariu
Currently, if macless or shared Ethernet drivers have several buffer pools only the first buffer pool will be initialized with a seeding procedure. With this patch all configured buffer pools will have a seeding procedure. Also, this patch removes unnecessary BUG_ON() from the bp initialization function and fixes the release of bp structures. Change-Id: Ie1fe6689867e921ccc75afbf50dfd5560c9216e9 Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9873 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: Ruxandra Ioana Radulescu <ruxandra.radulescu@freescale.com> (cherry picked from commit fda11c93afa1bdb71e34d07509305ff0df4a62a0) Reviewed-on: http://git.am.freescale.net:8181/10176
2014-03-24t2080qds/dts: remove nand partitions in dtsShengzhou Liu
we use mtdparts way to setup the partitions of flash devices instead of putting partitions info in dts. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I74abccf2c32f5f4da8cccf4aec3a85814d4718af Reviewed-on: http://git.am.freescale.net:8181/10014 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24QE-TDM: Add PM support for QE-TDMJiucheng Xu
Add suspend and resume function to qe-tdm. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I81cac61575196957d28071ebf3f77be848494ff7 Reviewed-on: http://git.am.freescale.net:8181/9216 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10111
2014-03-24QE-TDM: add support to make QE-TDM work on 36bit physical addressJiucheng Xu
Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I3841888a780f6d4d3d38589c5de4cdd3916921ef Reviewed-on: http://git.am.freescale.net:8181/9214 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10110
2014-03-24Corenet: Add QE platform support for CorenetZhao Qiang
There is QE on platform T104x, add support. Call funcs qe_ic_init and qe_init if CONFIG_QUICC_ENGINE is defined. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I7d33f4237aabadfc63d4e55d96ebdb64fb396736 Reviewed-on: http://git.am.freescale.net:8181/10099 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24split function mpc85xx_qe_init() into two functions.Zhao Qiang
micro QE is a kind of cutted QE, it has only 2 UCCs while normal QE has up to 8 UCCs. micro QE doesn't have par_io, it doesn't need to init par_io for micro QE. Split function mpc85xx_qe_init() into mpc85xx_qe_init() and mpc85xx_qe_par_io_init(). Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I267d044d6b0c6ff1c4bba984566d430e6b3dc682 Reviewed-on: http://git.am.freescale.net:8181/10098 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/85xx: Add QE common init functionZhao Qiang
Define a QE init function in common file, and avoid the same codes being duplicated in board files. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I394c2eac02ef40fb923b5ee5f74e919065f8a4ac Reviewed-on: http://git.am.freescale.net:8181/10106 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24qe-tdm/ucc: modify an "if conditions error"Zhao Qiang
There is an "if condition" uncorrect, modify it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I5c3931a34e41c0eec34aead95254a37e919c45bb Reviewed-on: http://git.am.freescale.net:8181/10097 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24fsl/usb: Add support for USB controller version-2.5Nikhil Badola
Support added for USB controller version-2.5 used in T4240 rev2.0, T1023, B3421, T1040, T2080 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: Ib45b486a23d177ef3570ee234fe9a5af06f36b43 Reviewed-on: http://git.am.freescale.net:8181/9643 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/t4240: Change t4240 USB controller versionNikhil Badola
Change USB controller version to 2.5 in compatible string for T4240 rev2.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I92aa23cee236c13547b59bf62ef68f1d6002f2ff Reviewed-on: http://git.am.freescale.net:8181/9638 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/t2080: Change t2080 USB controller version Nikhil Badola
Change USB controller version to 2.5 in compatible string for T2080 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289 Reviewed-on: http://git.am.freescale.net:8181/7459 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit cd37bcac41666cccb7fdf84e475967630848d257) Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289 Reviewed-on: http://git.am.freescale.net:8181/9835 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24added support for PKC keygenYashpal Dutta
As a part of PKC support, RSA, DSA DH, ECDH, ECDSA requires key generation. The patch adds support for key generation support for DSA, ECDSA, DH, ECDH. The patch adds DH operation support too Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: I0dc9c144a23e2248bf8974a1615363341dc4886e Reviewed-on: http://git.am.freescale.net:8181/5867 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9551 Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24caam driver updates for public key cryptographyYashpal Dutta
CAAM driver updates as per public key infrastructure changes in cryptoAPI RSA, DSA, ECDSA are support as part of Public Key Crypto Operations Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: I3a6e4f71866a5ef157b9ea13e618c4d3d209f558 Reviewed-on: http://git.am.freescale.net:8181/5839 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9546 Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24Power Management support for CAAMYashpal Dutta
Platform can go in sleep where CAAM will remain power ON while in some cases CAAM will be powered off during deep-sleep. The patch handles graceful recovery of CAAM state in both the power-up and powered-down cases across deep-sleep. Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: Ie27fdfa78fc50c9a05f6316938ad42a70a89a48e Reviewed-on: http://git.am.freescale.net:8181/9771 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10085
2014-03-24power management support in caam job ring driverYashpal Dutta
Job ring is suspended gracefully and resume afresh. Pending Jobs not yet processed by CAAM are marked with error for producer to either discard Job or retry after resume. UIO based Job Rings are not handled by this patch. Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: I654734c460e0307243884a076350602ccb97a15a Reviewed-on: http://git.am.freescale.net:8181/9772 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9988
2014-03-24gianfar: Fix P1010 config regression (SQ polling)Claudiu Manoil
The P1010 device tree restricts the number of supported interrupt groups to 1, although the eth controller can support 2 interrupt groups and the driver assumes the Multi-Group mode ("fsl,etsec2" model). So, in this case the assumption that the Multi-Group mode (MQ_MG_MODE) devices always support 2 interrupt groups is false. To fix this, a check for the actual number of interrupt groups enabled in the board's device tree has been added in gfar_probe for the "fsl,etsec2" devices. Without this fix, P1010 based boards claim support for 2 Tx queues to the net stack but only one is actually allocated, leading to NULL access in xmit. This issue was introduced by enabling Single-Queue polling for the P1010 devices. Change-Id: I74e2d143557a7e2cebce8928ac42160e79957f0c Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9876 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-03-21dpa_offload: Add dts files for offloading apps on T2080Aurelian Zanoschi
Added dts files for running the dpa offloading applications on T2080QDS board. Change-Id: Ifa23fc1adbf479e2cc5542db3600ef243b96608e Signed-off-by: Aurelian Zanoschi <Aurelian.Zanoschi@freescale.com> Signed-off-by: Marian Chereji <marian.chereji@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/8821 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21phy: add freescale XFI 10GBASE-KR driverShaohui Xie
To support freescale XFI 10GBASE-KR, the driver comply with IEEE802.3-2008 to do auto-negotiation and link training with link partner(LP) which has capability of 10GBASE-KR. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I1847226078017b4ca74a39f0d611a96f66921d23 Reviewed-on: http://git.am.freescale.net:8181/9918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Heinz Wrobel <Heinz.Wrobel@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21crypto: caam - Check for CAAM block presence before registering with crypto ↵Ruchika Gupta
layer The layer which registers with the crypto API should check for the presence of the CAAM device it is going to use. If the platform's device tree doesn't have the required CAAM node, the layer should return an error and not register the algorithms with crypto API layer. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Change-Id: Idf361e8ae971929c55abdefaa29f9d7bc8441a72 Reviewed-on: http://git.am.freescale.net:8181/10043 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Horia Ioan Geanta Neag <horia.geanta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21mtd: m25p80: Modify the name of mtd_infoHou Zhiqiang
To specify spi flash layouts by "mtdparts=..." in cmdline, we must give mtd_info a fixed name,because the cmdlinepart's parser will match the name of mtd_info given in cmdline. Now, if use DT, the mtd_info's name will be spi->dev->name. It consists of spi_master->bus_num, and the spi_master->bus_num maybe dynamically fetched. So, in this case, replace the component bus_num with thei physical address of spi master. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Change-Id: I36a6105a43ea408507576a98642cf80c2b2837e4 Reviewed-on: http://git.am.freescale.net:8181/10040 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SocsZhang Zhuoyu
According to the data provided by HW Team, at least 12 internal platform clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs. This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition latency to make DFS governors work normally on Freescale e500mc boards. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> Change-Id: Ia86f8c0f49571d697642fe7c4b98e0e9bfe92c03 Reviewed-on: http://git.am.freescale.net:8181/10024 Reviewed-by: Yang Li <LeoLi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21USB: Gadget: fsl driver pullup fixSuresh Gupta
This fix the fsl usb gadget driver in a way that the usb device will be only "pulled up" on requests only when vbus is powered Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: I1ca5d3e7121a12a4e11ab163504180233367eaf6 Reviewed-on: http://git.am.freescale.net:8181/9367 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21USB: Gadget: fsl: Set dma_ops for FSL USB Gadget DeviceSuresh Gupta
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: Ia9191415666afc968e6b29259730eafc8d0e0bdb Reviewed-on: http://git.am.freescale.net:8181/9366 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21crypto: caam - Enabled QI Support for SECNitesh Lal
At the time of merging few changes required for enabling QI support were missed. This patch adds those missing changes and hence enables QI support for SEC. Signed-off-by: Nitesh Lal <NiteshNarayanLal@freescale.com> Change-Id: I190ed1452317cb1f70faaf85f8a69be0a0c5a376 Reviewed-on: http://git.am.freescale.net:8181/9922 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21Ensure that the EQCR Cache Enabled Consumed Index is resetRoy Pledge
The QMan block keeps an internal copy of the CI index when stashing is enabled. In order to synchronize this internal copy with the external view the stash threshold must be set to 1 then 0 otherwise the state of the portal can be bad when it is reallocated by a different process Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: I1b4c0c7f385abb94ae3ff5e988179f0d328e3455 Reviewed-on: http://git.am.freescale.net:8181/9942 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/p1010rdb:update dts for pcie interrupt-mapZhao Qiang
p1010rdb-pb use the irq[4:5] for inta and intb to pcie, it is active-high, so set it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I29db41b4a8b5a67c18151099884edda6de4d9d1a Reviewed-on: http://git.am.freescale.net:8181/9915 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/p1010rdb:update mtd of nand to adapt to both old andZhao Qiang
new p1010rdb P1010rdb-pa and p1010rdb-pb have different mtd of nand. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Move the nand-mtd from p1010rdb.dtsi to p1010rdb-pa.dtsi. Modify p1010rdb-pb's nand-mtd, which can be overwrote from u-boot by set mtdparts. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I9e5652b9aa3136299bd6f8bbee529a153031240b Reviewed-on: http://git.am.freescale.net:8181/9914 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/mpc85xx: fix a build issue when user use mpc85xx_defconfigWang Dongsheng
if we enable cpufreq feature we will get a build error. drivers/cpufreq/mpc85xx-cpufreq.c: In function 'p1022_set_pll': drivers/cpufreq/mpc85xx-cpufreq.c:145:2: error: implicit declaration of function 'get_hard_smp_processor_id' [-Werror=implicit-function-declaration] It's miss a include <asm/smp.h> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I805969b909e269fcfeb1abce30b987baf9c60399 Reviewed-on: http://git.am.freescale.net:8181/9453 Reviewed-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-19powerpc/mpc85xx: Add deep sleep support for IFCPrabhakar Kushwaha
Add support of suspend, resume function to support deep sleep. Also make sure of SRAM initialization during resume. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Change-Id: Ia3d484ff272d6c7feebb74a5ad95f74fb91cdd68 Reviewed-on: http://git.am.freescale.net:8181/9444 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 82a066c3f93441a7e80c1a603ff185ee4d16bf25) Reviewed-on: http://git.am.freescale.net:8181/9928
2014-03-18iommu/fsl: Support for setting up PMAN PAACE entry.Varun Sethi
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I3aeb4ab1c4f91d5a1367fbe8f6ca31fe80357754 Reviewed-on: http://git.am.freescale.net:8181/9620 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: Enable OMT cache, before invalidating PAACT and SPAACT cache.Varun Sethi
Enable OMT cache, before invalidating PAACT and SPAACT cache. This is a PAMU hardware errata work around. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Iecf8dfcbf0ccc535dff4825a046b2badc660ec8b Reviewed-on: http://git.am.freescale.net:8181/9619 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18fsl/qman: Modifications for new stash attribute setup API.Varun Sethi
An additional parameter (window number) is required for API. Add the window number parameter while invoking the API. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7ff2552bf15bee25a7e41fd5e0a1781a323aceed Reviewed-on: http://git.am.freescale.net:8181/9618 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: PAMU driver changes for DSP stasing support.Varun Sethi
Modifications to PAMU driver for supporting DSP stashing. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1462806c85f0f398a332ac321bb7b67a8cabc1bb Reviewed-on: http://git.am.freescale.net:8181/9617 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: Setup operation mapping for FMAN.Varun Sethi
Setup operation mapping for FMAN. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1803c366979a28fe3f547526ee0e2f23a5dd03b7 Reviewed-on: http://git.am.freescale.net:8181/9616 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl : Factor out default PAACE setup code andVarun Sethi
enable all LIODNs. Factor out default PAACE entry setup code and enable all LIODNs for handling the autonomous case. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I31b81576e590569be614511b27d09f01cc4fcf86 Reviewed-on: http://git.am.freescale.net:8181/9615 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18e6500/defconfig: Enabled FSL_UIO_DMAVakul Garg
To enable direct access of DMA channels from user space, CONFIG_UIO_FSL_DMA needs to be turned on. User space DMA driver is used by applications using ipc and usdpaa sdk submodules. Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: Id874ead3d373281614f7638a52b1dc074a648ebe Reviewed-on: http://git.am.freescale.net:8181/9817 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Naveen Burmi <NaveenBurmi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18powerpc/p1010rdb:update dts to adapt to both old and new p1010rdbZhao Qiang
P1010rdb-pa and p1010rdb-pb have different phy interrupts. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I2e80e63576396a8fe726a6306246b16c25744cff Reviewed-on: http://git.am.freescale.net:8181/5607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9593 Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17crypto: caam - use NAPI instead of taskletNitesh Lal
This patch updates the current tasklet implementation to NAPI so as the system is more balanced in the terms that the packet submission and the packet forwarding after being processed can be done at the same priority Signed-off-by: Naveen Burmi <naveenburmi@freescale.com> rebased and tuned NAPI_WEIGHT. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> (cherry picked from commit c74e14d7ff270f8d85c7988e9286f64b721f34ee) Change-Id: I3a31db49a1a6060b3ad5cd0fc4ee4044858438bc Reviewed-on: http://git.am.freescale.net:8181/520 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Signed-off-by: Nitesh Lal <NiteshNarayanLal@freescale.com> Change-Id: I685d687d89a53387287912cd2273f8c1d6a6e4e4 Reviewed-on: http://git.am.freescale.net:8181/9753 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: update fsl_pci_ep.c according to kernel changesMinghuan Lian
1. Now in kernel the dev_attrs field is removed from struct class, and is converted to use dev_groups. So the patch uses pci_ep_groups instead of pci_ep_attrs. 2. The field pci_mem_offset of struct pci_controller has been changed to mem_offset[], so the patch update the related code. 3. Remove is_pcie initialization for this field has been removed from struct pci_dev. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I9a664b79a1528b52728dae60a929afe4b62aa8c2 Reviewed-on: http://git.am.freescale.net:8181/9607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix ATMU window attribute settingMinghuan Lian
If window size is 0, the bits of size will be 0xffffffff, so window attribute will be set a wrong value. The patch fixes this issue. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Ieac8428eb1b41a245c89637186d4eb27eedcff55 Reviewed-on: http://git.am.freescale.net:8181/9606 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
generated by cgit v0.10.2 at 2024-11-17 18:18:37 (GMT)