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application to get back the exact portal it was previously using by specifing the portals index value.
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I8233816f0519731eb65b3671d68a01266eee42dd
Reviewed-on: http://git.am.freescale.net:8181/4002
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: I199d6bedeb045f421da69d8ce99c45bea517fc32
Reviewed-on: http://git.am.freescale.net:8181/3948
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: I613fba4492d3d65dcf903d13735bc9e45e5d443c
Reviewed-on: http://git.am.freescale.net:8181/3731
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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These are required for ALU DSP stashing use case.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I7efacb81b60d23e6e5f91632547f8b9a04028a1f
Reviewed-on: http://git.am.freescale.net:8181/3442
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Setup and operation mapping index for PMAN.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I4384a247491293260c1da1d4cf6cfc3b2bec2034
Reviewed-on: http://git.am.freescale.net:8181/3441
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Stash ID and operation mapping can now be set per dma window.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I987abbcba0575fea1b43843c2bce342f4eae4df2
Reviewed-on: http://git.am.freescale.net:8181/3439
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Conflicts:
drivers/iommu/fsl_pamu.c
drivers/iommu/fsl_pamu.h
drivers/iommu/fsl_pamu_domain.c
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Represent operation mappings as an enum. These have been moved to iommu.h
to support IOMMU API for setting operation mappings per window.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I900274f8ed703b9e10a4b3fb7d6653bd8c3a080d
Reviewed-on: http://git.am.freescale.net:8181/3438
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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This API can be used for setting operation mapping per DMA window.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Iea6d7993f09bddbaae94c475fd192f5106784bde
Reviewed-on: http://git.am.freescale.net:8181/3440
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Conflicts:
drivers/iommu/fsl_pamu.c
drivers/iommu/fsl_pamu.h
drivers/iommu/fsl_pamu_domain.c
Change-Id: Iea6d7993f09bddbaae94c475fd192f5106784bde
Reviewed-on: http://git.am.freescale.net:8181/3440
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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B4860 has 1 PPC core cluster and 3 DSP core clusters.
Similarly B4420 has 1 PPC core cluster and 1 DSP core cluster.
Each DSP core cluster consists of 2 SC3900 cores and a shared L2 cache.
1. Add DSP clusters for B4420
2. Reorganized the L2 cache nodes such that they now appear in only the
soc specific dtsi files(b4860si-post.dtsi and b4420si-post.dtsi).
Earlier they were shown partly in common b4si-post.dtsi and si specific
b4860si-post.dtsi files .
3. Fixed an issue in b4860si-pre.dtsi, now DSP cluster correctly point to their
respective L2 caches
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: Ie09007f4c596fc5947e0b4b005225b8b1f9aa443
Reviewed-on: http://git.am.freescale.net:8181/4005
Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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Buffer pool id for frames enqueued to ipsec_offload inbound macless interface
must match the interface bpid.
Signed-off-by: Alexandru Badicioiu <alexandru.badicioiu@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: If2fda57aaf42719d0a3aae2256d513856583913b
Reviewed-on: http://git.am.freescale.net:8181/3427
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Changes open dma allocation to workaround erratum A006981
Also verify that it applies only to B4-rev1 while rev2 should have this erratum fixed
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: Icc0552269da9ad80763e8ad1394d6ad67ee143a8
Reviewed-on: http://git.am.freescale.net:8181/3428
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: I8bf5700cadb8e40dd68728f8aa78ba1a4d70f054
Reviewed-on: http://git.am.freescale.net:8181/3429
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Prevent sleeping function to be called from invalid context
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: I1fa7619489248c823d55a96b00cc4b7bd75bbf6d
Reviewed-on: http://git.am.freescale.net:8181/3430
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: Icda6a8547559ab45ceea7160cde566ca022e92e8
Reviewed-on: http://git.am.freescale.net:8181/3698
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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It was unused, and confusing efforts to implement support for
EQCR_CI-stashing.
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: Ia390a4b4b54efba60b4e9b12a73b7d1ec88bf530
Reviewed-on: http://git.am.freescale.net:8181/3697
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
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DPA Classifier API was updated by adding a new attribute (hmd)
to the struct dpa_cls_tbl_next_table_desc.
DPA IPSec is using the classifier feature for linking two tables,
if inbound policy verification is required but does not require
the hmd option.
A minor update had to be made to set the hdm
to -1 (not valid) otherwise the 0 value would have been concidered
valid by classifier and crash since not hmd is required here.
Signed-off-by: Andrei Varvara <andrei.varvara@freescale.com>
Change-Id: I76eccbf6a60b7d563540de539be5144112c1567c
Reviewed-on: http://git.am.freescale.net:8181/3474
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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The dpa ipsec component was not supporting ESP with
NULL encryption. The patch is adding this suport.
Signed-off-by: Andrei Varvara <andrei.varvara@freescale.com>
Change-Id: I89111367e60c4592289687b0a13d84ac2911d23c
Reviewed-on: http://git.am.freescale.net:8181/3473
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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This define is required for making descriptors
with NULL encryption.
Change-Id: If71ee727f18f1ea23a6bbe67b03046d526897a52
Signed-off-by: Andrei Varvara <andrei.varvara@freescale.com>
Change-Id: I61ef1a7d6bcf115f99f5160f76154c09e5f7f7da
Reviewed-on: http://git.am.freescale.net:8181/3472
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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userspace during look-up by key or by ref operations
Multicast group and hmanip descriptors were copied to userspace in classifier
wrapper during look-up by key or by ref operations.
The patch fixes the above issue.
Signed-off-by: Radu Bulie <radu.bulie@freescale.com>
Change-Id: Ibba7869bcbe339a3ef23bd4071a3aaa682fe7b9d
Reviewed-on: http://git.am.freescale.net:8181/3353
Reviewed-by: Bulie Radu-Andrei-B37577 <Radu.Bulie@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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by ref operations
Not all parameters were copied to userspace in classifier wrapper during look-up by
key or by ref operations.
The patch fixes the above issue.
Change-Id: I4c33455a327c8dfd6fd0fa28d13cc7e28b856714
Signed-off-by: Radu Bulie <radu.bulie@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/3281
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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FM_PCD_MatchTableGetMissStatistics and FM_PCD_HashTableGetMissStatistics
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: I56a02300f4603245344effc898ff9fdd137d8e4c
Reviewed-on: http://git.am.freescale.net:8181/3905
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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Apparently reset values of B4/T4 in fmd are not completely
reliable. will use this definition to force fman init
values.
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: Id0b16cf7faf8c53ab9741bcd370e27e91a9ab2a0
Reviewed-on: http://git.am.freescale.net:8181/3904
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
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Added support in DPA Stats to retrieve the statistics for
the miss-entry of either a Classification Node or a
Classification Table. The user can request statistics for
miss-entry by providing the key set to NULL. The Classification
counter API was changed in order to allow the user to
provide NULL instead of a valid key.
Signed-off-by: Anca Jeanina FLOAREA <anca.floarea@freescale.com>
Change-Id: Id871766e5cc7b494c934096829e12af15ded7544
Reviewed-on: http://git.am.freescale.net:8181/3830
Reviewed-by: Zanoschi Aurelian-B43522 <Aurelian.Zanoschi@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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Added a new function to query classification table miss action details.
This function is only advertised as internal API and is needed by the
DPA Stats component to acquire Miss Action Statistics.
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Change-Id: If9f506316c887bc44ebd5363c526a8f4fda3da1c
Reviewed-on: http://git.am.freescale.net:8181/3829
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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- miss entry in a CC Node
- miss entry in the hash table
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: Iacbebff6f8f7ef1fa9c97b24d1072515f5098860
Reviewed-on: http://git.am.freescale.net:8181/3828
Reviewed-by: Lavi Mandy-R52568 <Mandy.Lavi@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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- Add dsp nodes in B4860 pre silicon device file
- Add L2 cache nodes for dsp/Starcores in B4860 post silicon file
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: I10329607b97961a44f46bc814032fc9faa0e7f96
Reviewed-on: http://git.am.freescale.net:8181/3693
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject
to a similar race condition as doing mftbu/mftbl on 32-bit. The lower
half of timebase is updated before the upper half; thus, we can share
the workaround for a similar bug on Cell. This workaround involves
looping if the lower half of timebase is zero, thus avoiding the need
for a scratch register (other than CR0). This workaround must be
avoided when the timebase is frozen, such as during the timebase sync
code.
This deals with kernel and vdso accesses, but other userspace accesses
will of course need to be fixed elsewhere.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I88da5fef252872ba17c4496ed1a053dc4be645af
---
v2: Share the Cell workaround instead of using the workaround suggested
by the erratum.
Reviewed-on: http://git.am.freescale.net:8181/3749
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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"default y" prevents the mere absence of those config lines from
turning off the errata.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: Ib825e8c5941f422990a997a79412669bda677d79
Reviewed-on: http://git.am.freescale.net:8181/3748
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
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For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO and RMan EISR bit
value of error interrupts in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I3eacf5ebee6da5ac847d6ab93fe1e38a07e57176
Reviewed-on: http://git.am.freescale.net:8181/3616
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
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This patch enables the direct schemesupport when a miss action is configured.
Signed-off-by: Radu Bulie <radu.bulie@freescale.com>
Change-Id: Ie16ab1e611a06b026fb5927ec2efea314bb0e2e1
Reviewed-on: http://git.am.freescale.net:8181/3354
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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When multicast group was preallocated from a xml PCD file, the handle to the group
was given as a multicast group parameter.
To align the multicast component with header manipulation and classifier
components, the group handle will be given as a resource input parameter
to the function that creates a multicast group.
Signed-off-by: Radu Bulie <radu.bulie@freescale.com>
Change-Id: I254d1c681cc016513d4cb569e0dfcf5c56478163
Reviewed-on: http://git.am.freescale.net:8181/3279
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
ENGR00270413
Change-Id: I9ca855698d1eaa93b7cb131d811f4c9dd6c72088
Reviewed-on: http://git.am.freescale.net:8181/3297
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
ENGR00269928
Change-Id: I7fa7fec2f1eef4b8233ed0d0069e30557adb4bda
Reviewed-on: http://git.am.freescale.net:8181/3296
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
ENGR00258538
Change-Id: If05f2a070c35c9884782d879566b04f40accfab8
Reviewed-on: http://git.am.freescale.net:8181/3295
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: I69b5d2f92045daa71fd8dd6765596397fe736ef5
Reviewed-on: http://git.am.freescale.net:8181/3292
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Reviewed-by: Hamciuc Bogdan-BHAMCIU1 <bogdan.hamciuc@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The device file in the file system is created automatically at init by
the driver without need of any mknod commands.
Change-Id: Ib0d5d4a47d3e92ec3d7a8813223017e0c24503a5
Signed-off-by: Aurelian Zanoschi <Aurelian.Zanoschi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/2881
Reviewed-by: Varvara Andrei-B21317 <andrei.varvara@freescale.com>
Reviewed-by: Floarea Anca Jeanina-B12569 <anca.floarea@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Bulie Radu-Andrei-B37577 <Radu.Bulie@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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This fixes the problem where the kernel build breaks, when PCI
support is disabled.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I698626ec0a40ba81ef132890bc339c6be10d8673
Reviewed-on: http://git.am.freescale.net:8181/3282
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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This fixes the problem where the kernel build breaks, when PCI
support is disabled.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I698626ec0a40ba81ef132890bc339c6be10d8673
Reviewed-on: http://git.am.freescale.net:8181/3282
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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If CONFIG_E500 is enabled, the compilation flags are updated
specifying the target core -mcpu=e5500/e500mc/8540
Also remove -Wa,-me500, being incompatible with -mcpu=e5500/e6500
The assembler option is redundant if the -mcpu= flag is set.
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Change-Id: Id786d80825d09aa40052666bc5be173cc89bc1ec
Reviewed-on: http://git.am.freescale.net:8181/3068
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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If the system gets into an out-of-memory state, we are unable to
refill the default buffer pool with new buffers. While this lasts,
just release any incoming frame back to the pool without further
processing.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Change-Id: Ia7fe59c44aa371f81540b45d197aef896b6d6b3a
Reviewed-on: http://git.am.freescale.net:8181/3050
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The DPA Classifier is computing a CRC64 ECMA by using the Frame
Manager driver. Because the CRC64 ECMA generic module was recently
accepted in linux/lib it will now use this CRC64 module instead of
the implementation from FMan driver.
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Change-Id: I97acd884302d7ab53ec78b045dd5978da2bf904a
Reviewed-on: http://git.am.freescale.net:8181/3257
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Function free_resources was not taking in account error codes returned
by free_cnts_resources and free_reqs_resources functions. In case an
error occurred, function should be exited, so that the DPA Stats
structure is not released.
Signed-off-by: Anca Jeanina FLOAREA <anca.floarea@freescale.com>
Change-Id: I74800a38f52634ca1e38e1d68d5637a4480bf525
Reviewed-on: http://git.am.freescale.net:8181/2967
Reviewed-by: Zanoschi Aurelian-B43522 <Aurelian.Zanoschi@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The same error logging and display functions should be used all
over the DPAA offloading drivers. "pr_err" calls were replaced with
the newer "log_err" macros in DPA Classifier.
Change-Id: I170b52ea716a5c0a5cae83a20e42a52fa55c8659
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/3008
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Bulie Radu-Andrei-B37577 <Radu.Bulie@freescale.com>
Reviewed-by: Zanoschi Aurelian-B43522 <Aurelian.Zanoschi@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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When modifying a header manipulation operation at runtime, the DPA
Classifier uses the FMD call FM_PCD_ManipNodeReplace. This function
locks the entire PCD and will fail if the PCD is already locked (it is
not a blocking function). The parallel access protection mechanism in DPA
Classifier would only protect against parallel access ON THE SAME MANIP
NODE. It used to ALLOW parallel access on DIFFERENT HM nodes, but this
will fail due to the locking system in the FMD.
This patch updates the locking mechanism in DPA Classifier for the HM
runtime modification functions so that a single call to
FM_PCD_ManipNodeReplace can happen at any one time.
Change-Id: I833b96e177e57f76d109ec000bd34c603df5ba71
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/3007
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Bulie Radu-Andrei-B37577 <Radu.Bulie@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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next_table action
The DPA Classifier API did not allow the user to add header
manipulation on an entry whose action was sending the frames to
a new classification table. This change adds this support
to the DPA Classifier by adding an "hmd" (header manipulation
descriptor) attribute to the "dpa_cls_tbl_next_table_desc"
parameters structure.
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Change-Id: I126cdfad8e76a8bec4453c8f7b506ad3380349e2
Reviewed-on: http://git.am.freescale.net:8181/3106
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Added implementation of CRC64 ECMA checksum.
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Change-Id: Ibfe1fc6ec77b6748e30d362b776803b8574c3398
Reviewed-on: http://git.am.freescale.net:8181/3033
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Varvara Andrei-B21317 <andrei.varvara@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Added the Traffic Manager counter implementation into DPA Stats
component. For getting the Class Queue or the Class Congestion Group
counter values, the component will call QMan functions
qman_ceetm_cq_get_dequeu_statistics, respectively
qman_ceetm_ccg_get_reject_statistics. For both Traffic Manager Class or
Congestion Group the values returned can be the number of bytes or the
number of frames dequeued from a Class Queue, respectively rejected in
all Class Queues that belong to the Congestion Group.
Change-Id: I3d1e0b0c5a2e206de68d5745e02727b0e2aa0fad
Signed-off-by: Aurelian Zanoschi <Aurelian.Zanoschi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/2877
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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When system memory is depleted, the Rx buffers are put back into
their pool. Bad accounting on that error path made it so the software
software counters remained behind the hardware counters, eventually
allowing for negative totals.
Fix this and keep the software pool counters in sync with the hardware
counters.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Change-Id: I46191bc38f12aa6a25378eba3e5891bc3f18cbc6
Reviewed-on: http://git.am.freescale.net:8181/3049
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Sovaiala Cristian-Constantin-B39531 <Cristian.Sovaiala@freescale.com>
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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