Age | Commit message (Collapse) | Author |
|
The Thermal Monitoring Unit node for LS1021A.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
|
|
DSPI new driver can select transfer mode(tcfq/eoq) to work.
The property will be read from dtsi node.
Add the property tcfq-mode for LS1021a.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Change-Id: I09efa9277364b79d075a1de94bd04111e2434576
Reviewed-on: http://git.am.freescale.net:8181/39515
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Erratum A-008022 has been fixed on LS1021A Rev2.0.
So we can use DSPI2 now, this patch enable DSPI2 in dts for LS1021ATWR.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Change-Id: I00c76415c155a290eecbde8b37e6148b11ed2c07
Reviewed-on: http://git.am.freescale.net:8181/39514
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Change-Id: Iae6ec5f13ae85e26c2bf50efe55e81d91eba3d8d
Reviewed-on: http://git.am.freescale.net:8181/39246
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds the device nodes for flexcan controller(s) present
on LS1021A-Rev2 SoC.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
Change-Id: Ia301d4db49d337e37def2e6667b6e4e1586fd8fc
Reviewed-on: http://git.am.freescale.net:8181/38096
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node.
Fix following non-critical issues and inconsistencies:
- eTSEC can support 8 H/W queues, show this in the device tree;
- remove "fsl,[r|t]x-bit-map" properties, they are obsoleted;
- register block size is 0x1000 (4kB memory page), not 0x8000;
- reg property has 2 "address" and resp. 2 "size" cells, not 1;
- use register block address as queue-group id for consistency;
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: Iada02221d1f3e06cc019a7b067c9b676c7c0b77d
Reviewed-on: http://git.am.freescale.net:8181/37273
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
mapping table
According to the new mapping table, the partition for NOR flash
is adjusted.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: Id535115a4ac53aeadd4c144425800fc566ab76b8
Reviewed-on: http://git.am.freescale.net:8181/37068
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Add deep sleep support on TWR-LS1021A-PB, which has CPLD on board
instead of FPGA.
Enable the ftm0 node in .dts to enable wake-on-Flextimer feature.
Change-Id: I0b1234cdd80d852140964240234576705764cd89
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/36250
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
As SAI's registers are configured as little-endian mode,
big-endian-regs property is not needed.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: Ibcd07bbdc1a3fa4e738e9e20c977f35405f54d32
Reviewed-on: http://git.am.freescale.net:8181/36160
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
As the load address of U-Boot for NOR boot is changed,
the partition for NOR flash is adjusted accordingly.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: Ibf71d76071c78784f651f8e00a7dc65c2cfc5b75
Reviewed-on: http://git.am.freescale.net:8181/36373
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required
or not
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Iab5ad0062acdbc03035d2ca98de071a52074e844
Reviewed-on: http://git.am.freescale.net:8181/33663
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
|
|
|
|
Added SATA device node and enabled AHCI config by default.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Change-Id: I288e6bffea28ea31804e20190dfa6b580fa2d7eb
Reviewed-on: http://git.am.freescale.net:8181/31841
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
arch/arm/kvm/mmu.c
arch/arm/mm/proc-v7-3level.S
arch/powerpc/kernel/vdso32/getcpu.S
drivers/crypto/caam/error.c
drivers/crypto/caam/sg_sw_sec4.h
drivers/usb/host/ehci-fsl.c
|
|
|
|
This patch adds HDMI hardware parameters in ls1021a-qds.dts for
DCU on ls1021aqds board
Signed-off-by: Jianwei.wang <b52261@freescale.com>
Change-Id: Idde265ee04bbf5120483a621347fe5fd5a2a6e4c
Reviewed-on: http://git.am.freescale.net:8181/29683
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
If a device works as a wakeup source, it will keep working in the peroid of
sleep/deep sleep. This patch sets the wakeup devices according to the wakeup
attribute of device.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: If49a8ad282115ac415fb03d0197964c5ae10c86d
Reviewed-on: http://git.am.freescale.net:8181/29152
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The dspi1 is not availiable on LS1021A-R1.0, thus the node can't
be verified. This patch removes the dspi1 node from the TWR board
dts for consistent with this limitation.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: Ic9178b89c2cc78c3c805e999c8fa24817cbcb06f
Reviewed-on: http://git.am.freescale.net:8181/25580
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
According to the H/W reference manual, eTSEC1 (EC1)
is a valid wake-up event source. The supported wake-up
events are magic packet and user defined packet (eTSEC filer).
Change-Id: Ife1a0d1f0afcfa8641c6630cb12c9e40775b9e47
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/24220
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
|
|
This patch adjust the size of QSPI AMBA Bus memory map to 64M
to avoid the issue that system default vmalloc size is not
enough.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: Ie917be03b0a0479f2c49dc02b9c36cb04ecc87c8
Reviewed-on: http://git.am.freescale.net:8181/24671
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
|
|
U-boot patches up the device tree crypto node for the era property.
crypto node alias was missing in the ls1020 device trees.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Change-Id: I335cc0765a1f66c72d98bab737aab3012448bf18
Reviewed-on: http://git.am.freescale.net:8181/23508
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Horia Ioan Geanta Neag <horia.geanta@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: Iaf58815549266cde2d082e789c34a975259d854f
Reviewed-on: http://git.am.freescale.net:8181/23497
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
Remove qspi the second flash support for LS1 SDK.
The QSPI driver was back-ported from the upstream QSPI driver. The
upstream version does not support the reading/writing for the second
flash chip. This patch removed the second flash support to avoid error information during kernel bringup.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: I57b02083ebe8e9a34673243be74d8cfd1c80aa9d
Reviewed-on: http://git.am.freescale.net:8181/22587
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Added the compatible "simple-bus" to fix the problem.
Change-Id: I629a6f5c54f51dbe18c65c2ff8cdc6e97bb0ed0f
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22481
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: Ib0ecd4424f3d356fe1bcd687d3befd61527be5ab
Reviewed-on: http://git.am.freescale.net:8181/21974
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Dspi flash is at45db021d on ls1021aqds board.
Reduce its frequency to improve the data transfer stability.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: If4e4d03d52fc28dea2dca3e6c6872024d3d1229a
Reviewed-on: http://git.am.freescale.net:8181/21973
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
DSPI new driver can select transfer mode(tcfq/eoq) to work.
The property will be read from dtsi node.
Add the property tcfq-mode for LS1021a.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: Ib659338777a4a8a5fdef7914c556c3ca8b4c483d
Reviewed-on: http://git.am.freescale.net:8181/21908
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds dts nodes for audio support on LS1021AQDS/TWR.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: I5e98a2377a7230598401ad932c4016951435b240
Reviewed-on: http://git.am.freescale.net:8181/21061
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Added device_type property to soc node to facilitate its use.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I4c50770215608f8ca718e78072a28f69afdf1bc2
Reviewed-on: http://git.am.freescale.net:8181/21690
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Fixed some error in clockgen node.
This patch also added clock source to CPU nodes to support
CPU frequency switch dynamically.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I2d40c3bc9c766d62d9cb8a3c00b9d5e1c2e65f41
Reviewed-on: http://git.am.freescale.net:8181/21689
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
add qe node(qe-tdm and qe-uart) into ls1021a-qds.dts
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I1ab52c2330246e807fd4c96103d2c063b6d8d8ba
Reviewed-on: http://git.am.freescale.net:8181/21868
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds the device nodes for 4 FlexCAN IP instances
available on LS1021A SoC in the ls1021a.dtsi file and enables
only the first two instances which are supported on the QDS
board in ls1021a-qds.dts file.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Previous version of this patch under review upstream:
http://patchwork.ozlabs.org/patch/363588/
Will re-spin the patch with the DTS
Change-Id: I592e5f8562ad173801a53433aec9a91b00ba8bb0
Reviewed-on: http://git.am.freescale.net:8181/21855
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: Ib16b8e2466757d782ec4bb5e8549f2dcb9208e32
Reviewed-on: http://git.am.freescale.net:8181/21801
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Correct qspi flash information on ls1021a-qds board.
And remove flash partion in node, it is not useful.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: I8b2dc47446c5d54ce12e3d7d138fa9d9a3b9ba6c
Reviewed-on: http://git.am.freescale.net:8181/21364
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Correct qspi flash information on ls1021a-qds board.
And remove flash partion in node, it is not useful.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: Ib9b3964127984457032f73be53bbfc847cf438bf
Reviewed-on: http://git.am.freescale.net:8181/21360
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The new QSPI driver add DDR read mode,
so add qspi-memory map for QSPI access in DDR mode in dts node.
Modify qspi node compatible for LS1 paltform.
Signed-off-by: Chao Fu <b44548@freescale.com>
Change-Id: Ia92dda63bf857b845767ae62f2c7eb9a84371aa1
Reviewed-on: http://git.am.freescale.net:8181/21356
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The regmap framework has one feature of register cache, which
will be more easy to add big endian mode and PM support.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
--
The first DRM version will be send out to the community
before 15 Dec 2014.
Change-Id: I3aa3c30f4ab42b64b80669b483b45a62ae31d6bb
Reviewed-on: http://git.am.freescale.net:8181/21571
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
The first DRM version will be send out to the community
before 30 November 2014.
Change-Id: Ia5538da4db87431fd80ffaacc07c201d20a8bc2b
Reviewed-on: http://git.am.freescale.net:8181/19651
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds DCU node in SoC level DTS for Freescale LS1021A-TWR.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
The first DRM version will be send out to the community
before 30 November 2014.
Change-Id: I74671a92d530699be6868f7f1591eadbd40a6879
Reviewed-on: http://git.am.freescale.net:8181/19649
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
The first DRM version will be send out to the community
before 30 November 2014.
Change-Id: I6a20f9f5c1b8b8c596e635b25aa37055e23f82a7
Reviewed-on: http://git.am.freescale.net:8181/19648
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
add qe node to ls1021atwr fdt.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
---
upstream link: http://patchwork.ozlabs.org/patch/398470/
it is under discussion.
Change-Id: I4f0bc40003265f85bde01a9982ef7f91edd1d08e
Reviewed-on: http://git.am.freescale.net:8181/21121
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I5deb88a99bd7b5d40251a4935d4d8a556abad7ae
Reviewed-on: http://git.am.freescale.net:8181/19712
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: I08008c3dcd2b85b0c54b9f9ee939287f57745517
Reviewed-on: http://git.am.freescale.net:8181/19641
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Add ftm0 node, cause of ftm0 can be set as a alarm before system
going to deep sleep.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Ie337ec554f6acd625cd691a0e07ffb96807cfa10
Reviewed-on: http://git.am.freescale.net:8181/19838
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Change-Id: I7aa37e4914623a303eb520c6d8fd6d4f84e9ddb2
Reviewed-on: http://git.am.freescale.net:8181/19815
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Remove #address-cells and #size-cells from USB 2.0 node in ls1021a
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Ia2ff9aea201ef18b352437bda267571c235db689
Reviewed-on: http://git.am.freescale.net:8181/15675
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This add an alias named sysclk for the sysclk node for fdt
fixup procedure locating it uniquely.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I7e6bd6cb4d81fe44c73944be91cab3fe56810094
Reviewed-on: http://git.am.freescale.net:8181/19199
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The sysclk could be well probed by "fixed-clock" compatible,
no custom compatible is needed any more.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I17a21e20ced4304e716e5a9ba07ff56b2adb45a7
Reviewed-on: http://git.am.freescale.net:8181/17833
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
remove the tbi node which will be added to boards level dts.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I1b7893526e63d0207637f2ae0576c9d5f62a6a06
Reviewed-on: http://git.am.freescale.net:8181/17829
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This add aliases for enet phy to make it be found easily
in u-boot on dynamically change the enet "phy-handle" and
"phy-connection-type" property.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I60e19aa48856c9b9048415d1c8924b626d70332a
Reviewed-on: http://git.am.freescale.net:8181/17831
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|