| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: Iaf58815549266cde2d082e789c34a975259d854f
Reviewed-on: http://git.am.freescale.net:8181/23497
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
For LPAE, we have the following means for encoding writable or dirty
ptes:
L_PTE_DIRTY L_PTE_RDONLY
!pte_dirty && !pte_write 0 1
!pte_dirty && pte_write 0 1
pte_dirty && !pte_write 1 1
pte_dirty && pte_write 1 0
So we can't distinguish between writeable clean ptes and read only
ptes. This can cause problems with ptes being incorrectly flagged as
read only when they are writeable but not dirty.
This patch renumbers L_PTE_RDONLY from AP[2] to a software bit #58,
and adds additional logic to set AP[2] whenever the pte is read only
or not dirty. That way we can distinguish between clean writeable ptes
and read only ptes.
HugeTLB pages will use this new logic automatically.
We need to add some logic to Transparent HugePages to ensure that they
correctly interpret the revised pgprot permissions (L_PTE_RDONLY has
moved and no longer matches PMD_SECT_AP2). In the process of revising
THP, the names of the PMD software bits have been prefixed with L_ to
make them easier to distinguish from their hardware bit counterparts.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit ded9477984690d026e46dd75e8157392cea3f13f)
Conflicts:
arch/arm/mm/dump.c
Change-Id: Ia71696dc811c7aeb8596334a26e67c24813a039f
Reviewed-on: http://git.am.freescale.net:8181/23333
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
Long descriptors on ARM are 64 bits, and some pte functions such as
pte_dirty return a bitwise-and of a flag with the pte value. If the
flag to be tested resides in the upper 32 bits of the pte, then we run
into the danger of the result being dropped if downcast.
For example:
gather_stats(page, md, pte_dirty(*pte), 1);
where pte_dirty(*pte) is downcast to an int.
This patch introduces a new macro pte_isset which performs the bitwise
and, then performs a double logical invert (where needed) to ensure
predictable downcasting. The logical inverse pte_isclear is also
introduced.
Equivalent pmd functions for Transparent HugePages have also been
added.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit f2950706871c4b6e8c0f0d7c3f62d35930b8de63)
Change-Id: I2d17ab87a364a3e839c71fab3f4507e722288daf
Reviewed-on: http://git.am.freescale.net:8181/23332
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
|
|
The pte_accessible macro can be used to identify page table entries
capable of being cached by a TLB. In principle, this differs from
pte_present, since PROT_NONE mappings are mapped using invalid entries
identified as present and ptes designated as `old' can use either
invalid entries or those with the access flag cleared (guaranteed not to
be in the TLB). However, there is a race to take care of, as described
in 20841405940e ("mm: fix TLB flush race between migration, and
change_protection_range"), between a page being migrated and mprotected
at the same time. In this case, we can check whether a TLB invalidation
is pending for the mm and if so, temporarily consider PROT_NONE mappings
as valid.
This patch implements a quick pte_accessible macro for ARM by simply
checking if the pte is valid/present depending on the mm. For classic
MMU, these checks are identical and will generate some false positives
for PROT_NONE mappings, but this is better than the current asm-generic
definition of ((void)(pte),1).
Finally, pte_present_user is moved to use pte_valid (and renamed
appropriately) since we don't care about cache flushing for faulting
mappings.
Acked-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 1971188aa19651d8f447211c6535fb68661d77c5)
Change-Id: I27ad2dbe398483d18ebb587e7c1e65b198421070
Reviewed-on: http://git.am.freescale.net:8181/23331
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
When enable LPAE and big-endian in a hisilicon board, while specify
mem=384M mem=512M@7680M, will get bad page state:
Freeing unused kernel memory: 180K (c0466000 - c0493000)
BUG: Bad page state in process init pfn:fa442
page:c7749840 count:0 mapcount:-1 mapping: (null) index:0x0
page flags: 0x40000400(reserved)
Modules linked in:
CPU: 0 PID: 1 Comm: init Not tainted 3.10.27+ #66
[<c000f5f0>] (unwind_backtrace+0x0/0x11c) from [<c000cbc4>] (show_stack+0x10/0x14)
[<c000cbc4>] (show_stack+0x10/0x14) from [<c009e448>] (bad_page+0xd4/0x104)
[<c009e448>] (bad_page+0xd4/0x104) from [<c009e520>] (free_pages_prepare+0xa8/0x14c)
[<c009e520>] (free_pages_prepare+0xa8/0x14c) from [<c009f8ec>] (free_hot_cold_page+0x18/0xf0)
[<c009f8ec>] (free_hot_cold_page+0x18/0xf0) from [<c00b5444>] (handle_pte_fault+0xcf4/0xdc8)
[<c00b5444>] (handle_pte_fault+0xcf4/0xdc8) from [<c00b6458>] (handle_mm_fault+0xf4/0x120)
[<c00b6458>] (handle_mm_fault+0xf4/0x120) from [<c0013754>] (do_page_fault+0xfc/0x354)
[<c0013754>] (do_page_fault+0xfc/0x354) from [<c0008400>] (do_DataAbort+0x2c/0x90)
[<c0008400>] (do_DataAbort+0x2c/0x90) from [<c0008fb4>] (__dabt_usr+0x34/0x40)
The bad pfn:fa442 is not system memory(mem=384M mem=512M@7680M), after debugging,
I find in page fault handler, will get wrong pfn from pte just after set pte,
as follow:
do_anonymous_page()
{
...
set_pte_at(mm, address, page_table, entry);
//debug code
pfn = pte_pfn(entry);
pr_info("pfn:0x%lx, pte:0x%llxn", pfn, pte_val(entry));
//read out the pte just set
new_pte = pte_offset_map(pmd, address);
new_pfn = pte_pfn(*new_pte);
pr_info("new pfn:0x%lx, new pte:0x%llxn", pfn, pte_val(entry));
...
}
pfn: 0x1fa4f5, pte:0xc00001fa4f575f
new_pfn:0xfa4f5, new_pte:0xc00000fa4f5f5f //new pfn/pte is wrong.
The bug is happened in cpu_v7_set_pte_ext(ptep, pte):
An LPAE PTE is a 64bit quantity, passed to cpu_v7_set_pte_ext in the r2 and r3 registers.
On an LE kernel, r2 contains the LSB of the PTE, and r3 the MSB.
On a BE kernel, the assignment is reversed.
Unfortunately, the current code always assumes the LE case,
leading to corruption of the PTE when clearing/setting bits.
This patch fixes this issue much like it has been done already in the
cpu_v7_switch_mm case.
CC stable <stable@vger.kernel.org>
Signed-off-by: Jianguo Wu <wujianguo@huawei.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 86f40622af7329375e38f282f6c0aab95f3e5f72)
Change-Id: If59198ba23237cc9cb98fa357795c6fece20666a
Reviewed-on: http://git.am.freescale.net:8181/23330
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
|
|
* set the bit 0 of the target address of long jump to 1 for THUMB mode
* compile the resume entry code in arm instruction set
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I01a96158ac39e14dcaebc7305b03eb277712011b
Reviewed-on: http://git.am.freescale.net:8181/23209
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Remove the workaround which disables qe for deepsleep.
qe blocked deepsleep, so the workaround was added,
Now the qe can work with deepsleep, so remove it.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I0f1ef2ec45b2ee8129c6ab958162f432d8a76c5d
Reviewed-on: http://git.am.freescale.net:8181/23143
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
|
|
This patch enables some device drivers and functions on LS1021A
QDS/TWR boards: PCIe, CPU frequency, Power Management, SPI, SAI audio,
DCU framebuffer, DVI/HDMI, USB3.0, PWM, CAAM.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I122a248490de5c80538fbced40e6c4e7a9db9ccd
Reviewed-on: http://git.am.freescale.net:8181/23176
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Hongtao Jia <hongtao.jia@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
upstream link of the patch:
http://patchwork.ozlabs.org/patch/400406/
Change-Id: I55e42d2515bcd35d0bc5198cb13d5ed91850b50e
Reviewed-on: http://git.am.freescale.net:8181/22796
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Remove qspi the second flash support for LS1 SDK.
The QSPI driver was back-ported from the upstream QSPI driver. The
upstream version does not support the reading/writing for the second
flash chip. This patch removed the second flash support to avoid error information during kernel bringup.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: I57b02083ebe8e9a34673243be74d8cfd1c80aa9d
Reviewed-on: http://git.am.freescale.net:8181/22587
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Added the compatible "simple-bus" to fix the problem.
Change-Id: I629a6f5c54f51dbe18c65c2ff8cdc6e97bb0ed0f
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22481
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Commit 1fcf7ce0c602 (arm: kvm: implement CPU PM notifier) added
support for CPU power-management, using a cpu_notifier to re-init
KVM on a CPU that entered CPU idle.
The code assumed that a CPU entering idle would actually be powered
off, loosing its state entierely, and would then need to be
reinitialized. It turns out that this is not always the case, and
some HW performs CPU PM without actually killing the core. In this
case, we try to reinitialize KVM while it is still live. It ends up
badly, as reported by Andre Przywara (using a Calxeda Midway):
[ 3.663897] Kernel panic - not syncing: unexpected prefetch abort in Hyp mode at: 0x685760
[ 3.663897] unexpected data abort in Hyp mode at: 0xc067d150
[ 3.663897] unexpected HVC/SVC trap in Hyp mode at: 0xc0901dd0
The trick here is to detect if we've been through a full re-init or
not by looking at HVBAR (VBAR_EL2 on arm64). This involves
implementing the backend for __hyp_get_vectors in the main KVM HYP
code (rather small), and checking the return value against the
default one when the CPU notifier is called on CPU_PM_EXIT.
Reported-by: Andre Przywara <osp@andrep.de>
Tested-by: Andre Przywara <osp@andrep.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <rob.herring@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit b20c9f29c5c25921c6ad18b50d4b61e6d181c3cc)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I3f123215dfd2673e3abae201b6e75c11ac9cfe63
Reviewed-on: http://git.am.freescale.net:8181/22059
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
unmap_range() was utterly broken, to quote Marc, and broke in all sorts
of situations. It was also quite complicated to follow and didn't
follow the usual scheme of having a separate iterating function for each
level of page tables.
Address this by refactoring the code and introduce a pgd_clear()
function.
Reviewed-by: Jungseok Lee <jays.lee@samsung.com>
Reviewed-by: Mario Smarduch <m.smarduch@samsung.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 4f853a714bf16338ff5261128e6c7ae2569e9505)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I478878114142926836b4f6674c4a04cb94b23955
Reviewed-on: http://git.am.freescale.net:8181/22058
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds support for running Cortex-A7 guests on Cortex-A7 hosts.
As Cortex-A7 is architecturally compatible with A15, this patch is largely just
generalising existing code. Areas where 'implementation defined' behaviour
is identical for A7 and A15 is moved to allow it to be used by both cores.
The check to ensure that coprocessor register tables are sorted correctly is
also moved in to 'common' code to avoid each new cpu doing its own check
(and possibly forgetting to do so!)
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit e8c2d99f8277d68d28a9f99d16289712bc2aee7f)
Conflicts:
arch/arm/kvm/reset.c
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Id420a5e767cb428dc5b9735673c87ef97322c8df
Reviewed-on: http://git.am.freescale.net:8181/22057
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Upon CPU shutdown and consequent warm-reboot, the hypervisor CPU state
must be re-initialized. This patch implements a CPU PM notifier that
upon warm-boot calls a KVM hook to reinitialize properly the hypervisor
state so that the CPU can be safely resumed.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
(cherry picked from commit 1fcf7ce0c60213994269fb59569ec161eb6e08d6)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I09e329449b8e5e767cdfec1000f2c8f82193a0b8
Reviewed-on: http://git.am.freescale.net:8181/22056
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The ARM architected timer driver doesn't compile without
GENERIC_CLOCKEVENTS selected, so ensure that we select it when building
for a platform that has the timer.
Without this patch, mach-virt fails to build without something like
mach-vexpress also selected.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 0c403462d6822227ea37fb0293a3e9f511e6929f)
Change-Id: I349317968df072d8539702adcf376e4bea4b43cb
Reviewed-on: http://git.am.freescale.net:8181/22055
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ia801e4e9ee128b35a5ec0fad42c71e2b91e4e808
Reviewed-on: http://git.am.freescale.net:8181/22054
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The use of p*d_addr_end with stage-2 translation is slightly dodgy,
as the IPA is 40bits, while all the p*d_addr_end helpers are
taking an unsigned long (arm64 is fine with that as unligned long
is 64bit).
The fix is to introduce 64bit clean versions of the same helpers,
and use them in the stage-2 page table code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit a3c8bd31af260a17d626514f636849ee1cd1f63e)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I1db223265c876a17edbc79777f59479f12bafa19
Reviewed-on: http://git.am.freescale.net:8181/22053
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The mach-virt machine is entirely specified by device tree.
However the kernel does not initialize the clocks from device tree
and it will refuse to probe the PL011 console.
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I5f90396a872f2db9a0164cd003babaf9b8efdcad
Reviewed-on: http://git.am.freescale.net:8181/22052
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Compiling with THP enabled leads to the following warning:
arch/arm/kvm/mmu.c: In function ‘unmap_range’:
arch/arm/kvm/mmu.c:177:39: warning: ‘pte’ may be used uninitialized in this function [-Wmaybe-uninitialized]
if (kvm_pmd_huge(*pmd) || page_empty(pte)) {
^
Code inspection reveals that these two cases are mutually exclusive,
so GCC is a bit overzealous here. Silence it anyway by initializing
pte to NULL and testing it later on.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 56041bf920d2937b7cadcb30cb206f0372eee814)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ie4c704ea6441c405cd409cc6a2b1e833936a2df4
Reviewed-on: http://git.am.freescale.net:8181/22051
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The KVM_HPAGE_DEFINES are a little artificial on ARM, since the huge
page size is statically defined at compile time and there is only a
single huge page size.
Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit dc6f6763dfeaf2dfec906bb78875dcea162accd9)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I057413e3c7268842e6e12b0b158c1c498da0cb58
Reviewed-on: http://git.am.freescale.net:8181/22049
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Support transparent huge pages in KVM/ARM and KVM/ARM64. The
transparent_hugepage_adjust is not very pretty, but this is also how
it's solved on x86 and seems to be simply an artifact on how THPs
behave. This should eventually be shared across architectures if
possible, but that can always be changed down the road.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 9b5fdb9781f74fb15827e465bfb5aa63211953c8)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I0a35b3b7cbb482b0fd8ad828c6db2a5e7b59869f
Reviewed-on: http://git.am.freescale.net:8181/22044
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Support huge pages in KVM/ARM and KVM/ARM64. The pud_huge checking on
the unmap path may feel a bit silly as the pud_huge check is always
defined to false, but the compiler should be smart about this.
Note: This deals only with VMAs marked as huge which are allocated by
users through hugetlbfs only. Transparent huge pages can only be
detected by looking at the underlying pages (or the page tables
themselves) and this patch so far simply maps these on a page-by-page
level in the Stage-2 page tables.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit ad361f093c1e31d0b43946210a32ab4ff5c49850)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I74ce26713f4720f8024692664ebfb14a364bd84d
Reviewed-on: http://git.am.freescale.net:8181/22043
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
KVM does not have a notion of multiple clusters for CPUs, just a linear
array of CPUs. When using a system with cores in more than one cluster, the
current method for calculating the virtual MPIDR will leak the (physical)
cluster information into the virtual MPIDR. One effect of this is that
Linux under KVM fails to boot multiple CPUs that aren't in the 0th cluster.
This patch does away with exposing the real MPIDR fields in favour of simply
using the virtual CPU number (but preserving the U bit, as before).
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 1158fca401e09665c440a9fe4fd4f131ee85c13b)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Iaf8b973671e1ea2a203fb2d69c3c8aa9cafbf91f
Reviewed-on: http://git.am.freescale.net:8181/22041
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
For implementing CPU=host, we need a mechanism for querying
preferred VCPU target type on underlying Host.
This patch implements KVM_ARM_PREFERRED_TARGET vm ioctl which
returns struct kvm_vcpu_init instance containing information
about preferred VCPU target type and target specific features
available for it.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 42c4e0c77ac91505ab94284b14025e3a0865c0a5)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Iaace1d63c4bd6f66b7808f4b8e9201b8326ed4ee
Reviewed-on: http://git.am.freescale.net:8181/22039
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch implements kvm_vcpu_preferred_target() function for
KVM ARM which will help us implement KVM_ARM_PREFERRED_TARGET ioctl
for user space.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 4a6fee805d5e278e4733bf933cb5b184b7a8be1f)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I10beaa7f4275742c9f86ba957a7d70adcf5babb0
Reviewed-on: http://git.am.freescale.net:8181/22037
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The T{0,1}SZ fields of TTBCR are 3 bits wide when using the long descriptor
format. Likewise, the T0SZ field of the HTCR is 3-bits. KVM currently
defines TTBCR_T{0,1}SZ as 3, not 7.
The T0SZ mask is used to calculate the value for the HTCR, both to pick out
TTBCR.T0SZ and mask off the equivalent field in the HTCR during
read-modify-write. The incorrect mask size causes the (UNKNOWN) reset value
of HTCR.T0SZ to leak in to the calculated HTCR value. Linux will hang when
initializing KVM if HTCR's reset value has bit 2 set (sometimes the case on
A7/TC2)
Fixing T0SZ allows A7 cores to boot and T1SZ is also fixed for completeness.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 5e497046f005528464f9600a4ee04f49df713596)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I1c5fc3e65d8821f50fab529ab1ff320cc10b9649
Reviewed-on: http://git.am.freescale.net:8181/22036
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Very minor typo in comments of inject_abt() when we update fault status
register for injecting prefetch abort.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit b373e492f3a3469c615c2ae218d2f723900bf981)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I4932dd95838b11a832209328dd59cbf2e43b298c
Reviewed-on: http://git.am.freescale.net:8181/22035
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The temporary workaround will disable the QE device before entering
deep sleep. It makes deep sleep work, and should be removed after
resolving the problem.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: Ib8c079ef67773eb3e058cf03331a0ed9c7707113
Reviewed-on: http://git.am.freescale.net:8181/21981
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: Ib0ecd4424f3d356fe1bcd687d3befd61527be5ab
Reviewed-on: http://git.am.freescale.net:8181/21974
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Dspi flash is at45db021d on ls1021aqds board.
Reduce its frequency to improve the data transfer stability.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: If4e4d03d52fc28dea2dca3e6c6872024d3d1229a
Reviewed-on: http://git.am.freescale.net:8181/21973
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Qiu Wujie <B49553@freescale.com>
Change-Id: I30e6c4e9c5f6859aecc586b21d6426a802160699
Reviewed-on: http://git.am.freescale.net:8181/21964
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
LS1 supports deep sleep feature that can switch off most parts of
the SoC when it is in deep sleep state.
The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
Patch Sent Upstream
url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296411.html
Change-Id: If96ace364c21786cc88ea4979d7cbb4e177da0a2
Reviewed-on: http://git.am.freescale.net:8181/21920
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This is only a CPU pseudo-hotplug, and incompatible with kexec mechanics.
As per the discussion with Russell King in opensource community, CPU hotplug
should reset the secondary core to be compatible with kexec.
"In the kexec case, when the secondary CPU wakeup, the code it is executing
can already been overwritten, which then means that the CPU ends up executing
some random code instead."
For LS102x platforms, resetting core can be realized, but come across cache
coherence problem which is still unresolved, we will submit another patch to
implement CPU hotplug by resetting core once cache coherence issue resloved.
Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
---
Patch Sent Upstream
url: https://lkml.org/lkml/2014/9/26/422
Change-Id: I36509f99299f874ef0df891a33c907a749649527
Reviewed-on: http://git.am.freescale.net:8181/21918
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This code is becoming duplicated in many places. So let's consolidate
it into a handy macro that is known to be right and available for reuse.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
cherry-pick from 39792c7cf3111d69dc4aa0923859d8b929e9039f
Change-Id: I9e2e9715425bcb8493c32b46ecb41c568d8235c5
Reviewed-on: http://git.am.freescale.net:8181/21917
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
LPAE enabled kernels use the 64-bit version of TTBR0 and TTBR1
registers. If we're running an LPAE kernel, fill the upper half
of TTBR0 with 0 because we're setting it to the idmap here (the
idmap is guaranteed to be < 4Gb) and fully restore TTBR1 instead
of just restoring the lower 32 bits. Failure to do so can cause
failures on resume from suspend when these registers are only
half restored.
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
cherry-pick from f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8
Change-Id: I7e91a04ac2fda61f9c8a5e60d8d503d00a3cf9c1
Reviewed-on: http://git.am.freescale.net:8181/21910
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
On CPUs with virtualization extensions the kernel installs HYP mode
configuration on both primary and secondary cpus upon cold boot.
On platforms where CPUs are shutdown in idle paths (ie CPU core gating),
when a CPU resumes from low-power states it currently does not execute
code that reinstalls the HYP configuration, which means that the kernel
cannot run eg KVM properly on such machines.
This patch, mirroring cold-boot behaviour, executes position independent
code that reinstalls HYP configuration and drops to SVC mode safely on
warmboot, so that deep idle states can be enabled in kernel running as
hosts on platforms with power management HW.
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Dave Martin <dave.martin@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
cherry-pick from 0e0779da2233f2dfc85e9c3a6ea142476d326811
Change-Id: Iafed877cc49e799d7c31f1cb265a0b38be708c88
Reviewed-on: http://git.am.freescale.net:8181/21909
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
DSPI new driver can select transfer mode(tcfq/eoq) to work.
The property will be read from dtsi node.
Add the property tcfq-mode for LS1021a.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: Ib659338777a4a8a5fdef7914c556c3ca8b4c483d
Reviewed-on: http://git.am.freescale.net:8181/21908
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds dts nodes for audio support on LS1021AQDS/TWR.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: I5e98a2377a7230598401ad932c4016951435b240
Reviewed-on: http://git.am.freescale.net:8181/21061
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Added device_type property to soc node to facilitate its use.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I4c50770215608f8ca718e78072a28f69afdf1bc2
Reviewed-on: http://git.am.freescale.net:8181/21690
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Fixed some error in clockgen node.
This patch also added clock source to CPU nodes to support
CPU frequency switch dynamically.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I2d40c3bc9c766d62d9cb8a3c00b9d5e1c2e65f41
Reviewed-on: http://git.am.freescale.net:8181/21689
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
add qe node(qe-tdm and qe-uart) into ls1021a-qds.dts
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I1ab52c2330246e807fd4c96103d2c063b6d8d8ba
Reviewed-on: http://git.am.freescale.net:8181/21868
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
This patch adds the device nodes for 4 FlexCAN IP instances
available on LS1021A SoC in the ls1021a.dtsi file and enables
only the first two instances which are supported on the QDS
board in ls1021a-qds.dts file.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Previous version of this patch under review upstream:
http://patchwork.ozlabs.org/patch/363588/
Will re-spin the patch with the DTS
Change-Id: I592e5f8562ad173801a53433aec9a91b00ba8bb0
Reviewed-on: http://git.am.freescale.net:8181/21855
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Change-Id: I501144de5deaecb1bbbe913fc1ef82e8102d84a3
Reviewed-on: http://git.am.freescale.net:8181/21811
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: Ib16b8e2466757d782ec4bb5e8549f2dcb9208e32
Reviewed-on: http://git.am.freescale.net:8181/21801
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
LS1021a-qds has the same controller as GPIO on
powerpc platform(MPC8XXX), so remove
GPIO_MXC and add the one for GPIO_MPC8XXX
Enable gpio as default
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: I13531087c312ef9fa3bb607b5202592d13b29727
Reviewed-on: http://git.am.freescale.net:8181/21800
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Correct qspi flash information on ls1021a-qds board.
And remove flash partion in node, it is not useful.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: I8b2dc47446c5d54ce12e3d7d138fa9d9a3b9ba6c
Reviewed-on: http://git.am.freescale.net:8181/21364
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
Correct qspi flash information on ls1021a-qds board.
And remove flash partion in node, it is not useful.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: Ib9b3964127984457032f73be53bbfc847cf438bf
Reviewed-on: http://git.am.freescale.net:8181/21360
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
|
The new QSPI driver add DDR read mode,
so add qspi-memory map for QSPI access in DDR mode in dts node.
Modify qspi node compatible for LS1 paltform.
Signed-off-by: Chao Fu <b44548@freescale.com>
Change-Id: Ia92dda63bf857b845767ae62f2c7eb9a84371aa1
Reviewed-on: http://git.am.freescale.net:8181/21356
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
