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2015-03-26t1024qds/dts: Added usdpaa shared interface device treeSandeep Singh
Signed-off-by: Sandeep Singh <sandeep@freescale.com> Change-Id: I30414c790280bed668b4a2e407a0917e5a95a7b9 Reviewed-on: http://git.am.freescale.net:8181/32930 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-26t1024rdb/dts: Added usdpaa shared interface device treeSandeep Singh
Signed-off-by: Sandeep Singh <sandeep@freescale.com> Change-Id: I7dccc8996cf572f49353296287b4ae68d130f1c7 Reviewed-on: http://git.am.freescale.net:8181/32929 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-26arm: KVM: Don't return PSCI_INVAL if waitqueue is inactiveChristoffer Dall
The current KVM implementation of PSCI returns INVALID_PARAMETERS if the waitqueue for the corresponding CPU is not active. This does not seem correct, since KVM should not care what the specific thread is doing, for example, user space may not have called KVM_RUN on this VCPU yet or the thread may be busy looping to user space because it received a signal; this is really up to the user space implementation. Instead we should check specifically that the CPU is marked as being turned off, regardless of the VCPU thread state, and if it is, we shall simply clear the pause flag on the CPU and wake up the thread if it happens to be blocked for us. Further, the implementation seems to be racy when executing multiple VCPU threads. There really isn't a reasonable user space programming scheme to ensure all secondary CPUs have reached kvm_vcpu_first_run_init before turning on the boot CPU. Therefore, set the pause flag on the vcpu at VCPU init time (which can reasonably be expected to be completed for all CPUs by user space before running any VCPUs) and clear both this flag and the feature (in case the feature can somehow get set again in the future) and ping the waitqueue on turning on a VCPU using PSCI. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> (cherry picked from commit 478a8237f656d86d25b3e4e4bf3c48f590156294) Conflicts: arch/arm/kvm/psci.c Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com> Change-Id: Ifdb4ff10bd3f02de20ee2302024a7dbedd1ddbf0 Reviewed-on: http://git.am.freescale.net:8181/31349 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-25powerpc/defconfig: enable CONFIG_REALTEK_PHYShengzhou Liu
Enable CONFIG_REALTEK_PHY to support Realtek PHY RTL8211F which is used on freescale's T1023 RDB board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I91d7b0e22a6223f5d8fd973bcdfe51e0b82958fa Reviewed-on: http://git.am.freescale.net:8181/33220 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-25powerpc: pm: save/restore CR register when doing deep sleepChenhui Zhao
Save and restore CR (Condition Register) register when doing deep sleep. Otherwise, conditional statement will get wrong result after resuming from deep sleep. Free memory which is allocated in suspend code. Change-Id: Ibe50138e85c164d0218a01f0f481bf484a02a45a Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/33411 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-25powerpc/fsl-booke: Add T1040D4RDB/T1042D4RDB board supportPriyanka Jain
T1040D4RDB/T1042D4RDB are Freescale Reference Design Board which can support T1040/T1042 QorIQ Power Architecture™ processor respectively T1040D4RDB/T1042D4RDB board Overview ------------------------------------- - SERDES Connections, 8 lanes supporting: - PCI - SGMII - SATA 2.0 - QSGMII(only for T1040D4RDB) - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR4 UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Add support for T1040/T1042D4RDB board: -add device tree -Add entry corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Change-Id: I4ff308a7884107dec88fac26e91feb3e85065d3f Reviewed-on: http://git.am.freescale.net:8181/33157 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-23powerpc/t1023rdb: Add T1023RDB board supportShengzhou Liu
T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC. This patch addes support for t1023rdb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I58c350794d657c653ff0b37bfede1179a7b39370 Reviewed-on: http://git.am.freescale.net:8181/32940 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-23t102x/diu: move display alias to t1024si-post.dtsiShengzhou Liu
As DIU/display feature exists on t1024 instead of t1023, so move display alias to t1024si-post.dtsi. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I831f211f8f85142622e63706204df2265f80ed0d Reviewed-on: http://git.am.freescale.net:8181/32939 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-23t1024rdb/dts: add support for 2.5G SGMIIShengzhou Liu
Add 2.5G SGMII support for T1024RDB Rev-B. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I5e278f2dacde8c27b42c6486808366f8009186a2 Reviewed-on: http://git.am.freescale.net:8181/26736 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-23fmd: create new config flavor for FManV3LMandy Lavi
CONFIG_FMAN_T4240 was eliminated Instead, there are now two flags representing FmanV3: CONFIG_FMAN_V3H for FmanV3H arch and CONFIG_FMAN_V3L for FmanV3L arch. FmanV3H h/w block is integrated in B4860, B4420, T4240, T4160, T2080 etc FmanV3L h/w block is integrated in T1040, T1024, T1020, T1022 etc defconfig files changes: corenet64_fmanv3_smp_defconfig -> corenet64_fmanv3l_smp_defconfig corenet32_fmanv3_smp_defconfig -> corenet32_fmanv3l_smp_defconfig 85xx/e6500rev2_defconfig -> corenet64_fmanv3h_smp_defconfig Change-Id: I9fcfb454bc3bd2d72c5d55c616400a808e181413 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/30539 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-20powerpc: Make boot_cpuid common between 32 and 64-bitBenjamin Herrenschmidt
Move the definition to setup-common.c and set the init value to -1 on both 32 and 64-bit (it was 0 on 64-bit). Additionally add a check to prom.c to garantee that the init value has been udpated after the DT scan. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Change-Id: I3aa6499dd65bfa5410d382880ca42f259906cdea Reviewed-on: http://git.am.freescale.net:8181/33084 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-20powerpc/mpc85xx: Add ranges to etsec2 nodesScott Wood
Commit 746c9e9f92dd "of/base: Fix PowerPC address parsing hack" limited the applicability of the workaround whereby a missing ranges is treated as an empty ranges. This workaround was hiding a bug in the etsec2 device tree nodes, which have children with reg, but did not have ranges. Signed-off-by: Scott Wood <scottwood@freescale.com> Reported-by: Alexander Graf <agraf@suse.de> Change-Id: I4c77ddeeb3c8de2ae180d8a24aae9871f2988fa6 Reviewed-on: http://git.am.freescale.net:8181/33083 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-20Merge remote-tracking branch 'ls1-linux/LS1-SDK'Olivia Yin-R63875
2015-03-20powerpc/e6500: Optimize hugepage TLB missesScott Wood
Some workloads take a lot of TLB misses despite using traditional hugepages. Handle these TLB misses in the asm fastpath rather than going through a bunch of C code. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I84a1f6fad189130c32a44e73ff60a26ffadfd59b Reviewed-on: http://git.am.freescale.net:8181/32729 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-19Merge branch 'qoriq-sdk' into LS1-SDKJason Jin
2015-03-16Revert "Revert "powerpc/hugetlb: Replace __get_cpu_var with get_cpu_var""Scott Wood
This reverts commit 978464fa78fef73e7c225e3a316662b6bfd1c261. Change-Id: I7d529835a9503cfc130da2da7bcda536b9c58762 Reviewed-on: http://git.am.freescale.net:8181/32820 Reviewed-by: Scott Wood <scottwood@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
2015-03-16Revert "powerpc/hugetlb: Replace __get_cpu_var with get_cpu_var"Honghua Yin
This reverts commit 64ded519fc23ff43dc257dce37dfd1b7801f1e99. Change-Id: I31b93b7ed5e2e5acd1198be4f90d0414e39aad61 Reviewed-on: http://git.am.freescale.net:8181/32782 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-16Revert "powerpc/perf: fix fsl_emb_pmu_start to write correct pmc value"Honghua Yin
This reverts commit a82bc85b91aabe41b47eb7ef4b15c466f671ecbc. Change-Id: If8da9358abad19bef990e0578a81b48e92487799 Reviewed-on: http://git.am.freescale.net:8181/32775 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-16powerpc/perf: fix fsl_emb_pmu_start to write correct pmc valueTom Huynh
PMCs on PowerPC increases towards 0x80000000 and triggers an overflow interrupt when the msb is set to collect a sample. Therefore, to setup for the next sample collection, pmu_start should set the pmc value to 0x80000000 - left instead of left which incorrectly delays the next overflow interrupt. Same as commit 9a45a9407c69 ("powerpc/perf: power_pmu_start restores incorrect values, breaking frequency events") for book3s. Change-Id: I5ba1acaec8436973970d00fdbd4b100107559a32 Reviewed-on: http://git.am.freescale.net:8181/29119 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-16powerpc/hugetlb: Replace __get_cpu_var with get_cpu_varTiejun Chen
Replace __get_cpu_var safely with get_cpu_var to avoid the following call trace: [ 7253.637591] BUG: using smp_processor_id() in preemptible [00000000 00000000] code: hugemmap01/9048 [ 7253.637601] caller is free_hugepd_range.constprop.25+0x88/0x1a8 [ 7253.637605] CPU: 1 PID: 9048 Comm: hugemmap01 Not tainted 3.10.20-rt14+ #114 [ 7253.637606] Call Trace: [ 7253.637617] [cb049d80] [c0007ea4] show_stack+0x4c/0x168 (unreliable) [ 7253.637624] [cb049dc0] [c031c674] debug_smp_processor_id+0x114/0x134 [ 7253.637628] [cb049de0] [c0016d28] free_hugepd_range.constprop.25+0x88/0x1a8 [ 7253.637632] [cb049e00] [c001711c] hugetlb_free_pgd_range+0x6c/0x168 [ 7253.637639] [cb049e40] [c0117408] free_pgtables+0x12c/0x150 [ 7253.637646] [cb049e70] [c011ce38] unmap_region+0xa0/0x11c [ 7253.637671] [cb049ef0] [c011f03c] do_munmap+0x224/0x3bc [ 7253.637676] [cb049f20] [c011f2e0] vm_munmap+0x38/0x5c [ 7253.637682] [cb049f40] [c000ef88] ret_from_syscall+0x0/0x3c [ 7253.637686] --- Exception: c01 at 0xff16004 Signed-off-by: Tiejun Chen<tiejun.chen@windriver.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> (cherry picked from commit 94b09d75546247ec7e0d441f352f548946619fe8) Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Iaafa3adce6ef75d8838f8e94caa759905ed77bf8 Reviewed-on: http://git.am.freescale.net:8181/29328 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-03-09arm: ls1021a: enable WoL by enabling error interrupts of eTSEC1Chenhui Zhao
In deep sleep case, when enabling Wake-on-LAN feature, receiving a magic packet will trigger an error interrupt on eTSEC1. Therefore, enable these interrupts in setting PMC interrupt registers for deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I3a2ca3e98e261d1c5c2f422203943959b871d7bd Reviewed-on: http://git.am.freescale.net:8181/32216 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-03-05arm: ls1021a: OCRAM1 does not power down in deep sleepChenhui Zhao
In the case of SD boot, system can't wake from deep sleep if OCRAM1 is powered down. Therefore, keep it on when doing deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib5f6b1c46f7c66e83595fc4fbe17789e557adee9 Reviewed-on: http://git.am.freescale.net:8181/31996 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-03-03arm: ls1021a: added SATA supportAlison Wang
Added SATA device node and enabled AHCI config by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I288e6bffea28ea31804e20190dfa6b580fa2d7eb Reviewed-on: http://git.am.freescale.net:8181/31841 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-02-13Merge branch 'rtmerge'Scott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com> Conflicts: arch/arm/kvm/mmu.c arch/arm/mm/proc-v7-3level.S arch/powerpc/kernel/vdso32/getcpu.S drivers/crypto/caam/error.c drivers/crypto/caam/sg_sw_sec4.h drivers/usb/host/ehci-fsl.c
2015-02-13powerpc-preempt-lazy-support.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13arm-preempt-lazy-support.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13x86-preempt-lazy.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13cpumask: Disable CONFIG_CPUMASK_OFFSTACK for RTThomas Gleixner
We can't deal with the cpumask allocations which happen in atomic context (see arch/x86/kernel/apic/io_apic.c) on RT right now. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13crypto: Reduce preempt disabled regions, more algosSebastian Andrzej Siewior
Don Estabrook reported | kernel: WARNING: CPU: 2 PID: 858 at kernel/sched/core.c:2428 migrate_disable+0xed/0x100() | kernel: WARNING: CPU: 2 PID: 858 at kernel/sched/core.c:2462 migrate_enable+0x17b/0x200() | kernel: WARNING: CPU: 3 PID: 865 at kernel/sched/core.c:2428 migrate_disable+0xed/0x100() and his backtrace showed some crypto functions which looked fine. The problem is the following sequence: glue_xts_crypt_128bit() { blkcipher_walk_virt(); /* normal migrate_disable() */ glue_fpu_begin(); /* get atomic */ while (nbytes) { __glue_xts_crypt_128bit(); blkcipher_walk_done(); /* with nbytes = 0, migrate_enable() * while we are atomic */ }; glue_fpu_end() /* no longer atomic */ } and this is why the counter get out of sync and the warning is printed. The other problem is that we are non-preemptible between glue_fpu_begin() and glue_fpu_end() and the latency grows. To fix this, I shorten the FPU off region and ensure blkcipher_walk_done() is called with preemption enabled. This might hurt the performance because we now enable/disable the FPU state more often but we gain lower latency and the bug is gone. Cc: stable-rt@vger.kernel.org Reported-by: Don Estabrook <don.estabrook@gmail.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13x86: crypto: Reduce preempt disabled regionsPeter Zijlstra
Restrict the preempt disabled regions to the actual floating point operations and enable preemption for the administrative actions. This is necessary on RT to avoid that kfree and other operations are called with preemption disabled. Reported-and-tested-by: Carsten Emde <cbe@osadl.org> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Cc: stable-rt@vger.kernel.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13x86-kvm-require-const-tsc-for-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13arm-enable-highmem-for-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13arm/highmem: flush tlb on unmapSebastian Andrzej Siewior
The tlb should be flushed on unmap and thus make the mapping entry invalid. This is only done in the non-debug case which does not look right. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13x86/highmem: add a "already used pte" checkSebastian Andrzej Siewior
This is a copy from kmap_atomic_prot(). Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13mm, rt: kmap_atomic schedulingPeter Zijlstra
In fact, with migrate_disable() existing one could play games with kmap_atomic. You could save/restore the kmap_atomic slots on context switch (if there are any in use of course), this should be esp easy now that we have a kmap_atomic stack. Something like the below.. it wants replacing all the preempt_disable() stuff with pagefault_disable() && migrate_disable() of course, but then you can flip kmaps around like below. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> [dvhart@linux.intel.com: build fix] Link: http://lkml.kernel.org/r/1311842631.5890.208.camel@twins [tglx@linutronix.de: Get rid of the per cpu variable and store the idx and the pte content right away in the task struct. Shortens the context switch code. ]
2015-02-13mips-disable-highmem-on-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13arm/unwind: use a raw_spin_lockSebastian Andrzej Siewior
Mostly unwind is done with irqs enabled however SLUB may call it with irqs disabled while creating a new SLUB cache. I had system freeze while loading a module which called kmem_cache_create() on init. That means SLUB's __slab_alloc() disabled interrupts and then ->new_slab_objects() ->new_slab() ->setup_object() ->setup_object_debug() ->init_tracking() ->set_track() ->save_stack_trace() ->save_stack_trace_tsk() ->walk_stackframe() ->unwind_frame() ->unwind_find_idx() =>spin_lock_irqsave(&unwind_lock); Cc: stable-rt@vger.kernel.org Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13arm-disable-highmem-on-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13power-disable-highmem-on-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13Powerpc: Use generic rwsem on RTThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13irq_work: allow certain work in hard irq contextSebastian Andrzej Siewior
irq_work is processed in softirq context on -RT because we want to avoid long latencies which might arise from processing lots of perf events. The noHZ-full mode requires its callback to be called from real hardirq context (commit 76c24fb ("nohz: New APIs to re-evaluate the tick on full dynticks CPUs")). If it is called from a thread context we might get wrong results for checks like "is_idle_task(current)". This patch introduces a second list (hirq_work_list) which will be used if irq_work_run() has been invoked from hardirq context and process only work items marked with IRQ_WORK_HARD_IRQ. This patch also removes arch_irq_work_raise() from sparc & powerpc like it is already done for x86. Atleast for powerpc it is somehow superfluous because it is called from the timer interrupt which should invoke update_process_times(). Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13x86-no-perf-irq-work-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13x86: Use generic rwsem_spinlocks on -rtThomas Gleixner
Simplifies the separation of anon_rw_semaphores and rw_semaphores for -rt. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13x86: stackprotector: Avoid random pool on rtThomas Gleixner
CPU bringup calls into the random pool to initialize the stack canary. During boot that works nicely even on RT as the might sleep checks are disabled. During CPU hotplug the might sleep checks trigger. Making the locks in random raw is a major PITA, so avoid the call on RT is the only sensible solution. This is basically the same randomness which we get during boot where the random pool has no entropy and we rely on the TSC randomnness. Reported-by: Carsten Emde <carsten.emde@osadl.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13x86/mce: Defer mce wakeups to threads for PREEMPT_RTSteven Rostedt
We had a customer report a lockup on a 3.0-rt kernel that had the following backtrace: [ffff88107fca3e80] rt_spin_lock_slowlock at ffffffff81499113 [ffff88107fca3f40] rt_spin_lock at ffffffff81499a56 [ffff88107fca3f50] __wake_up at ffffffff81043379 [ffff88107fca3f80] mce_notify_irq at ffffffff81017328 [ffff88107fca3f90] intel_threshold_interrupt at ffffffff81019508 [ffff88107fca3fa0] smp_threshold_interrupt at ffffffff81019fc1 [ffff88107fca3fb0] threshold_interrupt at ffffffff814a1853 It actually bugged because the lock was taken by the same owner that already had that lock. What happened was the thread that was setting itself on a wait queue had the lock when an MCE triggered. The MCE interrupt does a wake up on its wait list and grabs the same lock. NOTE: THIS IS NOT A BUG ON MAINLINE Sorry for yelling, but as I Cc'd mainline maintainers I want them to know that this is an PREEMPT_RT bug only. I only Cc'd them for advice. On PREEMPT_RT the wait queue locks are converted from normal "spin_locks" into an rt_mutex (see the rt_spin_lock_slowlock above). These are not to be taken by hard interrupt context. This usually isn't a problem as most all interrupts in PREEMPT_RT are converted into schedulable threads. Unfortunately that's not the case with the MCE irq. As wait queue locks are notorious for long hold times, we can not convert them to raw_spin_locks without causing issues with -rt. But Thomas has created a "simple-wait" structure that uses raw spin locks which may have been a good fit. Unfortunately, wait queues are not the only issue, as the mce_notify_irq also does a schedule_work(), which grabs the workqueue spin locks that have the exact same issue. Thus, this patch I'm proposing is to move the actual work of the MCE interrupt into a helper thread that gets woken up on the MCE interrupt and does the work in a schedulable context. NOTE: THIS PATCH ONLY CHANGES THE BEHAVIOR WHEN PREEMPT_RT IS SET Oops, sorry for yelling again, but I want to stress that I keep the same behavior of mainline when PREEMPT_RT is not set. Thus, this only changes the MCE behavior when PREEMPT_RT is configured. Signed-off-by: Steven Rostedt <rostedt@goodmis.org> [bigeasy@linutronix: make mce_notify_work() a proper prototype, use kthread_run()] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13x86/mce: fix mce timer intervalMike Galbraith
Seems mce timer fire at the wrong frequency in -rt kernels since roughly forever due to 32 bit overflow. 3.8-rt is also missing a multiplier. Add missing us -> ns conversion and 32 bit overflow prevention. Cc: stable-rt@vger.kernel.org Signed-off-by: Mike Galbraith <bitbucket@online.de> [bigeasy: use ULL instead of u64 cast] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2015-02-13x86: Convert mce timer to hrtimerThomas Gleixner
mce_timer is started in atomic contexts of cpu bringup. This results in might_sleep() warnings on RT. Convert mce_timer to a hrtimer to avoid this. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13softirq-disable-softirq-stacks-for-rt.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13ARM: Initialize ptl->lock for vector pageFrank Rowand
Without this patch, ARM can not use SPLIT_PTLOCK_CPUS if PREEMPT_RT_FULL=y because vectors_user_mapping() creates a VM_ALWAYSDUMP mapping of the vector page (address 0xffff0000), but no ptl->lock has been allocated for the page. An attempt to coredump that page will result in a kernel NULL pointer dereference when follow_page() attempts to lock the page. The call tree to the NULL pointer dereference is: do_notify_resume() get_signal_to_deliver() do_coredump() elf_core_dump() get_dump_page() __get_user_pages() follow_page() pte_offset_map_lock() <----- a #define ... rt_spin_lock() The underlying problem is exposed by mm-shrink-the-page-frame-to-rt-size.patch. Signed-off-by: Frank Rowand <frank.rowand@am.sony.com> Cc: Frank <Frank_Rowand@sonyusa.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/4E87C535.2030907@am.sony.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-02-13kconfig-disable-a-few-options-rt.patchThomas Gleixner
Disable stuff which is known to have issues on RT Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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