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2013-09-18Merge branch 'b4860rev2' into sdk-v1.4.xJ. German Rivera
2013-09-18fsl/powerpc: fix cpu_setup_fsl_booke.S build errorWang Dongsheng
when we use corenet32_smp_defconfig. Occur, the following error: cpu_setup_fsl_booke.S:83: undefined reference to `.has_pw20_altivec_idle' cpu_setup_fsl_booke.S:108: undefined reference to `.has_pw20_altivec_idle' The root cause is "bl .has_pw20_altivec_idle", the "." is only for 64bit, should be "bl has_pw20_altivec_idle". Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I13b654b400313a351e50b4105eabb9affa013c34 Reviewed-on: http://git.am.freescale.net:8181/4779 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhao Chenhui-B35336 <chenhui.zhao@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-17Merge branch 'b4860rev2' into sdk-v1.4.xJ. German Rivera
2013-09-17fsl/powerpc: fix kernel cannot boot under topazWang Dongsheng
when we have embedded hypervisor functionality, the MMUCFG[LPIDSIZE] is not zero, this is issue will occur. asm functions (setup_altivec_idle + setup_pw20_idle) that overwrite register r4. Register r4 holds the second parameter of the setup___setup_cpu_e* functions and is a pointer to the cpu spec features. Under baremetal the param is not used so the problem doesn't show up, but under hypervisor it is used. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Tested-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Change-Id: I0fe5f7814ff0a77988f3b8540933a522f3217679 Reviewed-on: http://git.am.freescale.net:8181/4789 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tudor Laurentiu-B10716 <Laurentiu.Tudor@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-16KVM: PPC: e500: Fix SPR PWRMGTCR0 typoMihai Caraman
Fix SPR PWRMGTCR0 typo Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: I3699ec72ed96e74cb5ba04aeef1d4f0c1e79d944 Reviewed-on: http://git.am.freescale.net:8181/4746 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-13KVM: PPC: e500: Fix default TLB for victim hintMihai Caraman
TLB search for victim hint in KVM relied on host to set default TLB. When hardware tablewalk support is enabled the kernel sets TLB0 as default which led KVM to evict the bolted entry. Set and restore the default TLB when searching for victim hint. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Idaa65fda62787a2b9b02641649b8c411ffe458fa Reviewed-on: http://git.am.freescale.net:8181/4698 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-12KVM: PPC: e500: Emulate power management control SPRMihai Caraman
e6500 rev2 Linux guest uses power management SPR to enable idle power down for a core and its devices setting up the idle count period at boot time. The host already controls the power management configuration and the guest will benefit from them, so emulate the guest requests as a nop. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Ic6be4493d89c82760500f21318ae326cabb74107 Reviewed-on: http://git.am.freescale.net:8181/4701 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-12powerpc/85xx: fix pw20&altivec idle can not work after cpuhotplug restoreWang Dongsheng
PW20 & AltiVec idle should be enabled, when the cpuhotplug restore. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: Ib4d2ac24eedde0a6a814f3b5f0b42ca03e20494c Reviewed-on: http://git.am.freescale.net:8181/4269 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-06powerpc/fs: Add VFAT file-system configsRamneek Mehresh
Add CONFIG_NLS_CODEPAGE_437, CONFIG_NLS_CODEPAGE_850, CONFIG_NLS_ISO8859_1 in default configs for 85xx and 86xx socs. Required for mounting vfat file-systems on USB devices Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Change-Id: I6b521f46e6a69a783147bf304ea74e189e89bf8a Reviewed-on: http://git.am.freescale.net:8181/4502 Reviewed-by: Aggrwal Poonam-B10812 <Poonam.Aggrwal@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Gupta Suresh-B42813 <suresh.gupta@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-04Revert "powerpc: remove default -mtune=power7/power4 flag"J. German Rivera
This reverts commit 0d22173d1a7cc3b094144a1dadc8164fca023fbf, which needed to be reverted, as it causes a compilation error for the linux kernel, when built for the 85xx/e6500rev2_defconfig configuration. See CR ENGR00278263.
2013-09-04powerpc/smp: fix build issueWang Dongsheng
Fix build problem caused by typo introduced by 18621b8153 (build error: unused variable 'smp_85xx_ops') Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I256530961f98a2bc81a62bf0911628979438d61c Reviewed-on: http://git.am.freescale.net:8181/4039 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Bhushan Bharat-R65777 <Bharat.Bhushan@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-09-04powerpc: dying cpus spins by defaultBharat Bhushan
When a cpu is dying, the dying cpu finally runs ppc_md.cpu_die(). Default set the ppc_md.cpu_die points to generic_mach_cpu_die(), which set the CPU state to CPU_DEAD and spins. Also fix to dereference guts_regs only when it is not NULL. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: I9372cb382d8306b429b9a94555c7e2123c53cd27 Reviewed-on: http://git.am.freescale.net:8181/3735 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-09-04powerpc: mpc85xx: generic timer sync is no more neededBharat Bhushan
Now in all socs which require timebase sync we have guts based timer sync mechanism and we should not use be using generic timebase sync anymore. This patch removes the generic timbase sync for KEXEC also as this can also use same guts based timebase sync. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: Ie1e5b55887862c6798ce45003cadcb4adb8d564a Reviewed-on: http://git.am.freescale.net:8181/3912 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-30Merge branch 'b4860rev2' into sdk-v1.4.xJ. German Rivera
2013-08-30powerpc: Update KBUILD_AFLAGS with core specific optionsCatalin Udma
Update also KBUILD_AFLAGS specifying the target core for CONFIG_E500 -mcpu=e5500/e500mc/8540 Add also -msoft-float. Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Change-Id: Ibaf93105792b84dae836c7020ff708ed7afbad6a Reviewed-on: http://git.am.freescale.net:8181/3764 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-27Merge branch 'b4860rev2' into sdk-v1.4.xJ. German Rivera
2013-08-27Enhance get_stash_id API to get the stashid for DSP L2 cache.Varun Sethi
The stashid for the DSP cluster L2 cache is programmed by SDOS. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7a8203e2dd99e6ccfeacd25305378a4c33becac2 Reviewed-on: http://git.am.freescale.net:8181/4036 Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-08-26powerpc/85xx: add hardware automatically enter pw20 stateWang Dongsheng
Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I199d6bedeb045f421da69d8ce99c45bea517fc32 Reviewed-on: http://git.am.freescale.net:8181/3948 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-26powerpc/85xx: add hardware automatically enter altivec idle stateWang Dongsheng
Each core's AltiVec unit may be placed into a power savings mode by turning off power to the unit. Core hardware will automatically power down the AltiVec unit after no AltiVec instructions have executed in N cycles. The AltiVec power-control is triggered by hardware. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I613fba4492d3d65dcf903d13735bc9e45e5d443c Reviewed-on: http://git.am.freescale.net:8181/3731 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-26Updates to device trees for B4860 for DSP clusters and their L2 cachesPoonam Aggrwal
B4860 has 1 PPC core cluster and 3 DSP core clusters. Similarly B4420 has 1 PPC core cluster and 1 DSP core cluster. Each DSP core cluster consists of 2 SC3900 cores and a shared L2 cache. 1. Add DSP clusters for B4420 2. Reorganized the L2 cache nodes such that they now appear in only the soc specific dtsi files(b4860si-post.dtsi and b4420si-post.dtsi). Earlier they were shown partly in common b4si-post.dtsi and si specific b4860si-post.dtsi files . 3. Fixed an issue in b4860si-pre.dtsi, now DSP cluster correctly point to their respective L2 caches Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Change-Id: Ie09007f4c596fc5947e0b4b005225b8b1f9aa443 Reviewed-on: http://git.am.freescale.net:8181/4005 Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-19powerpc/smp: fix build issueWang Dongsheng
Fix build problem caused by typo introduced by 18621b8153 (build error: unused variable 'smp_85xx_ops') Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I256530961f98a2bc81a62bf0911628979438d61c Reviewed-on: http://git.am.freescale.net:8181/4039 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Bhushan Bharat-R65777 <Bharat.Bhushan@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-16powerpc: remove default -mtune=power7/power4 flagJames Yang
The default optimization flag -mtune=power7 has questionable performance effects on many other implementations. This patch removes the flag and leaves it up to the compiler default, a target-specific config-option -mtune=, or a -mcpu= flag to choose the tuning. Change-Id: Ia307644104ef10e75fa511d621ee158cb6e65baa Signed-off-by: James Yang <James.Yang@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/3960 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-16powerpc/85xx: add hardware automatically enter pw20 stateWang Dongsheng
Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I199d6bedeb045f421da69d8ce99c45bea517fc32 Reviewed-on: http://git.am.freescale.net:8181/3948 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-15powerpc: mpc85xx: generic timer sync is no more neededBharat Bhushan
Now in all socs which require timebase sync we have guts based timer sync mechanism and we should not use be using generic timebase sync anymore. This patch removes the generic timbase sync for KEXEC also as this can also use same guts based timebase sync. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: Ie1e5b55887862c6798ce45003cadcb4adb8d564a Reviewed-on: http://git.am.freescale.net:8181/3912 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-14powerpc/85xx: add hardware automatically enter altivec idle stateWang Dongsheng
Each core's AltiVec unit may be placed into a power savings mode by turning off power to the unit. Core hardware will automatically power down the AltiVec unit after no AltiVec instructions have executed in N cycles. The AltiVec power-control is triggered by hardware. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I613fba4492d3d65dcf903d13735bc9e45e5d443c Reviewed-on: http://git.am.freescale.net:8181/3731 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-13powerpc: dying cpus spins by defaultBharat Bhushan
When a cpu is dying, the dying cpu finally runs ppc_md.cpu_die(). Default set the ppc_md.cpu_die points to generic_mach_cpu_die(), which set the CPU state to CPU_DEAD and spins. Also fix to dereference guts_regs only when it is not NULL. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: I9372cb382d8306b429b9a94555c7e2123c53cd27 Reviewed-on: http://git.am.freescale.net:8181/3735 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-07powerpc/b4860: Add StarCore/SC3900 nodes in B4860 device filesShaveta Leekha
- Add dsp nodes in B4860 pre silicon device file - Add L2 cache nodes for dsp/Starcores in B4860 post silicon file Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Change-Id: I10329607b97961a44f46bc814032fc9faa0e7f96 Reviewed-on: http://git.am.freescale.net:8181/3693 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-07powerpc/fsl-booke: Work around erratum A-006958Scott Wood
Erratum A-006598 says that 64-bit mftb is not atomic -- it's subject to a similar race condition as doing mftbu/mftbl on 32-bit. The lower half of timebase is updated before the upper half; thus, we can share the workaround for a similar bug on Cell. This workaround involves looping if the lower half of timebase is zero, thus avoiding the need for a scratch register (other than CR0). This workaround must be avoided when the timebase is frozen, such as during the timebase sync code. This deals with kernel and vdso accesses, but other userspace accesses will of course need to be fixed elsewhere. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I88da5fef252872ba17c4496ed1a053dc4be645af --- v2: Share the Cell workaround instead of using the workaround suggested by the erratum. Reviewed-on: http://git.am.freescale.net:8181/3749 Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-07powerpc/e6500: skip rev1 errata workaround on rev2Scott Wood
"default y" prevents the mere absence of those config lines from turning off the errata. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ib825e8c5941f422990a997a79412669bda677d79 Reviewed-on: http://git.am.freescale.net:8181/3748 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2013-08-02powerpc/dts: fix sRIO and RMan error interrupts for b4860Minghuan Lian
For B4 platform, MPIC EISR register is in reversed bitmap order, instead of "Error interrupt source 0-31. Bit 0 represents SRC0." the correct ordering is "Error interrupt source 0-31. Bit 0 represents SRC31." This patch is to fix sRIO and RMan EISR bit value of error interrupts in dts node. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I3eacf5ebee6da5ac847d6ab93fe1e38a07e57176 Reviewed-on: http://git.am.freescale.net:8181/3616 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com> Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
2013-07-12Update compilation flags with core specific optionsCatalin Udma
If CONFIG_E500 is enabled, the compilation flags are updated specifying the target core -mcpu=e5500/e500mc/8540 Also remove -Wa,-me500, being incompatible with -mcpu=e5500/e6500 The assembler option is redundant if the -mcpu= flag is set. Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Change-Id: Id786d80825d09aa40052666bc5be173cc89bc1ec Reviewed-on: http://git.am.freescale.net:8181/3068 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-07-05powerpc/hibernate: PPC64 fix user threads access to kernel spaceWang Dongsheng
If PID is used in the TLB, after hibernation resume, the user threads will access to kernel space. We must restore PID register, because TLB will use PID. The hibernation suspend flow is trapped from user space to kernel space, the PID register is user thread pid. The hibernation resume is begin in kernel start flow, the PID alway 0. After the kernel thread back to user thread, there is not have context switch and the pid can not update, because the kernel thread is trapped form user space. So if we did't restore PID the user space of thread will be addressing in the kernel space. There are two ways to restore PID: 1/ In swsusp_arch_suspend/swsusp_arch_resume, save/resotre PID register. 2/ Form restore_processor_state to restore. this function will do context switch. switch_mmu_context(current->active_mm, current->active_mm) PPC32 Using the second method. For consistency reason, PPC64 using the same way. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I0563be5cc5da67877e0083256c7425096cbc95e6 Reviewed-on: http://git.am.freescale.net:8181/2908 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Yang-R58472 <LeoLi@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-06-07powerpc/bsc9132: dts: Add tbi handle to enet1 nodeHarninder Rai
Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Change-Id: If1dcb88515b720a82d4193cbd11814c296cd1ed9 Reviewed-on: http://git.am.freescale.net:8181/2896 Reviewed-by: Burmi Naveen-B16502 <NaveenBurmi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-06-06KVM: PPC: use pr_debug not printk for KVM debug printsStuart Yoder
the printk always executes whenever a vcpu is moved to a new physical cpu, which adds unnessary overhead to context switches...switch to pr_debug which only executes when enabled at compile time Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Change-Id: I9856ddcdb061ee6818e2b5ec090728ee1841c8f4 Reviewed-on: http://git.am.freescale.net:8181/2872 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-06-05Update RX default queue FQID for shared mac in T4/B4 device treesKuldip Giroh
- RX default FQID must match with the queue base in default distribution in the policy file. - RX error queue FQIDs are also updated for shared mac node. Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Change-Id: If404811a621a97ef113685b608077e9a2c54f160 Reviewed-on: http://git.am.freescale.net:8181/2848 Reviewed-by: Garg Vakul-B16394 <vakul@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-31Powerpc/dts: Correct sdhci quirk for bsc9131 and bsc9132Haijun.Zhang
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12" to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Change-Id: Id994e69850578d907de047dde318883675911852 Reviewed-on: http://git.am.freescale.net:8181/2795 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xie Xiaobo-R63061 <X.Xie@freescale.com> Reviewed-by: Rai Harninder-B01044 <harninder.rai@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-31powerpc/85xx: l2sram - Add compatible string for BSC9132 platformHarninder Rai
Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Change-Id: Ia55010a7b82b67058e49677f2cac3030e3b3cdf1 Reviewed-on: http://git.am.freescale.net:8181/2814 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Burmi Naveen-B16502 <NaveenBurmi@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-31dpaa_eth: Use the driver Tx queue selection mechanismIoana Radulescu
Fix the defconfigs such that the driver internal Tx queue selection mechanism is enabled. The alternative was using the kernel XPS, which causes massive damage to the recycling algorithm on forwarding scenarios. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Change-Id: I983a0de4a4bd4b88d30595d74207250cf16968d7 Reviewed-on: http://git.am.freescale.net:8181/2808 Reviewed-by: Sovaiala Cristian-Constantin-B39531 <Cristian.Sovaiala@freescale.com> Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Hamciuc Bogdan-BHAMCIU1 <bogdan.hamciuc@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-30KVM: PPC: Book3e: Get vcpu's last instruction for emulationMihai Caraman
lwepx faults needs to be handled by KVM and this implies additional code in DO_KVM (for DTB_MISS, DSI and LRAT) to check ESR[EPID] and EPLC[EGS] which is too intrusive for the host. Get rid of lwepx and acquire last instuction in kvmppc_handle_exit() by searching for the physical address and kmap it. This fixes an infinite loop caused by lwepx data TLB miss handled in the host and the TODO for TLB eviction and execute-but-not-read entries. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Id1255d31406a2322292ff06a63c164e861c45fd3 Reviewed-on: http://git.am.freescale.net:8181/2679 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-29powerpc: Remove default Y from WSP platformsScott Wood
Default Y is generally antisocial behavior to begin with, and WSP code breaks with CONFIG_SMP turned off. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I020a237b72676e31339496865d6de4838d52d95a Reviewed-on: http://git.am.freescale.net:8181/2746 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-29B4860QDS: Disable mdio node by defaultSuresh Gupta
MDIO node get enable during fdt fixup on basis of fsl_b4860_serdes2 string in hwconfig. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: I4686310afde78456d53c95ef5de727bee04b489a Reviewed-on: http://git.am.freescale.net:8181/2742 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Aggrwal Poonam-B10812 <Poonam.Aggrwal@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-28powerpc/85xx: Disable CTS pin for QE UART0Xie Xiaobo
On P1025TWR board, the UCC7 acted as UART port0. However, The UCC7's CTS pin is low level in default, it will impact the transmission in full duplex communication. So disable the Flow control pin - CTS. The UCC7 UART just can use RXD and TXD pins. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Change-Id: I8ab9b3edb0edb6440ce32a83fbcf0200c8eb54f7 Reviewed-on: http://git.am.freescale.net:8181/2706 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-28Add macless and shared mac nodes in device trees for T4/B4Kuldip Giroh
- Macless enables communication between user space config commands and USDPAA app. - Shared mac enables kernel and USDPAA to receive traffic from a shared ethernet port on the basis of defined PCD rules. For T4, fm2-mac10 is made shared node and for B4, fm1-mac10 is made shared node. Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Change-Id: I5e5399fb7be3826bc3b89f4613bdd632e5e7f338 Reviewed-on: http://git.am.freescale.net:8181/2710 Reviewed-by: Sovaiala Cristian-Constantin-B39531 <Cristian.Sovaiala@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24powerpc/32bit,PREEMPT:Load TI_FLAGS to check NEED_RESCHEDPriyanka Jain
Add instruction to load TI_FLAGS in r8 While returning from exception handling in case of PREEMPT enabled, _TIF_NEED_RESCHED bit is checked in TI_FLAGS (thread_info flag) of current task. Only if this bit is set, it should continue with the process of calling preempt_schedule_irq() to schedule highest priority task if available. Current code assumes that r8 contains TI_FLAGS and check this for _TIF_NEED_RESCHED, but as r8 is modified in the code which executes before this check, r8 no longer contains the expected TI_FLAGS information. As a result check for comparison with _TIF_NEED_RESCHED was failing even if NEED_RESCHED bit is set in the current thread_info flag. Due to this, preempt_schedule_irq() and in turn scheduler was not getting called even if highest priority task is ready for execution leading to increase in latency issue. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Change-Id: Ibc2c94ba9031488fc1e8e2ceae864dcea171ceae Reviewed-on: http://git.am.freescale.net:8181/2645 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24powerpc/fsl: Introduce a generic pci-e compatible named "fsl,qoriq-pcie"Laurentiu Tudor
This will allow future code to simply check the pci-e controller version register plus getting rid of the redundant version from within the compatible string. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Change-Id: I7211a7c426f9e11920369355900ccd236fc248a1 Reviewed-on: http://git.am.freescale.net:8181/2670 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24kvm/ppc/booke: Hold srcu lock when calling gfn functionsScott Wood
KVM core expects arch code to acquire the srcu lock when calling gfn_to_memslot and similar functions. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ie62a99a1b4447201b31bda839cc6ef32f1fcbd51 Reviewed-on: http://git.am.freescale.net:8181/2682 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24powerpc/85xx: Enabled FMAN write data stashing for t4/b4 platformsVakul Garg
Stashing of FMAN writes into platform cache improves USDPAA IPSEC and Linux IPFwd performance. Without this, the performance of USPAA IPSEC on T4 is lower than P4080. Change-Id: Ic9136162df108dfbd4da99df3b3a3744537c9909 Signed-off-by: Vakul Garg <vakul@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/2652 Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24powerpc/85xx: Enabled stashing of FMAN write dataVakul Garg
This patch enables translation of FMAN write transactions into write-with-stashing (to CPC) using IOMMU operation mapping mechanism. This is required for USDPAA IPSEC application so that SEC is able to DMA data faster and show better performance. On T4240, this patch shows up 20% performance gain for USDPAA IPSEC. Change-Id: I17620c2ee44812adb5d02eee217f0ff2e9e85f67 Signed-off-by: Vakul Garg <vakul@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/2651 Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24powerpc/bsc913x: fix power node and mpic timer nodeZhao Chenhui
* Add power node. * Fix the mpic timer node. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Change-Id: I2cfdda17170a8680b19b55da261f712c2068580d Reviewed-on: http://git.am.freescale.net:8181/2665 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Burmi Naveen-B16502 <NaveenBurmi@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-22powerpc/mpic: fix interrupts distribution problem on 64-bit platformsZhao Chenhui
For the mpic with a flag MPIC_SINGLE_DEST_CPU, only one bit should be set in interrupt destination registers. This change is applicable to 32-bit and 64-bit platforms. Change-Id: If573a1911eca4465f253f427fa141e42fdceabae Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/2504 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
generated by cgit v0.10.2 at 2024-10-05 12:33:49 (GMT)