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The module is called caamalg_qi. This module implements offloading aead
algos to caam using queue interface backend. Since the queue interface
based caam response processing automatically scales with the number of
cores, it shows up as better performance than job ring based module
(caamalg).
For IPSEC (on P4080), the performance is 1.5 times with QI based backend
than JR based backend driver.
Change-Id: I74df81abce13c913a7743cecb5d5481221f360b7
Signed-off-by: Vakul Garg <vakul@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/2076
Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com>
Reviewed-by: Porosanu Alexandru-B06830 <alexandru.porosanu@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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CAAM supports two interfaces for crypto job submission. These are job
ring based and QMAN based interfaces. QMAN based interfaces are present
of DPAA enabled platforms. This patch adds a platform device for
accessing the caam's queue interface. The requests are submitted to caam
using one frame queue per cryptographic context. Each crypto context
has one shared descriptor. This shared descriptor is attached to
frame queue associated with corresponding driver context using
context_a.
The driver hides the mechanics of FQ creation, initialisation from its
applications. Each cryptographic context needs to be associated with
driver context which houses the FQ to be used to transport the job to
SEC. The driver provides apis for:
(a) Context creation
(b) Job submission
(c) Context deletion
(d) Checking if path to SEC or from SEC is congested
The driver supports affining its context to a particular CPU. This means
that any responses from the SEC for the context in question would arrive
at the given CPU. This helps in implementing one cpu per pkt round trip
in ipsec application.
The driver processes the caam respones under NAPI contexts. NAPI
contexts are instantiated only on cores with affined portals since only
cores having their own portal can receive responses from DQRR.
The responses from CAAM for all cryptographic contexts ride on a fixed
set of FQs. We use one response FQ per portal owning core. The response
FQ is configured in each core's and thus portal's dedicated channel.
This gives the flexibility to direct the caam's responses for a crypto
context on a given core.
Change-Id: Id9661caae0ecda933e35eef40fb0b25013365397
Signed-off-by: Vakul Garg <vakul@freescale.com>
Change-Id: I79819af83d57c64acb4a76213452ce912cba0273
Reviewed-on: http://git.am.freescale.net:8181/2075
Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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caam_read copies random bytes from two buffers into output.
caam rng can fill empty buffer 0xffff bytes at a time,
but the buffer sizes are rounded down to multiple of cacheline size.
Signed-off-by: Yuan Kang <Yuan.Kang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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caam supports ahash hmac with sha algorithms and md5.
Signed-off-by: Yuan Kang <Yuan.Kang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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create separate files for split key generation and scatterlist functions.
Signed-off-by: Yuan Kang <Yuan.Kang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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The SEC4 supercedes the SEC2.x/3.x as Freescale's
Integrated Security Engine. Its programming model is
incompatible with all prior versions of the SEC (talitos).
The SEC4 is also known as the Cryptographic Accelerator
and Assurance Module (CAAM); this driver is named caam.
This initial submission does not include support for Data Path
mode operation - AEAD descriptors are submitted via the job
ring interface, while the Queue Interface (QI) is enabled
for use by others. Only AEAD algorithms are implemented
at this time, for use with IPsec.
Many thanks to the Freescale STC team for their contributions
to this driver.
Signed-off-by: Steve Cornelius <sec@pobox.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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