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While obtaining the stash destination from the device tree, current code
was assuming a single cpu reg property value. In case of t4240, the e6500
cpu node has two entries per reg property. Thus, for certain cpu values code
wasn't able to find a valid device tree node.
The code also lacked a check to identify if a valid cpu node (cpu node for a stash
target) had been found. Thus, resulting in a crash on null cpu node pointer access.
This patch fixes the issue, by introducing a mechanism to process all cpu
reg property values per cpu node. Also, introduced chek to identify if
cpu node corresponding to the stash vcpu has been found or not.
Additionally, added a check for l3-cache-controller compatible strings
for T4 and B4 devices.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Iced2d9b85cb87a01a6cbc8cb1a592f92e9f7f704
Reviewed-on: http://git.am.freescale.net:8181/1276
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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This patch contains the following fixes:
1. Support for finding guts node on T4 & B4 platforms.
2. Make iova dma_addr_t constistent with iova_to_phys API change.
3. Disable SPAACE while reconfiguring it.
4. Make API and internal function static.
5. Free data pointer in case of an error.
6. Update comment description and remove unneeded comment.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I4763d9783e9f3d8057c991ca424e48e337c20f3b
Reviewed-on: http://git.am.freescale.net:8181/884
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Following is a brief description of the PAMU hardware:
PAMU determines what action to take and whether to authorize the action on
the basis of the memory address, a Logical IO Device Number (LIODN), and
PAACT table (logically) indexed by LIODN and address. Hardware devices which
need to access memory must provide an LIODN in addition to the memory address.
Peripheral Access Authorization and Control Tables (PAACTs) are the primary
data structures used by PAMU. A PAACT is a table of peripheral access
authorization and control entries (PAACE).Each PAACE defines the range of
I/O bus address space that is accessible by the LIOD and the associated access
capabilities.
There are two types of PAACTs: primary PAACT (PPAACT) and secondary PAACT
(SPAACT).A given physical I/O device may be able to act as one or more
independent logical I/O devices (LIODs). Each such logical I/O device is
assigned an identifier called logical I/O device number (LIODN). A LIODN is
allocated a contiguous portion of the I/O bus address space called the DSA window
for performing DSA operations. The DSA window may optionally be divided into
multiple sub-windows, each of which may be used to map to a region in system
storage space. The first sub-window is referred to as the primary sub-window
and the remaining are called secondary sub-windows.
This patch provides the PAMU driver (fsl_pamu.c) and the corresponding IOMMU
API implementation (fsl_pamu_domain.c). The PAMU hardware driver (fsl_pamu.c)
has been derived from the work done by Ashish Kalra and Timur Tabi.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
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