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path: root/drivers/iommu
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2013-08-27Update the operation mapping settings required by the DSP side for MapleVarun Sethi
and DMA. For the DSP side the basic requirement for stashing is to prevent device initiated reads and writes going to the DDR. RWNITC and WWSOT operation mappings aid in achieving these objectives. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1634ff877d9c8e7c6a3de95aee4a3848cc149973 Reviewed-on: http://git.am.freescale.net:8181/4128 Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-08-27Enhance get_stash_id API to get the stashid for DSP L2 cache.Varun Sethi
The stashid for the DSP cluster L2 cache is programmed by SDOS. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7a8203e2dd99e6ccfeacd25305378a4c33becac2 Reviewed-on: http://git.am.freescale.net:8181/4036 Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-08-27Check for valid window before proceeding to set the stash or the omi attribute.Varun Sethi
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I6bbad9f1f1240fa23ae6997f5a0cdc6cb49228e1 Reviewed-on: http://git.am.freescale.net:8181/4035 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Tested-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-08-26Add operation mapping for DMA controller and Maple.Varun Sethi
These are required for ALU DSP stashing use case. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7efacb81b60d23e6e5f91632547f8b9a04028a1f Reviewed-on: http://git.am.freescale.net:8181/3442 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-08-26Add operation mapping for PMAN.Varun Sethi
Setup and operation mapping index for PMAN. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I4384a247491293260c1da1d4cf6cfc3b2bec2034 Reviewed-on: http://git.am.freescale.net:8181/3441 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-08-26Make stash id and operation mapping index per window attributes.Varun Sethi
Stash ID and operation mapping can now be set per dma window. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I987abbcba0575fea1b43843c2bce342f4eae4df2 Reviewed-on: http://git.am.freescale.net:8181/3439 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Conflicts: drivers/iommu/fsl_pamu.c drivers/iommu/fsl_pamu.h drivers/iommu/fsl_pamu_domain.c
2013-08-26Move operation mapping index to iommu.h.Varun Sethi
Represent operation mappings as an enum. These have been moved to iommu.h to support IOMMU API for setting operation mappings per window. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I900274f8ed703b9e10a4b3fb7d6653bd8c3a080d Reviewed-on: http://git.am.freescale.net:8181/3438 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-08-26Introduce an API for setting operation mapping index per window.Varun Sethi
This API can be used for setting operation mapping per DMA window. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Iea6d7993f09bddbaae94c475fd192f5106784bde Reviewed-on: http://git.am.freescale.net:8181/3440 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Conflicts: drivers/iommu/fsl_pamu.c drivers/iommu/fsl_pamu.h drivers/iommu/fsl_pamu_domain.c Change-Id: Iea6d7993f09bddbaae94c475fd192f5106784bde Reviewed-on: http://git.am.freescale.net:8181/3440 Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com> Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
2013-07-12Put the PCI specific code in the PAMU driver under CONFIG_PCI.Varun Sethi
This fixes the problem where the kernel build breaks, when PCI support is disabled. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I698626ec0a40ba81ef132890bc339c6be10d8673 Reviewed-on: http://git.am.freescale.net:8181/3282 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-30[PATCH v3] iommu/fsl: Modify PAMU access violation handler.Varun Sethi
Don't panic in case of an access violation, just disable the LIODN. Also, handle the hardware errata where access violation can be generated in case of an invalid LIODN. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Ia6be04bf158cf6b722564c5ae690fba2b511d5f3 Reviewed-on: http://git.am.freescale.net:8181/2790 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-30iommu/fsl : Enable PAMU window for all possible LIODNSVarun Sethi
The "enable_rmaining_liodn" function opens the PAMU window for all possible LIODN values. This provides a workaround to the bug in u-boot, where it fails to program LIODN values (in device tree), for cases where packet frame descriptors from FMAN can be enqueued directly to hardware blocks like SEC and RMAN. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I454d37dc7b7bc5bc74de0af815e19eb2796937b8 Reviewed-on: http://git.am.freescale.net:8181/2789 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bulie Radu-Andrei-B37577 <Radu.Bulie@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-24powerpc/85xx: Enabled stashing of FMAN write dataVakul Garg
This patch enables translation of FMAN write transactions into write-with-stashing (to CPC) using IOMMU operation mapping mechanism. This is required for USDPAA IPSEC application so that SEC is able to DMA data faster and show better performance. On T4240, this patch shows up 20% performance gain for USDPAA IPSEC. Change-Id: I17620c2ee44812adb5d02eee217f0ff2e9e85f67 Signed-off-by: Vakul Garg <vakul@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/2651 Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-20Merge tag 'v3.8.13'Scott Wood
This is the 3.8.13 stable release
2013-05-11iommu/amd: Properly initialize irq-table lockJoerg Roedel
commit 197887f03daecdb3ae21bafeb4155412abad3497 upstream. Fixes a lockdep warning. Reviewed-by: Shuah Khan <shuahkhan@gmail.com> Signed-off-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-05-10Subject: [PATCH v5] Support for dummy vfio iommu driver.Varun Sethi
This is primarily required for supporting vfio direct device assignment on platforms that don't have a hardware IOMMU. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Id3e968a7c4110fe392354b053112e2dc083adebd Reviewed-on: http://git.am.freescale.net:8181/2401 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Bhushan Bharat-R65777 <Bharat.Bhushan@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-01Fix PAMU allocations while in spinlockRoy Pledge
Change-Id: I21d60327af9f68c6e13e5774f54cd2accb80575f Reviewed-on: http://git.am.freescale.net:8181/2307 Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-19fsl iommu: add get_dev_iommu_domainBharat Bhushan
returns the iommu_domain of the requested device for fsl pamu. Use PCI controller dev struct for pci devices as current LIODN schema assign LIODN to PCI controller not PCI device. This will be corrected with proper LIODN schema. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: Icf07380a0f83e766b994b7a840085396fc470077 Reviewed-on: http://git.am.freescale.net:8181/1491 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-19iommu: add api to get iommu_domain of a deviceBharat Bhushan
This api return the iommu domain to which the device is attached. The iommu_domain is required for making API calls related to iommu. Follow up patches which use this API to know iommu maping. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: Ib4ff98b9e12f32bdbd8ecbe8379b102f7b10efa7 Reviewed-on: http://git.am.freescale.net:8181/1490 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-19iommu: Fix potential memory leak issueBharat Bhushan
The dma_domain->win_arr is allocated when geometry is set. But if domain is destroyed then the allocated memory is not freed. When the dma_domain is created again then dma_domain is allocated again, so previous win_arr pointer is lost and never freed. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: Ie6d964215c43aa59b9e38ac544169b58aba4bc1a Reviewed-on: http://git.am.freescale.net:8181/1488 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-19Fix geometry configured status checkBharat Bhushan
Checking dma_domain->win_cnt is not sufficient to conclude that geometry it set. Either it should check dma_domain->geom_size also or it should check dma_domain->win_arr as this is allocated when geometry is set. We are using dma_domain->win_arr pointer check in this patch. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Change-Id: I67418215ca6e9f495ec80d90a77a15a9cb766d90 Reviewed-on: http://git.am.freescale.net:8181/1487 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17Merge tag 'v3.8.8'Scott Wood
This is the 3.8.8 stable release Conflicts: include/linux/preempt.h
2013-04-15iommu/fsl: PAMU driver fix for t4240.Varun Sethi
While obtaining the stash destination from the device tree, current code was assuming a single cpu reg property value. In case of t4240, the e6500 cpu node has two entries per reg property. Thus, for certain cpu values code wasn't able to find a valid device tree node. The code also lacked a check to identify if a valid cpu node (cpu node for a stash target) had been found. Thus, resulting in a crash on null cpu node pointer access. This patch fixes the issue, by introducing a mechanism to process all cpu reg property values per cpu node. Also, introduced chek to identify if cpu node corresponding to the stash vcpu has been found or not. Additionally, added a check for l3-cache-controller compatible strings for T4 and B4 devices. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Iced2d9b85cb87a01a6cbc8cb1a592f92e9f7f704 Reviewed-on: http://git.am.freescale.net:8181/1276 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-10squash! iommu/fsl: PAMU driver fixes.Emil Medve
7. Aperture size calculation was off by one byte Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I10c7d34f5a8c541b8b3d6290629e1d87ea8a2ea0 Reviewed-on: http://git.am.freescale.net:8181/1170 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05iommu/amd: Make sure dma_ops are set for hotplug devicesJoerg Roedel
commit c2a2876e863356b092967ea62bebdb4dd663af80 upstream. There is a bug introduced with commit 27c2127 that causes devices which are hot unplugged and then hot-replugged to not have per-device dma_ops set. This causes these devices to not function correctly. Fixed with this patch. Reported-by: Andreas Degert <andreas.degert@googlemail.com> Signed-off-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-04-05iommu/fsl: PAMU driver fixes.Varun Sethi
This patch contains the following fixes: 1. Support for finding guts node on T4 & B4 platforms. 2. Make iova dma_addr_t constistent with iova_to_phys API change. 3. Disable SPAACE while reconfiguring it. 4. Make API and internal function static. 5. Free data pointer in case of an error. 6. Update comment description and remove unneeded comment. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I4763d9783e9f3d8057c991ca424e48e337c20f3b Reviewed-on: http://git.am.freescale.net:8181/884 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05iommu/fsl: Make iova dma_addr_t in the iova_to_phys API.Varun Sethi
Make iova dma_addr_t instead of u64. dma_addrt_t is more appropriate in our case as it is a DMA address. Also, as we support 64 bit physical addresses dma_addr_t is u64 even on 32 bit e500mc based platforms. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Icbb83a6eae00a2be86c20b272eb537b095173f36 Reviewed-on: http://git.am.freescale.net:8181/883 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-03-21iommu/fsl: Freescale PAMU driver and iommu implementation.Varun Sethi
Following is a brief description of the PAMU hardware: PAMU determines what action to take and whether to authorize the action on the basis of the memory address, a Logical IO Device Number (LIODN), and PAACT table (logically) indexed by LIODN and address. Hardware devices which need to access memory must provide an LIODN in addition to the memory address. Peripheral Access Authorization and Control Tables (PAACTs) are the primary data structures used by PAMU. A PAACT is a table of peripheral access authorization and control entries (PAACE).Each PAACE defines the range of I/O bus address space that is accessible by the LIOD and the associated access capabilities. There are two types of PAACTs: primary PAACT (PPAACT) and secondary PAACT (SPAACT).A given physical I/O device may be able to act as one or more independent logical I/O devices (LIODs). Each such logical I/O device is assigned an identifier called logical I/O device number (LIODN). A LIODN is allocated a contiguous portion of the I/O bus address space called the DSA window for performing DSA operations. The DSA window may optionally be divided into multiple sub-windows, each of which may be used to map to a region in system storage space. The first sub-window is referred to as the primary sub-window and the remaining are called secondary sub-windows. This patch provides the PAMU driver (fsl_pamu.c) and the corresponding IOMMU API implementation (fsl_pamu_domain.c). The PAMU hardware driver (fsl_pamu.c) has been derived from the work done by Ashish Kalra and Timur Tabi. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
2013-03-21iommu/fsl: Add the window permission flag as a parameter to ↵Varun Sethi
iommu_window_enable API. Each iommu window can have access permissions associated with it. Extended the window_enable API to incorporate window access permissions. In case of PAMU each window can have its specific set of permissions. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
2013-03-21iommu/fsl: Make iova u64 in the iommu_iova_to_phys API.Varun Sethi
This is required as in case of PAMU iova can be > u32, as it can support a window size of up to 64G (even on 32bit). Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
2013-03-21iommu: Add DOMAIN_ATTR_WINDOWS domain attributeJoerg Roedel
This attribute can be used to set and get the number of subwindows on IOMMUs that are window-based. Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-03-21iommu: Add domain window handling functionsJoerg Roedel
Add the iommu_domain_window_enable() and iommu_domain_window_disable() functions to the IOMMU-API. These functions will be used to setup domains that are based on subwindows and not on paging. Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-03-21iommu: Implement DOMAIN_ATTR_PAGING attributeJoerg Roedel
This attribute of a domain can be queried to find out if the domain supports setting up page-tables using the iommu_map() and iommu_unmap() functions. Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-03-21iommu: Check for valid pgsize_bitmap in iommu_map/unmapJoerg Roedel
In case the page-size bitmap is zero the code path in iommu_map and iommu_unmap is undefined. Make it defined and return -ENODEV in this case. Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-03-21iommu: moving initialization earlierAlexey Kardashevskiy
The iommu_init() initializes IOMMU internal structures and data required for the IOMMU API as iommu_group_alloc(). It is registered as a subsys_initcall now. One of the IOMMU users is going to be a PCI subsystem on POWER. It discovers new IOMMU tables during the PCI scan so the logical place to call iommu_group_alloc() is the moment when a new group is discovered. However PCI scan is done from subsys_initcall hook as IOMMU does so PCI hook can be (and is) called before the IOMMU one. The patch moves IOMMU subsystem initialization one step earlier to make sure that IOMMU is initialized before PCI scan begins. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-03-03iommu/amd: Initialize device table after dma_opsJoerg Roedel
commit f528d980c17b8714aedc918ba86e058af914d66b upstream. When dma_ops are initialized the unity mappings are created. The init_device_table_dma() function makes sure DMA from all devices is blocked by default. This opens a short window in time where DMA to unity mapped regions is blocked by the IOMMU. Make sure this does not happen by initializing the device table after dma_ops. Signed-off-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-02-28intel/iommu: force writebuffer-flush quirk on Gen 4 ChipsetsDaniel Vetter
commit 210561ffd72d00eccf12c0131b8024d5436bae95 upstream. We already have the quirk entry for the mobile platform, but also reports on some desktop versions. So be paranoid and set it everywhere. References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: "Sankaran, Rajesh" <rajesh.sankaran@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-30Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds
Pull drm fixes from Dave Airlie: "Intel, radeon and exynos fixes. Nothing too major or wierd: one dmar fix and a radeon cursor corruption, along with misc exynos fixes." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (21 commits) drm/exynos: add check for the device power status drm/exynos: Make 'drm_hdmi_get_edid' static drm/exynos: fimd and ipp are broken on multiplatform drm/exynos: don't include plat/gpio-cfg.h drm/exynos: Remove "internal" interrupt handling drm/exynos: Add missing static specifiers in exynos_drm_rotator.c drm/exynos: Replace mdelay with usleep_range drm/exynos: Make ipp_handle_cmd_work static drm/exynos: Make g2d_userptr_get_dma_addr static drm/exynos: consider DMA_NONE flag to dmabuf import drm/exynos: free sg object if dma_map_sg is failed drm/exynos: added validation of edid for vidi connection drm/exynos: let drm handle edid allocations drm/radeon: Enable DMA_IB_SWAP_ENABLE on big endian hosts. drm/radeon: fix a rare case of double kfree radeon_display: Use pointer return error codes drm/radeon: fix cursor corruption on DCE6 and newer drm/i915: dump UTS_RELEASE into the error_state iommu/intel: disable DMAR for g4x integrated gfx drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits ...
2013-01-28IOMMU, AMD Family15h Model10-1Fh erratum 746 WorkaroundSuravee Suthikulpanit
The IOMMU may stop processing page translations due to a perceived lack of credits for writing upstream peripheral page service request (PPR) or event logs. If the L2B miscellaneous clock gating feature is enabled the IOMMU does not properly register credits after the log request has completed, leading to a potential system hang. BIOSes are supposed to disable L2B micellaneous clock gating by setting L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b. This patch corrects that for those which do not enable this workaround. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Acked-by: Borislav Petkov <bp@suse.de> Cc: stable@vger.kernel.org Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-01-23iommu/intel: disable DMAR for g4x integrated gfxDaniel Vetter
DMAR support on g4x/gm45 integrated gpus seems to be totally busted. So don't bother, but instead disable it by default to allow distros to unconditionally enable DMAR support. v2: Actually wire up the right quirk entry, spotted by Adam Jackson. Note that according to intel marketing materials only g45 and gm45 support DMAR/VT-d. So we have reports for all relevant gen4 pci ids by now. Still, keep all the other gen4 ids in the quirk table in case the marketing stuff confused me again, which would not be the first time. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=51921 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=538163 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=538163 Cc: Adam Jackson <ajax@redhat.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: stable@vger.kernel.org Acked-By: David Woodhouse <David.Woodhouse@intel.com> Tested-by: stathis <stathis@npcglib.org> Tested-by: Mihai Moldovan <ionic@ionic.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-01-03Drivers: iommu: remove __dev* attributes.Greg Kroah-Hartman
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: Mauro Carvalho Chehab <mchehab@redhat.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-20Merge tag 'iommu-updates-v3.8' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: "A few new features this merge-window. The most important one is probably, that dma-debug now warns if a dma-handle is not checked with dma_mapping_error by the device driver. This requires minor changes to some architectures which make use of dma-debug. Most of these changes have the respective Acks by the Arch-Maintainers. Besides that there are updates to the AMD IOMMU driver for refactor the IOMMU-Groups support and to make sure it does not trigger a hardware erratum. The OMAP changes (for which I pulled in a branch from Tony Lindgren's tree) have a conflict in linux-next with the arm-soc tree. The conflict is in the file arch/arm/mach-omap2/clock44xx_data.c which is deleted in the arm-soc tree. It is safe to delete the file too so solve the conflict. Similar changes are done in the arm-soc tree in the common clock framework migration. A missing hunk from the patch in the IOMMU tree will be submitted as a seperate patch when the merge-window is closed." * tag 'iommu-updates-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (29 commits) ARM: dma-mapping: support debug_dma_mapping_error ARM: OMAP4: hwmod data: ipu and dsp to use parent clocks instead of leaf clocks iommu/omap: Adapt to runtime pm iommu/omap: Migrate to hwmod framework iommu/omap: Keep mmu enabled when requested iommu/omap: Remove redundant clock handling on ISR iommu/amd: Remove obsolete comment iommu/amd: Don't use 512GB pages iommu/tegra: smmu: Move bus_set_iommu after probe for multi arch iommu/tegra: gart: Move bus_set_iommu after probe for multi arch iommu/tegra: smmu: Remove unnecessary PTC/TLB flush all tile: dma_debug: add debug_dma_mapping_error support sh: dma_debug: add debug_dma_mapping_error support powerpc: dma_debug: add debug_dma_mapping_error support mips: dma_debug: add debug_dma_mapping_error support microblaze: dma-mapping: support debug_dma_mapping_error ia64: dma_debug: add debug_dma_mapping_error support c6x: dma_debug: add debug_dma_mapping_error support ARM64: dma_debug: add debug_dma_mapping_error support intel-iommu: Prevent devices with RMRRs from being placed into SI Domain ...
2012-12-20intel-iommu: Free old page tables before creating superpageWoodhouse, David
The dma_pte_free_pagetable() function will only free a page table page if it is asked to free the *entire* 2MiB range that it covers. So if a page table page was used for one or more small mappings, it's likely to end up still present in the page tables... but with no valid PTEs. This was fine when we'd only be repopulating it with 4KiB PTEs anyway but the same virtual address range can end up being reused for a *large-page* mapping. And in that case were were trying to insert the large page into the second-level page table, and getting a complaint from the sanity check in __domain_mapping() because there was already a corresponding entry. This was *relatively* harmless; it led to a memory leak of the old page table page, but no other ill-effects. Fix it by calling dma_pte_clear_range (hopefully redundant) and dma_pte_free_pagetable() before setting up the new large page. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Tested-by: Ravi Murty <Ravi.Murty@intel.com> Tested-by: Sudeep Dutt <sudeep.dutt@intel.com> Cc: stable@kernel.org [3.0+] Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-12-16Merge branches 'iommu/fixes', 'dma-debug', 'x86/amd', 'x86/vt-d', ↵Joerg Roedel
'arm/tegra' and 'arm/omap' into next
2012-12-03iommu/omap: Adapt to runtime pmOmar Ramirez Luna
Use runtime PM functionality interfaced with hwmod enable/idle functions, to replace direct clock operations and sysconfig handling. Due to reset sequence, pm_runtime_[get|put]_sync must be used, to avoid possible operations with the module under reset. Because of this and given that the driver uses spin_locks to protect their critical sections, we must use pm_runtime_irq_safe in order for the runtime ops to be happy, otherwise might_sleep_if checks in runtime framework will complain. The remaining pm_runtime out of iommu_enable and iommu_disable corresponds to paths that can be accessed through debugfs, some of them doesn't work if the module is not enabled first, but in future if the mmu is idled withouth freeing, these are needed to debug. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Tested-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2012-12-03iommu/omap: Migrate to hwmod frameworkOmar Ramirez Luna
Use hwmod data and device attributes to build and register an omap device for iommu driver. - Update the naming convention in isp module. - Remove unneeded check for number of resources, as this is now handled by omap_device and prevents driver from loading. - Now unused, remove platform device and resource data, handling of sysconfig register for softreset purposes, use default latency structure. - Use hwmod API for reset handling. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Tested-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2012-12-03iommu/omap: Keep mmu enabled when requestedOmar Ramirez Luna
The purpose of the mmu is to handle the memory accesses requested by its users. Typically, the mmu is bundled with the processing unit in a single IP block, which makes them to share the same clock to be functional. Currently, iommu code assumes that its user will be indirectly clocking it, but being a separate mmu driver, it should handle its own clocks, so as long as the mmu is requested it will be powered ON and once detached it will be powered OFF. The remaining clock handling out of iommu_enable and iommu_disable corresponds to paths that can be accessed through debugfs, some of them doesn't work if the module is not enabled first, but in future if the mmu is idled withouth freeing, these are needed to debug. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Tested-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2012-12-03iommu/omap: Remove redundant clock handling on ISROmar Ramirez Luna
For the interrupt to be generated, the mmu clock should be already enabled while translating a virtual address, so, this call to clock handling is just increasing/decreasing the counter. This works now, because its users need the same clock and they indirectly power the mmu, in this interrupt context the handling of clocks inside the ISR doesn't seem to be needed nor helping. Next patch should also correct the dependency on clients to handle iommu clocks. Signed-off-by: Omar Ramirez Luna <omar.luna@linaro.org> Tested-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2012-12-03Merge branch 'omap-for-v3.8/cleanup-headers-iommu' of ↵Joerg Roedel
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/omap
2012-12-02iommu/amd: Remove obsolete commentJoerg Roedel
The AMD IOMMU driver only uses the page-sizes it gets from IOMMU core and uses the appropriate page-size. So this comment is not necessary. Signed-off-by: Joerg Roedel <joro@8bytes.org>
2012-12-02iommu/amd: Don't use 512GB pagesJoerg Roedel
There is a bug in the hardware that will be triggered when this page size is used. Make sure this does not happen. Signed-off-by: Joerg Roedel <joro@8bytes.org>
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