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Several bug reports have come in, noting that disabling CONFIG_PCI_MSI
has fixed their problems with this driver. This may be generic system
issues, but there is also the probability of unimplemented hardware
errata workarounds. Until this ream of bug reports is sorted out, we
can get them going in non-MSI interrupt mode.
As such, this change adds an 'msi' module option, which defaults to off.
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Reflect changes in SCSI midlayer and updated to use new
ordered request implementation
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jens Axboe <axboe@suse.de>
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Some hardware does not support the PACKET command at all.
Other hardware supports ATAPI, but the driver does something nasty such
as calling BUG() when an ATAPI command is issued.
For these such cases, we mark them with a new flag, ATA_FLAG_NO_ATAPI.
Initial version contributed by Ben Collins.
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- remove err_mask from the parameter list of the complete functions
- move err_mask to ata_queued_cmd
- initialize qc->err_mask when needed
- for each function call to ata_qc_complete(), replace the err_mask parameter with qc->err_mask.
Signed-off-by: Albert Lee <albertcc@tw.ibm.com>
===============
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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Hi,
the patch below marks several libata (and libata-driver) structures
const so that they end up in the .rodata segment and don't false-share
cachelines with things that get dirtied often.
Signed-off-by: Arjan van de Ven <arjan@infradead.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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Handle errata (it was unintentional on this h/w, whereas its intentional
on others) whereby the nIEN bit in Device Control is ignored, leading to
a situation where a hardware interrupt completes the qc before the
polling code has a chance to.
This will get fixed The Right Way(tm) once Albert Lee's irq-pio
branch is merged, as the more natural PIO method on this hardware is
interrupt-driven.
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- DMA boundary was being handled incorrectly. Copied the code from
ata_fill_sg(), since Marvell has the same DMA boundary needs.
(we can't use ata_fill_sg directly since we have different hardware
descriptors)
- cleaned up the SATA phy reset code, to deal with various errata
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No content changes. Move 60xx code to be closer to other 60xx code.
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Implement flash reset and PCI reset on 50xx and 60xx.
Implement LED enable on 50xx.
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- eliminate a bunch of redundant tests by creating a per-chip-family
set of hooks, mv_hw_ops
- implement more errata, from newer Marvell GPL'd driver
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No content change, just prepping up future mv_hw_ops modularization.
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Based largely on the GPL'd Marvell vendor driver.
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- clear SError and EDMA irq cause registers, after re-init'ing the phy
- move enums with type suffix 'U' to their own enum
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Contributed by Jeroen <dekien@pandora.be>
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Use ata_pad_{alloc,free} in two drivers, to factor out common code.
Add ata_pad_{alloc,free} to two other drivers, which needed the padding
but had not been updated.
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A few drivers were not following the standard meme of printing out
their driver name and version at module load time; this is fixed
as well.
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The second argument to ata_qc_complete() was being used for two
purposes: communicate the ATA Status register to the completion
function, and indicate an error. On legacy PCI IDE hardware, the latter
is often implicit in the former. On more modern hardware, the driver
often completely emulated a Status register value, passing ATA_ERR as an
indication that something went wrong.
Now that previous code changes have eliminated the need to use drv_stat
arg to communicate the ATA Status register value, we can convert it to a
mask of possible error classes.
This will lead to more flexible error handling in the future.
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We now depend on ->tf_read() to provide us with the contents
of the Error shadow register.
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Enforce access rules where appropriate.
If the compiler is smart enough, this may buy us an optimization or two
as a side effect.
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Jeff found an endian bug in the Marvell driver (thanks!). Here's the
fix for it.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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shuffle ifdef location to fix the following warning:
drivers/scsi/sata_mv.c:471: warning: 'mv_dump_mem' defined but not used
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adds helpful function header comments.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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This should fix up lockups that people were seeing due to
improper spinlock placement. Also, the start/stop DMA routines put
guarded trust in the cached state of DMA.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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This is my libata compatible low level driver for the Marvell SATA
family. Currently it runs in DMA mode on a 6081 chip.
The 5xxx series parts are not yet DMA capable in this driver because
the registers have differences that haven't been accounted for yet.
Basically, I'm focused on the 6xxx series right now. I apologize for
those seeing problems on the 5xxx series, I've not had a chance to
look at those problems yet.
For those curious, the previous bug causing the SCSI timeout and
subsequent panics was caused by an improper clear of hc_irq_cause in
mv_host_intr().
This version is running well in my environment (6081 chips,
with/without SW raid1) and is showing equal or better performance
compared to the Marvell driver (mv_sata) in my initial tests (timed
dd's of reads/writes to/from memory/disk).
I still need to look at the causes of occasional problems such as this:
ata11: translating stat 0x35 err 0x00 to sense
ata11: status=0x35 { DeviceFault SeekComplete CorrectedError Error }
SCSI error : <10 0 0 0> return code = 0x8000002
Current sda: sense key Hardware Error
end_request: I/O error, dev sda, sector 3155010
and this, seen at init time:
ATA: abnormal status 0x80 on port 0xE093911C
but they aren't showstoppers.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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* sata_mv: remove pci_intx(), now that the same function is in PCI core
* sata_sis: fix variable initialization bug, trim trailing whitespace
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This function will go away when pci_intx() finally makes it
into the core PCI layer.
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This is my libata compatible low level driver for the Marvell SATA
family. Currently it successfully runs in PIO mode on a 6081 chip.
EDMA support is in the works and should be done shortly. Review,
testing (especially on other flavors of Marvell), comments welcome.
Signed-off-by: Brett Russ <russb@emc.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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