Age | Commit message (Collapse) | Author |
|
|
|
Also rework the fragment management to eliminate fragmentation
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: Ieb1aaf3b7d7e3d42b78efe2411952f10bbd2803d
Reviewed-on: http://git.am.freescale.net:8181/4774
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
|
|
Commit 88d4c504 "fsl_qman: implement CEETM CCSCI and update some ccg
APIs" inadvertently flips the QM_PIRQ_CSCI bit, reactivating a bug
which allowed congestion state to become irreversible because of a
missed interrupt.
Clearing the CSCI bit puts the system back on track.
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Change-Id: I18ffa06a694911567a7a690c7a7aa1e7b4cd85b9
Reviewed-on: http://git.am.freescale.net:8181/3031
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Commit 88d4c504 "fsl_qman: implement CEETM CCSCI and update some ccg
APIs" inadvertently flips the QM_PIRQ_CSCI bit, reactivating a bug
which allowed congestion state to become irreversible because of a
missed interrupt.
Clearing the CSCI bit puts the system back on track.
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Change-Id: I18ffa06a694911567a7a690c7a7aa1e7b4cd85b9
Reviewed-on: http://git.am.freescale.net:8181/3031
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
|
|
|
|
and fix the mask value for correctly getting the XSFDR value.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I72ba857bd01b93ca6042e354c7ca8c391f430e83
Reviewed-on: http://git.am.freescale.net:8181/4059
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
|
|
|
|
This patch modifies the USDPAA code to allow non power of 4 DMA
maps. The code will use multiple TLB1 entries if needed. DMA
maps are still phyically and virually contiguous.
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I42942067059a3c06f0b0d031d266d228295c7c45
Reviewed-on: http://git.am.freescale.net:8181/3857
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
|
|
application to get back the exact portal it was previously using by specifing the portals index value.
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I8233816f0519731eb65b3671d68a01266eee42dd
Reviewed-on: http://git.am.freescale.net:8181/4002
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
|
|
Stash ID and operation mapping can now be set per dma window.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I987abbcba0575fea1b43843c2bce342f4eae4df2
Reviewed-on: http://git.am.freescale.net:8181/3439
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Conflicts:
drivers/iommu/fsl_pamu.c
drivers/iommu/fsl_pamu.h
drivers/iommu/fsl_pamu_domain.c
|
|
This patch modifies the USDPAA code to allow non power of 4 DMA
maps. The code will use multiple TLB1 entries if needed. DMA
maps are still phyically and virually contiguous.
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I42942067059a3c06f0b0d031d266d228295c7c45
Reviewed-on: http://git.am.freescale.net:8181/3857
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
|
|
This allows an application to get back the exact portal it was
previously using by specifing the portals index value.
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I8233816f0519731eb65b3671d68a01266eee42dd
Reviewed-on: http://git.am.freescale.net:8181/4002
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
|
|
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: Icda6a8547559ab45ceea7160cde566ca022e92e8
Reviewed-on: http://git.am.freescale.net:8181/3698
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
|
|
It was unused, and confusing efforts to implement support for
EQCR_CI-stashing.
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: Ia390a4b4b54efba60b4e9b12a73b7d1ec88bf530
Reviewed-on: http://git.am.freescale.net:8181/3697
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com>
|
|
|
|
Stash ID and operation mapping can now be set per dma window.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I987abbcba0575fea1b43843c2bce342f4eae4df2
Reviewed-on: http://git.am.freescale.net:8181/3439
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
In some situations frame queues may still be on a work queue when
a retirement command is sent during cleanup. In order to reach the
retired state these frame queues must be scheduled. This patch sets
an appropriate SDQCR value to ensure that the Frame Queue is scheduled.
Since Frame Queues could be 'locked' to a particular portal if the
Hold Active feature is enabled the shutrown routine must service
all portals to ensure that the FQ reaches a retired state
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I97f79d35c62f179f21b6bd11c23bc0150e54ff5f
Reviewed-on: http://git.am.freescale.net:8181/3339
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
because the later pointer assignments overwrite the results of the kmalloc.
This memleak can be detect after turning on kernel memleak detector.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: If21cc0f8084271d9fe6f73e51dd3ad200ebdad67
Reviewed-on: http://git.am.freescale.net:8181/2747
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Pledge Roy-R01356 <roy.pledge@freescale.com>
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
The cgr and cgrd are passed as parameters to the qman_query_cgr api.
Initialise to all zero before using them.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: I3a6c3fdb0107ded82aec61842ae6463d4849512c
Reviewed-on: http://git.am.freescale.net:8181/2680
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
In 32-bit builds, the ROUNDING macro was breaking kernel assumptions when
fed with 64-bit parameters. This forces it to use the recommended
wrappers in <linux/math64.h> instead.
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: Id708cdad58593f38683112adf59984ffd3d763f7
Reviewed-on: http://git.am.freescale.net:8181/2580
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: I3e47ac16f9d119194aeb15da1186d6038f33f722
Reviewed-on: http://git.am.freescale.net:8181/2530
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Also properly respect the NONBLOCK flag in the read() API
Make sure IRQ is properly inhibited in the IRQ handler
Create a dependancy between USDPAA and USDPAA_IRQ file pointers
Change-Id: Idc0c33c8448a402d5d127e7e4e22e629dbfa5912
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/2310
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
pool channel ID variable
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I076964896bd1a54cf72aa16a25270a978c7d73d3
Reviewed-on: http://git.am.freescale.net:8181/2493
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
The <linux/smp.h> header only includes <asm/smp.h> if CONFIG_SMP is
defined, yet it is required in the non-SMP case too.
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: I0644bca53a0afeb3eb331956f7e4b20959f2a3d6
Reviewed-on: http://git.am.freescale.net:8181/2419
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
which confused any SW checking for NULL pointers
Change-Id: Ic0ac5e61f1776ce8d4ddb622e401942ce2750705
Reviewed-on: http://git.am.freescale.net:8181/2062
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I60be3c3f94f50fca47a53328a70a552b74808ad1
Reviewed-on: http://git.am.freescale.net:8181/1772
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Pledge Roy-R01356 <roy.pledge@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
bman_create_affine_portal() calls bman_create_portal() which in turn calls
request_irq() to register portal_isr.
In case of PREEMPT_RT enabled, request_irq() is converted into
request_threaded_irq() as portal_isr is threaded IRQ handler. But this
request_threaded_irq() can sleep, so it is mandatory to call
request_threaded_irq() only from context that can sleep.
bman_create_affine_portal() is called from context that is already affine
to CPU or in other words this is non-migratable to other CPUs. Hence, it is
not required to run this function in non-preemptible context. Enabling
preemption will allow subsequent functions to sleep.
Call put_affine_portal() on entry i.e. before calling bman_create_portal()
to enable preemption.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Fixes CQ: ENGR00259733
kernel crash in bman_init when PREEMPT_RT is enabled
Change-Id: I628b6fbc986a5bd980ffa68af4fd1ec7a2661758
Reviewed-on: http://git.am.freescale.net:8181/1717
Reviewed-by: Medve Emilian-EMMEDVE1 <Emilian.Medve@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
This reverts commit 5f2780e55e6885e1b89c28fc23f998a27a26d455
I must have grabbed this one by accident. A proper solution needs to be discussed.
Change-Id: I276218aef9ea663d183a1233d79bf303e2113360
Reviewed-on: http://git.am.freescale.net:8181/1703
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I344f564af3cad4d46a1437559ece080dfef59cd2
Reviewed-on: http://git.am.freescale.net:8181/1639
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
- API shall be defined & Exported only when ASF QOS is in use
Change-Id: I026b34d6dec70f70cf44bcaa23573c18ff457b19
Signed-off-by: Sachin Saxena <sachin.saxena@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1378
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Add an API to query the usage levels of DMA memory
Elminates UIO and converts USDPAA to interact with the
kernel via a character devicc
Removed misc/devices fsl_usdpaa file
Remove unneeded file
Change-Id: I797548e2c79f7098e6378484bcae2b455f022cd4
Reviewed-on: http://git.am.freescale.net:8181/1546
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
The QMan revision on both T4240 and B4860 rev2 silicon is 3.1, and both T2080
and T1040 also have QMan rev3.1. Update the qman driver to support rev3.1.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I7ea2149f982023cd5f99729df6c6b61cba46b668
Reviewed-on: http://git.am.freescale.net:8181/1261
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
- Fix the parameter order in disable ceetm mode of sp.
- Alloc memory for CQ after confirming CQ is available for group CQs
- Check prio_b to be non-zero if group_b is set.
- Use object qm_ceetm_weight_code to convert wbfs and ratio.
- Adjust weight code index from W8 to W15 in set/get queue weight
- Fix the byte_cnt field of ceetm statistics counter
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I28e4978e1cc13957e64dd6f0e376d239d1161933
Reviewed-on: http://git.am.freescale.net:8181/1260
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
The CEETM congestion state change notification uses a seperate bit for CSCN
interrupt in software portal's ISR register, and different command to query
congestion state. This patch implmentes the CCSCI interrupt handling, and
combines the ccg's swp setting into qman_ceetm_ccg_set(), because we can only
register ccgr callback to the affine portal.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I246bd70ea33786d39b6a18ae90e03f9fa09c3912
Reviewed-on: http://git.am.freescale.net:8181/1259
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
CGR objects registered against a portal can receive CSCN notifications
via that portal, and this supports the existence of there being more than
one CGR object for the same CGRID (eg. two distinct drivers using the
same portal and using FQs that are subscribed to the same CGR). The
portal code was previously using a distinct list of registered CGRs for
every possible CGRID, ie. a 256-element array of lists! This meant that
when CSCN interrupts occurred and a 256-bit mask was calculated
indicating which CGRIDs had changed state, we would iterate that bitmask
and for each CGRID that had changed, we would iterate the corresponding
list from the array, invoking callbacks for all CGR objects.
Now, we just use a singe list for all CGRs, irrespective of CGRID. Rather
than iterating the bitmask by CGRID and, for each CGRID that had a
state-change, iterating the corresponding CGR list to invoke callbacks,
we now just iterate the single CGR list and for each CGR with a callback,
we check the bit in the bitmask corresponding to the CGRID to determine
whether to invoke the callback.
This is a more efficient use of memory (the 256-element array of lists
used 2KB per portal on 32-bit cores, 4KB on 64-bit), and the code becomes
simpler. And the "downside" doesn't occur, because there are never more
than a small handful of CGR objects per portal at most, and quite often
only one or two (or even none). So a single list is probably as efficient
or even better in the conventional use cases, and much less wasteful of
space.
Furthermore, this logic will be extended for CEETM CCGRs, of which there
are many more than for regular CGRs. So without this change, the
extensions for CEETM would continue the previous bad approach, but with 2
or 4 times the unwelcome footprint.
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: I00ff60edf191aabc9105c0b49e7437fad085f7dc
Reviewed-on: http://git.am.freescale.net:8181/1258
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
This is using thew new PAMU driver
This integration uses a *horrible hack* in order to provide the IOMMU/PAMU
driver with a 'struct device'. Making the QMan portal driver nice and
proper is part of the upstreaming effort
Change-Id: I5f03a3b662949162bff7ac8c7b14ad5fbc0394ce
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: Ic66bb3904ffa537e497ba00c67e22d851087b435
Reviewed-on: http://git.am.freescale.net:8181/1173
Reviewed-by: Ladouceur Jeffrey-R11498 <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
This is to make the ingration patch with the new IOMMU/PAMU driver more
readable
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: Ia8c2acef2f09d0dcbce47cc14f6f9dfbf1f55370
Reviewed-on: http://git.am.freescale.net:8181/1172
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
In case of depletion, the current output contains the BPID both as a number
and as a mask, with the non-zero 'mask' conveying depletion on the
respective bpool. Is less confusing to just use a binary/boolean value for
displaying the depletion status of a bpool
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: Idbab2fa2701405beb6f04327ea199377b36aea73
Reviewed-on: http://git.am.freescale.net:8181/1171
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Change-Id: I49eb1d51209d0df92e3d4add8854c40b31d1a7c2
Signed-off-by: Andy Fleming <afleming@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/971
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
|
|
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
|
|
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Signed-off-by: Hai-Ying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Jeffrey Ladouceur <jeffrey.ladouceur@freescale.com>
Signed-off-by: Jia-Fei Pan <Jiafei.Pan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
|